NSC LM12458

LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with
Self-Calibration
General Description
Key Specifications
The LM12454, LM12458, and LM12H458 are highly integrated Data Acquisition Systems. Operating on just 5V, they
combine a fully-differential self-calibrating (correcting linearity and zero errors) 13-bit (12-bit + sign) analog-to-digital
converter (ADC) and sample-and-hold (S/H) with extensive
analog functions and digital functionality. Up to 32 consecutive conversions, using two’s complement format, can be
stored in an internal 32-word (16-bit wide) FIFO data buffer.
An internal 8-word RAM can store the conversion sequence
for up to eight acquisitions through the LM12(H)458’s
eight-input multiplexer. The LM12454 has a four-channel
multiplexer, a differential multiplexer output, and a differential
S/H input. The LM12454 and LM12(H)458 can also operate
with 8-bit + sign resolution and in a supervisory “watchdog”
mode that compares an input signal against two programmable limits.
Programmable acquisition times and conversion rates are
possible through the use of internal clock-driven timers. The
reference voltage input can be externally generated for absolute or ratiometric operation or can be derived using the internal 2.5V bandgap reference.
All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either an
8-bit or 16-bit databus. The LM12454 and LM12(H)458 include a direct memory access (DMA) interface for
high-speed conversion data transfer.
An evaluation/interface board is available. Order number LM12458EVAL.
Additional applications information can be found in applications notes AN-906, AN-947 and AN-949.
(fCLK = 5 MHz; 8 MHz, H)
j
Resolution
j
13-bit conversion time
8.8 µs, 5.5 µs (H) (max)
j
9-bit conversion time
4.2 µs, 2.6 µs (H) (max)
j
13-bit Through-put rate
j
Comparison time
(“watchdog” mode)
j
ILE
j
VIN range
j
Power dissipation
j
Stand-by mode
j
Single supply
12-bit + sign or 8-bit + sign
88k samples/s (min),
140k samples/s (H) (min)
2.2 µs (max),
1.4 µs (H) (max)
± 1 LSB (max)
GND to VA+
30 mW, 34 mW (H) (max)
50 µW (typ)
3V to 5.5V
Features
n Three operating modes: 12-bit + sign, 8-bit + sign, and
“watchdog”
n Single-ended or differential inputs
n Built-in Sample-and-Hold and 2.5V bandgap reference
n Instruction RAM and event sequencer
n 8-channel (LM12(H)458), 4-channel (LM12454)
multiplexer
n 32-word conversion FIFO
n Programmable acquisition times and conversion rates
n Self-calibration and diagnostic mode
n 8- or 16-bit wide databus dmicroprocessor or DSP
interface
Applications
n
n
n
n
n
Data Logging
Instrumentation
Process Control
Energy Management
Inertial Guidance
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
AT ® is a registered trademark of International Business Machines Corporation.
© 1999 National Semiconductor Corporation
DS011264
www.national.com
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with Self-Calibration
July 1999
Ordering Information
Guaranteed
Guaranteed
Order
See NS
Clock Freq (min)
Linearity Error (max)
Part Number
Package Number
8 MHz
± 1.0 LSB
LM12H458CIV
V44A
LM12H458CIVF
VGZ44A
LM12H458MEL/883
EL44A
or 5962-9319502MYA
5 MHz
± 1.0 LSB
LM12454CIV
V44A
LM12458CIV
V44A
LM12458CIVF
VGZ44A
Connection Diagrams
DS011264-34
Order Number LM12458CIVF or LM12H458CIVF
See NS Package Number VGZ44A
DS011264-2
* Pin names in ( ) apply to the LM12454 and LM12H454.
Order Number LM12454CIV,
LM12458CIV or LM12H458CIV
See NS Package Number V44A
Order Number LM12H458MEL/883 or 5962-9319502MYA
See NS Package Number EL44A
www.national.com
2
Functional Diagrams
LM12454
DS011264-1
LM12(H)458
DS011264-21
3
www.national.com
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Notes 1, 2)
Supply Voltage (VA+ and VD+)
6.0V
Voltage at Input and Output Pins
except IN0–IN3 (LM12454)
−0.3V to V+ + 0.3V
and IN0–IN7 (LM12(H)458)
Voltage at Analog Inputs IN0–IN3 (LM12454)
and IN0–IN7 (LM12(H)458)
GND − 5V to V+ + 5V
300 mV
|VA+ − VD+|
± 5 mA
Input Current at Any Pin (Note 3)
± 20 mA
Package Input Current (Note 3)
Power Dissipation (TA = 25˚C)
V Package (Note 4)
875 mW
Storage Temperature
−65˚C to +150˚C
Lead Temperature
V Package, Infrared, 15 sec.
+300˚C
EL and W Packages,
Solder, 10 sec.
+250˚C
ESD Susceptibility (Note 5)
1.5 kV
LM12458MEL/883
2.0 kV
Temperature Range
(Tmin ≤ TA ≤ Tmax)
LM12454CIV/
LM12(H)458CIV
LM12458MEL/883
Supply Voltage
VA+, VD+
|VA+ − VD+|
VIN+ Input Range
VIN− Input Range
VREF+ Input Voltage
VREF− Input Voltage
VREF+ − VREF−
VREF Common Mode
Range (Note 16)
−40˚C ≤ TA ≤ 85˚C
−55˚C ≤ TA ≤ 125˚C
3.0V to 5.5V
≤100 mV
GND ≤ VIN+ ≤ VA+
GND ≤ VIN− ≤ VA+
1V ≤ VREF+ ≤ VA+
0V ≤ VREF− ≤ VREF+ − 1V
1V ≤ VREF ≤ VA+
0.1 VA+ ≤ VREFCM ≤ 0.6 VA+
Converter Characteristics (Notes 6, 7, 8, 9, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
ILE
Parameter
Positive and Negative Integral
Conditions
After Auto-Cal (Notes 12, 17)
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
± 1/2
±1
LSB (max)
13
Bits (max)
± 3⁄4
±1
± 1.5
±2
± 2.5
±2
± 2.5
± 3.5
LSB (max)
Linearity Error
TUE
DNL
Total Unadjusted Error
After Auto-Cal (Note 12)
Resolution with No Missing Codes
After Auto-Cal (Note 12)
Differential Non-Linearity
After Auto-Cal
Zero Error
After Auto-Cal (Notes 13, 17)
Positive Full-Scale Error
After Auto-Cal (Notes 12, 17)
LM12H458
±1
± 1/2
± 1/2
LM12(H)458MEL
Negative Full-Scale Error
After Auto-Cal (Notes 12, 17)
± 1/2
LM12(H)458MEL
ILE
DC Common Mode Error
(Note 14)
8-Bit + Sign and “Watchdog”
(Note 12)
±2
Mode Positive and Negative
LSB
LSB (max)
LSB (max)
LSB (max)
LSB (max)
± 1/2
LSB (max)
± 3/4
LSB (max)
9
Bits (max)
± 3/4
LSB (max)
± 1/2
LSB (max)
± 1/2
LSB (max)
Integral Linearity Error
TUE
8-Bit + Sign and “Watchdog” Mode
After Auto-Zero
± 1/2
Total Unadjusted Error
8-Bit + Sign and “Watchdog” Mode
Resolution with No Missing Codes
DNL
8-Bit + Sign and “Watchdog” Mode
Differential Non-Linearity
8-Bit + Sign and “Watchdog” Mode
After Auto-Zero
Zero Error
8-Bit + Sign and “Watchdog” Positive
and Negative Full-Scale Error
www.national.com
4
Converter Characteristics (Notes 6, 7, 8, 9, 19)
(Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
8-Bit + Sign and “Watchdog” Mode
± 1/8
LSB
± 0.05
LSB
DC Common Mode Error
Multiplexer Channel-to-Channel
Matching
VIN+
VIN−
VIN+ − VIN−
Non-Inverting Input Range
Inverting Input Range
Differential Input Voltage Range
Common Mode Input Voltage Range
PSS
Power Supply
Zero Error
Sensitivity
Full-Scale Error
(Note 15)
Linearity Error
VA+ = VD+ = 5V ± 10%
VREF+ = 4.5V, VREF− = GND
± 0.2
± 0.4
± 0.2
GND
V (min)
VA+
V (max)
GND
V (min)
VA+
V (max)
−VA+
V (min)
VA+
V (max)
GND
V (min)
VA+
V (max)
± 1.75
±2
LSB (max)
LSB (max)
LSB
CREF
VREF+/VREF− Input Capacitance
85
pF
CIN
Selected Multiplexer Channel Input
75
pF
Capacitance
Converter AC Characteristics (Notes 6, 7, 8, 9, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Clock Duty Cycle
tC
Conversion Time
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
40
% (min)
60
%
(max)
44 (tCLK)
44 (tCLK) + 50 ns
(max)
21 (tCLK)
21 (tCLK) + 50 ns
(max)
9 (tCLK)
9 (tCLK) + 50 ns
(max)
2 (tCLK)
2 (tCLK) + 50 ns
(max)
%
50
13-Bit Resolution,
Sequencer State S5 (Figure 15)
9-Bit Resolution,
Sequencer State S5 (Figure 15)
tA
Acquisition Time
Sequencer State S7 (Figure 15)
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and
“Watchdog” mode
tZ
Auto-Zero Time
Sequencer State S2 (Figure 15)
76 (tCLK)
76 (tCLK) + 50 ns
(max)
tCAL
Full Calibration Time
Sequencer State S2 (Figure 15)
4944 (tCLK)
4944 (tCLK) + 50 ns
(max)
89
88
kHz
142
140
(min)
11 (tCLK)
11 (tCLK) + 50 ns
(max)
Throughput Rate
(Note 18)
tWD
LM12H458
“Watchdog” Mode Comparison
Sequencer States S6, S4,
Time
and S5 (Figure 15)
5
www.national.com
Converter AC Characteristics (Notes 6, 7, 8, 9, 19)
(Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
12-bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for
VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless
otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
DSNR
SESNR
Parameter
Differential Signal-to-Noise Ratio
Single-Ended Signal-to-Noise
Ratio
DSINAD
Differential Signal-to-Noise +
Distortion Ratio
SESINAD Single-Ended Signal-to-Noise +
Distortion Ratio
DTHD
Differential Total Harmonic
Distortion
SETHD
DENOB
Limits
Unit
(Note 11)
(Limit)
77.5
dB
fIN = 20 kHz
fIN = 40 kHz
VIN = 5 Vp-p
75.2
dB
74.7
dB
fIN = 1 kHz
fIN = 20 kHz
fIN = 40 kHz
VIN = ± 5V
69.8
dB
69.2
dB
66.6
dB
fIN = 1 kHz
fIN = 20 kHz
76.9
dB
73.9
dB
fIN = 40 kHz
VIN = 5 Vp-p
70.7
dB
fIN = 1 kHz
fIN = 20 kHz
fIN = 40 kHz
VIN = ± 5V
69.4
dB
68.3
dB
65.7
dB
fIN = 1 kHz
fIN = 20 kHz
−85.8
dB
−79.9
dB
fIN = 40 kHz
−72.9
dB
Distortion
−80.3
dB
−75.6
dB
−72.8
dB
Differential Effective Number
fIN = 20 kHz
fIN = 40 kHz
VIN = ± 5V
fIN = 1 kHz
fIN = 20 kHz
12.6
Bits
12.2
Bits
fIN = 40 kHz
VIN = 5 Vp-p
12.1
Bits
fIN = 1 kHz
fIN = 20 kHz
fIN = 40 kHz
VIN = ± 5V
11.3
Bits
11.2
Bits
10.8
Bits
fIN = 1 kHz
fIN = 20 kHz
fIN = 40 kHz
87.2
dB
78.9
dB
72.8
dB
LM12454 MUXOUT Only
−76
dB
LM12(H)458 MUX
−78
dB
Single-Ended Effective Number
of Bits
DSFDR
VIN = ± 5V
fIN = 1 kHz
Typical
(Note 10)
VIN = 5 Vp-p
fIN = 1 kHz
Single-Ended Total Harmonic
of Bits
SEENOB
Conditions
Differential Spurious Free
Dynamic Range
Multiplexer Channel-to-Channel
Crosstalk
VIN = 5 VPP
fIN = 40 kHz
plus Converter
tPU
Power-Up Time
10
ms
tWU
Wake-Up Time
10
ms
www.national.com
6
DC Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V,
fCLK = 8.0 MHz (LM12H454/8) or fCLK = 5.0 MHz (LM12458), and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
ID+
IA+
IST
Parameter
VD+ Supply Current
VA+ Supply Current
Stand-By Supply Current (ID+ + IA+)
Multiplexer ON-Channel Leakage Current
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
LM12454/8
0.55
1.0
mA (max)
LM12H458
CS = “1”
0.55
1.2
LM12454/8
3.1
5.0
LM12H458
3.1
5.5
CS = “1”
Power-Down Mode Selected
Clock Stopped
10
µA (max)
8 MHz Clock
40
µA (max)
VA+ = 5.5V
ON-Channel = 5.5V
OFF-Channel = 0V
0.3
0.1
LM12(H)458MEL
ON-Channel = 0V
OFF-Channel = 5.5V
Multiplexer OFF-Channel Leakage Current
0.3
0.1
0.3
0.1
LM12454
VIN = 5V
VIN = 2.5V
VIN = 0V
Multiplexer Channel-to-Channel
RON matching
LM12454
VIN = 5V
VIN = 2.5V
VIN = 0V
µA (max)
0.5
0.3
0.1
LM12(H)458MEL
Multiplexer ON-Resistance
µA (max)
0.5
LM12(H)458MEL
ON-Channel = 0V
OFF-Channel = 5.5V
µA (max)
0.5
LM12(H)458MEL
VA+ = 5.5V
ON-Channel = 5.5V
OFF-Channel = 0V
RON
mA (max)
µA (max)
0.5
800
1500
Ω(max)
850
1500
Ω(max)
760
1500
Ω(max)
± 1.0%
± 1.0%
± 1.0%
± 3.0%
± 3.0%
± 3.0%
(max)
(max)
(max)
Internal Reference Characteristics (Notes 6, 7, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
VREFOUT
Parameter
Conditions
Internal Reference Output Voltage
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
2.5 ± 4%
V (max)
2.5
2.5 ± 6%
LM12(H)458MEL
∆VREF/∆T Internal Reference Temperature
40
ppm/˚C
Coefficient
∆REF/∆IL
Internal Reference Load Regulation
∆VREF
Line Regulation
ISC
Internal Reference Short Circuit Current
∆VREF/∆t
Long Term Stability
Sourcing (0 < IL ≤ +4 mA)
0.2
%/mA (max)
Sinking (−1 ≤ IIL < 0 mA)
1.2
%/mA (max)
4.5V ≤ VA+ ≤ 5.5V
VREFOUT = 0V
3
20
mV (max)
13
25
mA (max)
200
7
ppm/kHr
www.national.com
Internal Reference Characteristics (Notes 6, 7, 19)
(Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V unless otherwise specified.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Internal Reference Start-Up Time
tSU
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
VA+ = VD+ = 0V → 5V
CL = 100 µF
10
ms
Digital Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
VIN(1)
Logical “1” Input Voltage
VIN(0)
Logical “0” Input Voltage
IIN(1)
Logical “1” Input Current
VA+ = VD+ = 5.5V
VA+ = VD+ = 4.5V
VIN = 5V
Logical “0” Input Current
LM12(H)458MEL
VIN = 0V
IIN(0)
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
0.005
D0–D15 Input Capacitance
VOUT(1)
Logical “1” Output Voltage
−0.005
IOUT
TRI-STATE ® Output Leakage Current
1.0
µA (max)
−1.0
6
VOUT = 0V
VOUT = 5V
µA (max)
pF
2.4
V (min)
4.25
V (min)
0.4
V (max)
−0.01
−3.0
µA (max)
0.01
3.0
µA (max)
IOUT = −10 µA
VA+ = VD+ = 4.5V
IOUT = 1.6 mA
Logical “0” Output Voltage
V (max)
−2.0
VA+ = VD+ = 4.5V
IOUT = −360 µA
VOUT(0)
V (min)
0.8
2.0
LM12(H)458MEL
CIN
2.0
Digital Timing Characteristics (Notes 6, 7, 8, 19)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, tr = tf = 3 ns, and CL =
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
(See Figures 8, 9, 10)
1, 3
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
40
ns (min)
20
ns (min)
CS or Address Valid to ALE Low
Set-Up Time
2, 4
CS or Address Valid to ALE Low
Hold Time
5
ALE Pulse Width
45
ns (min)
6
RD High to Next ALE High
35
ns (min)
7
ALE Low to RD Low
20
ns (min)
8
RD Pulse Width
100
ns (min)
9
RD High to Next RD or WR Low
100
ns (min)
10
ALE Low to WR Low
20
ns (min)
11
WR Pulse Width
60
ns (min)
12
WR High to Next ALE High
75
ns (min)
13
WR High to Next RD or WR Low
140
ns (min)
14
Data Valid to WR High Set-Up Time
40
ns (min)
15
Data Valid to WR High Hold Time
30
ns (min)
16
RD Low to Data Bus Out of TRI-STATE
www.national.com
8
40
10
ns (min)
70
ns (max)
Digital Timing Characteristics (Notes 6, 7, 8, 19)
(Continued)
The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, tr = tf = 3 ns, and CL =
100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all
other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
(See Figures 8, 9, 10)
17
18
RL = 1 kΩ
RD High to TRI-STATE
RD Low to Data Valid (Access Time)
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
30
30
10
ns (min)
110
ns (max)
10
ns (min)
80
ns (max)
20
Address Valid or CS Low to RD Low
20
ns (min)
21
Address Valid or CS Low to WR Low
20
ns (min)
19
Address Invalid
10
ns (min)
from RD or WR High
22
23
INT High from RD Low
30
DMARQ Low from RD Low
30
10
ns (min)
60
ns (max)
10
ns (min)
60
ns (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > (VA+ or VD+)), the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction
to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150˚C, and the typical thermal resistance (θJA) of the LM12454 and
LM12(H)458 in the V package, when board mounted, is 47˚C/W, in the W package, when board mounted, is 50˚C/W (θJC = 5.8˚C/W), and in the EL package, when
board mounted, is 70˚C/W (θJC = 3.5˚C/W).
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND
will not damage the LM12454 or the LM12(H)458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an
example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.6 VDC to ensure accurate conversions.
DS011264-3
Note 7: VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V+ pin to assure conversion/
comparison accuracy.
Note 8: Accuracy is guaranteed when operating at fCLK = 5 MHz for the LM12454/8 and fCLK = 8 MHz for the LM12H458.
Note 9: With the test condition for VREF (VREF+ − VREF−) given as +5V, the 12-bit LSB is 1.22 mV and the 8-bit/“Watchdog” LSB is 19.53 mV.
Note 10: Typicals are at TA = 25˚C and represent most likely parametric norm.
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figure 6 Figure 7).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 8).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting output value when the inputs are driven with a 2.5V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with VA+ and VD+ at the specified extremes.
Note 16: VREFCM (Reference Voltage Common Mode Range) is defined as (VREF+ + VREF−)/2.
9
www.national.com
Digital Timing Characteristics (Notes 6, 7, 8, 19)
(Continued)
Note 17: The LM12(H)454/8’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result
in a repeatability uncertainty of ± 0.10 LSB.
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see Figure 15). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per conversion. The Throughput Rate is fCLK (MHz)/N, where N is the number of clock cycles/conversion.
Note 19: A military RETS specification is available upon request.
Electrical Characteristics
DS011264-22
VREF = VREF+ − VREF−
VIN = VIN+ − VIN−
GND ≤ VIN+ ≤VA+
GND ≤ VIN− ≤VA+
FIGURE 1. The General Case of Output Digital Code vs the Operating Input Voltage Range
www.national.com
10
Electrical Characteristics
(Continued)
DS011264-23
VREF+ − VREF− = 4.096V
VIN = VIN+ − VIN−
GND ≤ VIN+ ≤VA+
GND ≤ VIN− ≤VA+
FIGURE 2. Specific Case of Output Digital Code vs the Operating Input Voltage Range for VREF = 4.096V
11
www.national.com
Electrical Characteristics
(Continued)
DS011264-24
VREF = VREF+ − VREF−
FIGURE 3. The General Case of the VREF Operating Range
www.national.com
12
Electrical Characteristics
(Continued)
DS011264-25
VREF = VREF+ − VREF−
VA+ = 5V
FIGURE 4. The Specific Case of the VREF Operating Range for VA+ = 5V
DS011264-4
FIGURE 5. Transfer Characteristic
13
www.national.com
Electrical Characteristics
(Continued)
DS011264-5
FIGURE 6. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
DS011264-6
FIGURE 7. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
DS011264-7
FIGURE 8. Offset or Zero Error Voltage
www.national.com
14
Typical Performance Characteristics (Note 9) The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than
shown.
Linearity Error Change
vs Clock Frequency
Linearity Error Change
vs Temperature
DS011264-37
Linearity Error Change
vs Supply Voltage
Linearity Error Change
vs Reference Voltage
DS011264-38
Full-Scale Error Change
vs Clock Frequency
DS011264-40
Full-Scale Error Change
vs Reference Voltage
DS011264-39
Full-Scale Error Change
vs Temperature
DS011264-41
Full-Scale Error
vs Supply Voltage
DS011264-43
Zero Error Change
vs Clock Frequency
DS011264-44
15
DS011264-42
DS011264-45
www.national.com
Typical Performance Characteristics (Note 9) The following curves apply for 12-bit + sign mode after
auto-calibration unless otherwise specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than
shown. (Continued)
Zero Error Change
vs Temperature
Zero Error Change
vs Reference Voltage
DS011264-46
Analog Supply Current
vs Temperature
Zero Error Change
vs Supply Voltage
DS011264-47
Digital Supply Current
vs Clock Frequency
DS011264-49
DS011264-48
Digital Supply Current
vs Temperature
DS011264-50
VREFOUT Load Regulation
DS011264-51
VREFOUT Line Regulation
DS011264-53
DS011264-52
www.national.com
16
Typical Dynamic Performance Characteristics
The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified.
Bipolar Signal-to-Noise Ratio
vs Input Frequency
Bipolar Signal-to-Noise
+ Distortion Ratio
vs Input Frequency
Bipolar Signal-to-Noise
+ Distortion Ratio
vs Input Signal Level
DS011264-54
DS011264-55
Bipolar Spectral Response
with 1.028 kHz Sine Wave Input
Bipolar Spectral Response
with 10 kHz Sine Wave Input
DS011264-57
Bipolar Spectral Response
with 40 kHz Sine Wave Input
DS011264-58
Bipolar Spurious Free
Dynamic Range
DS011264-60
Bipolar Spectral Response
with 20 kHz Sine Wave Input
DS011264-59
Unipolar Signal-to-Noise Ratio
vs Input Frequency
DS011264-61
17
DS011264-56
DS011264-62
www.national.com
Typical Dynamic Performance Characteristics
The following curves apply for 12-bit + sign
mode after auto-calibration unless otherwise specified. (Continued)
Unipolar Signal-to-Noise
+ Distortion Ratio
vs Input Frequency
Unipolar Signal-to-Noise
+ Distortion Ratio
vs Input Signal Level
Unipolar Spectral Response
with 1.028 kHz Sine Wave Input
DS011264-65
DS011264-63
Unipolar Spectral Response
with 10 kHz Sine Wave Input
DS011264-64
Unipolar Spectral Response
with 20 kHz Sine Wave Input
DS011264-66
Unipolar Spectral Response
with 40 kHz Sine Wave Input
DS011264-67
DS011264-68
Test Circuits and Waveforms
DS011264-13
DS011264-12
DS011264-15
DS011264-14
FIGURE 9. TRI-STATE Test Circuits and Waveforms
www.national.com
18
Timing Diagrams
VA+ = VD+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0–D15 outputs.
DS011264-16
FIGURE 10. Multiplexed Data Bus
1, 3: CS or Address valid to ALE low set-up time.
2, 4: CS or Address valid to ALE low hold time.
5: ALE pulse width
6: RD high to next ALE high
7: ALE low to RD low
8: RD pulse width
9: RD high to next RD or WR low
10: ALE low to WR low
11: WR pulse width
12: WR high to next ALE high
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)
19
www.national.com
Timing Diagrams
VA+ = VD+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0–D15
outputs. (Continued)
DS011264-17
FIGURE 11. Non-Multiplexed Data Bus (ALE = 1)
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
18: RD low to data valid (access time)
19: Address invalid from RD or WR high (hold time)
20: CS low or address valid to RD low
21: CS low or address valid to WR low
8: RD pulse width
9: RD high to next RD or WR low
11: WR pulse width
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
VA+ = VD+ = +5V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0–D15 outputs.
DS011264-18
FIGURE 12. Interrupt and DMARQ
22: INT high from RD low
23: DMARQ low from RD low
www.national.com
20
Pin Description
VA+ VD+
D0–D15
RD
Input for the active low READ bus control signal.
The data input/output TRI-STATE buffers, as selected by the logic signal applied to the BW pin,
are enabled when RD and CS are both low. This
allows the LM12(H)454/8 to transmit information
onto the databus.
WR
Input for the active low WRITE bus control signal.
The data input/output TRI-STATE buffers, as selected by the logic signal applied to the BW pin,
are enabled when WR and CS are both low. This
allows the LM12(H)454/8 to receive information
from the databus.
CS
Input for the active low Chip Select control signal.
A logic low should be applied to this pin only during a READ or WRITE access to the
LM12(H)454/8. The internal clocking is halted
and conversion stops while Chip Select is low.
Conversion resumes when the Chip Select input
signal returns high.
Address Latch Enable input. It is used in systems
containing a multiplexed databus. When ALE is
asserted high, the LM12(H)454/8 accepts information on the databus as a valid address. A
high-to-low transition will latch the address data
on A0–A4 while the CS is low. Any changes on
A0–A4 and CS while ALE is low will not affect the
LM12(H)454/8. See Figure 10. When a
non-multiplexed bus is used, ALE is continuously
asserted high. See Figure 11.
External clock input pin. The LM12(H)454/8 operates with an input clock frequency in the range of
0.05 MHz to 10.0 MHz.
ALE
CLK
nal S/H to hold the input signal. The next rising
clock edge either starts a conversion or makes a
comparison to a programmable limit depending
on which function is requested by a programming
instruction. This pin will be an output if “I/O Select” is set high. The SYNC output goes high
when a conversion or a comparison is started
and low when completed. (See Section 2.2). An
internal reset after power is first applied to the
LM12(H)454/8 automatically sets this pin as an
input.
Analog and digital supply voltage pins. The
LM12(H)454/8’s supply voltage operating range
is +3.0V to +5.5V. Accuracy is guaranteed only if
VA+ and VD+ are connected to the same power
supply. Each pin should have a parallel combination of 10 µF (electrolytic or tantalum) and 0.1 µF
(ceramic) bypass capacitors connected between
it and ground.
The internal data input/output TRI-STATE buffers
are connected to these pins. These buffers are
designed to drive capacitive loads of 100 pF or
less. External buffers are necessary for driving
higher load capacitances. These pins allows the
user a means of instruction input and data output. With a logic high applied to the BW pin, data
lines D8–D15 are placed in a high impedance
state and data lines D0–D7 are used for instruction input and data output when the
LM12(H)454/8 is connected to an 8-bit wide data
bus. A logic low on the BW pin allows the
LM12(H)454/8 to exchange information over a
16-bit wide data bus.
A0–A4
The LM12(H)454/8’s address lines. They are
used to access all internal registers, Conversion
FIFO, and Instruction RAM.
SYNC
Synchronization input/output. When used as an
output, it is designed to drive capacitive loads of
100 pF or less. External buffers are necessary for
driving higher load capacitances. SYNC is an input if the Configuration register’s “I/O Select” bit
is low. A rising edge on this pin causes the inter-
BW
Bus Width input pin. This input allows the
LM12(H)454/8 to interface directly with either an
8- or 16-bit databus. A logic high sets the width to
8 bits and places D8–D15 in a high impedance
state. A logic low sets the width to 16 bits.
INT
Active low interrupt output. This output is designed to drive capacitive loads of 100 pF or less.
External buffers are necessary for driving higher
load capacitances. An interrupt signal is generated any time a non-masked interrupt condition
takes place. There are eight different conditions
that can cause an interrupt. Any interrupt is reset
by reading the Interrupt Status register. (See
Section 2.3.)
DMARQ Active high Direct Memory Access Request output. This output is designed to drive capacitive
loads of 100 pF or less. External buffers are necessary for driving higher load capacitances. It
goes high whenever the number of conversion
results in the conversion FIFO equals a programmable value stored in the Interrupt Enable register. It returns to a logic low when the FIFO is
empty.
GND
LM12(H)454/8 ground connection. It should be
connected to a low resistance and inductance
analog ground return that connects directly to the
system power supply ground.
The eight (LM12(H)458) or four (LM12454)
IN0–IN7
analog inputs. A given channel is selected
(IN0–IN3
LM12H454 through the instruction RAM. Any of the chanLM12454) nels can be configured as an independent
single-ended input. Any pair of channels,
whether adjacent or non-adjacent, can operate
as a fully differential pair.
S/H IN+
S/H IN−
The LM12454’s non-inverting and inverting inputs to the internal S/H.
MUXOUT+ The LM12454’s non-inverting and inverting outMUXOUT− puts from the internal multiplexer.
VREF−
The
negative
reference
input.
The
LM12(H)454/8 operate with 0V ≤ VREF− ≤
VREF+. This pin should be bypassed to ground
with a parallel combination of 10 µF and 0.1 µF
(ceramic) capacitors.
VREF+
The
positive
reference
input.
The
LM12(H)454/8 operate with 0V ≤ VREF+ ≤ VA+.
This pin should be bypassed to ground with a
parallel combination of 10 µF and 0.1 µF (ceramic) capacitors.
VREFOUT
The internal 2.5V bandgap’s output pin. This
pin should be bypassed to ground with a 100
µF capacitor.
21
www.national.com
Application Information
1.0 Functional Description
The analog input multiplexer can be configured for any combination of single-ended or fully differential operation. Each
input is referenced to ground when a multiplexer channel operates in the single-ended mode. Fully differential analog input channels are formed by pairing any two channels together.
The LM12454 and LM12(H)458 are multi-functional Data Acquisition Systems that include a fully differential
12-bit-plus-sign self-calibrating analog-to-digital converter
(ADC) with a two’s-complement output format, an 8-channel
(LM12(H)458) or a 4-channel (LM12454) analog multiplexer,
an internal 2.5V reference, a first-in-first-out (FIFO) register
that can store 32 conversion results, and an Instruction RAM
that can store as many as eight instructions to be sequentially executed. The LM12454 also has a differential multiplexer output and a differential S/H input. All of this circuitry
operates on only a single +5V power supply.
The LM12(H)454/8 have three modes of operation:
The LM12454’s multiplexer outputs and S/H inputs (MUXOUT+, MUXOUT− and S/H IN+, S/H IN−) provide the option
for additional analog signal processing. Fixed-gain amplifiers, programmable-gain amplifiers, filters, and other processing circuits can operate on the signal applied to the selected multiplexer channel(s). If external processing is not
used, connect MUXOUT+ to S/H IN+ and MUXOUT− to
S/H IN−.
The LM12(H)454/8’s internal S/H is designed to operate at
its minimum acquisition time (1.13 µs, 12 bits) when the
source impedance, RS, is ≤ 60Ω (fCLK ≤ 8 MHz). When 60Ω
< RS ≤ 4.17 kΩ, the internal S/H’s acquisition time can be increased to a maximum of 4.88 µs (12 bits, fCLK = 8 MHz).
See Section 2.1 (Instruction RAM “00”) Bits 12–15 for more
information.
An internal 2.5V bandgap reference output is available at pin
44. This voltage can be used as the ADC reference for ratiometric conversion or as a virtual ground for front-end analog
conditioning circuits. The VREFOUT pin should be bypassed
to ground with a 100 µF capacitor.
Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conversions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at any
time, interrogate the FIFO and retrieve its contents. It can
also wait for the LM12(H)454/8 to issue an interrupt when
the FIFO is full or after any number (≤32) of conversions
have been stored.
Conversion sequencing, internal timer interval, multiplexer
configuration, and many other operations are programmed
and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the
LM12(H)458’s operation. The diagnostic mode is disabled in
the LM12454. This mode internally connects the voltages
present at the VREFOUT, VREF+, VREF−, and GND pins to the
internal VIN+ and VIN− S/H inputs. This mode is activated by
setting the Diagnostic bit (Bit 11) in the Configuration register
to a “1”. More information concerning this mode of operation
can be found in Section 2.2.
12-bit + sign with correction
8-bit + sign without correction
8-bit + sign comparison mode (“watchdog” mode)
The fully differential 12-bit-plus-sign ADC uses a charge redistribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is used
by a successive approximation register to generate intermediate voltages between the voltages applied to VREF− and
VREF+. These intermediate voltages are compared against
the sampled analog input voltage as each bit is generated.
The number of intermediate voltages and comparisons
equals the ADC’s resolution. The correction of each bit’s accuracy is accomplished by calibrating the capacitor ladder
used in the ADC.
Two different calibration modes are available; one compensates for offset voltage, or zero error, while the other corrects
both offset error and the ADC’s linearity error.
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the full
calibration, the offset error is measured eight times, averaged, and a correction coefficient is created. After completion of either calibration mode, the offset correction coefficient is stored in an internal offset correction register.
The LM12(H)454/8’s overall linearity correction is achieved
by correcting the internal DAC’s capacitor mismatch. Each
capacitor is compared eight times against all remaining
smaller value capacitors and any errors are averaged. A correction coefficient is then created and stored in one of the
thirteen internal linearity correction registers. An internal
state machine, using patterns stored in an internal 16 x 8-bit
ROM, executes each calibration algorithm.
Once calibrated, an internal arithmetic logic unit (ALU) uses
the offset correction coefficient and the 13 linearity correction
coefficients to reduce the conversion’s offset error and linearity error, in the background, during the 12-bit + sign conversion. The 8-bit + sign conversion and comparison modes
use only the offset coefficient. The 8-bit + sign mode performs a conversion in less than half the time used by the
12-bit + sign conversion mode.
2.0 Internal User-Programmable
Registers
INSTRUCTION RAM
The instruction RAM holds up to eight sequentially executable instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit “RAM pointer” in the Configuration register. The
eight instructions are located at addresses 0000 through
0111 (A4–A1, BW = 0) when using a 16-bit wide data bus or
at addresses 00000 through 01111 (A4–A0, BW = 1) when
using an 8-bit wide data bus. They can be accessed and programmed in random order.
The LM12(H)454/8’s “watchdog” mode is used to monitor a
single-ended or differential signal’s amplitude. Each
sampled signal has two limits. An interrupt can be generated
if the input signal is above or below either of the two limits.
This allows interrupts to be generated when analog voltage
inputs are “inside the window” or, alternatively, “outside the
window”. After a “watchdog” mode interrupt, the processor
can then request a conversion on the input signal and read
the signal’s magnitude.
www.national.com
22
2.0 Internal User-Programmable
Registers (Continued)
non-inverting mode and the other operating in the inverting
mode. A code of “000” selects ground as the inverting input
for single ended operation.
Bit 8 is the SYNC bit. Setting Bit 8 to “1” causes the Sequencer to suspend operation at the end of the internal S/H’s
acquisition cycle and to wait until a rising edge appears at
the SYNC pin. When a rising edge appears, the S/H acquires the input signal magnitude and the ADC performs a
conversion on the clock’s next rising edge. When the SYNC
pin is used as an input, the Configuration register’s “I/O Select” bit (Bit 7) must be set to a “0”. With SYNC configured as
an input, it is possible to synchronize the start of a conversion to an external event. This is useful in applications such
as digital signal processing (DSP) where the exact timing of
conversions is important.
When the LM12(H)454/8 are used in the “watchdog” mode
with external synchronization, two rising edges on the SYNC
input are required to initiate two comparisons. The first rising
edge initiates the comparison of the selected analog input
signal with Limit #1 (found in Instruction RAM “01”) and the
second rising edge initiates the comparison of the same analog input signal with Limit #2 (found in Instruction RAM “10”).
Bit 9 is the TIMER bit. When Bit 9 is set to “1”, the Sequencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no “watchdog” comparisons
or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution. Setting Bit 10
to “1” selects 8-bit + sign and when reset to “0” selects 12-bit
+ sign.
Bit 11 is the “watchdog” comparison mode enable bit. When
operating in the “watchdog” comparison mode, the selected
analog input signal is compared with the programmable values stored in Limit #1 and Limit #2 (see Instruction RAM “01”
and Instruction RAM “10”). Setting Bit 11 to “1” causes two
comparisons of the selected analog input signal with the two
stored limits. When Bit 11 is reset to “0”, an 8-bit + sign or
12-bit + sign (depending on the state of Bit 10 of Instruction
RAM “00”) conversion of the input signal can take place.
Any Instruction RAM READ or WRITE can affect the sequencer’s operation:
The Sequencer should be stopped by setting the RESET
bit to a “1” or by resetting the START bit in the Configuration Register and waiting for the current instruction to finish execution before any Instruction RAM READ or
WRITE is initiated.
A soft RESET should be issued by writing a “1” to the
Configuration Register’s RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register’s 2-bit “RAM Pointer”, bits D8 and
D9. The first 16-bit Instruction RAM section is selected with
the RAM Pointer equal to “00”. This section provides multiplexer channel selection, as well as resolution, acquisition
time, etc. The second 16-bit section holds “watchdog” limit
#1, its sign, and an indicator that shows that an interrupt can
be generated if the input signal is greater or less than the
programmed limit. The third 16-bit section holds “watchdog”
limit #2, its sign, and an indicator that shows that an interrupt
can be generated if the input signal is greater or less than the
programmed limit.
Instruction RAM “00”
Bit 0 is the LOOP bit. It indicates the last instruction to be executed in any instruction sequence when it is set to a “1”.
The next instruction to be executed will be instruction 0.
Bit 1 is the PAUSE bit. This controls the Sequencer’s operation. When the PAUSE bit is set (“1”), the Sequencer will stop
after reading the current instruction and before executing it,
and the start bit in the Configuration register is automatically
reset to a “0”. Setting the PAUSE also causes an interrupt to
be issued. The Sequencer is restarted by placing a “1” in the
Configuration register’s Bit 0 (Start bit).
After the Instruction RAM has been programmed and the
RESET bit is set to “1”, the Sequencer retrieves Instruction
000, decodes it, and waits for a “1” to be placed in the Configuration’s START bit. The START bit value of “0” “overrides” the action of Instruction 000’s PAUSE bit when the Sequencer is started. Once started, the Sequencer executes
Instruction 000 and retrieves, decodes, and executes each
of the remaining instructions. No PAUSE Interrupt (INT 5) is
generated the first time the Sequencer executes Instruction
000 having a PAUSE bit set to “1”. When the Sequencer encounters a LOOP bit or completes all eight instructions, Instruction 000 is retrieved and decoded. A set PAUSE bit in
Instruction 000 now halts the Sequencer before the instruction is executed.
Bits 2–4 select which of the eight input channels (“000” to
“111” for IN0–IN7) will be configured as non-inverting inputs
to the LM12(H)458’s ADC. (See Page 27, Table 1.) They select which of the four input channels (“000” to “011” for
IN0–IN4) will be configured as non-inverting inputs to the
LM12454’s ADC. (See Page 27, Table 2.)
Bits 5–7 select which of the seven input channels (“001” to
“111” for IN1 to IN7) will be configured as inverting inputs to
the LM12(H)458’s ADC. (See Page 27, Table 1.) They select
which of the three input channels (“001” to “011” for IN1–IN4)
will be configured as inverting inputs to the LM12454’s ADC.
(See Page 27, Table 2.) Fully differential operation is created
by selecting two multiplexer channels, one operating in the
23
www.national.com
www.national.com
to
24
0 1 1
1 0 0
1 0 1
1
1
1
Purpose
dog
Timer
Register
Limit Status
FIFO
Conversion
=0
Actual Number of
or Sign
Address
Conversion
Data: MSBs
D6
VIN−
D5
D3
VIN+
D2
Limit #2
Limit #1
CAL
Zero
Limit #1: Status
Conversion Data: LSBs
Timer Preset Low Byte
INST7 INST6 INST5 INST4 INST3 INST2 INST1 INST0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
by
D0
Pause Loop
D1
Auto- Reset Start
(Note 20)
(MUXOUT+)
D4
Auto Chan Stand- Full
Sel Zeroec Mask
I/O
(Note 20)
(MUXOUT−)
D7
FIGURE 13. LM12(H)454/8 Memory Map for 16-Bit Wide Databus (BW = “0”, Test Bit = “0” and A0 = Don’t Care)
Limit #2: Status
Sign
Timer Preset High Byte
Executed
being
Instruction
Sequencer
of
Address
Address to
Sequencer
RAM
Pointer
Test
> / < Sign
> / < Sign
Generate INT1
Note 21: LM12(H)458 only. Must be set to “0” for the LM12454.
R
R
D8
to Generate INT2
in Conversion FIFO
Register
D9
8/12 Timer Sync
D10
in Conversion FIFO
Number of Conversions
(Note 21)
DIAG
Don’t Care
Register
R/W
D11
Watch-
Don’t Care
Don’t Care
Time
Acquisition
Conversion Results
R
R/W
R/W
R/W
R/W
R/W
Type D15 D14 D13 D12
Interrupt Status
Register
Interrupt Enable
Register
Configuration
(RAM Pointer = 10)
Instruction RAM
(RAM Pointer = 01)
Instruction RAM
(RAM Pointer = 00)
Instruction RAM
Note 20: LM12454 (Refer to Table 2).
0 1 0
0 0 1
1
1
0 0 0
1 1 1
to
0 0 0
1 1 1
to
0 0 0
1 1 1
1
0
0
0
0 0 0
A4 A3A2A1
2.0 Internal User-Programmable Registers
(Continued)
2.0 Internal User-Programmable Registers
A4
A3
A2
A1
0
0
0
0
to
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
0
0
Instruction
RAM
(RAM
Pointer =
10)
1
1
0
D6
D5
D4
R/W
1
0
0
0
0
1
1
D2
D1
D0
Pause
Loop
Timer
Sync
>/<
Sign
>/<
Sign
Reset
Start
WatchAcquisition Time
dog
8/12
Comparison Limit #1
R/W
Don’t Care
0
1
Comparison Limit #2
R/W
Don’t Care
R/W
Configuration
Register
I/O
Auto
Chan
Stand-
Full
Auto-
Sel
Zeroec
Mask
by
Cal
Zero
DIAG
(Note
23)
Test =
0
INT3
INT2
R/W
Don’t Care
1
D3
VIN+
(MUXOUT+) (Note 22)
VIN−
(MUXOUT−) (Note 22)
R/W
0
1
D7
R/W
Instruction
RAM
(RAM
Pointer =
01)
1
to
0
Instruction
RAM
(RAM
Pointer =
00)
0
1
Type
R/W
1
to
1
1
0
to
1
1
1
to
1
Purpose
0
1
to
1
A0
(Continued)
0
R/W
Interrupt
Enable
Register
1
INT7
R/W
INT6
INT5
INT4
Number of Conversions in Conversion
0
1
0
0
1
0
1
0
1
R
Interrupt
Status
Register
R
INST7
INST6
INST5
INST4
INT1
INT0
Sequencer Address to
FIFO to Generate INT2
1
RAM Pointer
Generate INT1
INST3
INST2
Actual Number of Conversions Results
INST1
INST0
Address of Sequencer
in Conversion FIFO
Instruction
being Executed
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
Timer
Register
R/W
Timer Preset: Low Byte
R/W
Timer Preset: High Byte
Conversion
FIFO
R
Limit Status
Register
R
Conversion Data: LSBs
Address or Sign
Sign
R
Limit #1 Status
R
Limit #2 Status
Conversion Data: MSBs
FIGURE 14. LM12(H)454/8 Memory Map for 8-Bit Wide Databus (BW = “1” and Test Bit = “0”)
Note 22: LM12454 (Refer toTable 2).
Note 23: LM12(H)458 only. Must be set to “0” for the LM12454.
25
www.national.com
2.0 Internal User-Programmable
Registers (Continued)
Bit 9 ’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #2 to generate an interrupt, while a “0” causes a voltage
less than limit #2 to generate an interrupt.
Bits 10–15 are not used.
Bits 12–15 are used to store the user-programmable acquisition time. The Sequencer keeps the internal S/H in the acquisition mode for a fixed number of clock cycles (nine clock
cycles, for 12-bit + sign conversions and two clock cycles for
8-bit + sign conversions or “watchdog” comparisons) plus a
variable number of clock cycles equal to twice the value
stored in Bits 12–15. Thus, the S/H’s acquisition time is (9 +
2D) clock cycles for 12-bit + sign conversions and (2 + 2D)
clock cycles for 8-bit + sign conversions or “watchdog” comparisons, where D is the value stored in Bits 12–15. The
minimum acquisition time compensates for the typical internal multiplexer series resistance of 2 kΩ, and any additional
delay created by Bits 12–15 compensates for source resistances greater than 60Ω (100Ω). (For this acquisition time
discussion, numbers in ( ) are shown for the LM12(H)454/8
operating at 5 MHz.) The necessary acquisition time is determined by the source impedance at the multiplexer input. If
the source resistance (RS) < 60Ω (100Ω) and the clock frequency is 8 MHz, the value stored in bits 12–15 (D) can be
0000. If RS > 60Ω (100Ω), the following equations determine
the value that should be stored in bits 12–15.
D = 0.45 x RS x fCLK
2.2 CONFIGURATION REGISTER
The Configuration register, 1000 (A4–A1, BW = 0) or 1000x
(A4–A0, BW = 1) is a 16-bit control register with read/write
capability. It acts as the LM12454’s and LM12(H)458’s “control panel” holding global information as well as start/stop, reset, self-calibration, and stand-by commands.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an indication of the Sequencer’s status. A “0” indicates that the Sequencer is stopped and waiting to execute the next instruction. A “1” shows that the Sequencer is running. Writing a “0”
halts the Sequencer when the current instruction has finished execution. The next instruction to be executed is
pointed to by the instruction pointer found in the status register. A “1” restarts the Sequencer with the instruction currently pointed to by the instruction pointer. (See Bits 8–10 in
the Interrupt Status register.)
Bit 1 is the LM12(H)454/8’s system RESET bit. Writing a “1”
to Bit 1 stops the Sequencer (resetting the Configuration register’s START/STOP bit), resets the Instruction pointer to
“000” (found in the Interrupt Status register), clears the Conversion FIFO, and resets all interrupt flags. The RESET bit
will return to “0” after two clock cycles unless it is forced high
by writing a “1” into the Configuration register’s Standby bit.
A reset signal is internally generated when power is first applied to the part. No operation should be started until the RESET bit is “0”.
Writing a “1” to Bit 2 initiates an auto-zero offset voltage calibration. Unlike the eight-sample auto-zero calibration performed during the full calibration procedure, Bit 2 initiates a
“short” auto-zero by sampling the offset once and creating a
correction coefficient (full calibration averages eight samples
of the converter offset voltage when creating a correction coefficient). If the Sequencer is running when Bit 2 is set to “1”,
an auto-zero starts immediately after the conclusion of the
currently running instruction. Bit 2 is reset automatically to a
“0” and an interrupt flag (Bit 3, in the Interrupt Status register)
is set at the end of the auto-zero (76 clock cycles). After
completion of an auto-zero calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, an auto-zero is performed immediately at the time
requested.
Writing a “1” to Bit 3 initiates a complete calibration process
that includes a “long” auto-zero offset voltage correction (this
calibration averages eight samples of the comparator offset
voltage when creating a correction coefficient) followed by
an ADC linearity calibration. This complete calibration is
started after the currently running instruction is completed if
the Sequencer is running when Bit 3 is set to “1”. Bit 3 is reset automatically to a “0” and an interrupt flag (Bit 4, in the Interrupt Status register) will be generated at the end of the
calibration procedure (4944 clock cycles). After completion
of a full auto-zero and linearity calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, a full calibration is performed immediately at the
time requested.
Bit 4 is the Standby bit. Writing a “1” to Bit 4 immediately
places the LM12(H)454/8 in Standby mode. Normal operation returns when Bit 4 is reset to a “0”. The Standby com-
for 12-bits + sign
D = 0.36 x RS x fCLK
for 8-bits + sign and “watchdog”
RS is in kΩ and fCLK is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer between the signal source and the LM12(H)458’s multiplexer
inputs. The value of D can also be used to compensate for
the settling or response time of external processing circuits
connected between the LM12454’s MUXOUT and S/H IN
pins.
Instruction RAM “01”
The second Instruction RAM section is selected by placing a
“01” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #1. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first, followed by a comparison of the
same sampled analog input signal with the value found in
limit #2 (Instruction RAM “10”).
Bit 8 holds limit #1’s sign.
Bit 9’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #1 to generate an interrupt, while a “0” causes a voltage
less than limit #1 to generate an interrupt.
Bits 10–15 are not used.
Instruction RAM “10”
The third Instruction RAM section is selected by placing a
“10” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #2. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12(H)454/8 performs a
“watchdog” comparison of the sampled analog input signal
with the limit #1 value first (Instruction RAM “01”), followed
by a comparison of the same sampled analog input signal
with the value found in limit #2.
Bit 8 holds limit #2’s sign.
www.national.com
26
2.0 Internal User-Programmable
Registers (Continued)
they are not masked (by the Interrupt Enable register). The
Interrupt Status register is then read to determine which of
the eight interrupts has been issued.
mand (“1”) disconnects the external clock from the internal
circuitry, decreases the LM12(H)454/8’s internal analog circuitry power supply current, and preserves all internal RAM
contents. After writing a “0” to the Standby bit, the
LM12(H)454/8 returns to an operating state identical to that
caused by exercising the RESET bit. A Standby completion
interrupt is issued after a power-up completion delay that allows the analog circuitry to settle. The Sequencer should be
restarted only after the Standby completion is issued. The Instruction RAM can still be accessed through read and write
operations while the LM12(H)454/8 are in Standby Mode.
TABLE 1. LM12(H)458 Input Multiplexer
Channel Configuration Showing Normal
Mode and Diagnostic Mode
Bit 5 is the Channel Address Mask. If Bit 5 is set to a “1”, Bits
13–15 in the conversion FIFO will be equal to the sign bit (Bit
12) of the conversion data. Resetting Bit 5 to a “0” causes
conversion data Bits 13 through 15 to hold the instruction
pointer value of the instruction to which the conversion data
belongs.
Bit 6 is used to select a “short” auto-zero correction for every
conversion. The Sequencer automatically inserts an
auto-zero before every conversion or “watchdog” comparison if Bit 6 is set to “1”. No automatic correction will be performed if Bit 6 is reset to “0”.
The LM12(H)454/8’s offset voltage, after calibration, has a
typical drift of 0.1 LSB over a temperature range of −40˚C to
+85˚C. This small drift is less than the variability of the
change in offset that can occur when using the auto-zero
correction with each conversion. This variability is the result
of using only one sample of the offset voltage to create a correction value. This variability decreases when using the full
calibration mode because eight samples of the offset voltage
are taken, averaged, and used to create a correction value.
Bit 7 is used to program the SYNC pin (29) to operate as either an input or an output. The SYNC pin becomes an output
when Bit 7 is a “1” and an input when Bit 7 is a “0”. With
SYNC programmed as an input, the rising edge of any logic
signal applied to pin 29 will start a conversion or “watchdog”
comparison. Programmed as an output, the logic level at pin
29 will go high at the start of a conversion or “watchdog”
comparison and remain high until either have finished. See
Instruction RAM “00”, Bit 8.
Bits 8 and 9 form the RAM Pointer that is used to select
each of a 48-bit instruction’s three 16-bit sections during
read or write actions. A “00” selects Instruction RAM section
one, “01” selects section two, and “10” selects section three.
Bit 10 activates the Test mode that is used only during production testing. Leave this bit reset to “0”.
Bit 11 is the Diagnostic bit and is available only in the
LM12(H)458. It can be activated by setting it to a “1” (the Test
bit must be reset to a “0”). The Diagnostic mode, along with
a correctly chosen instruction, allows verification that the
LM12(H)458’s ADC is performing correctly. When activated,
the inverting and non-inverting inputs are connected as
shown in Table I. As an example, an instruction with “001” for
both VIN+ and VIN− while using the Diagnostic mode typically
results in a full-scale output.
Channel
Selection
Data
VIN+
VIN−
VIN+
VIN−
000
IN0
GND
VREFOUT
GND
001
IN1
IN1
VREF+
VREF−
010
IN2
IN2
IN2
IN2
011
IN3
IN3
IN3
IN3
100
IN4
IN4
IN4
IN4
101
IN5
IN5
IN5
IN5
110
IN6
IN6
IN6
IN6
111
IN7
IN7
IN7
IN7
Normal
Diagnostic
Mode
Mode
TABLE 2. LM12454 Input Multiplexer
Channel Configuration
Channel
Selection
MUX+
MUX−
000
IN0
GND
001
IN1
IN1
010
IN2
IN2
011
IN3
IN3
1XX
OPEN
Data
OPEN
The Interrupt Status register, 1010 (A4–A1, BW = 0) or
1010x (A4–A0, BW = 1) must be cleared by reading it after
writing to the Interrupt Enable register. This removes any
spurious interrupts on the INT pin generated during an Interrupt Enable register access.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12(H)454/8 are operating in the “watchdog” comparison
mode. Two sequential comparisons are made when the
LM12(H)454/8 are executing a “watchdog” instruction. Depending on the logic state of Bit 9 in the Instruction RAM’s
second and third sections, an interrupt will be generated either when the input signal’s magnitude is greater than or less
than the programmable limits. (See the Instruction RAM, Bit
9 description.) The Limit Status register will indicate which
preprogrammed limit, #1 or #2 and which instruction was executing when the limit was crossed.
Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register’s bits 8–10. This flag appears before the instruction’s execution.
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value
stored in the Interrupt Enable register’s Bits 11–15. This
value ranges from 0001 to 1111, representing 1 to 31 conversions stored in the FIFO. A user-programmed value of 0000
has no meaning. See Section 3.0 for more FIFO information.
The completion of the short, single-sampled auto-zero calibration generates Interrupt 3.
2.3 INTERRUPTS
The LM12454 and LM12(H)458 have eight possible interrupts, all with the same priority. Any of these interrupts will
cause a hardware interrupt to appear on the INT pin (31) if
27
www.national.com
2.0 Internal User-Programmable
Registers (Continued)
member that the Sequencer continues to operate even if an
Instruction interrupt (INT 1) is internally or externally generated. The only mechanisms that stop the Sequencer are an
instruction with the PAUSE bit set to “1” (halts before instruction execution), placing a “0” in the Configuration register’s
START bit, or placing a “1” in the Configuration register’s RESET bit.
Bits 11–15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an internal interrupt. This internal interrupt appears in Bit 2 of the Interrupt Status register. If Bit 2 of the Interrupt Enable register
is set to “1”, an external interrupt will appear at pin 31 (INT).
The completion of a full auto-zero and linearity
self-calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters an
instruction that has its Pause bit (Bit 1 in Instruction RAM
“00”) set to “1”.
The LM12(H)454/8 issues Interrupt 6 whenever it senses
that its power supply voltage is dropping below 4V (typ). This
interrupt indicates the potential corruption of data returned
by the LM12(H)454/8.
Interrupt 7 is issued after a short delay (10 ms typ) while the
LM12(H)454/8 returns from Standby mode to active operation using the Configuration register’s Bit 4. This short delay
allows the internal analog circuitry to settle sufficiently, ensuring accurate conversion results.
2.5 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1,
BW = 0) or 1010x (A4–A0, BW = 1). The corresponding flag
in the Interrupt Status register goes high (“1”) any time that
an interrupt condition takes place, whether an interrupt is enabled or disabled in the Interrupt Enable register. Any of the
active (“1”) Interrupt Status register flags are reset to “0”
whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
Bit 0 is set to “1” when a “watchdog” comparison limit interrupt has taken place.
2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
(A4–A1, BW = 0) or 1001x (A4–A0, BW = 1) has READ/
WRITE capability. An individual interrupt’s ability to produce
an external interrupt at pin 31 (INT) is accomplished by placing a “1” in the appropriate bit location. Any of the internal
interrupt-producing operations will set their corresponding
bits to “1” in the Interrupt Status register regardless of the
state of the associated bit in the Interrupt Enable register.
See Section 2.3 for more information about each of the eight
internal interrupts.
Bit 0 enables an external interrupt when an internal “watchdog” comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 enables an external interrupt when the Conversion
FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable register, has been reached.
Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.
Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.
Bit 6 enables an external interrupt when a low power supply
condition (VA+ < 4V) has generated an internal interrupt.
Bit 7 enables an external interrupt when the LM12(H)454/8
return from power-down to active mode.
Bits 8–10 form the storage location of the
user-programmable value against which the Sequencer’s
address is compared. When the Sequencer reaches an address that is equal to the value stored in Bits 8–10, an internal interrupt is generated and appears in Bit 1 of the Interrupt
Status register. If Bit 1 of the Interrupt Enable register is set
to “1”, an external interrupt will appear at pin 31 (INT).
Bit 1 is set to “1” when the Sequencer has reached the address stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 is set to “1” when the Conversion FIFO’s limit, stored in
Bits 11–15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to “1” when the single-sampled auto-zero has
been completed.
Bit 4 is set to “1” when an auto-zero and full linearity
self-calibration has been completed.
Bit 5 is set to “1” when a Pause interrupt has been generated.
Bit 6 is set to “1” when a low-supply voltage condition
(VA+ < 4V) has taken place.
Bit 7 is set to “1” when the LM12(H)454/8 return from
power-down to active mode.
Bits 8–10 hold the Sequencer’s actual instruction address
while it is running.
Bits 11–15 hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.
2.6 LIMIT STATUS REGISTER
The read-only register is located at address 1101 (A4–A1,
BW = 0) or 1101x (A4–A0, BW = 1). This register is used in
tandem with the Limit #1 and Limit #2 registers in the Instruction RAM. Whenever a given instruction’s input voltage exceeds the limit set in its corresponding Limit register (#1 or
#2), a bit, corresponding to the instruction number, is set in
the Limit Status register. Any of the active (“1”) Limit Status
flags are reset to “0” whenever this register is read or a device reset is issued (see Bit 1 in the Configuration register).
This register holds the status of limits #1 and #2 for each of
the eight instructions.
Bits 0–7 show the Limit #1 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage exceeds the threshold stored in the instruction’s Limit #1 register. When, for example, instruction 3 is a “watchdog” operation (Bit 11 is set high) and the input for instruction 3 meets
the magnitude and/or polarity data stored in instruction 3’s
Limit #1 register, Bit 3 in the Limit Status register will be set
to a “1”.
The value stored in bits 8–10 ranges from 000 to 111, representing 0 to 7 instructions stored in the Instruction RAM. After the Instruction RAM has been programmed and the RESET bit is set to “1”, the Sequencer is started by placing a “1”
in the Configuration register’s START bit. Setting the INT 1
trigger value to 000 does not generate an INT 1 the first
time the Sequencer retrieves and decodes Instruction 000.
The Sequencer generates INT 1 (by placing a “1” in the Interrupt Status register’s Bit 1) the second time and after the
Sequencer encounters Instruction 000. It is important to rewww.national.com
28
2.0 Internal User-Programmable
Registers (Continued)
that generated the conversion and the resulting data. These
modes are selected according to the logic state of the Configuration register’s Bit 5.
The FIFO status should be read in the Interrupt Status register (Bits 11–15) to determine the number of conversion results that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion data into the
FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the
LM12(H)454/8’s interrupt capability be used to inform the
system controller that the FIFO is full.
The lower portion (A0 = 0) of the data word (Bits 0–7) should
be read first followed by a read of the upper portion (A0 = 1)
when using the 8-bit bus width (BW = 1). Reading the upper
portion first causes the data to shift down, which results in
loss of the lower byte.
Bits 0–12 hold 12-bit + sign conversion data. Bits 0–3 will
be 1110 (LSB) when using 8-bit plus sign resolution.
Bits 13–15 hold either the instruction responsible for the associated conversion data or the sign bit. Either mode is selected with Bit 5 in the Configuration register.
Using the FIFO’s full depth is achieved as follows. Set the
value of the Interrupt Enable register’s Bits 11–15 to 11111
and the Interrupt Enable register’s Bit 2 to a “1”. This generates an external interrupt when the 31st conversion is stored
in the FIFO. This gives the host processor a chance to send
a “0” to the LM12(H)454/8’s Start bit (Configuration register)
and halt the ADC before it completes the 32nd conversion.
The Sequencer halts after the current (32) conversion is
completed. The conversion data is then transferred to the
FIFO and occupies the 32nd location. FIFO overflow is
avoided if the Sequencer is halted before the start of the
32nd conversion by placing a “0” in the Start bit (Configuration register). It is important to remember that the Sequencer
continues to operate even if a FIFO interrupt (INT 2) is internally or externally generated. The only mechanisms
that stop the Sequencer are an instruction with the PAUSE
bit set to “1” (halts before instruction execution), placing a “0”
in the Configuration register’s START bit, or placing a “1” in
the Configuration register’s RESET bit.
Bits 8–15 show the Limit #2 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage exceeds the threshold stored in the instruction’s Limit #2 register. When, for example, the input to instruction 6 meets the
value stored in instruction 6’s Limit #2 register, Bit 14 in the
Limit Status register will be set to a “1”.
2.7 TIMER
The LM12(H)454/8 have an on-board 16-bit timer that includes a 5-bit pre-scaler. It uses the clock signal applied to
pin 23 as its input. It can generate time intervals of 0 through
221 clock cycles in steps of 25. This time interval can be used
to delay the execution of instructions. It can also be used to
slow the conversion rate when converting slowly changing
signals. This can reduce the amount of redundant data
stored in the FIFO and retrieved by the controller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4–A1, BW = 0) or 1011x (A4–A0, BW = 1) and is
pre-loaded automatically. Bits 0–7 hold the preset value’s
low byte and Bits 8–15 hold the high byte. The Timer is activated by the Sequencer only if the current instruction’s Bit 9
is set (“1”). If the equivalent decimal value “N” (0 ≤ N ≤ 216 −
1) is written inside the 16-bit Timer register and the Timer is
enabled by setting an instruction’s bit 9 to a “1”, the Sequencer will delay the same instruction’s execution by halting at state 3 (S3), as shown in Figure 15, for 32 x N + 2
clock cycles.
2.8 DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO interrupt
be enabled. The voltage on the DMARQ pin goes high when
the number of conversions in the FIFO equals the 5-bit value
stored in the Interrupt Enable register (bits 11–15). The voltage on the INT pin goes low at the same time as the voltage
on the DMARQ pin goes high. The voltage on the DMARQ
pin goes low when the FIFO is emptied. The Interrupt Status
register must be read to clear the FIFO interrupt flag in order
to enable the next DMA request.
DMA operation is optimized through the use of the 16-bit
databus connection (a logic “0” applied to the BW pin). Using
this bus width allows DMA controllers that have single address Read/Write capability to easily unload the FIFO. Using
DMA on an 8-bit databus is more difficult. Two read operations (low byte, high byte) are needed to retrieve each conversion result from the FIFO. Therefore, the DMA controller
must be able to repeatedly access two constant addresses
when transferring data from the LM12(H)454/8 to the host
system.
3.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100
(A4–A1, BW = 0) or 1100x (A4–A0, BW = 1). This register
has 32 16-bit wide locations. Each location holds 13-bit data.
Bits 0–3 hold the four LSB’s in the 12 bits + sign mode or
“1110” in the 8 bits + sign mode. Bits 4–11 hold the eight
MSB’s and Bit 12 holds the sign bit. Bits 13–15 can hold either the sign bit, extending the register’s two’s complement
data format to a full sixteen bits or the instruction address
29
www.national.com
4.0 Sequencer
State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in Figure 9) to retrieve the programmable conversion instructions stored in the Instruction RAM. The 3-bit counter is
reset to 000 during chip reset or if the current executed instruction has its Loop bit (Bit 1 in any Instruction RAM “00”)
set high (“1”). It increments at the end of the currently executed instruction and points to the next instruction. It will
continue to increment up to 111 unless an instruction’s Loop
bit is set. If this bit is set, the counter resets to “000” and execution begins again with the first instruction. If all instructions have their Loop bit reset to “0”, the Sequencer will execute all eight instructions continuously. Therefore, it is
important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be set.
Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be
unpredictable.
The Sequencer’s Instruction Pointer value is readable at any
time and is found in the Status register at Bits 8–10. The Sequencer can go through eight states during instruction execution:
32T + 2
where 0 ≤ T ≤ 216 −1.
State 7: Run the acquisition delay and read Limit #1’s
value if needed. The number of clock cycles for 12-bit + sign
mode varies according to
9 + 2D
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
The number of clock cycles for 8-bit + sign or “watchdog”
mode varies according to
2 + 2D
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
State 6: Perform first comparison. This state is 5 clock
cycles long.
State 4: Read Limit #2. This state is 1 clock cycle long.
State 0: The current instruction’s first 16 bits are read from
the Instruction RAM “00”. This state is one clock cycle long.
State 1: Checks the state of the Calibration and Start bits.
This is the “rest” state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low (“0”). When the Start bit is set to a “1”, this state is one
clock cycle long.
State 2: Perform calibration. If bit 2 or bit 6 of the Configuration register is set to a “1”, state 2 is 76 clock cycles long.
If the Configuration register’s bit 3 is set to a “1”, state 2 is
4944 clock cycles long.
www.national.com
State 5: Perform a conversion or second comparison. This
state takes 44 clock cycles when using the 12-bit + sign
mode or 21 clock cycles when using the 8-bit + sign mode.
The “watchdog” mode takes 5 clock cycles.
30
4.0 Sequencer
(Continued)
DS011264-19
FIGURE 15. Sequencer Logic Flow Chart (IP = Instruction Pointer)
31
www.national.com
5.0 Analog Considerations
can be increased. As an example, operating with a 5 MHz
clock frequency and maximum acquisition time, the
LM12(H)454/8’s analog inputs can handle source impedance as high as 6.67 kΩ. When operating at 8 MHz and
maximum acquisition time, the LM12H454/8’s analog inputs
can handle source impedance as high as 4.17 kΩ. Refer to
Section 2.1, Instruction RAM “00”, Bits 12–15 for further information.
5.1 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF+ and
VREF− defines the analog input voltage span (the difference
between the voltages applied between two multiplexer inputs
or the voltage applied to one of the multiplexer inputs and
analog ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving VREF+ or VREF−
must have very low output impedance and noise.
The ADC can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC’s reference voltage. When this voltage is the system power supply, the VREF+ pin is connected to VA+ and VREF− is connected to GND. This technique relaxes the system reference
stability requirements because the analog input voltage and
the ADC reference voltage move together. This maintains
the same output code for given input conditions.
For absolute accuracy, where the analog input voltage varies
between very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference inputs. Typically, the reference voltage’s magnitude will require
an initial adjustment to null reference voltage induced
full-scale errors.
When using the LM12(H)454/8’s internal 2.5V bandgap reference, a parallel combination of a 100 µF capacitor and a
0.1 µF capacitor connected to the VREFOUT pin is recommended for low noise operation. When left unconnected, the
reference remains stable without a bypass capacitor. However, ensure that stray capacitance at the VREFOUT pin remains below 50 pF.
5.5 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected between the analog input pins, IN0–IN7, and analog ground to
filter any noise caused by inductive pickup associated with
long input leads. It will not degrade the conversion accuracy.
5.6 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce the effects of the
noise sources.
5.7 POWER SUPPLIES
Noise spikes on the VA+ and VD+ supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. Low inductance tantalum capacitors of 10 µF or greater paralleled
with 0.1 µF monolithic ceramic capacitors are recommended
for supply bypassing. Separate bypass capacitors should be
used for the VA+ and VD+ supplies and placed as close as
possible to these pins.
5.2 INPUT RANGE
The LM12(H)454/8’s fully differential ADC and reference
voltage inputs generate a two’s-complement output that is
found by using the equation below.
5.8 GROUNDING
The LM12(H)454/8’s nominal high resolution performance
can be maximized through proper grounding techniques.
These include the use of separate analog and digital ground
planes. The digital ground plane is placed under all components that handle digital signals, while the analog ground
plane is placed under all analog signal handling circuitry. The
digital and analog ground planes are connected at only one
point, the power supply ground. This greatly reduces the occurrence of ground loops and noise.
It is recommended that stray capacitance between the analog inputs or outputs (LM12(H)454: IN0–IN3, MUXOUT+,
MUXOUT−, S/H IN+, S/H IN−; LM12(H)458: IN0–IN7,
VREF+, and VREF−) be reduced by increasing the clearance
(+1/16th inch) between the analog signal and reference pins
and the ground plane.
Round up to the next integer value between −4096 to 4095
for 12-bit resolution and between −256 to 255 for 8-bit resolution if the result of the above equation is not a whole number. As an example, VREF+ = 2.5V, VREF− = 1V, VIN+ = 1.5V
and VIN− = GND. The 12-bit + sign output code is positive
full-scale, or 0,1111,1111,1111. If VREF+ = 5V, VREF− = 1V,
VIN+ = 3V, and VIN− = GND, the 12-bit + sign output code is
0,1100,0000,0000.
5.9 CLOCK SIGNAL LINE ISOLATION
5.3 INPUT CURRENT
A charging current flows into or out of (depending on the input voltage polarity) the analog input pins, IN0–IN7 at the
start of the analog input acquisition time (tACQ). This current’s peak value will depend on the actual input voltage applied.
The LM12(H)454/8’s performance is optimized by routing the
analog input/output and reference signal conductors (pins
34–44) as far as possible from the conductor that carries the
clock signal to pin 23. Ground traces parallel to the clock signal trace can be used on printed circuit boards to reduce
clock signal interference on the analog input/output pins.
5.4 INPUT SOURCE RESISTANCE
For low impedance voltage sources ( < 100Ω for 5 MHz operation and < 60Ω for 8 MHz operation), the input charging
current will decay, before the end of the S/H’s acquisition
time, to a value that will not introduce any conversion errors.
For higher source impedances, the S/H’s acquisition time
6.0 Application Circuits
www.national.com
PC EVALUATION/INTERFACE BOARD
Figure 16 is the schematic of an evaluation/interface board
designed to interface the LM12(H)454 or LM12(H)458 with
an XT or AT ® style computer. The board can be used to de32
6.0 Application Circuits
TABLE 3. LM12(H)454/8 Evaluation/Interface
Board SW DIP-8 Switch Settings
for Available I/O Memory Locations
(Continued)
velop both software and hardware. The board hardwires the
BW (Bus Width) pin to a logic high, selecting an 8-bit wide
databus. Therefore, it is designed for an 8-bit expansion slot
on the computer’s motherboard.
The circuit operates on a single +5V supply derived from the
computer’s +12V supply using an LM340 regulator. This
greatly attenuates noise that may be present on the computer’s power supply lines. However, your application may only
need an LC filter.
Hexidecimal
SW DIP-8
I/O Memory
Base Address
Figure 16 also shows the recommended supply (VA+ and
VD+) and reference input (VREF+ and VREF−) bypassing. The
digital and analog supply pins can be connected together to
the same supply voltage. However, they need separate, multiple bypass capacitors. Multiple capacitors on the supply
pins and the reference inputs ensures a low impedance bypass path over a wide frequency range.
All digital interface control signals (IOR, IOW, and AEN),
data lines (DB0–DB7), address lines (A0–A9), and IRQ (interrupt request) lines (IRQ2, IRQ3, and IRQ5) connections
are made through the motherboard slot connector. All analog
signals applied to, or received by, the input multiplexer
(IN0–IN7 for the LM12(H)458 and IN0–IN3, MUXOUT+,
MUXOUT−, S/H IN+ and S/H IN− for the LM12(H)454),
VREF+, VREF−, VREFOUT, and the SYNC signal input/ output
are applied through a DB-37 connector on the rear side of
the board. Figure 16 shows that there are numerous analog
ground connections available on the DB-37 connector.
The voltage applied to VREF− and VREF+ is selected using
two jumpers, JP1 and JP2. JP1 selects between the voltage
applied to the DB-37’s pin 24 or GND and applies it to the
LM12(H)454/8’s VREF− input. JP2 selects between the
LM12(H)454/8’s internal reference output, VREFOUT, and the
voltage applied to the DB-37’s pin 22 and applies it to the
LM12(H)454/8’s VREF+ input.
SW1
SW2
SW3
SW4
(SEL0)
(SEL1)
(SEL2)
(SEL3)
100
ON
ON
ON
ON
120
OFF
ON
ON
ON
140
ON
OFF
ON
ON
160
OFF
OFF
ON
ON
180
ON
ON
OFF
ON
1A0
OFF
ON
OFF
ON
1C0
ON
OFF
OFF
ON
300
OFF
OFF
OFF
ON
340
ON
ON
ON
OFF
280
OFF
ON
ON
OFF
2A0
ON
OFF
ON
OFF
The board allows the use of one of three Interrupt Request
(IRQ) lines IRQ2, IRQ3, and IRQ5. The individual IRQ line
can be selected using switches 5, 6, and 7 of SW DIP-8.
When using any of these three IRQs, the user needs to ensure that there are no conflicts between the evaluation board
and any other boards attached to the computer’s motherboard.
Switches 1–4, along with address lines A5–A9 are used as
inputs to GAL16V8 Programmable Gate Array (U2). This device forms the interface between the computer’s control and
address lines and generates the control signals used by the
LM12(H)454/8 for CS, WR, and RD. It also generates the
signal that controls the data buffers. Several address ranges
within the computer’s I/O memory map are available. Refer
to Table III for the switch settings that gives the desired I/O
memory address range. Selection of an address range must
be done so that there are no conflicts between the evaluation
board and any other boards attached to the computer’s
motherboard. The GAL equations are shown in Figure 18.
The GAL functional block diagram is shown in Figure 19.
Figures 20, 21, 22, 23 show the layout of each layer in the
3-layer evaluation/interface board plus the silk-screen layout
showing parts placement. Figure 21 is the top or component
side, Figure 22 is the middle or ground plane layer, Figure 23
is the circuit side, and Figure 20 is the parts layout.
33
www.national.com
6.0 Application Circuits
(Continued)
DS011264-26
Note: The layout utilizes a split ground plane. The analog ground plane is placed under all analog signals and U5 pins 1, 34–44. The remaining signals and
pins are placed over the digital ground. The single point ground connection is at U6, pin 2, and this is connected to the motherboard pin B1.
FIGURE 16. Schematic for the LM12(H)454/8 Evaluation Interface
Board for XT and AT Style Computers, Order Number LM12458EVAL
www.national.com
34
6.0 Application Circuits
(Continued)
Parts List:
Y1
D1
L1
HC49U, 8 MHz crystal
1N4002
33 µH
P1
R1
R2
RN1
JP1, JP2
DB37F; parallel connector
10 MΩ, 5%, 1⁄4W
2 kΩ, 5%, 1⁄4W
10 kΩ, 6 resistor SIP, 5%, 1⁄8W
HX3, 3-pin jumper
S1
SW DIP-8; 8 SPST switches
C1–3, C6, C9–11,
C19, C22
C4
C5
C7, C21
C8, C12, C20
C13, C16
C14, C18
C15, C17
U1
0.1 µF, 50V, monolithic ceramic
68 pF, 50V, ceramic disk
15 pF, 50V, ceramic disk
100 µF, 25V, electrolytic
10 µF, 35V, electrolytic
0.01 µF, 50V, monolithic ceramic
1 µF, 35V, tantalum
100 µF, 50V, ceramic disk
MM74HCT244N
U2
U3
U4
U5
U6
SK1
A1
GAL16V8-20LNC
MM74HCT245N
MM74HCU04N
LM12(H)458CIV or LM12454CIV
LM340AT-5.0
44-pin PLCC socket
LM12(H)458/4 Rev. D PC Board
FIGURE 17. Parts List for the LM12(H)454/8 Evaluation Interface
Board for XT and AT Style Computers, Order Number LM12458EVAL
35
www.national.com
6.0 Application Circuits
(Continued)
DS011264-32
FIGURE 18. Logic Equations Used to Program the GAL16V8
www.national.com
36
6.0 Application Circuits
(Continued)
DS011264-27
FIGURE 19. GAL Functional Block Diagram
DS011264-31
FIGURE 20. Silk-Screen Layout Showing Parts Placement on the LM12(H)454/8 Evaluation/Interface Board
37
www.national.com
6.0 Application Circuits
(Continued)
DS011264-28
FIGURE 21. LM12(H)454/8 Evaluation/Interface Board Component-Side Layout Positive
www.national.com
38
6.0 Application Circuits
(Continued)
DS011264-29
FIGURE 22. LM12(H)454/8 Evaluation/Interface Board Ground-Plane Layout Negative
39
www.national.com
6.0 Application Circuits
(Continued)
DS011264-30
FIGURE 23. LM12(H)454/8 Evaluation/Interface Circuit-Side Layout Positive
www.national.com
40
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number LM12458MEL/883 or 5962-9319501MYA,
LM12H458MEL/883 or 5962-9319502MYA
NS Package Number EL44A
41
www.national.com
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Order Number LM12454CIV, LM12458CIV or LM12H458CIV
NS Package Number V44A
Order Number LM12H458CIVF or LM12458CIVF
NS Package Number VGZ44A
www.national.com
42
LM12454/LM12458/LM12H458
12-Bit + Sign Data Acquisition System with Self-Calibration
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.