1/4 STRUCTURE PRODUCT SERIES Silicon Monolithic Integrated Circuit 8-Channel Switching Regulator Controller for Digital Camera TYPE PIN ASSIGNMENT BLOCK DIAGRAM PACKAGE Functions BD９７５７MWV Fig.1 Fig.2 Fig.3 ●1.5V minimum input operating ●Supplies power for the internal circuit by step-up converter(CH1). ●Contains step-up converter(2ch), step-down converter(4ch), ,inverting (1ch), with 31 step brightness controller for step-up converter(1ch). ●5channels contain transistor for synchronous rectifying action mode. ●2channels contain FETs for the step-up converter. ●All channels contain internal compensation. ●It is possible separately control except CH1 and CH3. ●Operating frequency 1.2MHz(CH1～5), 600kHz(CH6～8). ●Contains output interception circuit when over load. ●2 channels have high side switches with soft start function. ●Thermally enhanced UQFN044V6060 package(6mm x 6mm, 0.4mm pitch). ○Absolute maximum ratings (Ta=25℃) Parameter P o w e r S u p p l y P o w e r O u t p I n p u t u P o w e r t J u n c t i o n Limit VBAT －0.3～7 V VHx1～5 －0.3～7 V V o l t a g e u r r e n t Unit HS78H －0.3～7 V VLx7,8 －0.3～22 V IomaxLx1 ±2.5 A IomaxHx1 ±1.5 A IomaxHx2,5 +1.0 A IomaxHx3,4 +0.8 A IomaxHS78 +1.2 A IomaxLx7,8 ±1.0 A Pd 0.54 (*1) W ℃ D i s s i p a t i o n O p e r a t i n g S t o r a g e C Symbol V o l t a g e T e m p e r a t u r e Topr －25～+85 T e m p e r a t u r e Tstg －55～+150 ℃ T e m p a r e t u r e Tjmax +150 ℃ (*1) Without external heat sink, the power dissipation reduces by 4.32mW/℃ over 25℃ ○Recommended operating conditions Parameter Power Supply Voltage VREF Pin Connecting Capacitor VREGA Pin Connecting Capacitor Symbol VBAT ○CH8 recommended operating conditions MIN Limit TYP MAX 1.5 - 5.5 Limit Unit Parameter Symbo V CVREF 0.47 1.0 4.7 μF CVREGA 0.47 1.0 4.7 μF Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority. REV. A Fixed H when determine brightness Fixed L when OFF Fixed H when setting brightness Fixed L when setting brightness Fixed H when EN start-up Fixed L before setting brightness Brightness setting time When start-up T(ON) T(OFF) T(H) T(L) T(EN) T(CLR) T(SET) Unit MIN TYP MAX 265X1/fosc 256X1/fosc 500 500 4X1/fosc 7X1/fosc - - 10000 10000 255X1/fosc 2048X1/fosc S S nS nS S S S 2/4 ○Electrical characteristics （Ta=25℃, VCCOUT=5.0V, VBAT=3V, STB13～7=3V,UPIC8=2.5V） Parameter Symbol MIN Limit TYP MAX 2.4 2.5 2.6 Unit Parameter Conditions VREGA V Io=5mA VREGA Monitor CH1 Highside SW ON Resistance CH1 Lowside SW ON Resistance CH2 Highside SW ON Resistance CH2 Lowside SW ON Resistance CH3 Highside SW ON Resistance CH3 Lowside SW ON Resistance CH4 Highside SW ON Resistance CH4 Lowside SW ON Resistance CH5 Highside SW ON Resistance CH5 Lowside SW ON Resistance CH6 Driver Output voltage H CH6 Driver Output voltage L CH7,8 NMOS SW ON Resistance CH7,8 Load SW ON Resistance 【Prevention Circuit of Miss Operation by Low voltage Input】 Threshold Vstd1 Voltage Hysteresis ⊿Vstd1 Width1 Threshold Vstd2 Voltage 2 Hysteresis ⊿Vstd1 Width 【Short Circuit Protection】 SCP detect Tscp time Timer start threshold Vtcinv voltage 【Start-up Circuit】 Frequency Fstart Start-up VBAT Vst1 Voltage Start-up CH Soft Start Tss1 Time - 2.0 2.3 V 50 100 200 mV - 2.4 2.5 V 100 200 300 mV 20 25 30 ms 0.38 0. 48 0.58 V 150 300 600 VCCOUT Monitor INV Monitor CH3～5 kHz 1.5 - - V 1.8 3.0 5.3 msec 【Oscillator】 Frequency CH1～5 Frequency CH6～8 Max duty 2,3,4,5 （step-down） Max duty 1 （step-up） Max duty 6,7,8 fosc1 1.0 1.2 1.4 MHz fosc2 0.5 0.6 0.7 MHz Dmax1d - - 100 % Dmax1u 86 92 96 % Dmax2 86 92 96 % STB Control voltage (※1) - 120 270 mΩ Hx1=5V RON1N - 80 240 mΩ VCCOUT=5.0V RON21p - 250 400 mΩ Hx2=3V RON21N - 250 400 mΩ VCCOUT=5.0V RON3p - 250 400 mΩ Hx3=3V , VCCOUT=5V RON3N - 250 400 mΩ VCCOUT=5.0V RON4p - 250 400 mΩ Hx4=3V, VCCOUT=5V RON4N - 250 400 mΩ VCCOUT=5.0V RON5p - 250 400 mΩ Hx5=3V Conditions - 150 300 mΩ VCCOUT=5.0V Vout6H VCCOUT -1.5 VCCOUT -1.0 - V IOUT6=50mA ,NON6=0.2V Vout6L - 0.5 1.0 V IOUT6=-50mA NON6=-0.2V RON7,8 N - 500 800 mΩ VCCOUT=5.0V RON7,8p - 200 350 mΩ HS7,8H=3V , VCCOUT=5.0V Active VSTBH 1 1.5 - 5.5 V Not Active VSTBL1 -0.3 - 0.3 V RSTB1 250 400 700 kΩ VUPIH 2.1 - 4.00 V 【UPIC8】 UPIC8 Control voltage IINV - 0 50 nA INV1～8, NON6=3.0V VINV1 0.79 0.80 0.81 V CH1～5 VINV2 0.99 1.00 1.01 V CH7,8V VINV3 370 400 430 mV VOUT6 -6.09 -6.00 -5.91 V DVLi - 4.0 12.5 mV VCCOUT=2.8～5.5V Ios 0.2 1.0 - mA Vref=0V Tss2,5 3.4 4.4 5.4 msec Tss3,4 1.2 2.2 3.2 msec Tss6 3.4 4.4 5.4 msec Tss7,8 4.4 5.4 6.6 msec VUPIL 0 - 0.40 V RUPIC1 30 50 80 kΩ ISTB1 - - 5 μA ISTB2 - - 5 μA Step down ISTB3 - - 5 μA Step up ISTB4 - - 5 μA IST - 150 450 μA VBAT=1.5V Icc1 - 45 150 μA VBAT=3.0V Icc2 - 5.0 9.7 mA INV1～8=1.2V , NON6=-0.2V 【Circuit Current】 VBAT terminal Hｘ terminal Stand-by Current Lx terminal HS7,8H terminal Circuit Current when start-up （VBAT current when voltage supplied for the terminal） Circuit Current 1 （VBAT current when voltage supplied for the terminal） Circuit Current 2 （VCCOUT current when voltage supplied for the terminal） CH8I NON5 12kΩ, 72kΩ (※2) Active Not Active Pull down Resistance 【Soft Start】 CH2,5 Soft Start Time CH3,4 Soft Start Time CH6 Soft Start Time CH7,8 Soft Start Time RON1p Unit RON5N Pull down Resistance 【For Inverting Base Bias Voltage Vref】 CH6 Output Voltage Line Regulation Output Current When Shorted MAX 【STB13～7】 【Error Amp】 Input Bias current INV threshold 1 INV threshold 2 INV threshold 3 (max) Limit TYP 【Output Driver】 【Internal Regulator VREGA】 Output Voltage MIN Symbol (※1)The protective circuit start working when circuit is operated by 100% duty. So it is possible to use only for transition time shorter than charge time for SCP. (※2)Recommend resistor value over 20kΩ between VREF to NON6, because VREF current is under 100uA. ◎This product is not designed for normal operation with in a radioactive environment REV. A 3/4 ○Block Diagram ○Pin Description 端子名 機 VBAT 能 Input for battery voltage Power Supply Input Terminal voltage (Input CH1 output voltage) Ground terminal Ground terminal for internal FET VREGA Output CH6 base bias voltage Terminal for connecting gate of CH6 PMOS Input terminal for synchronous High side switch, Power supply for Pch Driver Terminal for connecting inductors Power supply for internal load switch Output terminal for internal load switch Error AMP inverted input Error AMP non-inverted input Error AMP inverted input ON/OFF switch H: operating over 1.5V CH8 ON/OFF switch、 for CH8 brightness control VCCOUT GND PGND13, 24, 5, 678 VREGA VREF6 OUT6 Hx1,2,3,4,5 Lx1,,2,3,4,5,7,8 HS78H HS7L,HS8L INV1,2,3,4,5,7,8 NON6 INV8I STB13,2,4,5,6,7 UPIC8 ○Pin Assignment 36 37 38 39 40 41 42 43 44 27 B D ９ ７ ５ ７ M W LOT No. Fig.3 REV. A 25 24 BD9757MWV STB7 STB6 2 3 4 5 6 7 Fig.2 ○Package 26 23 INV3 28 LX7 OUT6 UPIC8 1 Fig.1 29 INV5 VCCOUT VREGA GND INV2 INV4 INV8 HS7L HS78H HS8L LX8 PGND678 30 8 9 10 INV1 22 VBAT HX1 HX1 LX1 21 20 19 18 LX1 PGND13 17 PGND13 LX3 HX3 STB13 15 HX2 LX2 PGND24 LX4 HX4 STB2 STB4 35 31 STB5 PGND5 LX5 HX5 34 32 INV7 NON6 VREF6 INV8I 33 11 16 14 13 12 4/4 ○Operation Notes １.) Absolute maximum ratings This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented when operating conditions beyond the absolute maximum ratings anticipated. ２.) GND potential Make sure GND is connected at lowest potential. All pins except NON6, must not have voltage below GND. Also, NON6 pin must not have voltage below - 0.3V on start up. ３.) Setting of heat Make sure that power dissipation does not exceed maximum ratings. ４.) Pin short and mistake fitting Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output to GND condition will not happen because this may damage the IC. ５.) Actions in strong magnetic field Exposing the IC within a strong magnetic field area may cause malfunction. ６.) Mutual impedance Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and capacitor network to keep the ripple voltage minimum. ７.) Voltage of STB pin The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V. The region between 0.3V and 1.5V is not recommended and may cause improper operation. The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF. ８.) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. ９.)Rush current at the time of power supply injection. An IC which has plural power supplies, or CMOS IC could have momentary rush current at the time of power supply injection. Please take care about power supply coupling capacity and width of power Supply and GND pattern wiring. １０.)IC Terminal Input This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed. For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.9): ○When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as a parasitic diode. ○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other elements in the proximity of the aforementioned parasitic diode. Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements Induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to the input terminal. Transistor (NPN) B （Terminal B）C Resistor （Terminal A） E GND （TerminalＡ） P P＋ N N P-board P P＋ P＋ N N Ｎ Parasitic element ～ ～ N P＋ Parasitic element N P-board Parasitic element GND Fig – 9 Simplified structure of a Bipolar IC REV. A GND Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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