LM3528 High Efficiency, Multi Display LED Driver with 128 Exponential Dimming Steps and Integrated OLED Power Supply in a 1.2mm × 1.6mm µSMD Package General Description Features The LM3528 current mode boost converter offers two separate outputs. The first output (MAIN) is a constant current sink for driving series white LED’s. The second output (SUB/FB) is configurable as a constant current sink for series white LED bias, or as a feedback pin to set a constant output voltage for powering OLED panels. As a dual output white LED bias supply, the LM3528 adaptively regulates the supply voltage of the LED strings to maximize efficiency and insure the current sinks remain in regulation. The maximum current per output is set via a single external low power resistor. An I2C compatible interface allows for independent adjustment of the LED current in either output from 0 to max current in 128 exponential steps. When configured as a white LED + OLED bias supply the LM3528 can independently and simultaneously drive a string of up to 6 white LED’s and deliver a constant output voltage of up to 21V for OLED panels. Output over-voltage protection shuts down the device if VOUT rises above 22V allowing for the use of small sized low voltage output capacitors. Other features include a dedicated general purpose I/O (GPIO) and a multi-function pin (HWEN/ PGEN/GPIO) which can be configured as a 32 bit pattern generator, a hardware enable input, or as a GPIO. When configured as a pattern generator, an arbitrary pattern is programmed via the I2C compatible interface and output at HWEN/PGEN/GPIO for indicator LED flashing or for external logic control. The LM3528 is offered in a tiny 12-bump µSMD package and operates over the -40°C to +85°C temperature range. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 128 Exponential Dimming Steps Programmable Auto-Dimming Function Up to 90% Efficient Low Profile 12 Bump µ-SMD Package (1.2mm x 1.6mm x 0.6mm) Integrated OLED Display Power Supply and LED Driver Programmable Pattern Generator Output for LED Indicator Function Drives up to 12 LED’s at 20mA Drives up to 5 LED’s at 20mA and delivers 18V at 40mA 1% Accurate Current Matching Between Strings Internal Soft-Start Limits Inrush Current True Shutdown Isolation for LED’s Wide 2.5V to 5.5V Input Voltage Range 22V Over-Voltage Protection 1.25MHz Fixed Frequency Operation Dedicated Programmable General Purpose I/O Active Low Hardware Reset Applications ■ ■ ■ ■ Dual Display LCD Backlighting for Portable Applications Large Format LCD Backlighting OLED Panel Power Supply Display Backlighting with Indicator Light 30020563 Typical PCB Layout 30020501 Typical Application Circuit © 2008 National Semiconductor Corporation 300205 www.national.com LM3528 High Efficiency, Multi Display LED Driver with 128 Exponential Dimming Steps and Integrated OLED Power Supply in micro SMD August 3, 2008 LM3528 Connection Diagram Top View 30020502 12-Bump (1.215mm × 1.615mm × 0.6mm) TMD12AAA Ordering Information Order Number Package Type NSC Package Drawing Top Mark LM3528TME 12-Bump µSMD TMD12AAA SE 250 units, Tape-and-Reel, No Lead Supplied As LM3528TMX 12-Bump µSMD TMD12AAA SE 3000 units, Tape-and-Reel, No Lead Pin Descriptions/Functions Pin Name A1 OVP Over-Voltage Protection Sense Connection. Connect OVP to the positive terminal of the output capacitor. A2 MAIN Main Current Sink Input. A3 SUB/FB Secondary Current Sink Input or 1.21V Feedback Connection for Constant Voltage Output. B1 GPIO1 Programmable General Purpose I/O. B2 SCL Serial Clock Input B3 SET LED Current Setting Connection. Connect a resistor from SET to GND to set the maximum LED current into MAIN or SUB/FB (when in LED mode), where ILED_MAX = 192×1.244V/RSET. C1 HWEN/PGEN/ GPIO Active High Hardware Enable Input. Programmable Pattern Generator Output, and Programmable General Purpose I/O. C2 SDA C3 IN D1 VIO Logic Voltage Level Input D2 SW Drain Connection for Internal NMOS Switch D3 GND www.national.com Function Serial Data Input/Output Input Voltage Connection. Connect IN to the input supply, and bypass to GND with a 1µF ceramic capacitor. Ground 2 Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN VSW, VOVP, VSUB/FB, VMAIN Junction Temperature Range (TJ)(Note 4) Ambient Temperature Range (TA)(Note 5) VIN VSW, VOVP, VSUB/FB, VMAIN VSCL, VSDA, VRESET\GPIO, VIO , VSET Continuous Power Dissipation Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Soldering, 10s)(Note 3) ESD Rating(Note 10) Human Body Model −0.3V to 6V −0.3V to 25V −0.3V to 23V −0.3V to 6V Internally Limited +150°C -65°C to +150°C (Notes 1, 2) 2.5V to 5.5V 0V to 23V 0V to 21V -40°C to +110°C -40°C to +85°C Thermal Properties Junction to Ambient Thermal Resistance (θJA)(Note 6) 68°C/W ESD Caution Notice +300°C National Semiconductor recommends that all integrated circuits be handled with appropriate ESD precautions. Failure to observe proper ESD handling techniques can result in damage to the device. 2.5kV Electrical Characteristics Specifications in standard type face are for TA = 25°C and those in boldface type apply over the Operating Temperature Range of TA = −40°C to +85°C. Unless otherwise specified VIN = 3.6V, VIO = 1.8V, VRESET/GPIO = VIN, VSUB/FB = VMAIN = 0.5V, R = 12.0kΩ, OLED = ‘0’, ENM = ENS = ‘1’, BSUB = BMAIN = Full Scale.(Notes 2, 7) SET Symbol ILED Parameter Conditions Min Typ Max 20 22 Units Output Current Regulation MAIN or SUB/FB Enabled UNI = ‘0’, or ‘1’, 2.5V < VIN < 5.5V Maximum Current Per Current Sink RSET = 8.0kΩ ILED-MATCH IMAIN to ISUB/FB Current Matching UNI = ‘1’, 2.5V < VIN < 5.5V (Note 11) 0.15 VSET SET Pin Voltage 3.0V < VIN < 5V 1.244 ILED/ISET ILED Current to ISET Current Ratio 192 VREG_CS Regulated Current Sink Headroom Voltage 500 VREG_OLED VSUB/FB Regulation Voltage 2.5V < VIN < 5.5V, OLED = ‘1’ in OLED Mode VHR Current Sink Minimum Headroom Voltage ILED = 95% of nominal 300 mV RDSON NMOS Switch On Resistance ISW = 100mA 0.43 Ω ICL NMOS Switch Current Limit 2.5V < VIN < 5.5V 645 770 900 VOVP Output Over-Voltage Protection ON Threshold, 2.5V < VIN < 5.5V 20.6 22 23 OFF Threshold, 2.7V < VIN < 5.5V 19.25 20.6 21.5 1.0 1.27 1.4 18.5 mA 30 1.170 1.21 1 % V mV 1.237 V mA V fSW Switching Frequency DMAX Maximum Duty Cycle 90 % DMIN Minimum Duty Cycle 10 % 3 MHz www.national.com LM3528 Absolute Maximum Ratings (Notes 1, 2) LM3528 Symbol IQ Parameter Quiescent Current, Device Not Switching ISHDN Shutdown Current Conditions Min Typ Max Units VMAIN and VSUB/FB > VREG_CS, BSUB = BMAIN = 0x00, 2.5V < VIN < 5.5V 350 390 VSUB/FB > VREG_OLED, OLED=’1’, ENM=ENS=’0’, RSET Open, 2.5V < VIN < 5.5V 250 260 ENM = ENS = OLED = '0', 2.5V < VIN < 5.5V 1.8 3 µA 0.5 V µA HWEN/PGEN/GPIO, GPIO1 Pin Voltage Specifications VIL Input Logic Low 2.5V < VIN <5.5V, MODE bit =0 VIH Input Logic High 2.5V < VIN < 5.5V, MODE bit =0 VOL Output Logic Low ILOAD=3mA, MODE bit = 1 I2C Compatible Voltage Specifications (SCL, SDA, VIO) VIO Serial Bus Voltage Level 2.5V < VIN < 5.5V (Note 9) VIL Input Logic Low 2.5V < VIN < 5.5V VIH Input Logic High 2.5V < VIN < 5.5V VOL Output Logic Low ILOAD = 3mA V 1.1 1.7 400 mV VIN V 0.36×VIO V 0.7×VIO V 400 mV I2C Compatible Timing Specifications (SCL, SDA, VIO, see Figure 1) (Notes 8, 9) t1 SCL Clock Period 2.5 µs t2 Data In Setup Time to SCL High 100 ns t3 Data Out Stable After SCL Low 0 ns SDA Low Setup Time to SCL Low (Start) 100 ns SDA High Hold Time After SCL High (Stop) 100 ns t4 t5 Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1112: Micro SMD Wafer LEvel Chip Scale Package (AN-1112). Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=+150°C (typ.) and disengages at TJ=+140°C (typ.). Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +105°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 6: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 114.3mm x 76.2mm x 1.6mm. The ground plane on the board is 113mm x 75mm. Thickness of copper layers are 71.5µm/35µm/35µm/71.5µm (2oz/1oz/1oz/2oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. For more information on these topics, please refer to National Semiconductor Application Note 1112, and JEDEC Standard JESD51-7. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical (Typ) numbers are not guaranteed, but represent the most likely norm. Note 8: SCL and SDA must be glitch-free in order for proper brightness control to be realized. Note 9: SCL and SDA signals are referenced to VIO and GND for minimum VIO voltage testing. VIO limits indicate the minimum voltage at VIO at which the part is operational. Note 10: The human body model is a 100pF capacitor discharged through 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7). Note 11: The matching specification between MAIN and SUB is calculated as 100 × ((IMAIN or ISUB) - IAVE) / IAVE. This simplifies out to be 100 × (IMAIN - ISUB)/(IMAIN + ISUB). www.national.com 4 LM3528 Timing Diagram 30020503 FIGURE 1. I2C Timing 5 www.national.com LM3528 Typical Performance Characteristics VIN = 3.6V, LEDs are Nichia (NSSW008C), COUT = 1µF (LED Mode), COUT = 2.2µF (OLED Mode), CIN = 1µF, L = TDK VLF4012AT-100MR79, (RL = 0.3Ω), RSET = 12.1kΩ, UNI = '1', ILED = ISUB + IMAIN, TA = +25°C unless otherwise specified. 2x6 LED Efficiency vs ILED (2 Strings of 6LEDs) 2x5 LED Efficiency vs ILED (2 Strings of 5LEDs) 30020508 30020509 2x4 LED Efficiency vs ILED (2 Strings of 4LEDs) 2x3 LED Efficiency vs ILED (2 Strings of 3LEDs) 30020510 www.national.com 30020511 6 LED Efficiency vs VIN (L = TDK VLF3012AT-100MR92, RL = 0.36Ω, ISUB + IMAIN = 40mA) 30020512 30020513 18V OLED Efficiency vs IOUT 12V OLED Efficiency vs IOUT 30020514 30020515 7 www.national.com LM3528 2x2 LED Efficiency vs ILED (2 Strings of 2LEDs) LM3528 LED Line Regulation (UNI = '0') OLED Line Regulation IOLED = 60mA 30020516 30020517 OLED Line Regulation IOLED = 60mA OLED Load Regulation VOLED = 18V 30020518 www.national.com 30020519 8 LM3528 OLED Load Regulation VOLED = 12V Peak Current Limit vs. VIN 30020521 30020520 Over Voltage Limit vs. VIN Switch On-Resistance vs. VIN 30020522 30020523 9 www.national.com LM3528 Switching Frequency vs. VIN Maximum Duty Cycle vs. VIN 30020524 30020525 Shutdown Current vs. VIN Switching Supply Current vs. VIN 30020526 www.national.com 30020527 10 LM3528 LED Current Accuracy vs CODE (RSET = 12kΩ±0.05%) LED Current Matching vs. CODE (Note 11) (UNI = '1', RSET = 12kΩ, TA = -40°C to +85°C) 30020529 30020528 LED Current vs CODE (IMAIN, ISUB, IIDEAL, RSET = 12kΩ±0.05%) ILED vs Current Source Headroom Voltage (VIN = 3V, UNI = '0') 30020531 30020530 11 www.national.com LM3528 Start-Up Waveform (LED Mode) (2 × 5 LEDs, 20mA per string) Start-Up Waveform (OLED Mode) (VOUT = 18V, IOUT = 60mA) 30020556 Channel 2: SDA (5V/div) Channel 1: VOUT (10V/div) Channel 3: ILED (20mA/div) Channel 4: IIN (200mA/div) Time Base: 400µs/div 30020555 Channel 1: SDA (5V/div) Channel 2: VOUT (10V/div) Channel 3: IOUT (20mA/div) Channel 4: IIN (200mA/div) Time Base: 400µs/div Load Step (OLED Mode) (VOUT = 18V, COUT = 2.2µF) Line Step (LED Mode) (2 × 5 LEDs, 20mA per String, COUT = 1µF, VIN from 3V to 3.6V) 30020552 30020553 Channel 2: VOUT (AC Coupled, 500mV/div) Channel 3: IOUT (20mA/div) Time Base: 200µs/div www.national.com Channel 3: ISUB (5mA/div) Channel 4: IMAIN (5mA/div) Channel 2: VIN (AC Coupled, 500mV/div) Time Base: 100µs/div 12 LM3528 Line Step (OLED Mode) (VOUT = 18V, COUT = 2.2µF, VIN from 3V to 3.6V) HWEN Functionality 30020557 Channel 2: VOUT (AC Coupled, 100mV/div) Channel 3: VIN (AC Coupled, 500mV/div) Time Base: 200µs/div 30020551 Channel 4: ISUB (20mA/div) Channel 3: IMAIN (20mA/div) Channel 2: HWEN (5V/div) Time Base: 200ns/div GPIO1 Functionality (GPIO1 Configured as OUTPUT, fSCL = 360kHz) Ramp Rate Functionality (RMP1, RMP0 = '11') 30020554 30020558 Channel 2: GPIO (2V/div) Channel 1: SCL (5V/div) Channel 1:SDA (5V/div) Time Base: 40µs/div Channel 1:SDA (2V/div) Channel 4: ISUB (10mA/div) Channel 3: ISUB (10mA/div) Time Base: 400ms/div 13 www.national.com LM3528 Block Diagram 30020533 FIGURE 2. LM3528 Block Diagram ramp while the output capacitor supplies power to the white LED’s and/or OLED panel. The error signal at the output of the error amplifier is compared against the sensed inductor current. When the sensed inductor current equals the error signal, or when the maximum duty cycle is reached, the NMOS switch turns off causing the external Schottky diode to pick up the inductor current. This allows the inductor current to ramp down causing its stored energy to charge the output capacitor and supply power to the load. At the end of the clock period the PWM controller is again set and the process repeats itself. Operation Description The LM3528 Current Mode PWM boost converter operates from a 2.7V to 5.5V input and provides two regulated outputs for White LED and OLED display biasing. The first output, MAIN, provides a constant current of up to 30mA to bias up to 6 series white LED’s. The second output, SUB/FB, can be configured as a current source for up to 6 series white LED’s at at up to 30mA, or as a feedback voltage pin to regulate a constant output voltage of up to 21V. When both MAIN and SUB/FB are configured for white LED bias the current for each LED string is controlled independently or in unison via an I2C compatible interface. When MAIN is configured for white LED bias and SUB/FB is configured as a feedback voltage pin, the current into MAIN is controlled via the I2C compatible interface and SUB/FB becomes the middle tap of a resistive divider used to regulate the output voltage of the boost converter. The core of the LM3528 is a Current Mode Boost converter. Operation is as follows. At the start of each switching cycle the internal oscillator sets the PWM converter. The converter turns the NMOS switch on, allowing the inductor current to www.national.com ADAPTIVE REGULATION When biasing dual white led strings (White LED mode) the LM3528 maximizes efficiency by adaptively regulating the output voltage. In this configuration the 500mV reference is connected to the non-inverting input of the error amplifier via mux S2 (see Figure 2, Block Diagram). The lowest of either VMAIN or VSUB/FB is then applied to the inverting input of the error amplifier via mux S1. This ensures that VMAIN and VSUB/ 14 UNISON/NON-UNISON MODE Within White LED mode there are two separate modes of operation, Unison and Non-Unison. Non-Unison mode provides for independent current regulation, while Unison mode gives up independent regulation for more accurate matching between LED strings. When in Non-Unison mode the LED currents IMAIN and ISUB/FB are independently controlled via registers BMAIN and BSUB respectively (see Brightness Registers BMAIN and BSUB section). When in Unison mode BSUB is disabled and both IMAIN and ISUB/FB are controlled via BMAIN only. OUTPUT CURRENT ACCURACY AND CURRENT MATCHING The LM3528 provides both precise current accuracy (% error from ideal value) and accurate current matching between the MAIN and SUB/FB current sinks. Two modes of operation affect the current matching between IMAIN and ISUB/FB. The first mode (Non-Unison mode) is set by writing a 0 to bit 2 of the General Purpose register (UNI bit). Non-Unison mode allows for independent programming of IMAIN and ISUB/FB via registers BMAIN and BSUB respectively. In this mode typical matching between current sinks is 1%. Writing a 1 to UNI configures the device for Unison mode. In Unison mode, BSUB is disabled and IMAIN and ISUB/FB are both controlled via register BMAIN. In this mode typical matching is 0.15%. START-UP The LM3528 features an internal soft-start, preventing large inrush currents during start-up that can cause excessive voltage ripple on the input. For the typical application circuits when the device is brought out of shutdown the average input current ramps from zero to 450mA in approximately 1.2ms. See Start Up Plots in the Typical Performance Characteristics. LIGHT LOAD OPERATION The LM3528 boost converter operates in three modes; continuous conduction, discontinuous conduction, and skip mode operation. Under heavy loads when the inductor current does not reach zero before the end of the switching period the device switches at a constant frequency. As the output current decreases and the inductor current reaches zero before the end of the switching cycle, the device operates in discontinuous conduction. At very light loads the LM3528 will enter skip mode operation causing the switching period to lengthen and the device to only switch as required to maintain regulation at the output. OLED MODE When the LM3528 is configured for a single White LED bias + OLED display bias (OLED mode), the non-inverting input of the error amplifier is connected to the internal 1.21V reference via MUX S2. MUX S1 switches SUB/FB to the inverting input of the error amplifier while disconnecting the internal current sink at SUB/FB. The voltage at MAIN is not regulated in OLED mode so when the application requires white LED + OLED panel biasing, ensure that at least 300mV of headroom is maintained at MAIN to guarantee proper regulation of IMAIN. (see the Typical Performance Characteristics for a plot of ILED vs Current Source Headroom Voltage) HARDWARE ENABLE/PATTERN GENERATOR/ GENERAL PURPOSE I/O (HWEN/PGEN/GPIO) HWEN/PGEN/GPIO can be configured for three different modes of operation; Hardware Enable, Pattern Generation, and General Purpose I/O. Register HPG at address 0x80 controls the functionality of this pin (see Table 6). PEAK CURRENT LIMIT The LM3528’s boost converter has a peak current limit for the internal power switch of 770mA typical (650mA minimum). When the peak switch current reaches the current limit the duty cycle is terminated resulting in a limit on the maximum output current and thus the maximum output power the LM3528 can deliver. Calculate the maximum LED current as a function of VIN, VOUT, L and IPEAK as: HARDWARE ENABLE (HWEN) On initial power-up HWEN/PGEN/GPIO defaults to the Hardware Enable (HWEN) state. In this mode HWEN/PGEN/GPIO is an active high open-drain input enable to the device. When in HWEN mode HWEN/PGEN/GPIO must be pulled up to at least 0.7 × VIO to enable the device. In HWEN mode pulling HWEN/PGEN/GPIO below 0.36 × VIO will shutdown the LM3528, resetting all registers, and forcing MAIN, SUB/FB, and SW high impedance. Bit 0 of the HPG register controls the HWEN function. Writing a ‘0’ to this bit enables the HWEN mode. Writing a ‘1’ to this bit disables the HWEN mode and allows selection between the other two modes. PATTERN GENERATOR (PGEN) With bit 0 of the HPG register set to 1, HWEN/PGEN/GPIO can be programmed as an open drain Pattern Generator Output (PGEN). In PGEN mode a 32 bit pattern is output at HWEN/PGEN/GPIO. This pattern can be programmed to repeat itself at 4 different frequencies and 6 different duty cycles. The arbitrary pattern is programmed into four 8 bit registers; PGEN0 (address 0x90), PGEN1 (address 0x91), PGEN2 (address 0x92), and PGEN3 (address 0x93) (see ƒSW = 1.27MHz. Typical values for efficiency and IPEAK can be found in the efficiency and IPEAK curves in the Typical Performance Characteristics. OVER VOLTAGE PROTECTION The LM3528's output voltage (VOUT) is limited on the high end by the Output Over-Voltage Protection Threshold (VOVP) of 21.2V (min). In White LED mode during output open circuit 15 www.national.com LM3528 conditions the output voltage will rise to the over voltage protection threshold. When this happens the controller will stop switching causing VOUT to droop. When the output voltage drops below 19.7V (min) the device will resume switching. If the device remains in an over voltage condition the LM3528 will repeat the cycle causing the output to cycle between the high and low OVP thresholds. See waveform for OVP condition in the Typical Performance Characteristics. are at least 500mV, thus providing enough voltage headroom at the input to the current sinks for proper current regulation. In the instance when there are unequal numbers of LEDs or unequal currents from string to string, the string with the highest voltage will be the regulation point. FB LM3528 Figures 12 - 15). Figure 16 details an example of a 32 bit pattern at a specific programmed duty cycle and frequency. A ‘1’ written to the PGEN_ registers forces HWEN/PGEN/GPIO low. A ‘0’ causes HWEN/PGEN/GPIO to go open drain. Bits <5:3> in the HPG register have three functions; GPIO enable, duty cycle select, and pattern latch. Any combination of these bits other than ‘000’ or ’111’ puts HWEN/PGEN/GPIO into PGEN mode at the specified duty cycle shown in Table 6. Writing a ‘111’ to bits <5:3> latches the 32 bit pattern programmed into the 4 pattern generator registers PGEN0, PGEN1, PGEN2, PGEN3 into the internal shift register. When bits <5:3> = ‘000’ the PGEN mode is off and HWEN/PGEN/ GPIO is configured as a GPIO. Bits <7:6> of the HPG register control the pattern frequency. See Table 6 for the detailed breakdown of each available frequency. Figure 16 details the pattern programming and figure 17 shows the pattern output at HWEN/PGEN/GPIO. of the HPG register and their power-on-reset values. Note that the logic output levels for the GPIO function of this pin are inverted compared to the PGEN functions. For example, a 1 written to the PGEN registers cause the HWEN/PGEN/GPIO pin to pull low while a 1 written to the bit 2 of the HPG register causes the pin to go open drain. GENERAL PURPOSE I/O (GPIO0) The GPIO pin is a dedicated General Purpose I/O (open drain) and is controlled via the GPIO register at address 0x81. Bit 1 holds the logic data while bit 0 controls the logic direction (Input or Output). Bits <7:2> are un-used and will always read back as logic '1'. With bit 0 set to ‘0’ GPIO is configured as an output. In this mode a ‘0’ written to bit 1 forces GPIO to a logic low. Likewise, a ‘1’ written to bit 1 will force GPIO to logic high. When bit 0 is set to ‘1’ GPIO is configured as a logic input. In this mode when GPIO is externally pulled low a ‘0’ is written to bit 1 of the GPIO register. Likewise, when GPIO is externally pulled high a ‘1’ is written to bit 2 of the HPG register. Table 7 and Figure 11 detail the bit functions and power-onreset values of GPIO. During an initial GPIO write two I2C sequences (Slave I.D, Register Address, Register Data) are required to change the state of the GPIO pin. The first write configures the GPIO pin as an output. The second write will change the state of the GPIO output to the desired logic '1' or '0'. GENERAL PURPOSE I/O (GPIO1) With bits <5:3> and bit 0 of the HPG register all set to ‘0’ HWEN/PGEN/GPIO functions as an open drain General Purpose I/O. In this mode, bit 1 of the HPG register controls the logic direction (Input or Output) and bit 2 holds the logic data. With bit 1 set to ‘0’ HWEN/PGEN/GPIO is configured as an output. In this mode a ‘0’ written to bit 2 forces HWEN/PGEN/ GPIO to logic low. Likewise, a ‘1’ written to bit 2 will force HWEN/PGEN/GPIO open drain. When bit 1 is set to ‘1’ HWEN/PGEN/GPIO is configured as a logic input. In this mode when HWEN/PGEN/GPIO is externally pulled low a ‘0’ is written to bit 2 of the HPG register. Likewise, when HWEN/ PGEN/GPIO is externally pulled high a ‘1’ is written to bit 2 of the HPG register. Table 6 and Figure 10 detail the bit functions www.national.com THERMAL SHUTDOWN The LM3528 offers a thermal shutdown protection. When the die temperature reaches +140°C the device will shutdown and not turn on again until the die temperature falls below +120°C. 16 30020537 FIGURE 3. Start and Stop Sequences WRITE and R/W = 1 indicates a READ. The second byte following the chip address selects the register address to which the data will be written. The third byte contains the data for the selected register. I2C COMPATIBLE ADDRESS The chip address for the LM3528 is 0110110 (36h). After the START condition, the I2C master sends the 7-bit chip address followed by a read or write bit (R/W). R/W= 0 indicates a 30020538 FIGURE 4. Chip Address pulse. The LM3528 pulls down SDA during the 9th clock pulse, signifying an acknowledge. An acknowledge is generated after each byte has been received. Figure 5 is an example of a write sequence to the General Purpose register of the LM3528. TRANSFERRING DATA Every byte on the SDA line must be eight bits long, with the most significant bit (MSB) transferred first. Each byte of data must be followed by an acknowledge bit (ACK). The acknowledge related clock pulse (9th clock pulse) is generated by the master. The master releases SDA (HIGH) during the 9th clock 30020539 FIGURE 5. Write Sequence to the LM3528 17 www.national.com LM3528 START condition and free after a STOP condition. During data transmission, the I2C master can generate repeated START conditions. A START and a repeated START conditions are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. I2C COMPATIBLE INTERFACE The LM3528 is controlled via an I2C compatible interface. START and STOP conditions classify the beginning and the end of the I2C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP conditions. The I2C bus is considered busy after a LM3528 REGISTER DESCRIPTIONS There are 4, 8 bit registers within the LM3528 as detailed in Table 1. TABLE 1. LM3528 Register Descriptions Hex Address Power -On-Value General Purpose (GP) Register Name 0x10 0xC0 Brightness Main (BMAIN) 0xA0 0xE0 Brightness Sub (BSUB) 0xB0 0xE0 HWEN/PGEN/GPIO Control (HPG) 0x80 0XF8 General Purpose I/O Control (GPIO) 0x81 0xFC Pattern Register 0 (PGEN0) 0x90 0x00 Pattern Register 1 (PGEN1) 0x91 0x00 Pattern Register 2 (PGEN2) 0x92 0x00 Pattern Register 3 (PGEN3) 0x93 0x00 Description), and selects between White LED and OLED mode. Figure 6 and Table 2 describes each bit available within the General Purpose Register. Table 3 summarizes the output state of the LM3528 for the different combinations of General Purpose register settings. GENERAL PURPOSE REGISTER (GP) The General Purpose register has four functions. It controls the on/off state of MAIN and SUB/FB, it selects between Unison or Non-Unison mode, provides for control over the rate of change of the LED current (see Brightness Rate of Change 30020540 FIGURE 6. General Purpose Register Description TABLE 2. General Purpose Register Bit Function Bit Name 0 ENM Enable MAIN. Writing a 1 to this bit enables the main current sink (MAIN). Writing a 0 to this bit disables the main current sink and forces MAIN high impedance. Function Power-On-Value 0 1 ENS Enable SUB/FB. Writing a 1 to this bit enables the secondary current sink (SUB/ FB). Writing a 0 to this bit disables the secondary current sink and forces SUB/ FB high impedance. 0 2 UNI Unison Mode Select. Writing a 1 to this bit disables the BSUB register and causes the contents of BMAIN to set the current in both the MAIN and SUB/ FB current sinks. Writing a 0 to this bit allows the current into MAIN and SUB/ FB to be independently controlled via the BMAIN and BSUB registers respectively. 0 3 RMP0 RMP1 Brightness Rate of Change. Bits RMP0 and RMP1 set the rate of change of the LED current into MAIN and SUB/FB in response to changes in the contents of registers BMAIN and BSUB (see brightness rate of change description). 0 4 5 OLED OLED = 0 places the LM3528 in White LED mode. In this mode both the MAIN and SUB/FB current sinks are active. The boost converter ensures there is at least 500mV at VMAIN and VSUB/FB. 0 0 OLED = 1 places the LM3528 in OLED mode. In this mode the boost converter regulates VSUB/FB to 1.244V. VMAIN is unregulated and must be > 400mV for the MAIN current sink to maintain current regulation. 6 Don't Care These are non-functional read only bits. They will always read back as a 1. 7 www.national.com 18 1 LM3528 TABLE 3. Operational Truth Table UNI OLED ENM ENS Result X 0 0 0 LM3528 Disabled 1 0 1 X MAIN and SUB/FB current sinks enabled. Current levels set by contents of BMAIN. 1 0 0 X MAIN and SUB/FB Disabled 0 0 0 1 SUB/FB current sink enabled. Current level set by BSUB. 0 0 1 0 MAIN current sink enabled. Current level set by BMAIN. 0 0 1 1 MAIN and SUB/FB current sinks enabled. Current levels set by contents of BMAIN and BSUB respectively. X 1 1 X SUB/FB current sink disabled (SUB/FB configured as a feedback pin). MAIN current sink enabled current level set by BMAIN. X 1 0 X SUB/FB current sink disabled (SUB/FB configured as a feedback pin). MAIN current sink disabled. * ENM ,ENS, or OLED high enables analog circuitry. With the UNI bit (General Purpose register) set to 1 (Unison mode), BSUB is disabled and BMAIN sets both IMAIN and ISUB/ FB. This prevents the independent control of IMAIN and ISUB/ FB, however matching between current sinks goes from typically 1%(with UNI = 0) to typically 0.15% (with UNI = 1). Figure 7 and Figure 8 show the register descriptions for the Brightness MAIN and Brightness SUB registers. Table 4 and Figure 9 show IMAIN and/or ISUB/FB vs. brightness data as a percentage of ILED_MAX. BRIGHTNESS REGISTERS (BMAIN and BSUB) With the UNI bit (General Purpose register) set to 0 (NonUnison mode) both brightness registers (BMAIN and BSUB) independently control the LED currents IMAIN and ISUB/FB respectively. BMAIN and BSUB are both 8 bit, but with only the 7 LSB’s controlling the current. The MSB’s is a don’t care. The LED current control is designed to approximate an exponentially increasing response of the LED current vs increasing code in either BMAIN or BSUB (see Figure 9). Program ILED_MAX by connecting a resistor (RSET) from SET to GND, where: 30020542 FIGURE 7. Brightness MAIN Register Description 30020543 FIGURE 8. Brightness SUB Register Description 19 www.national.com LM3528 TABLE 4. ILED vs. Brightness Register Data BMAIN or BSUB Brightness Data % of ILED_MAX BMAIN or BSUB Brightness Data BMAIN or BSUB Brightness Data % of ILED_MAX 0000000 0.000% 0100000 0.803% 1000000 0000001 0.166% 0100001 0.845% 1000001 4.078% 1100000 20.713% 4.290% 1100001 21.792% 0000010 0.175% 0100010 0.889% 0000011 0.184% 0100011 0.935% 1000010 4.514% 1100010 22.928% 1000011 4.749% 1100011 0000100 0.194% 0100100 24.122% 0.984% 1000100 4.996% 1100100 25.379% 0000101 0.204% 0000110 0.214% 0100101 1.035% 1000101 5.257% 1100101 26.701% 0100110 1.089% 1000110 5.531% 1100110 0000111 28.092% 0.226% 0100111 1.146% 1000111 5.819% 1100111 29.556% 0001000 0.237% 0101000 1.205% 1001000 6.122% 1101000 31.096% 0001001 0.250% 0101001 1.268% 1001001 6.441% 1101001 32.716% 0001010 0.263% 0101010 1.334% 1001010 6.776% 1101010 34.420% 0001011 0.276% 0101011 1.404% 1001011 7.129% 1101011 36.213% 0001100 0.291% 0101100 1.477% 1001100 7.501% 1101100 38.100% 0001101 0.306% 0101101 1.554% 1001101 7.892% 1101101 40.085% 0001110 0.322% 0101110 1.635% 1001110 8.303% 1101110 42.173% 0001111 0.339% 0101111 1.720% 1001111 8.735% 1101111 44.371% 0010000 0.356% 0110000 1.809% 1010000 9.191% 1110000 46.682% 0010001 0.375% 0110001 1.904% 1010001 9.669% 1110001 49.114% 0010010 0.394% 0110010 2.003% 1010010 10.173% 1110010 51.673% 0010011 0.415% 0110011 2.107% 1010011 10.703% 1110011 54.365% 0010100 0.436% 0110100 2.217% 1010100 11.261% 1110100 57.198% 0010101 0.459% 0110101 2.332% 1010101 11.847% 1110101 60.178% 0010110 0.483% 0110110 2.454% 1010110 12.465% 1110110 63.313% 0010111 0.508% 0111011 2.582% 1010111 13.114% 1110111 66.611% 0011000 0.535% 0110111 2.716% 1011000 13.797% 1111000 70.082% 0011001 0.563% 0111000 2.858% 1011001 14.516% 1111001 73.733% 0011010 0.592% 0111001 3.007% 1011010 15.272% 1111010 77.574% 0011011 0.623% 0111010 3.163% 1011011 16.068% 1111011 81.616% 0011100 0.655% 0111011 3.328% 1011100 16.905% 1111100 85.868% 0011101 0.689% 0111100 3.502% 1011101 17.786% 1111101 90.341% 0011110 0.725% 0111101 3.684% 1011110 18.713% 1111110 95.048% 0011111 0.763% 0111111 3.876% 1011111 19.687% 1111111 100.000% www.national.com % of ILED_MAX BMAIN or BSUB % of ILED_MAX Brightness Data 20 LM3528 30020544 FIGURE 9. IMAIN or ISUB vs BMAIN or BSUB Data Step 2: Write 1 to ENM (turning on MAIN) Step 3: IMAIN ramps to 20mA with a rate set by RMP0 and RMP1. (RMP0 and RMP1 bits set the duration spent at one brightness code before incrementing to the next). Step 4: ENM is set to 0 before 20mA is reached, thus the LED current fades off at a rate given by RMP0 and RMP1 without IMAIN going up to 20mA. Example 2: Step 1: ENM is 1, and BMAIN has been programmed with code 0x01. This results in a small current into MAIN. Step 2: BMAIN is programmed with 0x7F (full scale current). This causes IMAIN to ramp toward full-scale at the rate selected by RMP0 and RMP1. Step 3: Before IMAIN reaches full-scale BMAIN is programmed with 0x30. IMAIN will continue to ramp to full scale. Step 4: When IMAIN has reached full-scale value it will ramp down to the current corresponding to 0x30 at a rate set by RMP0 and RMP1. Example 3: Step 1: Write to BMAIN a value corresponding to IMAIN = 20mA. Step 2: Write a 1 to both RMP0 and RMP1. Step 3: Write 1 to ENM (turning on MAIN). Step 4: IMAIN ramps toward 20mA with a rate set by RMP0 and RMP1. (RMP0 and RMP1 bits set the duration spent at one brightness code before incrementing to the next). Step 5: After 1.222s IMAIN has ramped to 19.687% of ILED_MAX (0.19687 × 20mA = 3.9374mA). Simultaneously, RMP0 and RMP1 are both programmed with 0. Step 6: IMAIN continues ramping from 3.9374mA to 20mA, but at a new ramp rate of 12.75µs/step. BRIGHTNESS RATE OF CHANGE DESCRIPTION RMP0 and RMP1 control the rate of change of the LED current IMAIN and ISUB/FB in response to changes in BMAIN and/ or BSUB. There are 4 user programmable LED current rates of change settings for the LM3528 (see Table 5). TABLE 5. Rate of Change Bits RMP0 RMP1 Change Rate (tSTEP) 0 0 12.75µs/step 0 1 3.25ms/step 1 0 6.5ms/step 1 1 13ms/step For example, if RSET = 12.1kΩ then ILED_MAX = 20mA. With the contents of BMAIN set to 0x7F (IMAIN = 20mA), suppose the contents of BMAIN are changed to 0x00 resulting in (IMAIN = 0mA). With RMP0 =1 and RMP1 = 1 (13ms/step), IMAIN will change from 20mA to 0mA in 127 steps with 13ms elapsing between steps, excluding the step from 0x7F to 0x7E, resulting in a full scale current change in 1638ms. The total time to transition from one brightness code to another is: The following 3 additional examples detail possible scenarios when using the brightness register in conjunction with the rate of change bits and the enable bits. Example 1: Step 1: Write to BMAIN a value corresponding to IMAIN = 20mA. 21 www.national.com LM3528 TABLE 6. HPG Register Function Bits 7 – 6 (PGEN Bit Period) Bits 5 - 3 (PGEN Enable/Disable and Duty Cycle Selection) X X 00 = 1.6µs/ bit (625kHz) 01 = 26ms/ bit (38Hz) 10 = 52ms/ bit (19Hz) 11 = 105ms/ bit (9.5Hz) Note 1 X X Bit 2 (GPIO Data) X Bit 1 (GPIO Data Direction) Bit 0 (HWEN Control) Function X 0 HWEN/PGEN/GPIO is configured as an active high Hardware Enable Input (HWEN) 001 = 100% X 010 = 1/2 011 = 1/3 100 = 1/4 101 = 1/6 110 = 1/12 111 = Latch Pattern Into Shift Register Note 2 000 GPIO Read Data X 1 HWEN/PGEN/GPIO is configured as a Pattern Generator Output with the frequency set by bits <7:6> and the duty cycle set by bits <5:3>. (See Figure 11.) 1 1 HWEN/PGEN/GPIO is configured as a GPIO Input. Read data from bit 2. 000 0 1 HWEN/PGEN/GPIO is configured as a GPIO Output. A ‘1’ written to bit 2 will force HWEN/ PGEN/GPIO high; a 0 written to bit 2 will force HWEN/PGEN/GPIO low. GPIO Write Data Note 1: This represents the amount of time each programmed bit will be present at HWEN/PGEN/GPIO. The entire pattern period will be 32 × Bit Period. Note 2: This duty cycle indicates the fraction of time the pattern is being output at HWEN/PGEN/GPIO. For example the 1/2 duty cycle (bits <5:3> = 010) will have the 32 bit pattern output once followed by a dead time (HWEN/PGEN/GPIO high impedance) equal to 1×’s the pattern period (Deadtime = 32 × Bit_Period × (1/DutyCycle -1). For the 100% duty cycle setting the 32 bit pattern will repeat constantly with no deadtime. 30020546 FIGURE 10. HPG Register Description www.national.com 22 LM3528 GPIO Register Function Bits 7 - 2 GPIO Data (Bit 1) Data Direction (Bit 0) Function X X 0 GPIO is configured as a GPIO input with the input data read back via bit [1]. This is the default power on state. X X 1 GPIO is configured as a logic output. The output logic voltage is written to bit [1]. 30020564 FIGURE 11. GPIO Register Description Figures 12 – 15 detail the Pattern Generator Data Registers. These hold the 32 bit data that is output at HWEN/PGEN/ GPIO in PGEN mode. The data is output LSB first (Bit 0 of PGEN0) and MSB last (Bit 7 of PGEN3). 30020565 FIGURE 12. PGEN0 Register Description 30020566 FIGURE 13. PGEN1 Register Description 23 www.national.com LM3528 30020567 FIGURE 14. PGEN2 Register Description 30020568 FIGURE 15. PGEN3 Register Description Figure 16 shows a write sequence to the pattern generator programmed to output the waveform in Figure 17. In this example HPG register bits <7:6> = 01 (for 26ms/bit) and bits <5:3> = 010 (for 1/2 duty cycle). The pattern data in registers (PGEN0 – PGEN2) are all loaded with 0xAC. A ‘1’ will force the HWEN/PGEN/GPIO output low while a ‘0’ will force HWEN/PGEN/GPIO open drain. When set for a 26ms/bit period the pattern will be output LSB first (PGEN0, bit 0) and repeat every www.national.com When set for ½ duty cycle there will be a dead time (HWEN/ PGEN/GPIO high impedance) between each pattern and equal to the pattern period. In applications where HWEN/ PGEN/GPIO is used to pull current through an indicator LED a ‘1’ corresponds to the LED on and a ‘0’ corresponds to the LED off. 24 LM3528 30020569 FIGURE 16. Pattern Generation Write Sequence 30020570 FIGURE 17. Pattern Generation Output the SUB/FB current sink and force SUB/FB high impedance. Writing a 1 to ENM or ENS turns on the MAIN and SUB/FB current sinks respectively. When in shutdown the leakage current into MAIN or SUB/FB is typically 1.8µA. See Typical Performance Plots for start-up responses of the LM3528 using the ENM and ENS bits in White LED and OLED modes. SHUTDOWN AND OUTPUT ISOLATION The LM3528 provides a true shutdown for either MAIN or SUB/FB when configured as a White LED bias supply. Write a 0 to ENM (bit 1) of the General Purpose register to turn off the MAIN current sink and force MAIN high impedance. Write a 0 to ENS (bit 2) of the General Purpose register to turn off 25 www.national.com LM3528 INPUT CAPACITOR SELECTION Choosing the correct size and type of input capacitor helps minimize the input voltage ripple caused by the switching of the LM3528’s boost converter. For continuous inductor current operation the input voltage ripple is composed of 2 primary components, the capacitor discharge (delta VQ) and the capacitor’s equivalent series resistance (delta VESR). These ripple components are found by: Application Information LED CURRENT SETTING/MAXIMUM LED CURRENT Connect a resistor (RSET) from SET to GND to program the maximum LED current (ILED_MAX) into MAIN or SUB/FB. The RSET to ILED_MAX relationship is: where SET provides the constant 1.244V output. OUTPUT VOLTAGE SETTING (OLED MODE) Connect Feedback resistors from the converters output to SUB/FB to GND to set the output voltage in OLED mode (see R1 and R2 in the Typical Application Circuit (OLED Panel Power Supply). First select R2 < 100kΩ then calculate R1 such that: In the typical application circuit a 1µF ceramic input capacitor works well. Since the ESR in ceramic capacitors is typically less than 5mΩ and the capacitance value is usually small, the input voltage ripple is primarily due to the capacitive discharge. With larger value capacitors such as tantalum or aluminum electrolytic the ESR can be greater than 0.5Ω. In this case the input ripple will primarily be due to the ESR. In OLED mode the MAIN current sink continues to regulate the current through MAIN, however, VMAIN is no longer regulated. To avoid dropout and ensure proper current regulation the application must ensure that VMAIN > 0.3V. OUTPUT CAPACITOR SELECTION The LM3528’s output capacitor supplies the LED current during the boost converters on time. When the switch turns off the inductor energy is discharged through the diode supplying power to the LED’s and restoring charge to the output capacitor. This causes a sag in the output voltage during the on time and a rise in the output voltage during the off time. The output capacitor is therefore chosen to limit the output ripple to an acceptable level depending on LED or OLED panel current requirements and input/output voltage differentials. For proper operation ceramic output capacitors ranging from 1µF to 2.2µF are required. As with the input capacitor, the output voltage ripple is composed of two parts, the ripple due to capacitor discharge (delta VQ) and the ripple due to the capacitors ESR (delta VESR). For continuous conduction mode, the ripple components are found by: www.national.com Table 7 lists different manufacturers for various capacitors and their case sizes that are suitable for use with the LM3528. When configured as a dual output LED driver a 1µF output capacitor is adequate. In OLED mode for output voltages above 12V a 2.2µF output capacitor is required (see Low Output Voltage Operation (OLED) Section). 26 LM3528 TABLE 7. Recommended Output Capacitors Manufacturer Part Number Value Case Size Voltage Rating TDK C1608X5R1E105M 1µF 0603 25V Murata GRM39X5R105K25D539 1µF 0603 25V TDK C2012X5R1E225M 2.2µF 0805 25V Murata GRM219R61E225KA12 2.2µF 0805 25V INDUCTOR SELECTION The LM3528 is designed for use with a 10µH inductor, however 22µH are suitable providing the output capacitor is increased 2×. When selecting the inductor ensure that the saturation current rating (ISAT) for the chosen inductor is high enough and the inductor is large enough such that at the maximum LED current the peak inductor current is less than the LM3528’s peak switch current limit. This is done by choosing: Values for IPEAK can be found in the plot of peak current limit vs. VIN in the Typical Performance Characteristics graphs. Table 8 shows possible inductors, as well as their corresponding case size and their saturation current ratings. TABLE 8. Recommended Inductors Manufactur er Part Number Value Dimensions ISAT DC Resistance TDK VLF3012AT-100MR49 10µH 2.6mm×2.8mm×1mm 490mA 0.36Ω Coilcraft LPS3008-103ML 10µH 2.95mm×2.95mm×0.8mm 490mA 0.65Ω TDK VLF4012AT-100MR79 10µH 3.5mm×3.7mm×1.2mm 800mA 0.3Ω Coilcraft LPS4012-103ML 10µH 3.9mm×3.9mm×1.1mm 700mA 0.35Ω TOKO A997AS-100M 10µH 3.8mm×3.8mm×1.8mm 580mA 0.18Ω DIODE SELECTION The output diode must have a reverse breakdown voltage greater than the maximum output voltage. The diodes average current rating should be high enough to handle the LM3528’s output current. Additionally, the diodes peak current rating must be high enough to handle the peak inductor current. Schottky diodes are recommended due to their lower forward voltage drop (0.3V to 0.5V) compared to (0.6V to 0.8V) for PN junction diodes. If a PN junction diode is used, ensure it is the ultra-fast type (trr < 50ns) to prevent excessive loss in the rectifier. For Schottky diodes the B05030WS (or equivalent) work well for most designs. See Table 9 for a list of other Schottky Diodes with similar performance. 27 www.national.com LM3528 TABLE 9. Recommended Schottky Diodes Manufacturer Part Number Package Reverse Breakdown Voltage Average Current Rating On Semiconductor NSR0230P2T5G SOD-923 (0.8mm×0.6mm×0.4mm) 30V 200mA On Semicondcuctor NSR0230M2T5G SOD-723 (1mm×0.6mm×0.52mm) 30V 200mA On Semiconductor RB521S30T1 SOD-523 (1.2mm×0.8mm×0.6mm) 30V 200mA Diodes Inc. SDM20U30 SOD-523 (1.2mm×0.8mm×0.6mm) 30V 200mA Diodes Inc. B05030WS SOD-323 (1.6mm×1.2mm×1mm) 30V 0.5A Philips BAT760 SOD-323 (1.6mm×1.2mm×1mm) 20V 1A OUTPUT CURRENT RANGE (OLED MODE) The maximum output current the LM3528 can deliver in OLED mode is limited by 4 factors (assuming continuous conduction); the peak current limit of 770mA (typical), the inductor value, the input voltage, and the output voltage. Calculate the maximum output current (IOUT_MAX) using the following equation: OUTPUT VOLTAGE RANGE (OLED MODE) The LM3528's output voltage is constrained by 2 factors. On the low end it is limited by the minimum duty cycle of 10% (assuming continuous conduction) and on the high end it is limited by the over voltage protection threshold (VOVP) of 22V (typical). In order to maintain stability when operating at different output voltages the output capacitor and inductor must be changed. Refer to Table 10 for different VOUT, C OUT, and L combinations. TABLE 10. Component Values for Output Voltage Selection For the typical application circuit with VOUT = 18V and assuming 70% efficiency, the maximum output current at VIN = 2.7V will be approximately 70mA. At 4.2V due to the shorter on times and lower average input currents the maximum output current (at 70% efficiency) jumps to approximately 105mA. Figure 11 shows a plot of IOUT_MAX vs. VIN using the above equation, assuming 80% efficiency. In reality, factors such as current limit and efficiency will vary over VIN, temperature, and component selection. This can cause the actual IOUT_MAX to be higher or lower. 30020562 FIGURE 18. Typical Maximum Output Current in OLED Mode (assumed 80% efficiency) www.national.com 28 VOUT COUT L VIN Range 18V 2.2µF 10µH 2.7V to 5.5V 15V 2.2µF 10µH 2.7V to 5.5V 12V 4.7µF 10µH 2.7V to 5.5V 9V 10µF 10µH 2.7V to 5.5V 7V 10µF 4.7µH 2.7V to 5.5V 5V 22µF 4.7µH 2.7V to 4.5V LM3528 APPLICATION CIRCUITS 30020561 FIGURE 19. LED Backlight + OLED Power Supply to the PGND pin on the LM3528. This minimizes the inductance in series with the output capacitor and reduces the noise present at VOUT and at the PGND connection. This is important due to the large di/dt into and out of COUT. The returns for both CIN and COUT should terminate directly to the PGND pin. 4, Connect the inductor on the top layer close to the SW pin. There should be a low impedance connection from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the SW node should be small so as to reduce the capacitive coupling of the high dV/dt present at SW that can couple into nearby traces. 5, Route the traces for RSET and the feedback divider away from the SW node to minimize the capacitance between these nodes that can couple the high dV/dt present at SW into them. Furthermore, the feedback divider and RSETshould have dedicated returns that terminate directly to the PGND pin of the device. This will minimize any shared current with COUT or CIN that can lead to instability. Avoide routing the SUB/FB node close to other traces that can see high dV/dt such as the I2C pins. The capacitive coupling on the PCB between FB and these nodes can disturb the output voltage and cause large voltage spikes at VOUT. 6, Do not connect any external capacitance to the SET pin. 7, Refer to the LM3528 Evaluation Board as a guide for proper layout. LAYOUT CONSIDERATIONS Refer to AN-1112 for µSMD package soldering The high switching frequencies and large peak currents in the LM3528 make the PCB layout a critical part of the design. The proceeding steps should be followed to ensure stable operation and proper current source regulation. 1, CIN should be located on the top layer and as close to the device as possible. The input capacitor supplies the driver currents during MOSFET switching and can have relatively large spikes. Connecting the capacitor close to the device will reduce the inductance between CIN and the LM3528 and eliminate much of the noise that can disturb the internal analog circuitry. 2, Connect the anode of the Schottky diode as close to the SW pin as possible. This reduces the inductance between the internal MOSFET and the diode and minimizes the noise generated from the discontinuous diode current and the PCB trace inductance that will add ringing at the SW node and filter through to VOUT. This is especially important in VOUT mode when designing for a stable output voltage. 3, COUT should be located on the top layer to minimize the trace lengths between the diode and PGND. Connect the positive terminal of the output capacitor (COUT+) as close as possible to the cathode of the diode. Connect the negative terminal of the output capacitor (COUT-) as close as possible 29 www.national.com LM3528 Physical Dimensions inches (millimeters) unless otherwise noted 12 Bump µSMD For Ordering, Refer to Ordering Information Table NS Package Number TMD12 X1 = 1.215mm (±0.1mm), X2 = 1.615mm (±0.1mm), X3 = 0.6mm www.national.com 30 LM3528 Notes 31 www.national.com LM3528 High Efficiency, Multi Display LED Driver with 128 Exponential Dimming Steps and Integrated OLED Power Supply in micro SMD Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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