NSC LMH6503MAX

LMH6503
Wideband, Low Power, Linear Variable Gain Amplifier
General Description
Features
The LMH™6503 is a wideband DC coupled differential input
voltage controlled gain stage followed by a high-speed current feedback Op Amp which can directly drive a low impedance load. Gain adjustment range is more than 70dB for up
to 10MHz.
Maximum gain is set by external components and the gain
can be reduced all the way to cut-off. Power consumption is
370mW with a speed of 135MHz . Output referred DC offset
voltage is less than 350mV over the entire gain control
voltage range. Device-to-device Gain matching is within
0.7dB at maximum gain. Furthermore, gain at any VG is
tested and the tolerance is guaranteed. The output current
feedback Op Amp allows high frequency large signals (Slew
Rate = 1800V/µs) and can also drive heavy load current
(75mA). Differential inputs allow common mode rejection in
low level amplification or in applications where signals are
carried over relatively long wires. For single ended operation, the unused input can easily be tied to ground (or to a
virtual half-supply in single supply application). Inverting or
non-inverting gains could be obtained by choosing one input
polarity or the other.
VS = ± 5V, TA = 25˚C, RF = 1kΩ, RG = 174Ω, RL = 100Ω, AV
= AV(MAX) = 10, Typical values unless specified.
n -3dB BW
135MHz
n Gain control BW
100MHz
n Adjustment range (typical over temp)
70dB
± 0.7dB
n Gain matching (limit)
n Slew rate
1800V/µs
n Supply current (no load)
37mA
± 75mA
n Linear output current
± 3.2V
n Output voltage (RL = 100Ω)
n Input voltage noise
6.6nV/
n Input current noise
2.4pA/
n THD (20MHz, RL = 100Ω, VO = 2VPP)
−57dBc
n Replacement for CLC522
To further increase versatility when used in a single supply
application, gain control range is set to be from −1V to +1V
relative to pin 11 potential (ground pin). In single supply
operation, this ground pin is tied to a "virtual" half supply.
Gain control pin has high input impedance to simplify its
drive requirement. Gain control is linear in V/V throughout
the gain adjustment range. Maximum gain can be set to be
anywhere between 1V/V to 100V/V or higher. For linear in dB
gain control applications, see LMH6502 datasheet.
Applications
n
n
n
n
Variable attenuator
AGC
Voltage controller filter
Multiplier
The LMH6503 is available in the SOIC-14 and TSSOP-14
package.
Typical Application
20073913
Gain vs. VG for Various Temperature
20073933
AVMAX = 10V/V
LMH™ is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS200739
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LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
June 2004
LMH6503
Absolute Maximum Ratings (Note 1)
Infrared or Convection (20 sec)
235˚C
Wave Soldering (10 sec)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
260˚C
Storage Temperature Range
−65˚C to +150˚C
Junction Temperature
+150˚C
ESD Tolerance: (Note 4)
Human Body
2KV
Machine Model
Operating Ratings (Note 1)
200V
Supply Voltages (V+ - V−)
± 10mA
Input Current
VIN Differential
± (V −V )
Temperature Range
Output Current
120mA (Note 3)
Thermal Resistance:
+
Supply Voltages (V+ - V−)
Voltage at Input/ Output pins
−
12.6V
+
−
V +0.8V,V - 0.8V
5V to 12V
−40˚C to +85˚C
θJA
θJC
14-Pin SOIC
138˚C/W
45˚C/W
14-Pin TSSOP
160˚C/W
51˚C/W
Soldering Information:
Electrical Characteristics(Note 2)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VS = ± 5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF = ± 0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Units
Frequency Domain Response
BW
GF
-3dB Bandwidth
Gain Flatness
VOUT < 0.5PP
135
VOUT < 0.5PP, AV(MAX) = 100
50
VOUT < 0.5VPP,
−1V < VG < 1V, ± 0.2dB
40
MHz
MHz
Att Range Flat Band (Relative to Max Gain)
Attenuation Range (Note 13)
± 0.2dB Flatness, f < 30MHZ
± 0.1dB, f < 30MHZ
6.6
BW
Control
Gain Control Bandwidth
VG = 0V (Note 11)
100
MHz
PL
Linear Phase Deviation
DC to 60MHz
1.6
deg
G Delay
Group Delay
DC to 130MHz
2.6
ns
CT (dB)
Feed-through
VG = −1.2V, 30MHz (Output
Referred)
−48
dB
GR
Gain Adjustment Range
f < 10MHz
79
f < 30MHz
68
20
MHz
dB
Time Domain Response
t r , tf
Rise and Fall Time
0.5V Step
2.2
ns
OS%
Overshoot
0.5V Step
10
%
SR
Slew Rate
4V Step (Note 5)
1800
V/µs
∆G Rate
Gain Change Rate
VIN = 0.3V, 10%−90% of final
output
4.6
dB/ns
Distortion & Noise performance
HD2
2nd Harmonic Distortion
2VPP, 20MHz
−60
dBc
HD3
3rdHarmonic Distortion
2VPP, 20MHz
−61
dBc
THD
Total Harmonic Distortion
2VPP, 20MHz
−57
En tot
Total Equivalent Input Noise
1MHz to 150MHz
6.6
nV/
In
Input Noise Current
1MHz to 150MHz
2.4
pA/
DG
Differential Gain
f = 4.43MHz, RL = 150Ω, Neg.
Sync
0.15
%
DP
Differential Phase
f = 4.43MHz, RL = 150Ω, Neg.
Sync
0.22
deg
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2
dBc
(Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VS = ± 5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF = ± 0.1V, RL = 100Ω, VG = +1V. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Units
DC & Miscellaneous Performance
GACCU
Gain Accuracy (see Application
Notes)
VG =1.0V
+0.25
+0.9/−0.4
0V < VG < 1V
± 0.3
± 0.4
+1.3/−1.5
−0.7V < VG < 1V
G Match
Gain Matching (see Application
Notes)
VG = 1.0
–
± 0.7
0 < VG < 1V
–
+1.7/−1.1
−0.7V < VG < 1V
–
+4.0/−4.7
1.58
1.58
1.72
1.87
1.91
± 2.0
± 1.80
± 0.34
± 0.28
± 1.70
± 1.60
± 2.2
K
Gain Multiplier (see Application
Notes)
VCM
Input Voltage Range
Pin 3 & 6 Common Mode,
|CMRR| > 50dB (Note 9)
VIN_ DIFF
Differential Input Voltage
Across pins 3 & 6
IRG MAX
RG Current
Pins 4 & 5
IBIAS
Bias Current
Pins 3 & 6 (Note 7)
11
18
20
Pins 3 & 6 (Note 7),
VS= ± 2.5V
3
10
13
Bias Current Drift
Pin 3 & 6 (Note 8)
100
Offset Current
Pin 3 & 6
0.01
OFF
V/V
V
± 2.30
I
dB
V
± 0.37
TCBIAS
dB
+4.4/−4.3
mA
µA
nA/˚C
2.0
2.5
µA
TC IOFF
Offset Current Drift
(Note 8)
5
nA/˚C
RIN
Input Resistance
Pin 3 & 6
750
kΩ
CIN
Input Capacitance
Pin 3 & 6
5
pF
IVG
VG Bias Current
Pin 2, VG = 1.4V(Note 7)
45
µA
TC IVG
VG Bias Drift
Pin 2 (Note 8)
20
nA/˚C
R VG
VG Input Resistance
Pin 2
70
KΩ
C VG
VG Input Capacitance
Pin 2
1.3
pF
VOUT
Output Voltage Range
RL = 100Ω
± 3.00
± 2.97
± 3.95
± 3.90
RL Open
± 3.20
V
± 4.05
0.1
Ω
± 90
mA
ROUT
Output Impedance
DC
IOUT
Output Current
VOUT ± 4V from Rails
VO
Output Offset Voltage
−1V < VG < 1V
± 80
± 350
± 380
mV
+PSRR
+Power Supply Rejection Ratio
(see (Note 10))
Input Referred, 1V change,
VG = 1.4V
−80
−58
−56
dB
−PSRR
−Power Supply Rejection Ratio
(see (Note 10))
Input Referred, 1V change,
VG = 1.4V
−67
−57
−51
dB
CMRR
Common Mode Rejection Ratio
(see (Note 9))
Input Referred, VG = 1V
−1.8V < VCM < 1.8V
−67
IS
Supply Current
RL = Open
37
50
53
RL = Open, VS = ± 2.5V
12
20
23
± 75
± 70
OFFSET
3
dB
mA
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LMH6503
Electrical Characteristics(Note 2)
LMH6503
Electrical Characteristics(Note 2)
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.
Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of
the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA.
Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower.
Note 4: Human body model: 1.5kΩ in series with 100pF. Machine model: 0Ω in series with 200pF.
Note 5: Slew Rate is the average of the rising and falling rates.
Note 6: Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits.
Note 7: Positive current correspondes to current flowing in the device.
Note 8: Drift determined by dividing the change in parameter distribution at temperature extremes by the total temperature change.
Note 9: CMRR definition: [|∆VOUT/∆VCM|/AV] with 0.1V differential input voltage. ∆VOUT is the change in output voltage with offset shift subtracted out.
Note 10: +PSRR definition: [|∆VOUT/∆V+| /AV], -PSRR definition: [|∆VOUT/∆V−| /AV] with 0.1V differential input voltage. ∆VOUT is the change in output voltage with
offset shift subtracted out.
Note 11: Gain Control Frequency Response Schematic:
20073932
Note 12: Gain/Phase normalized to low frequency value at each AV.
Note 13: Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain flatness specified
(either ± 0.2dB or ± 0.1dB), relative to AVMAX gain. For example, for f < 30MHz, here are the Flat Band Attenuation ranges:
± 0.2dB:
± 0.1dB:
10V/V down to 1V/V=20dB range
10V/V down to 4.7V/V=6.5dB range
Connection Diagram
14-Pin SOIC/TSSOP
20073946
Top View
Ordering Information
Package
Part Number
Package Marking
Transport Media
NSC Drawing
14-pin SOIC
LMH6503MA
LMH6503MA
55 Units/Rail
M14A
LMH6503MAX
14-Pin TSSOP
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LMH6503MT
LMH6503MTX
2.5k Units Tape and Reel
94 Units/Rail
LMH6503MT
2.5k Units Tape and Reel
4
MTC14
Unless otherwise specified: VS = ± 5V, 25˚C, VG = VG_MAX, VCM
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output:
Small Signal Frequency Response (AV = 2)
Large Signal Frequency Response (AV = 2)
20073917
20073916
Frequency Response over Temperature (AV = 10)
Frequency Response for Various VG (AVMAX = 10)
20073919
20073920
Frequency Response for Various VG (AVMAX = 10)
( ± 2.5V)
Small Signal Frequency Response
20073914
20073930
5
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LMH6503
Typical Performance Charateristics
LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
Frequency Response for Various VG (AVMAX = 100)
(Small Signal)
Large Signal Frequency Response
20073915
20073943
Frequency Response for Various VG (AVMAX = 100)
(Large Signal)
Gain Control Frequency Response
20073944
20073928
IS vs. VS
IS vs. VS
20073964
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20073965
6
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
Input Bias Current vs. VS
AVMAX vs. VS
20073966
20073967
PSRR ± 5V
PSRR ± 2.5V
20073907
20073906
CMRR ± 5V
CMRR ± 2.5V
20073904
20073905
7
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
AVMAX vs. VCM
AVMAX vs. VCM
20073972
20073971
Supply Current vs. VCM
Supply Current vs. VCM
20073974
20073973
Output Offset Voltage vs.VCM (Typical Unit 1)
Output Offset Voltage vs.VCM (Typical Unit 2)
20073975
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20073976
8
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
Output Offset Voltage vs.VCM (Typical Unit 3)
Feed through Isolation
20073918
20073977
Gain Flatness and Linear Phase Deviation
Gain Flatness Frequency vs. Gain (Note 13)
20073921
20073924
Group Delay vs. Frequency
K Factor vs. RG
20073927
20073901
9
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
Gain vs. VG Including Limits
BW vs. RF for Various RG
20073912
20073903
Gain vs. VG ( ± 5V)
Output Offset Voltage vs. VG (Typical Unit 1)
20073913
20073968
Output Offset Voltage vs. VG (Typical Unit 2)
Output Offset Voltage vs. VG (Typical Unit 3)
20073970
20073969
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10
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
Output Offset Voltage vs. ± VS for Various VG
(Typical Unit 1)
Output Offset Voltage vs. ± VS for Various VG
(Typical Unit 2)
20073978
20073979
Output Offset Voltage vs. ± VS for Various VG
(Typical Unit 3)
Gain vs. VG ( ± 2.5V)
20073929
20073980
Noise vs. Frequency (AVMAX = 2)
Noise vs. Frequency (AVMAX = 10)
20073923
20073922
11
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
Noise vs. Frequency (AVMAX = 100)
−1dB Compression
20073931
20073911
Output Voltage vs. Output Current
HD2 vs. POUT
20073940
20073945
HD3 vs. POUT
THD vs. POUT
20073939
20073941
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= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
HD2 & HD3 vs. VG
THD vs. VG
20073942
20073938
VG Bias Current vs. VG
Step Response Plot
20073962
20073937
Step Response Plot
Gain vs. VG Step
20073963
20073981
13
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LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
LMH6503
Typical Performance Charateristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VG_MAX, VCM
= 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device
output: (Continued)
VG Feedthrough
20073982
Application Information
THEORY OF OPERATION
The LMH6503 is a linear wideband variable-gain amplifier as
illustrated in Figure 1. A voltage input signal may be applied
differentially between the two inputs (+VIN, −VIN), or singleendedly by grounding one of the two unused inputs. The
LMH6503 input buffers convert the input voltage to a current
(IRG) that is a function of the differential input voltage (VINPUT
= (+VIN) - (−VIN)) and the value of the gain setting resistor
(RG). This current (IRG) is then mirrored to a gain stage with
a current gain of K (1.72 nominal). The voltage controlled
two-quadrant multiplier attenuates this current which is then
converted to a voltage via the output amplifier. This output
amplifier is a current feedback op amp configured as a
Transimpedance amplifier. Its Transimpedance gain is the
feedback resistor (RF). The input signal, output, and gain
control are all voltages. The output voltage can easily be
calculated as shown in Equation 1:
(3)
Notice also that Equation 3 holds for both differential and
single ended operation.
20073951
(1)
FIGURE 1. LMH6503 Functional Block Diagram
Where K = 1.72 (Nominal)
since:
CHOOSING RF AND RG
RG is calculated from Equation 4. VINPUTMAX is the maximum peak
The gain of the LMH6503 is therefore a function of three
external variables: RG, RF, and VG as expressed in Equation
2:
(4)
input voltage (Vpk) determined by the application. IRGMAX is
the maximum allowable current through RG and is typically
2.3mA. Once AVMAX is determined from the minimum input
and desired output voltages, RF is then determined using
Equation 5. These values of RF and RG are
(2)
The gain control voltage (VG) has an ideal input range of −1V
< VG < +1V. At VG = +1V, the gain of the LMH6503 is at its
maximum as expressed in Equation 3:
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14
(Continued)
Once this is accomplished, the offset errors introduced by
the input stage and multiplier core can then be treated. The
second step requires the absence of an input signal and
matched source impedances on the two input pins in order to
cancel the bias current errors. This done, then +1.1V should
be applied to VG and the trim pot located at R10 adjusted in
order to null the offset voltage seen at the LMH6503’s output.
If a more limited gain range is anticipated, the above adjustments should be made at these operating points. These
steps will minimize the output offset voltage. However, since
the offset term itself varies with the gain setting, the correction is not perfect and some residual output offset will remain.
(5)
the minimum possible values that meet the input voltage and
maximum gain constraints. Scaling the resistor values will
decrease bandwidth and improve stability.
Figure 2 illustrates the resulting LMH6503 bandwidths as a
function of the maximum ( y axis) and minimum (related to x
axis) input voltages when VOUT is held constant at 1VPP.
GAIN ACCURACY
Defined as the ratio of measured gain (V/V), at a certain VG,
to the best fit line drawn through the typical gain (V/V)
distribution for −1V < VG < 1V (results expressed in dB)
(See Figure 4). The best fit gain (AV) is given by:
(6)
AV (V/V) = 4.87VG + 4.61
For: −1V ≤ VG ≤ + 1V, RF = 1kΩ, RG = 174Ω
For a VG range, the value specified in the tables represents
the worst case accuracy over the entire range. The "Typical"
value would be the worst case ratio between the "Typical
Gain" and the best fit line. The "Max" value would be the
worst case between the max/min gain limit and the best fit
line.
GAIN MATCHING
Defined as the limit on gain variation at a certain VG (expressed in dB) (See Figure 4). Specified as "Max" only (no
"Typical"). For a VG range, the value specified represents the
worst case matching over the entire range. The "Max" value
would be the worst case ratio between the max/min gain limit
and the typical gain.
20073902
FIGURE 2. Bandwidth vs. VINMAX and AVMAX
ADJUSTING OFFSETS
Treating the offsets introduced by the input and output
stages of the LMH6503 is accomplished with a two step
process. The offset voltage of the output stage is treated by
first applying −1.1V on VG, which effectively isolates the
input stage and multiplier core from the output stage. As
illustrated in Figure 3, the trim pot located at R14 on the
LMH6503 Evaluation Board (CLC730033) should then be
adjusted in order to null the offset voltage seen at the
LMH6503’s output (pin 10).
20073955
FIGURE 4. Gain Accuracy and Gain Matching
Parameters Defined
20073954
FIGURE 3. Nulling the Output Offset Voltage
15
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LMH6503
Application Information
LMH6503
Application Information
required of the layout. Minimizing the parasitic capacitances
at pins 3, 4, 5, 6, 9, 10 and 12 will assure best high frequency
performance. The parasitic inductance of component leads
or traces to pins 4, 5 and 9 should also be kept to a
minimum. Parasitic or load capacitance, CL, on the output
(pin 10) degrades phase margin and can lead to frequency
response peaking or circuit oscillation. The LMH6503 is fully
stable when driving a 100Ω load. With reduced load (e.g.
1kΩ) there is a possibility of instability at very high frequencies beyond 400MHz especially with a capacitive load.
When the LMH6503 is connected to a light load as such, it is
recommended to add a snubber network to the output (e.g.
100Ω and 39pF in series tied between the LMH6503 output
and ground). CL can also be isolated from the output by
placing a small resistor in series with the output (pin 10).
(Continued)
NOISE
Figure 5 describes the LMH6503’s output-referred spot
noise density as a function of frequency with AVMAX = 10V/V.
The plot includes all the noise contributing terms. However,
with both inputs terminated in 50Ω, the input noise contribution is minimal. At AVMAX = 10V/V, the LMH6503 has a typical
flat-band input-referred spot noise density (ein) of 6.6nV/
. For applications with −3dB BW extending well into the
flat-band region, the input RMS voltage noise can be determined from the following single-pole model:
(7)
Component parasitics also influence high frequency results.
Therefore it is recommended to use metal film resistors such
as RN55D or leadless components such as surface mount
devices. High profile sockets are not recommended.
National Semiconductor suggests the following evaluation
board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board Part
Number
LMH6503MA
SOIC-14
CLC730033
LMH6503MT
TSSOP-14
CLC730146
The evaluation board is shipped when a device sample
request is placed with National Semiconductor.
SINGLE SUPPLY OPERATION
It is possible to operate the LMH6503 with a single supply. To
do so, tie pin 11 (GND) to a potential about mid point
between V+ and V−. Two examples are shown in Figure 7 &
Figure 8.
20073922
FIGURE 5. Output Referred Voltage Noise vs.
Frequency
CIRCUIT LAYOUT CONSIDERATIONS
Good high-frequency operation requires all of the decoupling capacitors shown in Figure 6 to be placed as close
as possible to the power supply pins in order to insure a
proper high-frequency low-impedance bypass. Adequate
ground plane and low inductive power returns are also
20073935
FIGURE 7. AC Coupled Single Supply VGA
20073957
FIGURE 6. Required Power Supply Decoupling
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16
Figure 10 plots to make sure the region of operation is not
overly restricted by the "pinching" of VG_LIMIT, and VG_MAX curves.
(Continued)
c) "Max_gain" reduces. There is an intrinsic reduction in
max gain when the total supply voltage is reduced (see
Typical Performance Characteristics plots for Gain vs. VG
(VS = ± 2.5V). In addition, there is the more drastic
mechanism described in "b" above and shown in Figure
9.
Similar plots for V+ = 5V operation are shown in Figure 10 for
comparison and reference.
20073936
FIGURE 8. Transformer Coupled Single Supply VGA
OPERATING AT LOWER SUPPLY VOLTAGES
The LMH6503 is rated for operation down to 5V supplies (V+
- V−). There are some specifications shown for operation at
± 2.5V within the data sheet (i.e. Frequency Response,
CMRR, PSRR, Gain vs. VG, etc.). Compared to ± 5V operation, at lower supplies:
a) VG range constricts. Referring to Figure 9, note that
VG_MAX (VG voltage required to get maximum gain) is
0.5V (VS = ± 2.5V) compared to 1.0V for VS = ± 5V. At the
same time, gain cut-off (VG_MIN) would shift to −0.5V from
- 1V with VS = ± 5V.
Table 1 shows the approximate expressions for various
VG voltages as a function of V-:
20073926
FIGURE 9. VG_MAX, VG_LIMIT, & Max-gain vs. V(V+ = 2.5V)
Table 1: VG Definition Based on V−
VG
Definition
Expression (V)
VG_MIN
Gain Cut-off
0.2 x V−
VG_MID
AVMAX/2
0
VG_MAX
AVMAX
−0.2 x V−
b) VG_LIMIT (maximum permissible voltage on VG) is reduced. This is due to limitations within the device arising
from transistor headroom. Beyond this limit, device performance will be affected (non-destructive). Referring to
Figure 9, note that with V+ = 2.5V, and V− = −4V, VG_LIMIT
is approaching VG_MAX and already "Max gain" is reduced by 1dB. This means that operating under these
conditions has reduced the maximum permissible voltage
on VG to a level below what is needed to get Max gain. If
supply voltages are asymmetrical, reference Figure 9 and
20073925
FIGURE 10. VG_MAX, VG_LIMIT, & Max-gain vs. V(V+ = 5V)
17
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LMH6503
Application Information
LMH6503
2nd ORDER TUNABLE BANDPASS FILTER
Application Circuits
The LMH6503 Variable-Gain Amplifier placed into a feedback loop provides signal processing function such as in a
2nd order tunable bandpass filter. The center frequency of
the 2nd order bandpass shown in Figure 13 is adjusted
through the use of the LMH6503’s gain control voltage, VG.
The integrators implemented with two sections of a
LMH6682, provide the coefficients for the transfer function.
FOUR-QUADRANT MULTIPLIER
Applications requiring multiplication, squaring or other nonlinear functions can be implemented with four-quadrant multipliers. The LMH6503 implements a four-quadrant multiplier
as illustrated in Figure 11:
20073958
FIGURE 11. Four Quadrant Multiplier
FREQUENCY SHAPING
Frequency shaping and bandwidth extension of the
LMH6503 can be accomplished using parallel networks connected across the RG ports. The network shown in the
Figure 12 schematic will effectively extend the LMH6503’s
bandwidth.
20073960
20073961
FIGURE 13. Tunable Bandpass Filter
20073959
FIGURE 12. Frequency Shaping
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18
LMH6503
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Pin SOIC
NS Package Number M14A
14-Pin TSSOP
NS Package Number MTC14
19
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LMH6503 Wideband, Low Power, Linear Variable Gain Amplifier
Notes
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