LMH6704 650 MHz Progammable Gain Buffer with Disable General Description Features The LMH™6704 is a very wideband, DC coupled progammable gain buffer designed specifically for wide dynamic range systems requiring exceptional signal fidelity. The LMH6704 includes on chip feedback and gain set resistors, simplifying PCB layout while providing user programmable gains of +1, +2 and −1 V/V. The LMH6704 provides a disable pin, which places the amplifier in a high output impedance, low power mode. The Disable pin may be allowed to float high. With a 650 MHz Small Signal Bandwidth (AV = +1), full power gain flatness to 200 MHz, and excellent Differential Gain and Phase, the LMH6704 is optimized for video applications. High resolution video systems will benefit from the LMH6704’s ability to drive multiple video loads at low levels of differential gain or differential phase distortion. The LMH6704 is constructed with National’s proprietary high speed complementary bipolar process using National’s proven current feedback circuit architectures. It is available in 8-Pin SOIC and 6-Pin SOT23 packages. n Wideband operation 650 MHz — AV = +1, VO = 0.5 VPP 450 MHz — AV = +2, VO = 0.5 VPP 400 MHz — AV = +2, VO = 2 VPP ± 90 mA n High output current n Very low distortion — 2nd/3rd harmonics (10 MHz, RL = 100Ω): −62/−78 — Differential gain/Differential phase: 0.02%/0.02˚ n Low noise 2.3nV/ n High slew rate 3000 V/µs n Supply current 11.5 mA Applications n n n n n n HDTV, NTSC & PAL video systems Video switching and distribution ADC driver DAC buffer RGB driver High speed multiplexer Connection Diagram 8-Pin SOIC 6-Pin SOT23 20103634 20103613 Top View Top View Ordering Information Package 8-Pin SOIC 6-Pin SOT23 Part Number Package Marking LMH6704MA LMH6704MA LMH6704MAX LMH6704MF B07A LMH6704MFX Transport Media 95 Units Rail 2.5k Units Tape and Reel 1k Units Tape and Reel 3k Units Tape and Reel NSC Drawing M08A MF06A LMH™ is a trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201036 www.national.com LMH6704 650 MHz Progammable Gain Buffer with Disable February 2005 LMH6704 Absolute Maximum Ratings (Note 1) ESD Tolerance (Note 4) Human Body Model If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 13.5V Common-Mode Input Voltage Storage Temperature Range ± 4V to ± 6V Nominal Supply Voltage VS− to VS+ Maximum Junction Temperature 200V Operating Ratings (Note 1) (Note 3) IOUT 2000V Machine Model Operating Temperature 150˚C −40˚C to 85˚C Thermal Resistance −65˚C to 150˚C Package Soldering Information (θJC) (θJA) 235˚C 8-Pin SOIC 75˚C/W 160˚C/W Wave Soldering (10 sec.) 260˚C 6-Pin SOT23 120˚C/W 187˚C/W Lead Temp. (soldering 10 sec.) 300˚C Infrared or Convection (20 sec.) Electrical Characteristics (Note 2) TA = +25˚C , AV = +2, VS = ± 5V, RL = 100Ω; unless specified. Symbol Parameter Conditions Min (Note 6) Typ (Note 6) Max (Note 6) Units Dynamic Performance SSBW -3 dB Bandwidth SSBW LSBW VOUT = 0.5 VPP, AV = +1 650 VOUT = 0.5 VPP 450 VOUT = 2 VPP 400 MHz GF0.1dB 0.1 dB Gain Bandwidth VOUT = 2 VPP 200 MHz SR Slew Rate VOUT = 4 VPP, 40% to 60% (Note 5) 3000 V/µs TRS/TRL Rise and Fall Time (10% to 90%) 2V Step 0.9 ns ts Settling Time to 0.1% 2V Step 10 ns VOUT = 2.0 VPP, f = 10 MHz −62 VOUT = 2.0 VPP, f = 40 MHz −52 VOUT = 2.0 VPP, f = 10 MHz −78 VOUT = 2.0 VPP, f = 40 MHz −65 Distortion and Noise Response HD2L 2nd Harmonic Distortion HD2H HD3L 3rd Harmonic Distortion HD3H IMD Two-Tone Intermodulation f = 10 MHz, POUT = 10 dBm/tone −65 VN Output Noise Voltage f = 100 kHz AV = +2 10.5 AV = +1 9.3 AV = −1 10.5 INN Non-Inverting Input Noise Current dBc dBc dBc nV/ 3 pA/ DG Differential Gain RL = 150Ω, f = 4.43 MHz .02 % DP Differential Phase RL = 150Ω, f = 4.43 MHz 0.02 deg Static, DC Performance AV Gain 1.98 1.96 Gain Error 2.00 −1 −2 VIO Input Offset Voltage 2 DVIO Input Offset Voltage Average Drift 35 IBN Input Bias Current Non-Inverting (Note 7) −5 IBI Input Bias Current Inverting 5 www.national.com 2 2.02 2.04 V/V +1 +2 % ±7 ± 8.3 mV µV/˚C ± 15 ± 18 ± 22 ± 31 µA (Continued) TA = +25˚C , AV = +2, VS = ± 5V, RL = 100Ω; unless specified. Symbol Parameter Conditions CMIR Common Mode Input Range VIO ≤ 15 mV PSRR Power Supply Rejection Ratio DC VO Output Voltage Swing RL = ∞ RL = 100Ω IO Linear Output Current IS Supply Current (Enabled) VOUT ≤ 80 mV DIS = 2V, RL = ∞ Supply Current (Disabled) DIS = 0.8V, RL = ∞ R F & RG Internal RF and RG ROUT Closed Loop Output Resistance RIN+ CIN+ Min (Note 6) Typ (Note 6) ± 1.9 ±2 V 48 47 52 dB ± 3.3 ± 3.18 ± 3.2 ± 3.12 ± 55 ± 3.5 375 Max (Note 6) Units V ± 3.5 ± 90 mA 11.5 12.5 13.7 0.25 0.9 0.925 465 563 mA Ω 0.05 Ω Input Resistance 1 MΩ Input Capacitance 1 pF ns DC Enable/Disable Performance (Disabled Low) TON Enable Time 10 TOFF Disable Time 10 ns Output Glitch 50 mVPP VIH Enable Voltage DIS ≥ VIH 2.0 VIL Disable Voltage DIS ≤ VIL IIH Disable Input Bias Current, High DIS = V+, (Note 7) IIL Disable Input Bias Current, Low DIS = 0V (Note 7) IOZ Disabled Output Leakage Current AV = +1, VOUT = ± 1.8V V 0.8 0 −1 ± 50 µA −100 −350 µA 0.2 ± 25 ± 50 µA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise specified. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations. Note 4: Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 200 pF. Note 5: Slew Rate is the average of the rising and falling edges. Note 6: Typical numbers are the most likely parametric norm. Bold numbers refer to over temperature limits. Note 7: Negative current implies current flowing out of the device. 3 www.national.com LMH6704 Electrical Characteristics (Note 2) LMH6704 Typical Performance Characteristics (TA = 25˚C, VS = ± 5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified). Small Signal Frequency Response vs. Gain Frequency Response vs. VOUT 20103614 20103615 Small Signal Frequency Response vs. RLOAD Large Signal Gain Flatness 20103616 20103617 Small Signal Frequency Response vs. Capacitive Load Series Output Isolation Resistance vs. Capacitive Load 20103618 www.national.com 20103619 4 Large Signal Pulse Response Small Signal Pulse Response 20103620 20103621 Harmonic Distortion vs. Frequency Harmonic Distortion vs. Load 20103622 20103623 Harmonic Distortion vs. Output Voltage DG/DP 20103624 20103633 5 www.national.com LMH6704 Typical Performance Characteristics (TA = 25˚C, VS = ±5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified). (Continued) LMH6704 Typical Performance Characteristics (TA = 25˚C, VS = ±5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified). (Continued) PSRR vs. Frequency DC Errors vs. Temperature (A Typical Unit, (Note 7)) 20103628 20103629 Disable Timing Disable Output Glitch 20103630 www.national.com 20103631 6 LMH6704 Application Section GENERAL INFORMATION The LMH6704 is a high speed current feedback Programmable Gain Buffer (PGB), optimized for very high speed and low distortion. With its internal feedback and gain-setting resistors the LMH6704 offers excellent AC performance while simplifying board layout and minimizing the affects of layout related parasitic components. The LMH6704 has no internal ground reference so single or split supply configurations are both equally useful. SETTING THE CLOSED LOOP GAIN The LMH6704 is a current feedback amplifier with on-chip RF = RG = 465Ω. As such it can be configured with an AV = +2, AV = +1, or an AV = −1 by connecting pins 3 and 4 as described in the chart below. 20103603 GAIN AV FIGURE 1. Recommended Gain of +2 Circuit Input Connections Non-Inverting (Pin 3) Inverting (Pin 4) −1 V/V Ground Input Signal +1 V/V Input Signal NC (Open) +2 V/V Input Signal Ground The gain accuracy of the LMH6704 is accurate and guaranteed over temperature to within ± 1%. The internal gain setting resistors, RFand RG, match very well. The LMH6704 architecture takes advantage of the fact that the internal gain setting resistors track each other well over a wide range of temperature and process variation to keep the overall gain constant, despite the fact that the individual resistors have nominal temperature drifts. Therefore, using external resistors in series with RG to change the gain will result in poor gain accuracy over temperature. 20103604 FIGURE 2. Recommended Gain of +1 Circuit 20103609 FIGURE 4. Alternate Unity Gain Configuration 20103605 FIGURE 3. Recommended Gain of −1 Circuit 7 www.national.com LMH6704 Application Section For example, if an AV = +2 configuration is used with a source impedance of 37.5Ω (parallel combination of 75Ω source and 75Ω termination impedances), where “IBN” is and the output referred voltage noise (exclud18.5pA/ ing non-inverting input noise current) can be found in Table 1 below. The total noise (EO) at the output can be calculated as: (Continued) UNITY GAIN COMPENSATION With a current feedback PGB like the LMH6704, the feedback resistor is a compromise between the value needed for stability at unity gain and the optimized value needed at a gain of two. In standard open-loop current feedback operational amplifiers the feedback resistor, RF, is external and its value can be adjusted to match the required gain. Since the feedback resistor is integrated in the LMH6704, it is not possible to adjust it’s value. However, we can employ the circuit shown in Figure 4. This circuit modifies the noise gain of the amplifier to eliminate the peaking associated with using the circuit shown in Figure 2. The frequency response is shown in Figure 5. The decreased peaking does come at a price as the output referred voltage noise density increases by a factor of 1.1. TABLE 1. Measured Output Noise Voltage Gain (AV) +2 Output Referred Voltage Noise (nV/ ), excluding non-inverting noise current 10.5 +1 9.3 +1, alternate method shown in Figure 4 10.5 -1 10.5 Note: f ≥ 100 kHz ENABLE/DISABLE 20103632 FIGURE 5. Unity Gain Frequency Response OUTPUT VOLTAGE NOISE Open-loop operational amplifiers specify three input referred noise parameters: input voltage noise, non-inverting input current noise, and inverting input current noise. These specifications are used to calculate the total voltage noise produced at the output of the amplifier. The LMH6704 is a closed loop amplifier with internal resistors, thus only the non-inverting input current noise flows through external components. All other noise sources are internal to the part. There are four possible values for the noise at the output depending on the gain configuration as shown in Table 1. For more information on calculating noise in current feedback amplifiers see Application Notes OA-12 and AN104 available at www.national.com. The total noise voltage at the output can be calculated using the following formula: www.national.com 20103612 FIGURE 6. DIS Pin Simplified Schematic The LMH6704 has a TTL logic compatible disable function. Apply a logic low ( < .8V) to the DS pin and the LMH6704 is disabled. Apply a logic high ( > 2.0V), or let the pin float and the LMH6704 is enabled. Voltage, not current, at the Disable pin (DS) determines the enable/disable state. Care must be exercised to prevent the disable pin voltage from going more than .8V below the midpoint of the supply voltages (0V with split supplies, V+/2 with single supply biasing). Doing so could cause transistor Q1 to Zener resulting in damage to the disable circuit (See Figure 6 or the simplified internal schematic diagram). The core amplifier is unaffected by this, but the disable operation could become permanently slower as a result. 8 near the input and output pins. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as close to the device as possible. In Figure 1, Figure 2, and Figure 3 CSS is optional, but is recommended for best second order harmonic distortion. Another option to using CSS is to use pairs of 0.01 µF and 0.1 µF ceramic capacitors for each supply bypass. (Continued) Disabled, the LMH6704 inputs and output become high impedances. While disabled the LMH6704 quiescent current is approximately 250 µA. Because of the pull up resistor on the disable circuit, the ICC and IEE currents (positive and negative supply currents respectively) are not balanced in the disabled state. The positive supply current (ICC) is approximately 350 µA while the negative supply current (IEE) is only 250 µA. The remaining IEE current of 100 µA flows through the disable pin. The disable function can be used to create analog switches or multiplexers. Implement a single analog switch with one LMH6704 positioned between an input and output. Create an analog multiplexer with several LMH6704’s. Use the circuit shown in for multiplexer applications because there is no RG to shunt signals to ground. EVALUATION BOARDS National Semiconductor provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. Many of the datasheet plots were measured with these boards. Device Package Evaluation Board Part Number LMH6704MA SOIC-8 CLC730227 LMH6704MF SOT23-6 CLC730216 An evaluation board is shipped upon request when a sample order is placed with National Semiconductor. 20103608 FIGURE 8. Typical Video Application VIDEO PERFORMANCE The LMH6704 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless with DG of 0.02% and DP of 0.02˚. Best performance will be obtained with back terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage. Figure 8 shows a typical configuration for driving a 75Ω Cable. The amplifier is configured for a gain of two to make up for the 6 dB of loss in ROUT. 20103606 FIGURE 7. Decoupling Capacitive Loads DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor RISO. Figure 7 shows the use of a series output resistor, RISO, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. The chart “Suggested RISO vs. Cap Load” gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of RISO can be reduced slightly from the recommended values. POWER DISSIPATION Follow these steps to determine the Maximum power dissipation for the LMH6704: 1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS), where VS = V+ - V− 2. Calculate the RMS power dissipated in the output stage: PD (rms) = rms ((VS - VOUT)*IOUT), where VOUT and IOUT are the voltage and current across the external load and VS is the total supply current 3. Calculate the total RMS power: PT = PAMP+PD The maximum power that the LMH6704, package can dissipate at a given temperature can be derived with the following equation: LAYOUT CONSIDERATIONS Whenever questions about layout arise, use the evaluation board as a guide. The CLC730216 is the evaluation board supplied with samples of the LMH6704. To reduce parasitic capacitances ground and power planes should be removed 9 www.national.com LMH6704 Application Section LMH6704 Application Section V−) which are reverse biased and essentially have no effect under most normal operating conditions. There are occasions, however, when the ESD diodes will be evident. If the LMH6704 is driven by a large signal while the device is powered down, the ESD diodes might enter forward operating region and conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to inadvertently power up the LMH6704 with a large signal applied to the input pins. Shorting the power pins to each other will prevent the chip from being powered up through the input. (Continued) PMAX = (150˚ – TAMB)/ θJA, where TAMB = Ambient temperature (˚C) and θJA = Thermal resistance, from junction to ambient, for a given package (˚C/W). For the SOT23-6 package θJA is 187˚C/W. ESD PROTECTION The LMH6704 is protected against electrostatic discharge (ESD) on all pins. The LMH6704 will survive 2000V Human Body model and 200V Machine model events. Input and Output pins have ESD diodes to either supply pin (V+ and www.national.com 10 LMH6704 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 6-Pin SOT23 NS Package Number MF06A 11 www.national.com LMH6704 650 MHz Progammable Gain Buffer with Disable Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560