CLC5633 Triple, High Output, Programmable Gain Buffer General Description The CLC5633 is a triple, low cost, high speed (130MHz) buffer which features user programmable gains of +2, +1, and −1V/V. The CLC5633 also has a new output stage that delivers high output drive current (130mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear phase response up to one half of the −3dB frequency. The CLC5633 offers 0.1dB gain flatness to 20MHz and differential gain and phase errors of 0.03% and 0.06˚. These features area ideal for professional and consumer video applications. The CLC5633 offers superior dynamic performance with a 130MHz small-signal bandwidth, 410V/µs slew rate and 5.0ns rise/fall times (2VSTEP). The combination of low quiescent power, high output current drive, and high speed performance make the CLC5633 well suited for many battery powered personal communication/computing systems. The ability to drive low impedance, highly capacitive loads, with minimum distortion makes the CLC5633 ideal for cable applications. The CLC5633 will drive a 100Ω load with only −73/−92dBc second/third harmonic distortion (AV = +2, VOUT = 2VPP, f = 1MHz). With a 25Ω load, and the same conditions, it produces only −75/−75dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high resolution A/D converters, the CLC5633 provides excellent −92/−96dBc second/third harmonic distortion (AV = +2, VOUT = 2VPP, f = 1MHz, RL = 1kΩ) and fast settling time. n n n n n n n 3.0mA/ch supply current 130MHz bandwidth (Av =+2) −92/−96dBc HD2/HD3 (1MHz) 20ns settling to 0.05% 410V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V to ± 5V supplies Applications n n n n n n n Video line driver Coaxial cable driver Twisted pair driver Transformer/coil driver High capacitive load driver Portable/battery powered applications A/D driver Maximum Output Voltage vs. RL Features DS015005-1 n 130mA output current n 0.03%, 0.06˚ differential gain, phase Connection Diagram DS015005-3 Pinout DIP & SOIC © 2000 National Semiconductor Corporation DS015005 www.national.com CLC5633 Triple, High Output, Programmable Gain Buffer December 2000 CLC5633 Typical Application DS015005-2 Single Supply Cable Driver Ordering Information Package Temperature Range Industrial Packaging Marking NSC Drawing 14-pin plastic DIP −40˚C to +85˚C CLC5633IN N14A 14-pin plastic SOIC −40˚C to +85˚C CLC5633IM M14A, M14B CLC5633IMX www.national.com 2 Lead Temperature (soldering 10 sec) ESD (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC-VEE) Output Current (See note 4) Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range +300˚C 2000V Operating Ratings +14V 140mA VEE to VCC +150˚C −65˚C to +150˚C Thermal Resistance Package MDIP SOIC (θJC) 60˚C/W 55˚C/W (θJA) 110˚C/W 125˚C/W +5 Electrical Characteristics (AV = +2, RL =100Ω, VS = +5V1, VCM = VEE + (VS/2), RL tied to VCM, unless specified. Symbol Parameter Ambient Temperature Conditions CLC5633IN/IM Typ Min/Max Ratings (Note 2) +25˚C +25˚C 0 to 70˚C −40 to 85˚C Units Frequency Domain Response -3dB Bandwidth VO = 0.5VPP 100 80 70 70 MHz VO = 2.0VPP 97 79 74 72 MHz −0.1dB Bandwidth VO = 0.5VPP 20 17 17 13 MHz Gain Peaking 0 0.5 1.0 1.0 dB 0.2 0.5 0.6 0.6 dB Linear Phase Deviation < 200MHz, VO = 0.5VPP < 30MHz, VO = 0.5VPP < 30MHz, VO = 0.5VPP 0.15 0.3 0.4 0.4 deg Differential Gain NTSC, RL = 150Ω to −1V 0.04 – – – % Differential Phase NTSC, RL = 150Ω to −1V 0.1 – – – deg Rise and Fall Time 2V Step 4.8 6.4 6.8 7.3 ns Settling Time to 0.05% 1V Step 20 24 40 60 ns Overshoot 2V Step 5 7 11 14 % Slew Rate 2V Step 290 170 150 140 V/µs Gain Rolloff Time Domain Response Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion 2VPP, 1MHz −72 - - - dBc 2VPP, 1MHz; RL = 1KΩ −84 - - - dBc 2VPP, 5MHz −71 −54 −52 −52 dBc 2VPP, 1MHz −87 - - - dBc 2VPP, 1MHz; RL =1KΩ −95 - - - dBc 2VPP, 5MHz −78 −61 −54 −54 dBc Voltage (eni) > 1MHz 4.9 5.9 6.4 6.4 nV/ Non-Inverting Current (ibn) > 1MHz 6.6 8.5 9.3 9.3 pA/ Inverting Current (ibi) > 1MHz 11.1 14.7 15.8 15.8 pA/ Crosstalk (Input Referred) 10MHz, 1VPP −54 - - - dB Crosstalk, all Hostile (Input Referred) 10MHz, 1VPP −52 - - - dB Equivalent Input Noise Static, DC Performance Input Offset Voltage (Note 3) Average Drift Input Bias Current (Non-Inverting)(Note 3) Average Drift 3 13 30 35 35 mV 80 - - - µV/˚C 5 18 24 24 µA 30 - - - nA/˚C www.national.com CLC5633 Absolute Maximum Ratings (Note 1) CLC5633 +5 Electrical Characteristics (Continued) (AV = +2, RL =100Ω, VS = +5V1, VCM = VEE + (VS/2), RL tied to VCM, unless specified. Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units ± 0.3 ± 2.0 ± 26% ± 2.0 ± 30% µA Static, DC Performance 1000 ± 1.5 ± 20% Power Supply Rejection Ratio DC 48 45 43 43 dB Common Mode Rejection Ratio DC 44 41 39 39 dB Supply Current (Per Amplifier)(Note 3) RL = ∞ 3.0 3.4 3.6 3.6 mA Input Resistance (Non-Inverting) 1.0 0.62 0.56 0.56 MΩ Input Capacitance (Non-Inverting) 2.2 3.3 3.3 3.3 pF Input Voltage Range, High 4.2 4.1 4.0 4.0 V Gain Accuracy (Note 3) Internal Resistors (Rf, Rg Ω Miscellaneous Performance Input Voltage Range, Low 0.8 0.9 1.0 1.0 V Output Voltage Range, High RL = 100Ω 4.0 3.9 3.8 3.8 V Output Voltage Range, Low RL = 100Ω 1.0 1.1 1.2 1.2 V Output Voltage Range, High RL = ∞ RL = ∞ 4.1 4.0 4.0 3.9 V 0.9 1.0 1.0 1.1 V 100 80 65 40 mA 400 600 600 600 mΩ Output Voltage Range, Low Output Current (Note 4) Output Resistance, Closed Loop DC ± 5 Electrical Characteristics (AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) Symbol Parameter Ambient Temperature Conditions CLC5633IN/IM Typ Min/Max Ratings (Note 2) Units +25˚C +25˚C 0 to 70˚C −40 to 85˚C VO = 1.0VPP 130 100 90 90 MHz VO = 4.0VPP 80 60 55 55 MHz −0.1dB Bandwidth VO = 1.0VPP 20 17 12 12 MHz Gain Peaking 0 0.5 1.0 1.0 dB 0.1 0.3 0.5 0.5 dB Linear Phase Deviation < 200MHz, VO = 1.0VPP < 30MHz, VO = 1.0VPP < 30MHz, VO = 1.0VPP 0.2 0.4 0.6 0.6 deg Differential Gain NTSC, RL = 150Ω 0.03 0.08 – – % Differential Phase NTSC, RL = 150Ω 0.06 0.1 – – deg 2V Step 5.0 6.5 7.0 7.7 ns ns Frequency Domain Response -3dB Bandwidth Gain Rolloff Time Domain Response Rise and Fall Time Settling Time to 0.05% 2V Step 20 30 44 67 Overshoot 2V Step 14 17 18 19 % Slew Rate 2V Step 410 310 240 225 V/µs Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion 2VPP, 1MHz −73 – – – dBc 2VPP, 1MHz; RL = 1kΩ −92 – – – dBc 2VPP, 5MHz −69 −58 −56 −56 dBc 2VPP, 1MHz −92 – – – dBc 2VPP, 1MHz; RL = 1kΩ −96 – – – dBc 2VPP, 5MHz −72 −66 −65 −65 dBc Equivalent Input noise www.national.com 4 CLC5633 ± 5 Electrical Characteristics (Continued) (AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units Distortion And Noise Response Voltage (eni) > 1MHz 4.9 5.9 6.4 6.4 nV/ Non-Inverting Current (ibn) > 1MHz 6.6 8.5 9.3 9.0 pA/ Inverting Current (ibi) > 1MHz 11.1 14.7 15.8 15.8 pA/ Crosstalk (Input Referred) 10MHz, 1VPP −54 - - - dB Crosstalk, all Hostile (input referred) 10MHz, 1VPP −52 - - - dB 7 30 35 35 mV Static, DC Performance Input Offset Voltage Average Drift 80 - - - µV/˚C Input Bias Current (Non-Inverting) 5 18 25 25 µA Average Drift 40 - - - nA/˚C ± 0.3 ± 2.0 ± 26% ± 2.0 ± 30% % 43 43 dB 1000 ± 1.5 ± 20% Power Supply Rejection Ratio DC 48 45 Common Mode Rejection Ratio DC RL = ∞ 44 41 39 39 dB 3.2 3.8 4.0 4.0 mA Gain Accuracy Internal Resistors (Rf, Rg) Supply Current (per amplifier) Ω Miscellaneous Performance Input Resistance (Non-inverting) 1.1 0.63 0.57 0.57 MΩ Input Capacitance (Non-Inverting) 1.9 2.85 2.85 2.85 pF ± 4.2 ± 3.8 ± 4.0 ± 4.1 ± 3.6 ± 3.8 ± 4.1 ± 3.6 ± 3.8 ± 4.0 ± 3.5 ± 3.7 V 130 100 80 50 mA 400 600 600 600 mΩ Common Mode Input Range Output Voltage Range RL = 100Ω Output Voltage Range RL = ∞ Output Current (Note 4) Output Resistance, Closed Loop DC V V Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Note 4: The short circuit current can exceed the maximum safe output current Note 5: VS = VCC − VEE 5 www.national.com Frequency Response vs. RL Av = -1 Phase Vo = 0.5Vpp Magnitude (1dB/div) Gain 0 -90 Av = +2 -180 -270 RL = 1kΩ Gain Phase 0 -90 RL = 25Ω -180 RL = 100Ω -270 -360 -360 -450 1M 10M Phase (deg) Av = +1 Vo = 0.5Vpp Phase (deg) Normalized Magnitude (1dB/div) Frequency Response -450 1M 100M 10M Frequency (Hz) 100M Frequency (Hz) DS015005-4 Gain Flatness & Linear Phase DS015005-5 Frequency Response vs. VO (AV = 2) 0.05 Vo = 0.5Vpp Magnitude (0.05dB/div) Gain -0.1 Phase (deg) -0.05 Phase Vo = 0.1Vpp Magnitude (1dB/div) 0 -0.15 Vo = 1Vpp Vo = 2Vpp Vo = 2.5Vpp -0.2 0 10 20 1M 30 10M 100M Frequency (Hz) Frequency (MHz) DS015005-7 DS015005-6 Frequency Response vs. VO (AV = 1) Frequency Response vs. VO (AV = −1) Vo = 0.1Vpp Vo = 0.1Vpp Magnitude (1dB/div) Magnitude (1dB/div) CLC5633 +5V Typical Performance Characteristics Vo = 1.5Vpp Vo = 2Vpp Vo = 2.5Vpp 1M 10M 100M Vo = 2.5Vpp 10M 100M Frequency (Hz) DS015005-8 www.national.com Vo = 2Vpp 1M Frequency (Hz) Vo = 1Vpp DS015005-9 6 PSRR & CMRR (Continued) Equivalent Input Noise 12.5 3.6 60 Noise Voltage (nV/√Hz) CMRR 50 PSRR 40 30 20 10 0 10 3.5 Inverting Current 8.7pA/√Hz 3.4 Voltage 3.35nV/√Hz 5 3.3 2.5 3.2 1k 10k 100k 1M 10M 10k 100M 100k Frequency (Hz) 1M 10M Frequency (Hz) DS015005-10 2nd & 3rd Harmonic Distortion DS015005-11 2nd & 3rd Harmonic Distortion, RL = 25Ω -40 -50 Vo = 2Vpp -60 3rd, 10MHz 2nd RL = 100Ω Distortion (dBc) Distortion (dBc) 7.5 Non-Inverting Current 7pA/√Hz Noise Current (pA/√Hz) PSRR & CMRR (dB) CLC5633 +5V Typical Performance Characteristics -70 2nd RL = 1kΩ -80 3rd RL = 1kΩ -90 -60 2nd, 1MHz -70 3rd, 1MHz 3rd RL = 100Ω -100 2nd, 10MHz -50 -80 1M 0 10M Frequency (Hz) 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) DS015005-12 2nd & 3rd Harmonic Distortion, RL = 100Ω DS015005-13 2nd & 3rd Harmonic Distortion, RL = 1kΩ -50 -55 3rd, 10MHz 3rd, 10MHz -65 Distortion (dBc) Distortion (dBc) -60 2nd, 1MHz -75 2nd, 10MHz -85 2nd, 10MHz -70 -80 2nd, 1MHz -90 3rd, 1MHz -100 3rd, 1MHz -110 -95 0 0.5 1 1.5 2 0 2.5 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) Output Amplitude (Vpp) DS015005-14 DS015005-15 7 www.national.com (Continued) Output Impedance vs. Frequency Large & Small Signal Pulse Response Output Voltage (0.05V/div) 50 Output Impedance (Ω) Large Signal Small Signal 40 30 20 10 0 Time (10ns/div) 1k DS015005-16 10k 100k 1M 10M 100M Frequency (Hz) DS015005-17 2.5 7.5 1.5 7 0 6.5 0.5 6 IBN -1.5 IBN (µA) Offset Voltage VIO (mV) IBN, VIO vs. Temperature 5.5 VIO 5 -2.5 -60 -40 -20 0 20 40 80 60 100 Temperature (ϒC) DS015005-18 ± 5V Typical Performance Characteristics Frequency Response (AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) Frequency Response vs. RL Phase (deg) Av = +1 Av = -1 Gain Phase Vo = 1.0Vpp Magnitude (1dB/div) Vo = 1.0Vpp 0 -45 -90 Av = +2 -135 RL = 1kΩ Gain RL = 100Ω Phase 0 -90 -180 RL = 25Ω -270 -360 -180 -450 -225 1M 10M 1M 100M Frequency (Hz) 10M 100M Frequency (Hz) DS015005-19 www.national.com Phase (deg) Normalized Magnitude (1dB/div) CLC5633 +5V Typical Performance Characteristics DS015005-20 8 CLC5633 ± 5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) (Continued) Gain Flatness & Linear Phase Frequency Response vs. VO (AV = 2) 0 Vo = 0.1Vpp -0.2 -0.3 Phase Magnitude (1dB/div) -0.1 Gain Phase (deg) Magnitude (0.1dB/div) VO = 1Vpp -0.4 Vo = 2Vpp Vo = 5Vpp Vo = 1Vpp -0.5 0 5 10 15 20 1M 30 25 100M 10M Frequency (Hz) Frequency (MHz) DS015005-22 DS015005-21 Frequency Response vs. VO (AV = 1) Frequency Response vs. VO (AV = −1) Vo = 1Vpp Vo = 1Vpp Magnitude (1dB/div) Magnitude (1dB/div) Vo = 0.1Vpp Vo = 5Vpp Vo = 2Vpp 1M 10M 100M Vo = 5Vpp Vo = 2Vpp 1M 10M Frequency (Hz) 100M Frequency (Hz) DS015005-23 Large & Small Signal Pulse Response DS015005-24 Differential Gain and Phase 0.02 Large Signal -0.02 f = 3.58MHz 0 -0.04 Phase Neg Sync -0.06 -0.02 Gain (%) Small Signal Gain Neg Sync -0.04 -0.08 -0.06 -0.1 -0.08 -0.12 Phase Pos Sync Gain Pos Sync -0.1 -0.14 -0.12 Time (10ns/div) -0.16 1 DS015005-25 Phase (deg) Output Voltage (0.5V/div) Vo = 0.1Vpp 2 3 4 Number of 150 Ω Loads DS015005-26 9 www.national.com 2nd & 3rd Harmonic Distortion vs. Frequency (AV = +2, RL = 100Ω, VCC = ± 5V, unless 2nd & 3rd Harmonic Distortion, RL = 25Ω -45 2nd, 10MHz Distortion (dBc) -50 3rd, 10MHz -55 -60 -65 -70 2nd, 1MHz -75 -80 3rd, 1MHz -85 0 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) DS015005-28 DS015005-27 2nd & 3rd Harmonic Distortion, RL = 100Ω 2nd & 3rd Harmonic Distortion, RL = 1kΩ -60 -60 3rd, 10MHz -65 -70 Distortion (dBc) Distortion (dBc) 2nd, 10MHz -70 2nd, 10MHz -75 2nd, 1MHz -80 -85 3rd, 1MHz 3rd, 10MHz -80 -90 2nd, 1MHz 3rd, 1MHz -100 -90 -95 -110 0 0.5 1 1.5 2 2.5 0 1 Output Amplitude (Vpp) 2 3 4 5 Output Amplitude (Vpp) DS015005-29 Short Term Settling Time DS015005-30 Long Term Settling Time 0.2 0.2 Vo = 2V step Vo = 2V step 0.15 0.15 Vo (% Output Step) Vo (% Output Step) CLC5633 ± 5V Typical Performance Characteristics specified) (Continued) 0.1 0.05 0 -0.05 -0.1 -0.15 0 -0.05 -0.1 -0.15 -0.2 -0.2 1 10 100 1000 10000 1µ Time (ns) 10µ 100µ 1m 10m Time (s) DS015005-31 www.national.com 0.1 0.05 DS015005-32 10 CLC5633 ± 5V Typical Performance Characteristics (AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) (Continued) Channel Matching 2.5 7.0 1.5 6.5 0.5 6.0 -0.5 VOS 5.5 -1.5 IBN 5.0 -60 -20 20 60 Channel 2 Magnitude (0.5dB/div) 7.5 IBN (µA) Offset Voltage VOS(mV) IBN, VOS vs. Temperature Channel 3 Channel 1 -2.5 100 1M Temperature (ϒC) 10M 100M Frequency (Hz) DS015005-33 DS015005-34 All Hostile Crosstalk Pulse Crosstalk Active Output Channel 1 Magnitude (dB) -40 -50 -60 Inactive Output Channel 2 Inactive Output Channel 3 Inactive Channel Amplitude (20mV/div) Active Channel Amplitude (0.2V/div) -30 -70 Time (10ns/div) -80 1M 10M DS015005-36 100M Frequency (Hz) DS015005-35 Application Division CLC5633 Operation The CLC5633 is a current feedback buffer fabricated in an advanced complementary bipolar process. The CLC5633 operates from a single 5V supply or dual ± 5V supplies. Operating from a single 5V supply, the CLC5633 has the following features: • Gains of +1, −1, and 2V/V are achievable without external resistors • Provides 100mA of output current while consuming only 15mW of power • • Offers low −84/−95dBc 2nd and 3rd harmonic distortion Current Feedback Amplifiers Some of the key features of current feedback technology are: • Independence of AC bandwidth and voltage gain • Inherently stable at unity gain • Adjustable frequency response with feedback resistor • High slew rate • Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. Provides BW > 90MHz and 1MHz distortion < −70dBc at VO = 2VPP Vo = Vin The CLC5633 performance is further enhanced in ± 5V supply applications as indicated in the ± 5V Electrical Characteristics table and ± 5V Typical Performance plots. If gains other than +1, −1, or +2V/V are required, then the CLC5602 can be used. The CLC5602 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors. Av Rf 1+ Z(jω ) (1) where: • • 11 AV is the closed loop DC voltage gain Rf is the feedback resistor www.national.com Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. • Z(jω) is the CLC5633’s open loop transimpedance gain • Z(jω)/Rf is the loop gain The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the −3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: • Decreases loop gain • Decreases bandwidth • Reduces gain peaking • Lowers pulse response overshoot • Affects frequency response phase linearity CLC5633 Design Information Closed Loop Gain Selection The CLC5633 is a current feedback op amp with Rf = Rg = 1kΩ on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and −1V/V by connecting pins 5 and 6 (or 9 and 10, or 12 and 13) as described in the chart below. Channel 2 and 3 not shown. VCC 6.8µF 0.1µF 4 −1V/V ground input signal +1V/V input signal NC (open) +2V/V input signal ground Vin - + 11 10 + - 6 Rt Vcm 1kΩ 9 1kΩ Vo 7 RL Vcm 8 CLC5633 Vcm Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ. DS015005-39 FIGURE 1. DC Coupled, AV = −1V/V Configuration Note: Rt and RL are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 and 3 not shown. VCC 6.8µF 1 14 1kΩ 2 + 13 1kΩ 3 4 Vin 12 1kΩ 1kΩ - + 11 5 Rt 6 10 + - 1kΩ 9 1kΩ Vo 7 RL Vcm 8 CLC5633 Vcm DS015005-40 The gain accuracy of the CLC5633 is excellent and stable over temperature change. The internal gain setting resistors, Rf and Rg are diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of −2000ppm/˚C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer. Single Supply Operation (VCC =+5V, VEE=GND) FIGURE 2. DC Coupled, AV = +1V/V Configuration Note: Rt and RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 and 3 not shown. VCC 6.8µF 1 14 1kΩ 2 + The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5633 is typically +0.8V to +4.2V. The typical output range with RL =100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. DC Coupled Single Supply Operation 1kΩ 3 0.1µF 4 Vin Rt Vcm 6 13 12 1kΩ 1kΩ - + 5 Vcm 11 10 + - 1kΩ 9 1kΩ Vo 7 RL 8 CLC5633 Vcm DS015005-41 FIGURE 3. DC Coupled, AV = +2V/V Configuration Figure 1, Figure 2, and Figure 3 on the following page, show the recommended configurations for input signals that remain above 0.8V DC. Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 and 3 not shown. www.national.com 12 1kΩ 1kΩ 5 Rb 13 - + Inverting (pins 6, 9, & 13) 1kΩ 3 Input Connections Non-Inverting (pins 5, 10, & 12) 14 1kΩ 0.1µF Gain AV 1 2 + - + CLC5633 (Continued) - + Application Division AC Coupled Single Supply Operation Figure 4, Figure 5, and Figure 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. 12 Dual Supply Operation (Continued) The CLC5633 operates on dual supplies as well as signal supplies. The non-inverting and inverting configurations are shown in Figure 7, Figure 8, and Figure 9. Note: Channel 2 and 3 not shown. 1 6.8µF 2 VCC - + + 1kΩ 3 0.1µF 1kΩ 1kΩ - + Vo = − Vin + 2.5 Low frequency cutoff = where Rg = 1kΩ. 0.1µF 9 Vin Rb 11 10 + - 6 Rt 13 12 - + 5 8 0.1µF 1kΩ 9 1kΩ Vo 7 + 8 6.8µF CLC5633 1 , 2πR gCC 1kΩ 1kΩ 1kΩ 4 1kΩ 7 14 1kΩ 2 3 1kΩ Vo 1 11 10 + - 6 CC VCC 6.8µF + 5 Vin 13 12 4 R R Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ. Channel 2 and 3 not shown. 14 1kΩ - + VCC CLC5633 VEE DS015005-45 FIGURE 7. Dual Supply, AV = −1V/V Configuration DS015005-42 FIGURE 4. AC Coupled, AV = −1V/V Configuration Note: Channel 2 and 3 not shown. VCC 6.8µF 3 14 - + 1kΩ 3 0.1µF CC 1 4 R - + 6 C R where Rin = 2 10 9 7 6.8µF FIGURE 8. Dual Supply, AV = +1V/V Configuration 8 Note: Channel 2 and 3 not shown. VCC DS015005-43 6.8µF 1 14 1kΩ 2 + 1kΩ 3 0.1µF Note: Channel 2 and 3 not shown. Vin CC 1 R 2 1kΩ 4 6 C Vo Vo = 2Vin + 2.5 Low frequency cutoff = where Rin = R 2 1 , 2πRinCC R >> R source 13 - + 6 Vo 11 10 + - 0.1µF 1kΩ 9 1kΩ 7 + 8 CLC5633 11 10 + - - + 6.8µF 12 1kΩ 1kΩ 5 R Rt 1kΩ 13 12 1kΩ 1kΩ 5 14 3 0.1µF 4 Vin - + + VCC VEE DS015005-46 9 FIGURE 5. AC Coupled, AV = +1V/V Configuration 6.8µF + 8 CLC5633 1 , 2πRinCC R >> R source VCC 0.1µF 1kΩ + - 1kΩ 7 Vo = 2Vin + 2.5 Low frequency cutoff = 11 CLC5633 1kΩ Vo Vo 10 + - - + 1kΩ 11 5 R 6 Rt 13 12 1kΩ 1kΩ 5 13 12 1kΩ 1kΩ 4 Vin 1kΩ VCC Vin 0.1µF 2 + 1kΩ - + 6.8µF 14 1kΩ Note: Channel 2 and 3 not shown. VCC 1 2 + - + The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V). VEE DS015005-47 1kΩ 9 FIGURE 9. Dual Supply, AV = + 2V/V Configuration 8 Load Termination The CLC5633 can source and sink near equal amounts of current. For optimum performance, the load should be tied to VCM. 1kΩ 7 CLC5633 DS015005-44 FIGURE 6. AC Coupled, AV = +2V/V Configuration 13 www.national.com CLC5633 Application Division Note: Channel 2 and 3 not shown. Driving Cables and Capacitive Loads 1 14 1kΩ R1 When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5633 will improve stability and settling performance. The Frequency Response vs. CL plot, shown below in Figure 10, gives the recommended series resistance value for optimum flatness at various capacitive loads. Z0 1kΩ 3 V2 +- R2 R4 V1 +- R3 2 4 - + 5 Z0 6 13 12 1kΩ 1kΩ 11 10 + - 1kΩ 9 1kΩ R5 7 8 CLC5633 R6 C6 Vo = 1Vpp Magnitude (1dB/div) CLC5633 (Continued) - + Application Division CL = 10pF Rs = 49.9Ω Power Dissipation Follow these steps to determine the power consumption of the CLC5633: 1. Calculate the quiescent (no-load) power: Pamp=ICC (VCCVEE) 2. Calculate the RMS power at the output stage: PO =(VCCVLOAD)(ILOAD), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt =Pamp+PO Rs 1k CL 1k 1k 1M 10M 100M Frequency (Hz) The maximum power that the DIP and SOIC, packages can dissipate at a given temperature is illustrated in Figure 12. The power derating curve for any CLC5633 package can be derived by utilizing the following equation: DS015005-48 FIGURE 10. Frequency Response vs. CL Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 11 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-Inverting gain applications: • Connect pin 2 as indicated in the table in the Closed Loop Gain Selection section. • • Make R1, R2, R6, and R7 equal to ZO. where Tamb = Ambient temperature (˚C) θJA = Thermal resistance, from junction to ambient, for a given package (˚C/W) Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Inverting gain applications: • Connect R3 directly to ground. • Make the resistors R4, R6, and R7 equal to ZO. • Make R5\Rg =ZO. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. DS015005-51 FIGURE 12. Power Derating Curve www.national.com R7 DS015005-49 CL = 1000pF Rs = 6.7Ω - Vo FIGURE 11. Transmission Line Matching CL = 100pF Rs = 21Ω + Z0 14 • (Continued) Layout Considerations • Place the 6.8µF capacitors within 0.75 inches of the power pins. • Place the 0.1µF capacitors less than 0.1 inches from the power pins. • Figure 13 below shows the CLC5633 driving 10m of 75Ω coaxial cable. The CLC5633 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at VO. The response after 10m of cable is illustrated in Figure 14. +5V 1 6.8µF + 2 Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. +5V Vin 1kΩ 3 0.1µF 0.1µF 14 5kΩ 4 Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information A data sheet is available for the CLC730075/CLC730074 evaluation boards. The evaluation board data sheets provide: 5kΩ 0.1µF 13 12 1kΩ 1kΩ - + 5 • Note: Channel 2 and 3 not shown. 1kΩ - + Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Reproduce typical DC, AC, Transient, and Noise performance • Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. Application Circuits Single Supply Cable Driver A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC5633 (CLC730075-DIP, CLC730074-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: • CLC5633 Application Division 11 10 + - 6 1kΩ 9 75Ω 10m of 75Ω Coaxial Cable 1kΩ 7 8 0.1µF Vo 75Ω CLC5633 DS015005-52 FIGURE 13. Single Supply Cable Driver • Evaluation board schematics • Evaluation board layouts • General information about the boards The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Special Evaluation Board Considerations for the CLC5633 To optimize off-isolation of the CLC5633, cut the Rf trace on both the CLC730074 and the CLC730075 evaluation boards. This cut minimizes capacitive feedthrough between the input and the output. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: • Support Berkeley SPICE 2G and its many derivatives 100mV/div Vin = 10MHz, 0.5Vpp 20ns/div DS015005-53 FIGURE 14. Response After 10m of Cable 15 www.national.com CLC5633 Physical Dimensions inches (millimeters) unless otherwise noted 14-Pin SOIC NSC Package Number M14A 14-Pin SOIC NSC Package Number M14B www.national.com 16 CLC5633 Triple, High Output, Programmable Gain Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Pin MDIP NSC Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.