SLVS521B − JULY 2004 − REVISED OCTOBER 2004 D Available in the Texas Instruments D D D D D D D D D D NanoStar Chip Scale Package Fixed/ADJ Versions Output Tolerance of: − 0.75% (A Grade) − 1.25% (Standard Grade) Ultra-Low Dropout, Typically − 200 mV at Full Load of 100 mA − 7 mV at 1 mA Wide VIN Range . . . 16 V Max Low IQ . . . 600 µA Typ at Full Load of 100 mA Shutdown Current . . . 0.01 µA Typ Fast Transient Response to Line and Load Overcurrent and Thermal Protection High Peak Current Capability Portable Applications − Mobile Phones − Laptops − Personal Digital Assistants (PDAs) − Digital Cameras and Camcorders − CD and MP3 Players DBV (SOT-23) PACKAGE (TOP VIEW) VIN GND ON/OFF 1 5 VOUT 4 ADJ/NC† 2 3 YEQ, YEU, YZQ, OR YZU (WCSP) PACKAGE (TOP VIEW) GND ADJ/NC† VOUT 1 5 ON/OFF 2 3 4 VIN † Must be left open in fixed-output versions description/ordering information The LP2981 family of fixed-output, low-dropout regulators offers exceptional, cost-effective performance for both portable and nonportable applications. Available in adjustable version and in fixed voltages of 1.8 V, 2.5 V, 2.7 V, 2.8 V, 2.9 V, 3 V, 3.2 V, 3.3 V, 3.6 V, and 5 V, the family has an output tolerance of 0.75% for the A-grade devices (1.25% for the standard grade) and is capable of delivering 100-mA continuous load current. Standard regulator features, such as over-current and over-temperature protection, are included. The LP2981 has features that make the regulator an ideal candidate for a variety of portable applications: • • • • Low dropout: A PNP pass element allows a typical dropout of 200 mV at 100-mA load current and 7 mV at 1-mA load. Low quiescent current: The use of a vertical PNP process allows for quiescent currents that are considerably lower than those associated with traditional lateral PNP regulators. Shutdown: A shutdown feature is available, allowing the regulator to consume only 0.01 µA when the ON/OFF pin is pulled low. Small packaging: For the most space-constraint needs, the regulator is available in SOT-23 package and NanoStar chip scale packaging. NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar is a trademark of Texas Instruments. Copyright 2004, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 description/ordering information (continued) ORDERING INFORMATION TJ PART GRADE VOUT (NOM) ADJ 1.25 V 1.8 V 2.5 V 2.7 V 2.8 V −40°C to 125°C A grade: 0.75% tolerance ORDERABLE PART NUMBER PACKAGE† SOT23-5 (DBV) 2.9 V 3V 3.2 V 3.3 V 3.6 V 5V Reel of 3000 LP2981DBVR Reel of 250 LP2981DBVT Reel of 3000 LP2981A-125DBVR Reel of 250 LP2981A-125DBVT Reel of 3000 LP2981A-18DBVR Reel of 250 LP2981A-18DBVT Reel of 3000 LP2981A-25DBVR Reel of 250 LP2981A-25DBVT Reel of 3000 LP2981A-27DBVR Reel of 250 LP2981A-27DBVT Reel of 3000 LP2981A-28DBVR Reel of 250 LP2981A-28DBVT Reel of 3000 LP2981A-29DBVR Reel of 250 LP2981A-29DBVT Reel of 3000 LP2981A-30DBVR Reel of 250 LP2981A-30DBVT Reel of 3000 LP2981A-32DBVR Reel of 250 LP2981A-32DBVT Reel of 3000 LP2981A-33DBVR Reel of 250 LP2981A-33DBVT Reel of 3000 LP2981A-36DBVR Reel of 250 LP2981A-36DBVT Reel of 3000 LP2981A-50DBVR Reel of 250 LP2981A-50DBVT TOP-SIDE MARKING‡ PREVIEW PREVIEW PREVIEW PREVIEW PREVIEW LP6_ PREVIEW LP8_ PREVIEW LPC_ PREVIEW PREVIEW † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV: The actual top-side marking has one additional character that designates the assembly/test site. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) ORDERABLE PART NUMBER PACKAGE† ADJ LP2981YEQR 1.25 V LP2981A-125YEQR 1.8 V LP2981A-18YEQR 2.5 V LP2981A-25YEQR 2.7 V 2.8 V −40°C to 125°C A grade: 0.75% tolerance LP2981A-27YEQR NanoStar − WCSP 0.17-mm Bump (YEQ) Reel of 3000 LP2981A-28YEQR 2.9 V LP2981A-29YEQR 3V LP2981A-30YEQR 3.2 V LP2981A-32YEQR 3.3 V LP2981A-33YEQR 5V LP2981A-50YEQR ADJ LP2981YZQR 1.25 V LP2981A-125YZQR 1.8 V LP2981A-18YZQR 2.5 V LP2981A-25YZQR 2.7 V 2.8 V 2.9 V TOP-SIDE MARKING‡ NanoFree − WCSP 0.17-mm Bump (YZQ, Pb-free) LP2981A-27YZQR Reel of 3000 LP2981A-28YZQR LP2981A-29YZQR 3V LP2981A-30YZQR 3.2 V LP2981A-32YZQR 3.3 V LP2981A-33YZQR 5V LP2981A-50YZQR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ YEQ/YZQ: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) ORDERABLE PART NUMBER PACKAGE† ADJ LP2981YEUR 1.25 V LP2981A-125YEUR 1.8 V LP2981A-18YEUR 2.5 V LP2981A-25YEUR 2.7 V 2.8 V −40°C to 125°C A grade: 0.75% tolerance LP2981A-27YEUR NanoStar − WCSP 0.30-mm Bump (YEU) Reel of 3000 LP2981A-28YEUR 2.9 V LP2981A-29YEUR 3V LP2981A-30YEUR 3.2 V LP2981A-32YEUR 3.3 V LP2981A-33YEUR 5V LP2981A-50YEUR ADJ LP2981YZUR 1.25 V LP2981A-125YZUR 1.8 V LP2981A-18YZUR 2.5 V LP2981A-25YZUR 2.7 V 2.8 V 2.9 V TOP-SIDE MARKING‡ NanoFree − WCSP 0.30-mm Bump (YZU, Pb-free) LP2981A-27YZUR Reel of 3000 LP2981A-28YZUR LP2981A-29YZUR 3V LP2981A-30YZUR 3.2 V LP2981A-32YZUR 3.3 V LP2981A-33YZUR 5V LP2981A-50YZUR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) ADJ 1.25 V 1.8 V 2.5 V 2.7 V 2.8 V −40°C to 125°C Standard grade: 1.25% tolerance ORDERABLE PART NUMBER PACKAGE† SOT-23 (DBV) 2.9 V 3V 3.2 V 3.3 V 3.6 V 5V Reel of 3000 LP2981DBVR Reel of 250 LP2981DBVT Reel of 3000 LP2981-125DBVR Reel of 250 LP2981-125DBVT Reel of 3000 LP2981-18DBVR Reel of 250 LP2981-18DBVT Reel of 3000 LP2981-25DBVR Reel of 250 LP2981-25DBVT Reel of 3000 LP2981-27DBVR Reel of 250 LP2981-27DBVT Reel of 3000 LP2981-28DBVR Reel of 250 LP2981-28DBVT Reel of 3000 LP2981-29DBVR Reel of 250 LP2981-29DBVT Reel of 3000 LP2981-30DBVR Reel of 250 LP2981-30DBVT Reel of 3000 LP2981-32DBVR Reel of 250 LP2981-32DBVT Reel of 3000 LP2981-33DBVR Reel of 250 LP2981-33DBVT Reel of 3000 LP2981-36DBVR Reel of 250 LP2981-36DBVT Reel of 3000 LP2981-50DBVR Reel of 250 LP2981-50DBVT TOP-SIDE MARKING‡ PREVIEW PREVIEW PREVIEW PREVIEW PREVIEW LP5_ PREVIEW LP7_ PREVIEW LPB_ PREVIEW PREVIEW † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV: The actual top-side marking has one additional character that designates the assembly/test site. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) ORDERABLE PART NUMBER PACKAGE† ADJ LP2981YEQR 1.25 V LP2981−125YEQR 1.8 V LP2981−18YEQR 2.5 V LP2981-25YEQR 2.7 V 2.8 V −40°C to 125°C Standard grade: 1.25% tolerance LP2981-27YEQR NanoStar − WCSP 0.17-mm Bump (YEQ) Reel of 3000 LP2981-28YEQR 2.8 V LP2981-29YEQR 3V LP2981-30YEQR 3.2 V LP2981-32YEQR 3.3 V LP2981-33YEQR 5V LP2981-50YEQR ADJ LP2981YZQR 1.25 V LP2981−125YZQR 1.8 V LP2981−18YZQR 2.5 V LP2981-25YZQR 2.7 V 2.8 V 2.8 V TOP-SIDE MARKING‡ NanoFree − WCSP 0.17-mm Bump (YZQ, Pb-free) LP2981-27YZQR Reel of 3000 LP2981-28YZQR LP2981-29YZQR 3V LP2981-30YZQR 3.2 V LP2981-32YZQR 3.3 V LP2981-33YZQR 5V LP2981-50YZQR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ YEQ/YZQ: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) ORDERABLE PART NUMBER PACKAGE† ADJ LP2981YEUR 1.25 V LP2981−125YEUR 1.8 V LP2981−18YEUR 2.5 V LP2981-25YEUR 2.7 V 2.8 V −40°C to 125°C Standard grade: 1.25% tolerance LP2981-27YEUR NanoStar − WCSP 0.30-mm Bump (YEU) Reel of 3000 LP2981-28YEUR 2.8 V LP2981-29YEUR 3V LP2981-30YEUR 3.2 V LP2981-32YEUR 3.3 V LP2981-33YEUR 5V LP2981-50YEUR ADJ LP2981YZUR 1.25 V LP2981−125YZUR 1.8 V LP2981−18YZUR 2.5 V LP2981-25YZUR 2.7 V 2.8 V 2.8 V TOP-SIDE MARKING‡ NanoFree − WCSP 0.30-mm Bump (YZU, Pb-free) LP2981-27YZUR Reel of 3000 LP2981-28YZUR LP2981-29YZUR 3V LP2981-30YZUR 3.2 V LP2981-32YZUR 3.3 V LP2981-33YZUR 5V LP2981-50YZUR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 functional block diagram VIN ON/OFF VREF 1.23 V − + ADJ/NC† R1 VOUT Overcurrent/ Overtemperature Protection R2 GND † Fixed versions: Must be left open ADJ versions: R1 = ∞, R2 = ∞ Figure 1 basic application circuit LP2981A-xxDBVR (Fixed Version) VIN 1 VOUT 5 3.3 µF† 1 µF† GND 2 ON/OFF‡ 3 4 NC§ † Minimum Cout value for stability (can be increased without limit for improved stability and transient response) ‡ ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. § Must be left open Figure 2 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 basic application circuit (continued) LP2981-xxDBVR (Adjustable Version) VIN 1 ǒ R VOUT = VREF 1 ) ADJ R1 5 Ǔ 3.3 µF† 1 µF† GND 2 ON/OFF‡ 3 RADJ 4 ADJ R1 3 39.5 kW‡ † Minimum Cout value for stability (can be increased without limit for improved stability and transient response) ‡ See Application Information Figure 3 absolute maximum ratings over the virtual junction temperature range (unless otherwise noted)† Continuous input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V ON/OFF input voltage range, VON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 9 V Input/output voltage differential range, VIN-VOUT (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V Output current, IOUT (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited (short-circuit protected) Package thermal impedance, θJA (see Notes 3 and 4): DBV package . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W YEQ/YZQ package . . . . . . . . . . . . . . . . . . TBD°C/W YEU/YZU package . . . . . . . . . . . . . . . . . . . TBD°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. If load is returned to a negative power supply, the output must be diode clamped to GND. 2. The PNP pass transistor has a parasitic diode connected between the input and output. This diode normally is reverse biased (VIN > VOUT), but will be forward biased if the output voltage exceeds the input voltage by a diode drop (see Application Information for more details). 3. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 4. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 recommended operating conditions MIN VIN VON/OFF Supply input voltage VIN-VOUT IOUT Input-output differential ON/OFF input voltage MAX 16 V 0 VIN 11 V 100 mA 125 °C 0.7 Output current Virtual junction temperature TJ † Minimum VIN of 2.2 V is needed for proper biasing of LDO control circuitry. UNIT 2.2† −40 V electrical characteristics at specified free-air temperature range, VIN = VOUT(NOM) + 1 V, VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF, ADJ version: ADJ connected to VOUT (unless otherwise noted) LP2981A-XX PARAMETER nVOUT nVOUT/nVIN TEST CONDITIONS Output voltage IL = 1 mA tolerance IL = 1 mA to 100 mA (see Note 5) Output voltage VIN = line regulation [VOUT(NOM) + 1 V] to 16 V TA MIN 25°C −0.75 25°C −40°C to 125°C IL = 1 mA −40°C to 125°C −2 2 −3.5 3.5 0.007 1 7 70 −40°C to 125°C 80 IGND 200 −40°C to 125°C 600 −40°C to 125°C VON/OFF < 0.3 V (OFF) VON/OFF < 0.15 V (OFF) ON/OFF input voltage (see Note 7) High = O/P ON 200 250 375 95 65 95 125 110 80 110 170 300 200 300 550 800 600 1500 0.01 0.8 0.01 0.8 0.05 2 0.05 2 −40°C to 125°C 5 5 1.4 1.4 1.6 −40°C to 125°C µA 800 25°C −40°C to 125°C mV 150 250 −40°C to 105°C 25°C Low = O/P OFF 100 1500 25°C VON/OFF 70 15 100 550 25°C IL = 100 mA 10 170 25°C IL = 25 mA 3 7 125 25°C Ground pin current 10 375 65 %/V 5 150 200 25°C IL = 1 mA 1 15 −40°C to 125°C −40°C to 125°C 3 %VNOM 0.014 0.032 5 25°C IL = 0 0.007 0.032 −40°C to 125°C IL = 100 mA 0.014 UNIT 1.25 1 25°C IL = 25 mA MAX 2.5 25°C VIN-VOUT TYP 0.75 −1.25 −40°C to 125°C −40°C to 125°C MIN −1 25°C IL = 0 MAX −2.5 25°C Dropout voltage (see Note 6) TYP LP2981-XX 1.6 0.5 V 0.5 0.15 0.15 NOTES: 5. VOUT = VREF for ADJ version 6. Dropout voltage is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. This dropout specification does not apply to the 1.8-V option, as the minimum VIN = 2.2 V must be observed for proper biasing of LDO control circuitry. 7. The ON/OFF input must be actively terminated. Connect to VIN if this function is not used (see Application Information). 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 electrical characteristics at specified free-air temperature range, VIN = VOUT(NOM) + 1 V, VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF, ADJ version: ADJ connected to VOUT (unless otherwise noted) (continued) LP2981A-XX PARAMETER TEST CONDITIONS TA MIN 25°C ION/OFF ON/OFF input current VON/OFF = 0 TYP VOUT≥VOUT(NOM) − 5% 25°C Vn Output noise voltage (RMS) BW = 300 Hz to 50 kHz, COUT = 10 µF 25°C nVOUT/nVIN Ripple rejection f = 1kHz, COUT = 10 µF IOUT(MAX) Short-circuit current RL = 0 (steady state) TYP −1 5 15 A µA 15 mA 160 160 µV 25°C 63 63 dB 25°C 150 150 mA • DALLAS, TEXAS 75265 400 UNIT 400 POST OFFICE BOX 655303 150 MAX 0.01 5 −40°C to 125°C Peak output current MIN −1 25°C IOUT(PK) MAX 0.01 −40°C to 125°C VON/OFF = 5 V LP2981-XX 150 11 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 APPLICATION INFORMATION capacitors input capacitor (Cin) A minimum value of 1 mF (over the entire operating temperature range) is required at the input of the LP2981. In addition, this input capacitor should be located within 1 cm of the input pin and connected to a clean analog ground. There is no Equivalent Series Resistance (ESR) requirement for this capacitor, and the capacitance can be increased without limit. A good quality ceramic or tantalum capacitor can be used. output capacitor (Cout) As a PNP regulator, the LP2981 requires the output capacitor to meet both a minimum capacitance and ESR value. Required ESR values as a function of load current are provided for various output voltages, load currents, and capacitances (see Figures 1–4). Minimum Cout: 3.3 µF (can be increased without limit to improve transient response stability margin) ESR − Ω ESR − Ω ESR range: see Figures 1–4 Load Current − mA Figure 5. 5-V/10-µF ESR Curves ESR − Ω ESR − Ω Figure 4. 5-V/3.3-µF ESR Curves Load Current − mA Load Current − mA Figure 6. 3-V/3.3-µF ESR Curves 12 POST OFFICE BOX 655303 Load Current − mA Figure 7. 3-V/10-µF ESR Curves • DALLAS, TEXAS 75265 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 APPLICATION INFORMATION output capacitor (Cout) (continued) It is critical that both the minimum capacitance and ESR requirement be met over the entire operating temperature range. Depending on the type of capacitor used, both of these parameters can vary significantly with temperature (see capacitor characteristics section). capacitor characteristics ceramics Due to their very low ESR values, ceramic capacitors are not suitable for use as the output capacitor. For instance, a typical 2.2-µF ceramic capacitor has an ESR in the range of 10 mΩ to 20 mΩ and, thus, easily can fall out of minimum ESR requirements under certain operating conditions. If a ceramic capacitor is used at the output, a 1-Ω resistor should be placed in series with the capacitor to raise the ESR seen by the regulator. tantalum Solid tantalum capacitors are optimal choices for the LP2981, but they still must meet the minimum ESR requirement. Note that the ESR of a tantalum capacitor increases as temperature drops, as much as double from 25°C to −40°C. Thus, ESR margins must be maintained over the temperature range to prevent regulator instability. For operation at very low temperatures, paralleling a tantalum capacitor with a ceramic one keeps the combined ESR from increasing near the upper limit of the ESR curve. aluminum Aluminum capacitors can be used, but use with the LP2981 is impractical due to their large physical dimensions. They also must meet the ESR requirements over the full temperature range. In this regard, aluminium capacitors are at a big disadvantage due to their sharp ESR increase as temperature drops. For example, over a temperature drop from 20°C to −40°C, the ESR of an aluminum electrolytic capacitor can increase by a factor of 50. In addition, some of the electrolytes used in these capacitors can freeze at −25°C, making the capacitor nonoperational. ON/OFF operation The LP2981 allows for a shutdown mode via the ON/OFF pin. If the shutdown feature is not used, ON/OFF should be connected to the input to ensure that the regulator is on at all times. To drive ON/OFF: • • • A LOW (≤0.3 V) turns the regulator OFF; a HIGH (≥1.6 V) turns it ON. Use either a totem-pole output or an open-collector output with a pullup resistor tied to VIN (or another logic supply). The HIGH signal can exceed VIN, but must not exceed the absolute maximum ratings of 20 V for the ON/OFF pin. Apply a signal with a slew rate of ≥40 mV/µs. A slow slew rate can cause the shutdown function to operate incorrectly. ADJ version From Figure 3, VOUT is set according to the following equation: ǒ VOUT = VREF 1 ) R ADJ R1 Ǔ where VREF = 1.23 V (nominal). Under no-load conditions, a minimum “bias” current is required through the RADJ and R1 divider to maintain regulator stability. Therefore, the maximum value for R1 should be X39.5 kΩ. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 APPLICATION INFORMATION reverse input-output voltage An inherent diode is present across the PNP pass element of the LP2981. VIN VOUT With the anode connected to the output, this diode is reverse biased during normal operation, since the input voltage is higher than the output. However, if the output is pulled one VBE higher than the input, or if the input is abruptly stepped below the output, this diode is forward biased and can cause a parasitic silicon-controlled rectifier (SCR) to latch, resulting in current flowing from the output to the input (values in excess of 100 mA can cause damage). Thus, to prevent possible damage to the regulator in any application where the output may be pulled above the input, an external Schottky diode must be connected between the output and input. With the anode on output, this Schottky limits the reverse voltage across the output and input pins to 0.3 V, preventing the regulator’s internal diode from forward biasing. Schottky VIN VOUT LP2981 pin 4: NC Pin 4 must be left OPEN. Do not connect anything to this pin, as it is used for post package trim. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 WAFER CHIP SCALE INFORMATION LP2981x-xxYEQ NanoStar (0.17-mm Bump) LP2981x-xxYZQ NanoFree (0.17-mm Pb-Free Bump) 987 1,037 1,287 1,337 Pin A1 Index Area 0,19 0,15 0,625 Max 0,15 0,10 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoStar package configuration. This package is tin-lead (SnPb); consult the factory for availability of lead-free material. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLVS521B − JULY 2004 − REVISED OCTOBER 2004 WAFER CHIP SCALE INFORMATION LP2981x-xxYEU NanoStar (0.30-mm Bump) LP2981x-xxYZU NanoFree (0.30-mm Pb-Free Bump) 987 1,037 1,287 1,337 Pin A1 Index Area 0,75 Max 0,30 0,20 NOTES: A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoStar package configuration. This package is tin-lead (SnPb); consult the factory for availability of lead-free material. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0,35 0,25 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION (1) Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty LP2981-28DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-28DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-28DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-28DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-30DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-30DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-30DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-30DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-33DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-33DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-33DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981-33DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-28DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-28DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-28DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-28DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-30DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-30DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-30DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-30DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-33DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-33DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-33DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM LP2981A-33DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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