SLVS522C − JULY 2004 − REVISED OCTOBER 2004 D Available in the Texas Instruments D D D D D D NanoStar and NanoFree Wafer Chip Scale Packages Output Tolerance of: − 1% (A Grade) − 1.5% (Standard Grade) Ultra-Low Dropout, Typically − 280 mV at Full Load of 150 mA − 7 mV at 1 mA Wide VIN Range . . . 16 V Max Low IQ . . . 850 µA at Full Load at 150 mA Shutdown Current . . . 0.01 µA Typ Low Noise . . . 30 µVRMS With 10-nF Bypass Capacitor DBV (SOT-23) PACKAGE (TOP VIEW) VIN GND ON/OFF 1 D D D D Ceramic Over-Current and Thermal Protection High Peak-Current Capability For VOUT Options 32.3 V, See LP2985LV Data Sheet Portable Applications − Cellular Phones − Palmtop and Laptop Computers − Personal Digital Assistants (PDAs) − Digital Cameras and Camcorders − CD Players − MP3 Players YEQ, YEU, YZQ, OR YZU (WCSP) PACKAGE (TOP VIEW) 5 VOUT 4 BYPASS 2 3 D Stable With Low-ESR Capacitors, Including VIN C3 C1 B2 ON/OFF VOUT BYPASS A3 A1 GND description/ordering information The LP2985 family of fixed-output, low-dropout regulators offers exceptional, cost-effective performance for both portable and nonportable applications. Available in voltages of 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.85 V, 3 V, 3.1 V, 3.2 V, 3.3 V, and 5 V, the family has an output tolerance of 1% for the A version (1.5% for the non-A version) and is capable of delivering 150-mA continuous load current. Standard regulator features, such as over-current and over-temperature protection, are included. The LP2985 has a host of features that makes the regulator an ideal candidate for a variety of portable applications: • • • • • Low dropout: A PNP pass element allows a typical dropout of 280 mV at 150-mA load current and 7 mV at 1-mA load. Low quiescent current: The use of a vertical PNP process allows for quiescent currents that are considerably lower than those associated with traditional lateral PNP regulators. Shutdown: A shutdown feature is available, allowing the regulator to consume only 0.01 µA when the ON/OFF pin is pulled low. Low-ESR-capacitor friendly: The regulator is stable with low-ESR capacitors, allowing the use of small, inexpensive, ceramic capacitors in cost-sensitive applications. Low noise: A BYPASS pin allows for low-noise operation, with a typical output noise of 30 µV (RMS), with the use of a 10-nF bypass capacitor. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2004, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !% " %," "!$ %!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( & %!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 description/ordering information (continued) • Small packaging: For the most space-constraint needs, the regulator is available in SOT-23 package, as well as NanoStar wafer chip scale packaging, offering an even smaller size with improved thermal and electrical characteristics. NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION TJ PART GRADE VOUT (NOM) PACKAGE† 2.5 V 2.6 V 2.7 V 2.8 V 2.85 V −40°C to 125°C A grade: 1% tolerance SOT23-5 (DBV) 3V 3.1 V 3.2 V 3.3 V 5V ORDERABLE PART NUMBER TOP-SIDE MARKING‡ Reel of 3000 LP2985A-25DBVR Reel of 250 LP2985A-25DBVT Reel of 3000 LP2985A-26DBVR Reel of 250 LP2985A-26DBVT Reel of 3000 LP2985A-27DBVR Reel of 250 LP2985A-27DBVT Reel of 3000 LP2985A-28DBVR Reel of 250 LP2985A-28DBVT Reel of 3000 LP2985A-285DBVR Reel of 250 LP2985A-285DBVT PREVIEW Reel of 3000 LP2985A-30DBVR PREVIEW Reel of 250 LP2985A-30DBVT Reel of 3000 LP2985A-31DBVR Reel of 250 LP2985A-31DBVT Reel of 3000 LP2985A-32DBVR Reel of 250 LP2985A-32DBVT Reel of 3000 LP2985A-33DBVR Reel of 250 LP2985A-33DBVT Reel of 3000 LP2985A-50DBVR Reel of 250 LP2985A-50DBVT PREVIEW PREVIEW PREVIEW LPJ_ PREVIEW PREVIEW LPK_ PREVIEW † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV: The actual top-side marking has one additional character that designates the assembly/test site. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) PACKAGE† 2.5 V LP2985A-25YEQR 2.6 V LP2985A-26YEQR 2.7 V LP2985A-27YEQR 2.8 V LP2985A-28YEQR 2.85 V 3V NanoStar − WCSP NanoStar 0.17-mm Bump (YEQ) LP2985A-31YEQR 3.2 V LP2985A-32YEQR 3.3 V LP2985A-33YEQR 5V LP2985A-50YEQR 2.5 V LP2985A-25YZQR 2.6 V LP2985A-26YZQR 2.7 V LP2985A-27YZQR 3V A grade: 1% tolerance LP2985A-30YEQR 3.1 V 2.85 V LP2985A-28YZQR NanoFree − WCSP NanoFree 0.17-mm Bump (YZQ, Pb-free) LP2985A-285YZQR Reel of 3000 LP2985A-30YZQR 3.1 V LP2985A-31YZQR 3.2 V LP2985A-32YZQR 3.3 V LP2985A-33YZQR 5V LP2985A-50YZQR 2.5 V LP2985A-25YEUR 2.6 V LP2985A-26YEUR 2.7 V LP2985A-27YEUR 2.8 V LP2985A-28YEUR 2.85 V 3V NanoFree − WCSP NanoFree 0.30-mm Bump (YEU) LP2985A-285YEUR Reel of 3000 LP2985A-30YEUR 3.1 V LP2985A-31YEUR 3.2 V LP2985A-32YEUR 3.3 V LP2985A-33YEUR 5V LP2985A-50YEUR 2.5 V LP2985A-25YZUR 2.6 V LP2985A-26YZUR 2.7 V LP2985A-27YZUR 2.8 V 2.85 V 3V TOP-SIDE MARKING‡ LP2985A-285YEQR Reel of 3000 2.8 V −40°C to 125°C ORDERABLE PART NUMBER LP2985A-28YZUR NanoFree − WCSP NanoFree 0.30-mm Bump (YZU, Pb-free) LP2985A-285YZUR Reel of 3000 LP2985A-30YZUR 3.1 V LP2985A-31YZUR 3.2 V LP2985A-32YZUR 3.3 V LP2985A-33YZUR 5V LP2985A-50YZUR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ YEQ/YZQ, YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) PACKAGE† 2.5 V 2.6 V 2.7 V 2.8 V 2.85 V −40°C to 125°C Standard grade: 1.5% tolerance SOT-23 (DBV) 3V 3.1 V 3.2 V 3.3 V 5V ORDERABLE PART NUMBER TOP-SIDE MARKING‡ Reel of 3000 LP2985-25DBVR Reel of 250 LP2985-25DBVT Reel of 3000 LP2985-26DBVR Reel of 250 LP2985-26DBVT Reel of 3000 LP2985-27DBVR Reel of 250 LP2985-27DBVT Reel of 3000 LP2985-28DBVR Reel of 250 LP2985-28DBVT Reel of 3000 LP2985-285DBVR Reel of 250 LP2985-285DBVT PREVIEW Reel of 3000 LP2985-30DBVR PREVIEW Reel of 250 LP2985-30DBVT Reel of 3000 LP2985-31DBVR Reel of 250 LP2985-31DBVT Reel of 3000 LP2985-32DBVR Reel of 250 LP2985-32DBVT Reel of 3000 LP2985-33DBVR Reel of 250 LP2985-33DBVT Reel of 3000 LP2985-50DBVR Reel of 250 LP2985-50DBVT PREVIEW PREVIEW PREVIEW LPG_ PREVIEW PREVIEW LPF_ PREVIEW † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV: The actual top-side marking has one additional character that designates the assembly/test site. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 ORDERING INFORMATION (continued) TJ PART GRADE VOUT (NOM) PACKAGE† 2.5 V LP2985-25YEQR 2.6 V LP2985-26YEQR 2.7 V LP2985-27YEQR 2.8 V LP2985-28YEQR 2.85 V 3V NanoStar − WCSP NanoStar 0.17-mm Bump (YEQ) LP2985-31YEQR 3.2 V LP2985-32YEQR 3.3 V LP2985-33YEQR 5V LP2985-50YEQR 2.5 V LP2985-25YZQR 2.6 V LP2985-26YZQR 2.7 V LP2985-27YZQR 3V Standard grade: 1.5% tolerance LP2985-30YEQR 3.1 V 2.85 V LP2985-28YZQR NanoFree − WCSP NanoFree 0.17-mm Bump (YZQ, Pb-free) LP2985-285YZQR Reel of 3000 LP2985-30YZQR 3.1 V LP2985-31YZQR 3.2 V LP2985-32YZQR 3.3 V LP2985-33YZQR 5V LP2985-50YZQR 2.5 V LP2985-25YEUR 2.6 V LP2985-26YEUR 2.7 V LP2985-27YEUR 2.8 V LP2985-28YEUR 2.85 V 3V NanoStar − WCSP NanoStar 0.30-mm Bump (YEU) LP2985-285YEUR Reel of 3000 LP2985-30YEUR 3.1 V LP2985-31YEUR 3.2 V LP2985-32YEUR 3.3 V LP2985-33YEUR 5V LP2985-50YEUR 2.5 V LP2985-25YZUR 2.6 V LP2985-26YZUR 2.7 V LP2985-27YZUR 2.8 V 2.85 V 3V TOP-SIDE MARKING‡ LP2985-285YEQR Reel of 3000 2.8 V −40°C to 125°C ORDERABLE PART NUMBER LP2985-28YZUR NanoFree − WCSP NanoFree 0.30-mm Bump (YZU, Pb-free) Reel of 3000 LP2985-285YZUR LP2985-30YZUR 3.1 V LP2985-31YZUR 3.2 V LP2985-32YZUR 3.3 V LP2985-33YZUR 5V LP2985-50YZUR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ YEQ/YZQ, YEU/YZU: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 functional block diagram VIN ON/OFF 1.23 V VREF − + BYPASS VOUT Over-Current/ Over-Temperature Protection basic application circuit LP2985A-xxDBVR VIN 1 VOUT 5 2.2 µF† 1 µF† GND 2 ON/OFF‡ 3 4 BYPASS 10 nF§ † Minimum COUT value for stability (can be increased without limit for improved stability and transient response) ‡ ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. § Optional BYPASS capacitor for low-noise operation 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 absolute maximum ratings over the virtual junction temperature range (unless otherwise noted)† Continuous input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V ON/OFF input voltage range, VON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 9 V Input/output voltage differential range, VIN-VOUT (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V Output current, IO (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited (short-circuit protected) Package thermal impedance, θJA (see Notes 3 and 4): DBV package . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W YEQ/YZQ package . . . . . . . . . . . . . . . . . . TBD°C/W YEU/YZU package . . . . . . . . . . . . . . . . . . . TBD°C/W Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. If load is returned to a negative power supply in a dual-supply system, the output must be diode clamped to GND. 2. The PNP pass transistor has a parasitic diode connected between the input and output. This diode normally is reverse biased (VIN > VOUT), but will be forward biased if the output voltage exceeds the input voltage by a diode drop (see Application Information for more details). 3. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/JA. Operating at the absolute maximum TJ of 150°C can affect reliability. 4. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN MAX VIN VON/OFF Supply input voltage ‡ 16 V ON/OFF input voltage 0 V IOUT Output current VIN 150 mA −40 125 °C Virtual junction temperature TJ ‡ Recommended minimum VIN is the greater of: a) 2.5 V or b) VOUT(max) + rated dropout voltage (max) for operating IL. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 7 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 electrical characteristics at specified virtual junction temperature range, VIN = VOUT (nominal) + 1 V, VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF (unless otherwise noted) LP2985A-XX PARAMETER TEST CONDITIONS IL = 1 mA nVOUT Output voltage tolerance 1 mA ≤ IL ≤ 50 mA 1 mA ≤ IL ≤ 150 mA Line regulation TJ MIN 1 −1.5 1.5 −2.5 2.5 −40°C to 125°C −2.5 2.5 −3.5 25°C −2.5 2.5 −3.0 3.5 %VNOM 3.0 −40°C to 125°C −3.5 3.5 −4.0 0.007 1 −40°C to 125°C IL = 50 mA −40°C to 125°C IL = 150 mA −40°C to 125°C 7 280 65 75 120 350 −40°C to 125°C VON/OFF < 0.15 V (OFF) VON/OFF ON/OFF input voltage (see Note 6) 850 −40°C to 125°C VON/OFF < 0.3 V (OFF) VON/OFF = HIGH ! O/P ON VON/OFF = LOW ! O/P OFF ON/OFF input current VON/OFF = 0 VON/OFF = 5 V 60 90 150 120 225 350 280 350 575 95 65 95 125 110 75 110 170 220 120 220 400 600 350 600 1500 850 2500 1500 2500 0.8 0.01 0.8 −40°C to 105°C 0.05 2 0.05 2 5 25°C −40°C to 125°C 5 1.4 1.4 1.6 25°C 1.6 0.55 −40°C to 125°C −40°C to 125°C V 0.55 0.15 0.01 −40°C to 125°C 25°C µA 1000 0.01 −40°C to 125°C mV 150 25°C 25°C ION/OFF 40 1000 25°C IL = 150 mA 15 60 400 25°C IL = 50 mA 10 170 25°C Ground pin current 7 %/V 5 10 125 25°C −40°C to 125°C 3 575 −40°C to 125°C IL = 10 mA 1 225 25°C −40°C to 125°C 3 90 120 0.014 0.032 15 40 25°C IL = 1 mA 4.0 0.007 5 25°C IL = 10 mA 0.014 0.032 25°C IGND UNIT 1.5 −40°C to 125°C IL = 0 MAX −1 25°C Dropout voltage (see Note 5) TYP −1.5 25°C VIN-VOUT MIN 25°C −40°C to 125°C IL = 1 mA MAX 25°C 25°C VIN = [VOUT(NOM) + 1 V] to 16 V −40°C to 125°C IL = 0 TYP LP2985-XX 0.15 0.01 −2 5 −2 5 15 µA 15 NOTES: 5. Dropout voltage is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. 6. The ON/OFF input must be properly driven for reliable operation (see Application Information). 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 electrical characteristics at specified virtual junction temperature range, VIN = VOUT (nominal) + 1 V, VON/OFF = 2 V, CIN = 1 mF, IL = 1 mA, COUT = 4.7 mF (unless otherwise noted) (continued) LP2985A-XX PARAMETER Vn Output noise (RMS) nVOUT/nVIN Ripple rejection IOUT(PK) Peak output current IOUT(SC) Short-circuit current TEST CONDITIONS BW = 300 Hz to 50 kHz, COUT = 10 µF, CBYPASS = 10 nF f = 1kHz, COUT = 10 µF, CBYPASS = 10 nF TJ MIN TYP MAX LP2985-XX MIN TYP MAX UNIT 25°C 30 30 µV 25°C 45 45 dB VOUT ≥ VO(NOM) − 5% 25°C 350 350 mA RL = 0 (steady state) (see Note 7) 25°C 400 400 mA NOTE 7: See Typical Characteristics Curve, Short-Circuit Current vs VOUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 APPLICATION INFORMATION capacitors input capacitor (Cin) A minimum value of 1 F (over the entire operating temperature range) is required at the input of the LP2985. In addition, this input capacitor should be located within 1 cm of the input pin and connected to a clean analog ground. There are no Equivalent Series Resistance (ESR) requirements for this capacitor, and the capacitance can be increased without limit. output capacitor (Cout) As an advantage over other regulators, the LP2985 permits the use of low-ESR capacitors at the output, including ceramic capacitors that can have an ESR as low as 5 mΩ. Tantalum and film capacitors also can be used if size and cost are not issues. The output capacitor also should be located within 1 cm of the output pin and be returned to a clean analog ground. As with other PNP LDOs, stability conditions require the output capacitor to have a minimum capacitance and an ESR that falls within a certain range. Minimum Cout: 2.2 µF (can be increased without limit to improve transient response stability margin) ESR − Ω ESR range: see Figure 1 Load Current − mA Figure 1. 2.2-V/3.3-µF ESR Curves It is critical that both the minimum capacitance and ESR requirement be met over the entire operating temperature range. Depending on the type of capacitors used, both these parameters can vary significantly with temperature (see capacitor characteristics section). noise bypass capacitor (Cbypass) The LP2985 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal bandgap reference via the BYPASS pin. This high-impedance bandgap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, its output − and, correspondingly, the output of the regulator − will change. Thus, for best output accuracy, dc leakage current through Cbypass should be minimized as much as possible and never should exceed 100 nA. A 10-nF capacitor is recommended for Cbypass; ceramic and film capacitors are well suited for this purpose. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 APPLICATION INFORMATION capacitor characteristics ceramics Ceramic capacitors are ideal choices for use on the output of the LP2985 for several reasons. For capacitances in the range of 2.2 µF to 4.7 µF, ceramic capacitors have the lowest cost and the lowest ESR, making them choice candidates for filtering high-frequency noise. For instance, a typical 2.2-µF ceramic capacitor has an ESR in the range of 10 mΩ to 20 mΩ and, thus, satisfies minimum ESR requirements of the regulator. Ceramic capacitors have one glaring disadvantage that must be taken into account − a poor temperature coefficient, where the capacitance can vary significantly with temperature. For instance, a large-value ceramic capacitor (≥2.2 µF) can lose more than half of its capacitance as the temperature rises from 25°C to 85°C. Thus, a 2.2-µF capacitor at 25°C will drop well below the minimum Cout required for stability, as ambient temperature rises. For this reason, select an output capacitor that maintains the minimum 2.2 µF required for stability over the entire operating temperature range. Note that there are some ceramic capacitors that can maintain a ±15% capacitance tolerance over temperature. tantalum Tantalum capacitors can be used at the output of the LP2985, but there are significant disadvantages that could prohibit their use: • • • In the 1-µF to 4.7-µF range, tantalum capacitors are more expensive than ceramics of the equivalent capacitance and voltage ratings. Tantalum capacitors have higher ESRs than their equivalent-sized ceramic counterparts. Thus, to meet the ESR requirements, a higher-capacitance tantalum may be required, at the expense of larger size and higher cost. The ESR of a tantalum capacitor increases as temperature drops, as much as double from 25°C to −40°C. Thus, ESR margins must be maintained over the temperature range in order to prevent regulator instability. ON/OFF operation The LP2985 allows for a shutdown mode via the ON/OFF pin. Driving the pin LOW (≤0.3 V) turns the device OFF; conversely, a HIGH (≥1.6 V) turns the device ON. If the shutdown feature is not used, ON/OFF should be connected to the input to ensure that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected, and apply a signal with a slew rate of ≥40 mV/µs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 APPLICATION INFORMATION reverse input-output voltage There is an inherent diode present across the PNP pass element of the LP2985. VIN VOUT With the anode connected to the output, this diode is reverse biased during normal operation, since the input voltage is higher than the output. However, if the output is pulled higher than the input for any reason, this diode is forward biased and can cause a parasitic silicon-controlled rectifier (SCR) to latch, resulting in high current flowing from the output to the input. Thus, to prevent possible damage to the regulator in any application where the output may be pulled above the input, an external Schottky diode should be connected between the output and input. With the anode on output, this Schottky limits the reverse voltage across the output and input pins to 0.3 V, preventing the regulator’s internal diode from forward biasing. Schottky VIN VOUT LP2985 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN (unless otherwise specified) OUTPUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs TEMPERATURE 0.45 3.345 0.4 150 mA VO = 3.3 V Cbyp = 10 nF 0.35 0.3 Dropout − V Output Voltage − V 3.335 VI = 4.3 V VO = 3.3 V Ci = 1 µF Co = 4.7 µF IO = 1 mA 3.325 3.315 0.25 0.2 50 mA 0.15 0.1 3.305 10 mA 0.05 1 mA 3.295 −50 −25 0 25 50 75 100 125 0 −50 150 −25 0 Temperature − °C SHORT-CIRCUIT CURRENT vs TIME Short-Circuit Current − A 0.4 0.5 VI = 6 V VO = 3.3 V Ci = 1 µF Cbyp = 0.01 µF 0.3 0.25 0.2 0.15 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.1 0.05 0.05 0 500 1000 Time − ms 150 VI = 16 V VO = 3.3 V Ci = 1 µF Cbyp = 0.01 µF 0.45 0.35 0 −500 125 SHORT-CIRCUIT CURRENT vs TIME Short-Circuit Current − A 0.45 100 Figure 3 Figure 2 0.5 25 50 75 Temperature − °C 1500 2000 0 −100 Figure 4 100 300 500 Time − ms 700 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN (unless otherwise specified) SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE GROUND-PIN CURRENT vs LOAD CURRENT 1200 320 VO = 3.3 V 300 Ground Pin Current − µA 1000 280 ISC − mA VO = 3.3 V Cbyp = 10 nF 1100 260 240 900 800 700 600 500 400 300 200 220 100 200 0 0 0.5 1 1.5 2 2.5 Output Voltage − V 3 3.5 20 0 40 Figure 6 140 160 RIPPLE REJECTION vs FREQUENCY 100 100 VI = 5 V VO = 3.3 V Co = 10 µF Cbyp = 0 nF 80 70 80 50 mA 1 mA 60 50 40 VI = 3.7 V VO = 3.3 V Co = 10 µF Cbyp = 0 nF 90 Ripple Rejection − dB 90 Ripple Rejection − dB 120 Figure 7 RIPPLE REJECTION vs FREQUENCY 150 mA 30 70 1 mA 60 50 50 mA 40 30 20 20 10 10 0 150 mA 0 10 100 1K 10K 100K 1M 10 Frequency − Hz 100 1K Figure 9 POST OFFICE BOX 655303 10K Frequency − Hz Figure 8 14 60 80 100 Load Current − mA • DALLAS, TEXAS 75265 100K 1M SLVS522C − JULY 2004 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN (unless otherwise specified) RIPPLE REJECTION vs FREQUENCY RIPPLE REJECTION vs FREQUENCY 100 80 80 70 1 mA 60 50 40 50 mA 30 20 VI = 5 V VO = 3.3 V Co = 4.7 µF Cbyp = 10 nF 90 Ripple Rejection − dB 90 Ripple Rejection − dB 100 VI = 5 V VO = 3.3 V Co = 4.7 µF Cbyp = 10 nF 70 1 mA 60 10 mA 50 40 100 mA 30 20 150 mA 10 10 0 10 100 1K 10K 100K 0 1M 10 100 1K 10K Frequency − Hz Frequency − Hz Figure 10 OUTPUT IMPEDANCE vs FREQUENCY 10 Ci = 1 µF Co = 10 µF VO = 3.3 V 1 1 mA Output Impedance − Ω Output Impedance − Ω 1 10 mA 100 mA 0.1 0.01 0.001 10 100 1K 1M Figure 11 OUTPUT IMPEDANCE vs FREQUENCY 10 100K 10K 100K 1M Ci = 1 µF Co = 4.7 µF VO = 3.3 V 1 mA 10 mA 100 mA 0.1 0.01 0.001 10 100 1K 10K 100K 1M Frequency − Hz Frequency − Hz Figure 13 Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN (unless otherwise specified) OUTPUT NOISE DENSITY vs FREQUENCY OUTPUT NOISE DENSITY vs FREQUENCY 10 10 ILOAD = 1 mA 1 Noise Density − nV/ Hz Noise Density − nV/ Hz ILOAD = 150 mA Cbyp = 100 nF Cbyp = 1 nF 0.1 Cbyp = 10 nF 1 Cbyp = 100 nF Cbyp = 1 nF 0.1 Cbyp = 10 nF 0.01 0.01 0.1 1 10 Frequency − kHz 0.1 100 1 Figure 14 10 Frequency − kHz 100 Figure 15 GROUND-PIN CURRENT vs TEMPERATURE INPUT CURRENT vs INPUT VOLTAGE 1400 1.8 VO = 3.3 V Cbyp = 10 nF 1.6 1200 RL = 3.3 kΩ VO = 3.3 V Cbyp = 10 nF 150 mA Ground Current − C Input Current − mA 1.4 1.2 1 0.8 RL = Open 0.6 1000 800 600 1 mA 400 50 mA 0.4 0 mA 200 0.2 0 10 mA 0 0 1 2 3 4 5 6 −50 −25 25 50 75 Temperature − °C Input Voltage − V Figure 17 Figure 16 16 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 125 150 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN (unless otherwise specified) 3.4 200 3.38 150 3.38 150 3.36 100 3.36 100 3.32 3.3 50 IL VO = 3.3 V Cbyp = 10 nF ∆IL = 100 mA 0 −50 VO 3.28 −100 3.26 IL 3.34 3.32 3.3 VO = 3.3 V Cbyp = 10 nF ∆IL = 150 mA 0 −50 VO 3.28 −100 −150 3.26 −150 3.24 −200 3.24 −200 3.22 −250 3.22 −250 20 µs/div" 20 µs/div" Figure 19 Figure 18 LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE 200 3.38 150 3.36 100 IL 3.34 3.32 3.3 VO = 3.3 V Cbyp = 0 nF ∆IL = 150 mA 0 −50 VO 3.28 50 −100 3.26 −150 3.24 −200 3.22 −250 3.41 5.5 3.39 5 VI 3.37 Output Voltage − V 3.4 Load Current − mA Output Voltage − V 50 3.35 VO = 3.3 V Cbyp = 0 nF IO = 150 mA 4.5 4 3.5 3.33 3.31 VO 3 3.29 2.5 3.27 2 20 µs/div" Input Voltage − V 3.34 Output Voltage − V 200 Load Current − mA Output Voltage − V 3.4 Load Current − mA LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 20 µs/div" Figure 21 Figure 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN (unless otherwise specified) LINE TRANSIENT RESPONSE 3.41 5.5 3.39 5 3.39 5 4.5 3.37 3.35 VO = 3.3 V Cbyp = 10 nF IO = 150 mA 4 3.33 3.5 3.31 3.29 VO 3.27 3.35 VI VO = 3.3 V Cbyp = 0 nF IO = 1 mA 4.5 Input Voltage − V VI 3.37 Output Voltage − V 5.5 Input Voltage − V Output Voltage − V LINE TRANSIENT RESPONSE 3.41 4 3.33 3.5 3 3.31 3 2.5 3.29 2.5 VO 3.27 2 2 20 µs/div" 20 µs/div" Figure 22 Figure 23 LINE TRANSIENT RESPONSE TURN-ON TIME 4 5.5 3.41 10 VO 3 5 3.39 8 VO = 3.3 V Cbyp = 10 nF IO = 1 mA 3.5 3.31 VO 1 6 0 −1 3 −2 2.5 −3 2 −4 VO = 3.3 V Cbyp = 0 IO = 150 mA 4 VON/OFF 3.29 3.27 18 0 100 µs/div" 100 µs/div" Figure 24 Figure 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 VON/OFF − V 4 3.35 3.33 4.5 Output Voltage − V Output Voltage − V 3.37 2 Input Voltage − V VIN SLVS522C − JULY 2004 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS CIN = 1 F, COUT = 4.7 F, VIN = VOUT(NOM) +1 V, TA = 255C, ON/OFF Pin Is Tied to VIN (unless otherwise specified) TURN-ON TIME TURN-ON TIME 10 4 10 4 VO VO 3 3 8 8 6 0 −1 VO = 3.3 V Cbyp = 100 pF ILOAD = 150 mA 4 −2 VON/OFF 1 6 0 −1 VO = 3.3 V Cbyp = 1 nF ILOAD = 150 mA 4 VON/OFF − V 1 Output Voltage − V 2 VON/OFF − V Output Voltage − V 2 VON/OFF −2 2 2 −3 −3 0 −4 0 −4 2 ms/div" 200 µs/div" Figure 27 Figure 26 TURN-ON TIME 4 Input 10 3 8 1 6 0 −1 4 VO = 3.3 V Cbyp = 10 nF ILOAD = 150 mA VON/OFF − V Output Voltage − V 2 Output −2 2 −3 0 −4 20 ms/div" Figure 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 WAFER CHIP SCALE INFORMATION LP2985x-xxYEQ NanoStar (0.17-mm Bump) LP2985x-xxYZQ NanoFree (0.17-mm Pb-Free Bump) 987 1,037 1,287 1,337 Pin A1 Index Area 0,625 Max 0,15 0,10 NOTES: A. B. C. D. 20 All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoStar package configuration This package is tin-lead (SnPb); consult the factory for availability of lead-free material. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0,19 0,15 SLVS522C − JULY 2004 − REVISED OCTOBER 2004 WAFER CHIP SCALE INFORMATION LP2985x-xxYEU NanoStar (0.30-mm Bump) LP2985x-xxYZU NanoFree (0.30-mm Pb-Free Bump) 987 1,037 1,287 1,337 Pin A1 Index Area 0,35 0,25 0,75 Max 0,30 0,20 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. NanoStar package configuration This package is tin-lead (SnPb); consult the factory for availability of lead-free material. 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