TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 LOW-NOISE, HIGH PSRR, RF 200-mA LOW-DROPOUT LINEAR REGULATORS FEATURES DESCRIPTION 1 • 200-mA RF Low-Dropout Regulator With Enable • Available in Fixed Voltages from 1.8V to 3.3V and Adjustable (1.22V to 5.5V) • High PSRR (68dB at 100Hz) • Ultralow-Noise (33μVRMS, TPS73018) • Fast Start-Up Time (50μs) • Stable With a 2.2μF Ceramic Capacitor • Excellent Load/Line Transient Response • Very Low Dropout Voltage (120mV at 200mA) • 5- and 6-Pin SOT23 (DBV), and Wafer Chip Scale (YZQ) Packages The TPS730xx family of low-dropout (LDO) low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow-noise, fast start-up, and excellent line and load transient responses a small SOT23 package. NanoStar™ packaging gives an ultrasmall footprint as well as an ultralow profile and package weight, making it ideal for portable applications such as handsets and PDAs. Each device in the family is stable, with a small 2.2μF ceramic capacitor on the output. The TPS730xx family uses an advanced, proprietary BiCMOS fabrication process to yield low dropout voltages (e.g., 120mV at 200mA, TPS73030). Each device achieves fast start-up times (approximately 50μs with a 0.001μF bypass capacitor) while consuming low quiescent current (170μA typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1μA. The TPS73018 exhibits approximately 33μVRMS of output voltage noise at 1.8V output with a 0.01μF bypass capacitor. Applications with analog components that are noise-sensitive, such as portable RF electronics, benefit from the high PSRR and low-noise features as well as the fast response time. 234 APPLICATIONS • • • • • RF: VCOs, Receivers, ADCs Audio Cellular and Cordless Telephones Bluetooth®, Wireless LAN Handheld Organizers, PDAs DBV PACKAGE (TOP VIEW) GND 2 EN 3 5 OUT 4 NR Fixed Option DBV PACKAGE (TOP VIEW) IN 1 6 OUT GND 2 5 FB EN 3 4 NR Adjustable Option YZQ PACKAGE (TOP VIEW) IN C3 A3 EN C1 B2 A1 OUT TPS73028 TPS73028 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY RIPPLE REJECTION vs FREQUENCY 0.30 100 VIN = 3.8 V COUT = 2.2 µF CNR = 0.1 µF 0.25 90 IOUT = 200 mA 80 Ripple Rejection (dB) 1 Output Spectral Noise Density (µV/√Hz) IN 0.20 0.15 IOUT = 1 mA 0.10 IOUT = 200 mA 70 60 50 40 IOUT = 10 mA 30 20 0.05 VIN = 3.8 V COUT = 10 µF CNR = 0.01 µF 10 0 0 100 1k 10 k Frequency (Hz) NR 100 k 10 100 1k 10 k 100 k 1M 10 M Frequency (Hz) GND Figure 1. 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar is a trademark of Texas Instruments. Bluetooth is a registered trademark of Bluetooth Sig, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2007, Texas Instruments Incorporated TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS730xxyyyz (1) VOUT XX is nominal output voltage (for example, 28 = 2.8V, 01 = Adjustable). YYY is package designator. Z is package quantity. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS Over operating temperature range (unless otherwise noted) (1) UNIT VIN range –0.3V to +6V VEN range –0.3V to +6V VOUT range –0.3V to VIN + 0.3V Peak output current Internally limited ESD rating, HBM 2kV ESD rating, CDM 500V Continuous total power dissipation See Dissipation Ratings Table Junction temperature range –40°C to +150°C Storage temperature range, Tstg –65°C to +150°C (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 DISSIPATION RATINGS TABLE TA ≤ +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING BOARD PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = +25°C Low-K (1) DBV 65°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW (2) DBV 65°C/W 180°C/W 5.6mW/°C 560mW 310mW 225mW Low-K (1) YZQ 27°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW High-K (2) YZQ 27°C/W 190°C/W 5.3mW/°C 530mW 296mW 216mW High-K (1) (2) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch, two layer board with 2 ounce copper traces on top of the board. The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. ELECTRICAL CHARACTERISTICS Over recommended operating temperature range TJ = –40 to +125°C, VEN = VIN, VIN = VOUT(nom) + 1 V (1), IOUT = 1mA, COUT = 10μF, CNR = 0.01μF (unless otherwise noted). Typical values are at +25°C. PARAMETER TEST CONDITIONS MIN VIN Input voltage (1) IOUT Continuous output current VFB Internal reference (TPS73001) Line regulation (ΔVOUT%/ΔVIN) (1) V 200 mA 1.225 –2% VOUT + 1V ≤ VIN ≤ 5.5V VOUT(nom) 0μA ≤ IOUT ≤ 200mA, TJ = +25°C Dropout voltage (2)(VIN = VOUT(nom) – 0.1V) IOUT = 200mA Output current limit VOUT = 0V GND pin current 0μA ≤ IOUT ≤ 200mA 170 Shutdown current (3) VEN = 0V, 2.7V ≤ VIN ≤ 5.5V 0.07 FB pin current VFB = 1.8V TPS73028 1.250 V 5.5 – VDO V +2% V 0.05 Load regulation (ΔVOUT%/ΔIOUT) Power-supply ripple rejection UNIT 0 VFB 0μA ≤ IOUT ≤ 200mA, 2.75V ≤ VIN < 5.5V Output voltage accuracy MAX 5.5 1.201 Output voltage range (TPS73001) TYP 2.7 %/V 5 120 285 mV 210 mV 600 mA 250 μA 1 μA 1 μA f = 100Hz, TJ = +25°C, IOUT = 200mA 68 dB Output noise voltage (TPS73018) BW = 200Hz to 100kHz, IOUT = 200mA CNR = 0.01μF 33 μVRMS Time, start-up (TPS73018) RL = 14Ω, COUT = 1μF CNR = 0.001μF High level enable input voltage 2.7V ≤ VIN ≤ 5.5V 1.7 VIN Low level enable input voltage 2.7V ≤ VIN ≤ 5.5V 0 0.7 V EN pin current VEN = 0 –1 1 μA UVLO threshold VCC rising 2.25 UVLO hysteresis (1) (2) (3) μs 50 2.65 100 V V mV Minimum VIN is 2.7V or VOUT + VDO, whichever is greater. Dropout is not measured for the TPS73018 and TPS73025 since minimum VIN = 2.7V. For adjustable versions, this applies only after VIN is applied; then VEN transitions high to low. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 FUNCTIONAL BLOCK DIAGRAMS ADJUSTABLE VERSION IN OUT UVLO 2.45V 59 k Current Sense ILIM GND R1 SHUTDOWN _ + FB EN R2 UVLO Thermal Shutdown Bandgap Reference 1.22V IN External to the Device QuickStart 250 kΩ Vref NR FIXED VERSION IN OUT UVLO 2.45V Current Sense GND SHUTDOWN ILIM _ R1 + EN UVLO R2 Thermal Shutdown R2 = 40 kΩ QuickStart Bandgap Reference 1.22V IN 250 kΩ Vref NR Table 1. Terminal Functions TERMINAL NAME 4 SOT23 ADJ SOT23 FIXED WCSP FIXED DESCRIPTION NR 4 4 B2 Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This improves power-supply rejection and reduces output noise. EN 3 3 A3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. FB 5 N/A N/A This terminal is the feedback input voltage for the adjustable device. GND 2 2 A1 Regulator ground IN 1 1 C3 Input to the device. OUT 6 5 C1 Output of the regulator. Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (SOT23 PACKAGE) TPS73028 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS73028 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 2.805 250 2.805 VIN = 3.8 V COUT = 10 µF TJ = 25°C 2.804 2.803 VIN = 3.8 V COUT = 10 µF 2.800 VOUT (V) 2.800 2.799 IGND (µA) 2.795 2.801 2.790 IOUT = 200 mA 2.785 2.798 100 50 2.780 VIN = 3.8 V COUT = 10 µF 2.796 2.795 0 50 100 150 2.775 200 IOUT = 200 mA 150 2.797 −40 −25 −10 5 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 IOUT (mA) 20 35 50 65 80 95 110 125 TJ (°C) TJ (°C) Figure 2. Figure 3. Figure 4. TPS73028 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY ROOT MEAN SQUARE OUTPUT NOISE vs CNR TPS73028 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 1.6 180 60 1.2 CNR = 0.001 µF CNR = 0.0047 µF 1.0 CNR = 0.01 µF 0.8 0.6 CNR = 0.1 µF 0.4 VOUT = 2.8 V IOUT = 200 mA COUT = 10 µF 50 VIN = 2.7 V COUT = 10 µF 160 140 40 120 VDO (mV) VIN = 3.8 V IOUT = 200 mA COUT = 10 µF 1.4 RMS, Output Noise (VRMS) Output Spectral Noise Density (µV/√Hz) IOUT = 1 mA 200 IOUT = 1 mA 2.802 VOUT (V) TPS73028 GROUND CURRENT vs JUNCTION TEMPERATURE 30 20 IOUT = 200 mA 100 80 60 40 10 0.2 IOUT = 10 mA 20 BW = 100 Hz to 100 kHz 0 100 1k 10 k 0 0.001 100 k 0.01 CNR (µF) Frequency (Hz) 0 −40 −25 −10 5 0.1 20 35 50 65 80 95 110 125 TJ (°C) Figure 5. Figure 6. Figure 7. TPS73028 RIPPLE REJECTION vs FREQUENCY TPS73028 OUTPUT VOLTAGE, ENABLE VOLTAGE vs TIME (START-UP) TPS73028 LINE TRANSIENT RESPONSE 90 4 VEN (V) IOUT = 200 mA 70 2 0 60 50 CNR = 0.001 µF 30 VIN = 3.8 V COUT = 10 µF CNR = 0.01 µF 10 0 10 100 1k 4.8 3.8 IOUT = 200 mA COUT = 2.2 µF CNR = 0.01 µF 20 3 IOUT = 10 mA 20 VIN = 3.8 V VOUT = 2.8 V IOUT = 200 mA COUT = 2.2 µF TJ = 25°C 2 CNR = 0.0047 µF 1 CNR = 0.01 µF VIN (mV) 40 VOUT (V) Ripple Rejection (dB) 80 VOUT (mV) 100 dv 0.4 V + µs dt 0 -20 0 10 k 100 k 1M 10 M Frequency (Hz) Figure 8. Copyright © 2004–2007, Texas Instruments Incorporated 0 20 40 60 80 100 120 140 160 180 200 0 10 20 30 40 50 60 Time (µs) Time (µs) Figure 9. Figure 10. 70 80 Submit Documentation Feedback 90 100 5 TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (SOT23 PACKAGE) (continued) TPS73028 LOAD TRANSIENT RESPONSE DROPOUT VOLTAGE vs OUTPUT CURRENT POWER-UP/POWER-DOWN 250 VIN = 3.8 V COUT = 10 µF VOUT = 3 V RL = 15 Ω TJ = 125°C −20 di 0.02A + µs dt 300 VDO (mV) −40 IOUT (mA) 200 0 500 mV/div ∆VOUT (mV) 20 VIN TJ = 25°C 100 VOUT 200 0 TJ = −55°C 50 1mA 100 0 150 0 50 100 150 200 250 300 350 400 450 500 0 1s/div 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Time (µs) Figure 11. Figure 12. TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT 100 COUT = 2.2 µF VIN = 5.5 V, VOUT ≥ 1.5 V TJ = −40°C to 125°C 10 Region of Instability 1 0.1 Region of Stability 0.01 COUT = 10 µF VIN = 5.5 V TJ = −40°C to 125°C 10 Region of Instability 1 0.1 Region of Stability 0.01 0 0.02 0.04 0.06 IOUT (A) Figure 14. 6 TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE (ESR) vs OUTPUT CURRENT ESR, Equivalent Series Resistance (Ω) ESR, Equivalent Series Resistance (Ω) 100 Figure 13. Submit Documentation Feedback 0.08 0.20 0 0.02 0.04 0.06 0.08 0.20 IOUT (A) Figure 15. Copyright © 2004–2007, Texas Instruments Incorporated TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 APPLICATION INFORMATION The TPS730xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (170μA typically), and enable-input to reduce supply currents to less than 1μA when the regulator is turned off. A typical application circuit is shown in Figure 16. VIN VOUT VIN IN VOUT OUT TPS730xx 0.1µF EN GND NR 2.2µF 0.01µF(1) NOTE: (1) This capacitor is optional. Figure 16. Typical Application Circuit External Capacitor Requirements A 0.1μF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS730xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated or the device is located several inches from the power source. Like most low dropout regulators, the TPS730xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 2.2μF. Any 2.2μF or larger ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. If load current is not expected to exceed 100mA, a 1.0μF ceramic capacitor can be used. The internal voltage reference is a key source of noise in an LDO regulator. The TPS730xx has an NR pin which is connected to the voltage reference through a 250kΩ internal resistor. The 250kΩ internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1μF to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the Functional Block Diagrams. As an example, the TPS73018 exhibits only 33μVRMS of output voltage noise using a 0.01μF ceramic bypass capacitor and a 2.2μF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the NR pin that is created by the internal 250kΩ resistor and external capacitor. Board Layout Recommendation to Improve PSRR and Noise Performance To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 Power Dissipation and Junction Temperature Specified regulator operation is assured to a junction temperature of +125°C; the maximum junction temperature should be restricted to +125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum power dissipation limit is determined using Equation 1: T max *T A P D(max) + J R QJA (1) Where: • • • TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package (see the Dissipation Ratings Table). TA is the ambient temperature. The regulator dissipation is calculated using Equation 2: P D + ǒVIN*V OUTǓ I OUT (2) Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. Programming the TPS73001 Adjustable LDO Regulator The output voltage of the TPS73001 adjustable regulator is programmed using an external resistor divider as shown in Figure 17. The output voltage is calculated using Equation 3: V OUT + VREF ǒ1 ) RR Ǔ 1 2 (3) Where: • VREF = 1.225V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50μA divider current. Lower value resistors can be used for improved noise performance, but the solution consumes more power. Higher resistor values should be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially increases/decreases the feedback voltage and thus erroneously decreases/increases VOUT. The recommended design procedure is to choose R2 = 30.1kΩ to set the divider current at 50μA, C1 = 15pF for stability, and then calculate R1 using Equation 4: R1 = VOUT VREF - 1 ´ R2 (4) In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. For voltages < 1.8V, the value of this capacitor should be 100pF. For voltages > 1.8V, the approximate value of this capacitor can be calculated as shown in Equation 5: (3 x 10*7) x (R 1 ) R 2) C1 + (R 1 x R2) (5) The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration) or if an output voltage < 1.8V is chosen, then the minimum recommended output capacitor is 4.7μF instead of 2.2μF. 8 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 OUTPUT VOLTAGE PROGRAMMING GUIDE VIN IN 1m F OUT TPS73001 EN NR VOUT R1 C1 2.2mF GND FB 0.01mF R2 OUTPUT VOLTAGE R1 R2 C1 1.22V short open 0pF 2.5V 31.6kW 30.1kW 22pF 3.3V 51kW 30.1kW 15pF 3.6V 59kW 30.1kW 15pF Figure 17. TPS73001 Adjustable LDO Regulator Programming Regulator Protection The TPS730xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate. The TPS730xx features internal current limiting and thermal protection. During normal operation, the TPS730xx limits output current to approximately 400mA. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum voltage ratings of the device. If the temperature of the device exceeds approximately +165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately +140°C, regulator operation resumes. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS730xx www.ti.com SBVS054H – NOVEMBER 2004 – REVISED OCTOBER 2007 TPS730xxYZQ NanoStar™ Wafer Chip Scale Information 0,79 0,84 1,30 1,34 0.625 Max NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. NanoStar package configuration. D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material. NanoStar is a trademark of Texas Instruments. Figure 18. NanoStar™ Wafer Chip Scale Package 10 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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