LP5907 www.ti.com SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 ULTRA LOW NOISE, 250-mA LINEAR REGULATOR FOR RF AND ANALOG CIRCUITS REQUIRES NO BYPASS CAPACITOR Check for Samples: LP5907 FEATURES 1 • • • • • Stable with 1-µF Ceramic Input and Output Capacitors No Noise Bypass Capacitor Required Remote Output Capacitor Placement Thermal-overload and Short-circuit Protection –40°C to +125°C Junction Temperature Range for Operation PACKAGE • • 4-Bump Ultra-Thin Micro SMD (Lead Free): 0.35-mm Pitch, 0.65 mm × 0.65 mm × 0.40 mm 5-Pin SOT23 (Lead Free): 2.92 mm x 1.6 mm x 1 mm xxx xxx APPLICATIONS • • • Cellular Phones PDA Handsets Wireless LAN Devices Typical Application Circuit VOUT VIN INPUT 1.0 PF OUTPUT 1.0 PF LP5907 KEY SPECIFICATIONS • • • • • • • • • • Input Voltage Range: 2.2 V to 5.5 V Output Voltage Range: 1.2 V to 4.5 V Output Current: 250 mA Low Output Voltage Noise: <10 µVRMS PSRR: 82 dB at 1 kHz Output Voltage Tolerance: ±2% Virtually Zero IQ (Disabled): <1 µA Very Low IQ (Enabled): 12 µA Startup Time: 80 µs Low Dropout: 120 mV Typical ENABLE VEN GND GND SVA-30180501 DESCRIPTION The LP5907 is a linear regulator capable of supplying 250-mA output current. Designed to meet the requirements of RF and analog circuits, the LP5907 device provides low noise, high PSRR, low quiescent current, and low line or load transient response figures. Using new innovative design techniques, the LP5907 offers class-leading noise performance without a noise bypass capacitor and the ability for remote output capacitor placement. The device is designed to work with a 1-µF input and a 1-µF output ceramic capacitor (no bypass capacitor is required). The device is available in an ultra-thin micro SMD package as well as a 5-pin SOT23 package. This device is available between 1.2 V and 4.5 V in 25-mV steps. Please contact Texas Instruments Sales for specific voltage option needs. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated LP5907 SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAMS 4-Bump Ultra-Thin micro SMD Package VIN VOUT VOUT VIN A1 A2 A2 A1 W B1 B2 GND B2 GND VEN B1 VEN BOTTOM VIEW TOP VIEW TOP MARKING SVA-30180502 Note: The actual physical placement of the package marking will vary from part to part. 5-Pin SOT23 Package (Top View) VIN 1 5 VOUT GND 2 EN 3 4 N/C SVA-30180519 PIN DESCRIPTIONS 2 NAME MICRO SMD PIN NO. SOT23 PIN NO. VIN A1 1 Input voltage supply. A 1-µF capacitor should be connected at this input. VOUT A2 5 Output voltage. A 1-µF Low ESR capacitor should be connected to this pin. Connect this output to the load circuit. An internal 280-Ω discharge resistor prevents a charge remaining on VOUT when VEN is low. VEN B1 N/A EN N/A 3 Enable input; disables the regulator when ≤0.4 V. Enables the regulator when ≥1.2 V. An internal 1-MΩ pulldown resistor connects this input to ground. GND B2 2 Common ground N/C N/A 4 No connect pin DESCRIPTION Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 LP5907 www.ti.com SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Input voltage –0.3 6 V VOUT Output voltage –0.3 to (VIN + 0.3 V) 6 V VEN Enable input voltage –0.3 to (VIN + 0.3 V) 6 V 150 °C 150 °C 260 °C 2 kV 200 V Continuous power dissipation (3) Internally Limited Junction temperature (TJMAX) Storage temperature range –65 Maximum lead temperature (soldering, 10 seconds) ESD rating (4) (1) (2) (3) (4) Human body model Machine model If Military or Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Internal thermal shutdown circuitry protects the device from permanent damage. The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 OPERATING RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) MIN VIN Input voltage range VEN Enable voltage range Recommended load current (3) NOM MAX UNIT 2.2 5.5 0 to (VIN + 0.3) 5.5 V V 0 250 mA TJ Junction temperature range –40 +125 °C TA Ambient temperature range (3) –40 +85 °C (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See applications section. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER θJA (1) (2) Junction to ambient thermal resistance (1) TEST CONDITIONS MIN TYP MAX Micro SMD 119.6 SOT23 188.8 4L cellphone board (micro SMD) 186.5 JEDEC board (2) UNIT °C/W Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Detailed description of the board can be found in JESD51-7 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 3 LP5907 SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (1) (2) (3) Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating junction temperature range (–40°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to LP5907 (all packages) Typical Application Circuit (pg. 1) with: VIN = VOUT (NOM) + 1 V, VEN = 1.2 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA. PARAMETER VIN TEST CONDITIONS Input voltage Output voltage tolerance ΔVOUT ILOAD MIN 2.2 5.5 –2 2 VIN = (VOUT(NOM) + 1 V) to 5.5 V, IOUT = 1 mA to 200 mA (VOUT < 1.8V, SOT23) -3 3 Line regulation VIN = (VOUT(NOM) + 1 V) to 5.5 V, IOUT = 1 mA Load regulation IOUT = 1 mA to 250 mA Load current See Ground current (6) IG Dropout voltage (7) VDO Short circuit current limit %/V 0.001 %/mA (4) mA 250 12 25 VEN = 1.2 V, IOUT = 250 mA 250 425 VEN = 0.3 V (Disabled) 0.2 1 IOUT = 0 mA (VEN = 1.2 V) 14 VOUT = 2.8 V, IOUT = 100 mA 50 VOUT = 2.8 V, IOUT = 250 mA 120 PSRR Power supply rejection ratio (9) eN Output noise voltage (9) TSHUTDOWN Thermal shutdown See V 0.02 VOUT = 2.8 V, IOUT = 250 mA (SOT23 package) ISC UNIT % VEN = 1.2 V, IOUT = 0 mA Quiescent current (5) MAX VIN = (VOUT(NOM) + 1 V) to 5.5 V, IOUT = 1 mA to 200 mA Maximum output current IQ TYP (8) µA 200 mV 250 250 500 f = 100 Hz, IOUT = 20 mA 90 f = 1 kHz, IOUT = 20 mA 82 f = 10 kHz, IOUT = 20 mA 65 f = 100 kHz, IOUT = 20 mA 60 BW = 10 Hz to 100 kHz µA IOUT = 1 mA 10 IOUT = 250 mA 6.5 Temperature mA dB µVRMS 160 Hysteresis °C 15 LOGIN INPUT THRESHOLDS VIL Low input threshold (VEN) VIN = 2.2 V to 5.5 V VIH High input threshold (VEN) VIN = 2.2 V to 5.5 V IEN Input current at VEN Pin (10) VEN = 5.5 V and VIN = 5.5 V VEN = 0 V and VIN = 5.5 V 0.4 1.2 V V 5.5 0.001 µA (1) (2) All voltages are with respect to the potential at the GND pin. Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. (3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). See applications section. (4) The device maintains a stable, regulated output voltage without a load current. (5) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. (6) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device. (7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. (8) Short Circuit Current is measured with VOUT pulled to 0 V and VIN worst case = 6 V. (9) This specification is ensured by design. (10) There is a 1-MΩ resistor between VEN and ground on the device. 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 LP5907 www.ti.com SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 ELECTRICAL CHARACTERISTICS(1)(2)(3) (continued) Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the full operating junction temperature range (–40°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to LP5907 (all packages) Typical Application Circuit (pg. 1) with: VIN = VOUT (NOM) + 1 V, VEN = 1.2 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TRANSIENT CHARACTERISTICS Line transient (11) VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) + 1.6 V) in 30 µs, IOUT = 1 mA –1 mV VIN = (VOUT(NOM) + 1.6 V) to (VOUT(NOM) + 1 V) in 30 µs, IOUT = 1 mA ΔVOUT Load transient (11) 1 IOUT = 1mA to 200 mA in 10 µs –40 IOUT = 200 mA to 1mA in 10 µs Overshoot on startup (11) Stated as a percentage of nominal VOUT Turn-on time To 95% of VOUT(NOM) mV 40 80 5 % 150 µs (11) This specification is ensured by design. OUTPUT AND INPUT CAPACITORS over operating free-air temperature range (unless otherwise noted) PARAMETER CIN Input capacitance COUT Output capacitance (2) ESR Output/Input capacitance (2) (1) (2) TEST CONDITIONS (2) Capacitance for stability MIN (1) TYP 0.7 1 0.7 1 5 MAX UNIT 10 500 µF mΩ Note: The minimum capacitance should be greater than 0.5 μF over the full range of operating conditions. The capacitor tolerance should be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions. This specification is guaranteed by design. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 5 LP5907 SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 www.ti.com BLOCK DIAGRAM IN OUT REFERENCE FILTER + Bandgap Rf VREFC Cf + A special integrated filter For noise suppression 1.2V SVA-30180506 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 LP5907 www.ti.com SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS Unless otherwise noted, these curves apply to the micro SMD package only, VOUT = 2.8 V, VIN = 3.7 V, EN = 1.2 V, CIN = 1 µF, COUT = 1 µF, TA = 25°C. Quiescent Current vs Input Voltage Ground Current vs Output Current 350 14 300 GROUND CURRENT ( A) 16 IQ( A) 12 10 8 6 4 250 200 150 100 VIN = 3.0V VIN = 3.8V VIN = 4.2V VIN = 5.5V 50 2 0 0 2.3 2.8 3.3 3.8 4.3 VIN(V) 4.8 5.3 0 5.8 50 SVA-30180569 Load Regulation 100 150 200 IOUT(mA) 250 300 SVA-30180571 Line Regulation 2.900 2.900 VIN= 3.6V 2.875 Load = 10 mA 2.875 2.850 2.825 2.825 VOUT(V) VOUT(V) 2.850 2.800 2.800 2.775 2.775 2.750 2.750 -40°C 90°C 25°C 2.725 -40°C 90°C 25°C 2.725 2.700 2.700 0 50 100 150 LOAD (mA) 200 250 3.0 3.5 SVA-30180567 Inrush Current VIN 4.0 4.5 VIN(V) 5.0 5.5 SVA-30180568 Line Transient = 3.2 V ↔ 4.2 V, Load = 1 mA 2V/DIV VOUT VOUT (AC Coupled) 10 mV/ DIV VIN 1V/DIV 2V/DIV VIN = VEN 1A/DIV IIN 10 s/DIV 2 ms/DIV SVA-30180510 SVA-30180509 VIN Line Transient = 3.2 V ↔ 4.2 V, Load = 250 mA VOUT (AC Coupled) 10 mV/ DIV VIN 1V/DIV Load Transient, Load = 0 mA ↔ 250 mA, -40°C VOUT 100 mV/DIV LOAD 200 mA/DIV 10 s/DIV 100 s/DIV SVA-30180511 SVA-30180512 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 7 LP5907 SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, these curves apply to the micro SMD package only, VOUT = 2.8 V, VIN = 3.7 V, EN = 1.2 V, CIN = 1 µF, COUT = 1 µF, TA = 25°C. Load Transient, Load = 0 mA ↔ 250 mA, 90°C Load Transient, Load = 0 mA ↔ 250 mA, 25°C VOUT 100 mV/DIV VOUT 100 mV/DIV LOAD 200 mA/DIV LOAD 200 mA/DIV 100 s/DIV 100 s/DIV SVA-30180514 SVA-30180513 Startup 0 mA Startup 250 mA 1V/DIV 1V/DIV VOUT VOUT 1V/DIV 1V/DIV EN EN 20 s/DIV 20 s/DIV SVA-30180516 SVA-30180515 Dropout Voltage vs Load Current Noise Density Test DROPOUT VOLTAGE (mV) 140 120 100 80 60 40 Dropout Voltage 20 0 0 50 100 150 200 LOAD CURRENT (mA) 250 SVA-30180573 SVA-30180521 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 LP5907 www.ti.com SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) Unless otherwise noted, these curves apply to the micro SMD package only, VOUT = 2.8 V, VIN = 3.7 V, EN = 1.2 V, CIN = 1 µF, COUT = 1 µF, TA = 25°C. PSRR Loads Averaged 20 Hz to 100 kHz PSRR Loads Averaged 100 Hz to 100 kHz 0 0 20 mA 20 mA GAIN (dB) -40 -60 -20 50 mA 100 mA 150 mA 200 mA -40 GAIN (dB) -20 250 mA -60 -80 -80 -100 -100 -120 20 100 1k 10k 100k -120 100 50 mA 100 mA 150 mA 200 mA 250 mA 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) SVA-30180507 SVA-30180508 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 9 LP5907 SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 www.ti.com APPLICATION INFORMATION POWER DISSIPATION AND DEVICE OPERATION The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. As stated in Note (3) of the electrical characteristics, the allowable power dissipation for the device in a given package can be calculated using the equation: PD = (TJMAX - TA) ¾ qJA (1) The actual power dissipation across the device can be represented by the following equation: PD = (VIN - VOUT) x IOUT (2) This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. EXTERNAL CAPACITORS Like any low-dropout regulator, the LP5907 requires external capacitors for regulator stability. The LP5907 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the output capacitor for good load transient performance. At least a 1-µF capacitor has to be connected between the LP5907 input pin and ground for stable operation over full load current range. Basically, it is ok to have more output capacitance than input, as long as the input is at least 1-µF. This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to connect the battery or other power source to the LP5907, then it is recommended to increase the input capacitor to at least 10 µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain 1 µF ±30% over the entire operating temperature range. OUTPUT CAPACITOR The LP5907 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A ceramic capacitor (dielectric types X5R or X7R) in the 1 µF to 10 µF range, and with ESR between 5 mΩ to 500 mΩ, is suitable in the LP5907 application circuit. For this device the output capacitor should be connected between the VOUT pin and a good ground connection. It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see CAPACITOR CHARACTERISTICS below). The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 LP5907 www.ti.com SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 CAPACITOR CHARACTERISTICS The LP5907 is designed to work with ceramic capacitors on the input and output to take advantage of the benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LP5907. The temperature performance of ceramic capacitors varies by type and manufacturer. Most large value ceramic capacitors (≥2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C. A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1 µF to 10 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed. REMOTE CAPACITOR OPERATION The LP5907 requires at least a 1-µF capacitor at output pin, but there is no strict requirements about the location of the capacitor in regards the LDO output pin. In practical designs the output capacitor may be located some 510 cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote capacitor feature helps user to minimize the number of capacitors in the system. As a good design practice, it is good to keep the wiring parasitic inductance at a minimum, which means to use as wide as possible traces from the LDO output to the capacitors, keeping the LDO trace layer as close as possible to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many as possible vias between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH. For the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to the sum of the capacitance at the output node for the best load transient performance. NO-LOAD STABILITY The LP5907 will remain stable and in regulation with no external load. ENABLE CONTROL The LP5907 may be switched ON or OFF by a logic input at the ENABLE pin. A high voltage at this pin will turn the device on. When the enable pin is low, the regulator output is off and the device typically consumes 3 nA. However if the application does not require the shutdown feature, the VEN pin can be tied to VIN to keep the regulator output permanently on. A 1-MΩ pulldown resistor ties the VEN input to ground, this ensures that the device will remain off when the enable pin is left open circuit. To ensure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. MICRO SMD MOUNTING The micro SMD package requires specific mounting techniques, which are detailed in Texas Instruments Application Note AN-1112. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the micro SMD device. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 11 LP5907 SNVS798D – APRIL 2012 – REVISED NOVEMBER 2012 www.ti.com MICRO SMD LIGHT SENSITIVITY Exposing the micro SMD device to direct light may cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the fluorescent lighting used inside most buildings has very little effect on performance. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: LP5907 PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish MSL Peak Temp Samples (3) (Requires Login) (2) LP5907MFE-1.2/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-1.8/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-2.7/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-2.8/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-2.85/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-3.0/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-3.1/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-3.2/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI LP5907MFE-4.5/NOPB PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI TBD Call TI Call TI SOT-23 DBV 5 3000 TBD Call TI Call TI TBD Call TI Call TI LP5907MFX-1.2 PREVIEW LP5907MFX-1.2/NOPB PREVIEW LP5907MFX-1.8 PREVIEW 5 LP5907MFX-2.8/NOPB PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI LP5907MFX-2.85/NOPB PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI LP5907MFX-3.0/NOPB PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI LP5907MFX-3.1/NOPB PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI LP5907MFX-3.2/NOPB PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI LP5907MFX-3.3/NOPB PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI LP5907MFX-4.5/NOPB PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI LP5907SNE-1.2/NOPB PREVIEW X2SON DQN 4 1 TBD Call TI Call TI 1 TBD Call TI Call TI TBD Call TI Call TI TBD Call TI Call TI TBD Call TI Call TI TBD Call TI Call TI LP5907SNE-2.8/NOPB PREVIEW X2SON DQN 4 LP5907SNE-2.85/NOPB PREVIEW X2SON DQN 4 LP5907SNE-3.1/NOPB PREVIEW X2SON DQN 4 LP5907SNX-1.2 PREVIEW X2SON DQN 4 LP5907SNX-1.2/NOPB PREVIEW X2SON DQN 4 LP5907SNX-1.8 PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907SNX-2.7 PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907SNX-2.8 PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907SNX-2.8/NOPB PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907SNX-2.85 PREVIEW X2SON DQN 4 TBD Call TI Call TI Addendum-Page 1 1 1 1 PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2012 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish MSL Peak Temp Samples (3) (Requires Login) (2) LP5907SNX-2.85/NOPB PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907SNX-3.0 PREVIEW X2SON DQN 4 TBD Call TI Call TI TBD Call TI Call TI TBD Call TI Call TI LP5907SNX-3.1 PREVIEW X2SON DQN 4 LP5907SNX-3.1/NOPB PREVIEW X2SON DQN 4 LP5907SNX-3.2 PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907SNX-3.3 PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907SNX-4.5 PREVIEW X2SON DQN 4 TBD Call TI Call TI LP5907UVE-1.2/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVE-1.8/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVE-2.8/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVE-2.85/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVE-3.0/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVE-3.1/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVE-3.3/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVE-4.5/NOPB ACTIVE DSBGA YKE 4 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVX-1.2/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVX-1.8/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVX-2.8/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVX-2.85/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVX-3.0/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVX-3.1/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Addendum-Page 2 1 PACKAGE OPTION ADDENDUM www.ti.com 19-Dec-2012 Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) LP5907UVX-3.3/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LP5907UVX-4.5/NOPB ACTIVE DSBGA YKE 4 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LP5907UVE-1.2/NOPB DSBGA YKE 4 250 178.0 8.4 LP5907UVE-1.8/NOPB DSBGA YKE 4 250 178.0 LP5907UVE-2.8/NOPB DSBGA YKE 4 250 178.0 LP5907UVE-2.85/NOPB DSBGA YKE 4 250 LP5907UVE-3.0/NOPB DSBGA YKE 4 LP5907UVE-3.1/NOPB DSBGA YKE LP5907UVE-3.3/NOPB DSBGA YKE LP5907UVE-4.5/NOPB DSBGA LP5907UVX-1.2/NOPB LP5907UVX-1.8/NOPB 0.71 0.71 0.51 4.0 8.0 Q1 8.4 0.71 0.71 0.51 4.0 8.0 Q1 8.4 0.71 0.71 0.51 4.0 8.0 Q1 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 250 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 4 250 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 4 250 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 YKE 4 250 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 LP5907UVX-2.8/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 LP5907UVX-2.85/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 LP5907UVX-3.0/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 LP5907UVX-3.1/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 LP5907UVX-3.3/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 LP5907UVX-4.5/NOPB DSBGA YKE 4 3000 178.0 8.4 0.71 0.71 0.51 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5907UVE-1.2/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVE-1.8/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVE-2.8/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVE-2.85/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVE-3.0/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVE-3.1/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVE-3.3/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVE-4.5/NOPB DSBGA YKE 4 250 203.0 190.0 41.0 LP5907UVX-1.2/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 LP5907UVX-1.8/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 LP5907UVX-2.8/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 LP5907UVX-2.85/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 LP5907UVX-3.0/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 LP5907UVX-3.1/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 LP5907UVX-3.3/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 LP5907UVX-4.5/NOPB DSBGA YKE 4 3000 206.0 191.0 90.0 Pack Materials-Page 2 MECHANICAL DATA YKE0004 0.400 ±0.045 D E TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE 04XXX (Rev ) D: Max = 0.695 mm, Min =0.595 mm E: Max = 0.695 mm, Min =0.595 mm 4215149/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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