TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 350mA, Ultra-Low VIN, RF Low-Dropout Linear Regulator with Bias Pin FEATURES DESCRIPTION 1 • 350mA High-Performance LDO • Low Quiescent Current: 38µA • Excellent Load Transient Response: ±15mV for ILOAD = 0mA to 350mA in 1µs • Excellent Line Transient Response: ΔVOUT = ±2mV for ΔVBIAS = ±600mV in 1µs ΔVOUT = ±200µV for ΔVIN = ±400mV in 1µs • Low Noise: 48µVRMS (10Hz to 100kHz) • 80dB VIN PSRR (10Hz to 10kHz) • 70dB VBIAS PSRR (10Hz to 10kHz) • Fast Start-Up Time: 140µs • Built-In Soft-Start with Monotonic VOUT Rise and Startup Current Limited to 100mA + ILOAD • Over-Current and Thermal Protection • Low Dropout: 110mV at ILOAD = 350mA • Stable with 2.2µF Output Capacitor • Available in 1,33mm x 0,96mm WCSP-5 and 2mm x 2mm SON-6 Packages 2 APPLICATIONS • • • • Digital Cameras Cellular Camera Phones Wireless LAN Handheld Products TPS720xx DRV PACKAGE 2mm x 2mm SON-6 (TOP VIEW) OUT 1 NC 2 EN 3 Thermal Pad 6 IN 5 GND 4 BIAS TPS720xx YZU PACKAGE 1,33mm x 0,96mm WCSP-5 (TOP VIEW) C3 BIAS B2 GND A3 The VBIAS rail that powers the control circuit of the LDO draws very low current (on the order of the quiescent current of the LDO) and can be connected to any power supply that is equal to or greater than 1.4V above the output voltage. The main power path is through VIN, which can be a lower voltage than VBIAS; it can be as low as VOUT + VDO, increasing the efficiency of the solution in many power-sensitive applications. For example, VIN can be an output of a high-efficiency, dc-dc step-down regulator. The TPS720xx supports a novel feature in which the output of the LDO regulates under light loads when the IN pin is left floating. The light-load drive current is sourced from VBIAS under this condition. This feature is particularly useful in power-saving applications where the dc/dc converter connected to the IN pin is disabled but the LDO is still required to regulate the voltage to a light load. The TPS720xx is stable with ceramic capacitors and uses an advanced BICMOS fabrication process that yields a dropout of 110mV at a 350mA output load. The TPS720xx has the unique feature of providing a monotonic VOUT rise (overshoot limited to 3%) with VIN inrush current limited to 100mA + ILOAD with an output capacitor of 2.2µF. The TPS720xx uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over load, line, process, and temperature extremes. An ultra-small wafer chip-scale package (WCSP) makes the TPS720xx ideal for handheld applications. The TPS720xx is also available in a SON-8 package. This family of devices is fully specified over the temperature range of TJ = –40°C to +125°C. VBATT C1 EN OUT The TPS720xx family of dual rail, low-dropout linear regulators (LDOs) offers outstanding ac performance (PSRR, load and line transient response), while consuming a very low quiescent current of 38µA. A1 BIAS Standalone dc/dc Converter or PMU 1.8V IN OUT 1.3V VCORE TPS720xx EN IN GND 2.2mF Ceramic VEN 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated TPS720xx SBVS100D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOUT (2) PRODUCT TPS720xxyyyz (1) (2) XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V). YYY is the package designator. Z is tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND. PARAMETER TPS720xx Input voltage range (steady-state), VIN (2) UNIT –0.3 to VBIAS or +5.0 Peak transient input voltage, VIN_PEAK (4) (3) V +5.5 V Bias voltage range, VBIAS –0.3 to +6.0 V Enable voltage range, VEN –0.3 to +6.0 V Output voltage range, VOUT –0.3 to +5.0 V Peak output current, IOUT Internally limited Output short-circuit duration Indefinite Total continuous power dissipation, PDISS See Dissipation Ratings Table Human body model (HBM) 2000 V Charged device model (CDM) 500 V ESD rating 100 V Operating junction temperature range, TJ Machine model (MM) –55 to +125 °C Storage temperature range, TSTG –55 to +150 °C (1) (2) (3) (4) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. To ensure proper operation of the device it is necessary that VIN ≤ VBIAS under all conditions. Whichever is less. For durations no longer than 1ms each, for a total of no more than 1000 occurrences over the lifetime of the device. DISSIPATION RATINGS BOARD PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C High-K (1) YZU 51°C/W 248°C/W 4mW/°C 403mW 222mW 160mW High-K (1) DRV 20°C/W 65°C/W 15.4mW/°C 1580mW 845mW 615mW (1) 2 The JEDEC high-K (2s2p) board used to derive this data was a 3- × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN ≥ VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER VIN Input voltage range VBIAS Bias voltage range Output voltage range VOUT (3) ΔVOUT/ΔVIN Output accuracy TEST CONDITIONS (4) TYP MAX UNIT (1) VBIAS or 4.5 (2) V 2.5 5.5 V 1.1 0.9 3.6 V Nominal TJ = +25°C –3.0 +3.0 mV Over VBIAS, VIN, IOUT, TJ = –40°C to +125°C VOUT + 1.4V ≤ VBIAS ≤ 5.5V, VOUT + 0.5V ≤ VIN ≤ 4.5V, 0mA ≤ IOUT ≤ 350mA –2.0 +2.0 % Over VBIAS, VIN, IOUT, TJ = –40°C to +125°C DRV package only: VOUT + 1.4V ≤ VBIAS ≤ 5.5V, VOUT + 0.5V ≤ VIN ≤ 4.5V, 0mA ≤ IOUT ≤ 350mA, VOUT < 1.2V –25 +25 mV Over VBIAS, VIN, IOUT, TJ = –10°C to +85°C YZU package only: VOUT + 1.4V ≤ VBIAS ≤ 5.5V, VOUT + 0.5V ≤ VIN ≤ 4.5V, 0mA ≤ IOUT ≤ 350mA 1.6V ≤ VOUT ≤ 3.3V –1.0 +1.0 % VIN floating VOUT + 1.4V ≤ VBIAS ≤ 5.5V, 0µA ≤ IOUT ≤ 500µA VIN line regulation ΔVOUT/ΔVBIAS VBIAS line regulation ±1.0 % VIN = (VOUT + 0.5V) to 4.5V, IOUT = 1mA 16 µV/V VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater) to 5.5V, IOUT = 1mA 16 µV/V VIN line transient ΔVIN = 400mV, tRISE = tFALL = 1µs ±200 µV VBIAS line transient ΔVBIAS = 600mV, tRISE = tFALL = 1µs ±0.8 mV Load regulation 0mA ≤ IOUT ≤ 350mA (no load to full load) –15 µV/mA Load transient 0mA ≤ IOUT ≤ 350mA, tRISE = tFALL = 1µs ±15 mV VIN dropout voltage (5) VIN = VOUT(NOM) – 0.1V, (VBIAS – VOUT(NOM)) = 1.4V, IOUT = 350mA 110 VBIAS dropout voltage (6) VIN = VOUT(NOM) + 0.3V, IOUT = 350mA ICL Output current limit VOUT = 0.9 × VOUT(NOM) IGND Ground pin current ISHDN Shutdown current (IGND) ΔVOUT/ΔIOUT VDO_IN VDO_BIAS PSRR (1) (2) (3) (4) (5) (6) MIN VIN power-supply rejection ratio 420 200 mV 1.09 1.4 V 525 800 mA µA IOUT = 100µA 38 IOUT = 0mA to 350mA 54 80 µA VEN ≤ 0.4V, TJ = -40°C to +85°C 0.5 2 µA VIN – VOUT ≥ 0.5V, VBIAS = VOUT + 1.4V, IOUT = 350mA f = 10Hz 85 dB f = 100Hz 85 dB f = 1kHz 85 dB f = 10kHz 80 dB f = 100kHz 70 dB f = 1MHz 50 dB Performance specifications are ensured up to a minimum VIN = VOUT + 0.5V. Whichever is less. Minimum VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater) and VIN= VOUT + 0.5V. VO nominal value is factory programmable through the onchip EEPROM. Measured for devices with VOUT(NOM) ≥ 1.2V. VBIAS – VOUT with VOUT = VOUT(NOM) – 0.1V. Measured for devices with VOUT(NOM) ≥ 1.8V. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS720xx SBVS100D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN ≥ VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER PSRR VIN – VOUT ≥ 0.5V, VBIAS = VOUT + 1.4V, IOUT = 350mA MIN dB 80 dB f = 1kHz 75 dB f = 10kHz 65 dB f = 100kHz 55 dB f = 1MHz 35 dB 48 µVRMS IVIN_INRUSH Inrush current on VIN VBIAS = (VOUT +1.4V) or 2.5V (whichever is greater), VIN = VOUT + 0.5V Startup time VOUT = 95% VOUT(NOM), IOUT = 350mA, COUT = 2.2µF VEN(LO) Enable pin low (disabled) IEN UVLO Undervoltage lockout VBIAS rising Hysteresis VBIAS falling TJ Operating junction temperature Submit Documentation Feedback mA 140 µs V 0 VEN = 5.5V, VIN = 4.5V, VBIAS = 5.5V Thermal shutdown temperature 100 + ILOAD 1.1 Enable pin current TSD UNIT f = 100Hz BW = 10Hz to 100kHz, VBIAS ≥ 2.5V, VIN = VOUT + 0.5V Enable pin high (enabled) MAX 80 Output noise voltage VEN(HI) TYP f = 10Hz VN tSTR 4 VBIAS power-supply rejection ratio TEST CONDITIONS 2.41 2.45 0.4 V 1.0 µA 2.49 V 150 mV Shutdown, temperature increasing +160 °C Reset, temperature decreasing +140 –40 °C +125 °C Copyright © 2008–2009, Texas Instruments Incorporated TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 DEVICE INFORMATION IN OUT Current Limit Thermal Shutdown BIAS UVLO Bandgap EN Functional Block Diagram PIN CONFIGURATION DRV PACKAGE SON-6 (TOP VIEW) YZU PACKAGE WCSP-5 (TOP VIEW) C3 OUT 1 NC 2 EN 3 Thermal Pad (1) 6 IN 5 GND 4 BIAS BIAS B2 GND A3 OUT (1) C1 EN A1 IN It is recommended that the SON (DRV) package thermal pad be connected to ground. PIN DESCRIPTIONS TPS720xx NAME DRV YZU DESCRIPTION OUT 1 A3 Output pin. A 2.2µF ceramic capacitor is connected from this pin to ground, for stability and to provide load transients. See Input and Output Capacitor Requirements in the Application Information section. NC 2 — No connection. EN 3 C3 Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT. A logic low on this pin turns off the device. BIAS 4 C1 Bias supply pin. It is recommended that this input be bypassed with a ceramic capacitor to ground for better transient performance. See Input and Output Capacitor Requirements in the Application Information section. GND 5 B2 Ground pin. IN 6 A1 Input pin. This pin can be a maximum of 4.5V; VIN must not exceed VBIAS. Bypass this input with a ceramic capacitor to ground. See Input and Output Capacitor Requirements in the Application Information section. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS720xx SBVS100D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C. VIN LINE REGULATION IOUT = 0mA (TPS72013YZU) 1.40 1.40 1.38 1.38 1.36 +85°C -10°C +25°C 1.34 1.36 -40°C 1.32 1.30 1.28 +105°C 1.26 1.32 1.30 1.28 +105°C +125°C 1.24 1.22 1.22 1.20 1.20 2.5 3.0 3.5 4.5 4.0 2.5 3.0 3.5 VIN (V) Figure 2. VBIAS LINE REGULATION IOUT = 0mA (TPS72013YZU) VBIAS LINE REGULATION IOUT = 350mA (TPS72013YZU) 1.40 1.38 +85°C -10°C +25°C 1.36 -40°C 1.32 1.30 1.28 +105°C 1.26 1.28 +105°C +125°C 1.22 1.20 1.20 2.5 3.0 3.5 4.5 4.0 5.5 5.0 2.5 3.5 4.5 4.0 VBIAS (V) Figure 3. Figure 4. LOAD REGULATION UNDER LIGHT LOADS (TPS72013YZU) LOAD REGULATION (TPS72013YZU) 1.40 1.38 1.38 +85°C -10°C +25°C 1.34 3.0 VBIAS (V) 1.40 1.36 1.36 -40°C 1.32 1.30 1.28 +105°C 1.26 5.0 5.5 -40°C 1.32 1.30 1.28 +105°C 1.26 +125°C 1.24 +85°C +25°C -10°C 1.34 VOUT (V) VOUT (V) 1.30 1.24 1.22 -40°C 1.32 1.26 +125°C 1.24 +85°C -10°C +25°C 1.34 VOUT (V) VOUT (V) Figure 1. 1.38 1.34 4.5 4.0 VIN (V) 1.40 1.36 +125°C 1.24 1.22 1.22 1.20 1.20 0 6 -40°C 1.26 +125°C 1.24 +85°C -10°C +25°C 1.34 VOUT (V) VOUT (V) VIN LINE REGULATION IOUT = 350mA (TPS72013YZU) 1 2 3 4 5 6 7 8 9 10 0 50 100 150 200 IOUT (mA) IOUT (mA) Figure 5. Figure 6. Submit Documentation Feedback 250 300 350 Copyright © 2008–2009, Texas Instruments Incorporated TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C. LOAD REGULATION WITH VIN FLOATING (TPS72013YZU) LOAD REGULATION WITH VIN FLOATING (TPS72013YZU) 1.40 1.40 TJ = +25°C 1.38 1.36 1.36 VBIAS = 3.0V 1.32 VBIAS = 4.0V 1.34 VBIAS = 5.0V VOUT (mA) VOUT (mA) 1.34 1.30 1.28 TJ = +125°C 1.32 1.30 TJ = -40°C 1.28 TJ = +25°C 1.26 1.26 1.24 VBIAS = 2.7V 1.22 VBIAS = 3.5V 0.5 1.0 1.5 2.0 2.5 3.0 TJ = +85°C 1.22 VBIAS = 5.5V 0 TJ = 0°C 1.24 VBIAS = 4.5V 1.20 TJ = +105°C 1.20 3.5 4.0 0 0.1 0.2 0.3 0.4 0.6 0.7 0.8 IOUT (mA) Figure 7. Figure 8. VIN DROPOUT VOLTAGE vs OUTPUT CURRENT (TPS72013YZU) VBIAS DROPOUT VOLTAGE vs TEMPERATURE (TPS72033YZU) 0.9 1.0 1.15 +125°C +105°C 120 100 80 60 -10°C -40°C +25°C 40 VDO_BIAS = VBIAS - VOUT (V) 1.14 140 +85°C 20 1.13 1.12 1.11 1.10 1.09 1.08 1.07 1.06 VOUT = VOUT(NOM) - 0.1 IOUT = 350mA 1.05 1.04 0 0 50 100 150 200 250 350 300 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ (°C) IOUT (mA) Figure 9. Figure 10. OUTPUT VOLTAGE vs TEMPERATURE (TPS72013YZU) GROUND PIN CURRENT vs VBIAS INPUT VOLTAGE (TPS72013YZU) 1.345 50 45 1.325 IOUT = 1mA 40 IOUT = 0mA 35 IOUT = 1mA 1.305 IGND (mA) VOUT (V) 0.5 IOUT (mA) 160 VDO_IN (mV) VBIAS = 2.7V 1.38 1.285 IOUT = 350mA 30 25 20 +125°C +105°C +85°C +25°C -10°C -40°C 15 1.265 10 5 0 1.245 -40 -25 -10 5 20 35 50 65 TJ (°C) Figure 11. Copyright © 2008–2009, Texas Instruments Incorporated 80 95 110 125 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VBIAS (V) Figure 12. Submit Documentation Feedback 7 TPS720xx SBVS100D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C. GROUND PIN CURRENT vs OUTPUT CURRENT (TPS72013YZU) GROUND PIN CURRENT vs TEMPERATURE (TPS72013YZU) 60 70 IOUT = 350mA 60 +125°C +105°C +85°C 50 +25°C 40 IGND (mA) IGND (mA) 50 40 30 20 -40°C -10°C 20 30 10 10 0 0 0 50 100 150 200 250 350 300 -40 -25 -10 5 20 35 50 65 80 95 110 125 IOUT (mA) TJ (°C) Figure 13. Figure 14. SHUTDOWN CURRENT vs VBIAS INPUT VOLTAGE (TPS72013YZU) CURRENT LIMIT vs VBIAS INPUT VOLTAGE (TPS72013YZU) 3.0 675 2.5 650 -10°C +25°C -40°C +25°C -10°C -40°C +85°C 1.5 +125°C ICL (V) ISHDN (mA) 2.0 625 600 1.0 +85°C +105°C +105°C +125°C 575 0.5 0 550 2.5 3.0 3.5 4.5 4.0 5.0 5.5 2.5 3.0 3.5 VBIAS (V) 4.5 4.0 5.0 Figure 15. Figure 16. CURRENT LIMIT vs VIN INPUT VOLTAGE (TPS72013YZU) VIN POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TPS72015YZU) 675 120 -10°C +25°C 5.5 VBIAS (V) -40°C 100 650 (VIN - VOUT) = 0.5V (VBIAS - VOUT) = 1.4V IOUT = 0mA PSRR (dB) ICL (mA) 80 625 600 +85°C +105°C IOUT = 350mA 40 +125°C 575 20 550 0 2.5 3.0 3.5 VIN (V) Figure 17. 8 IOUT = 50mA 60 Submit Documentation Feedback 4.0 4.5 10 100 1k 10k 100k 1M 10M Frequency (Hz) Figure 18. Copyright © 2008–2009, Texas Instruments Incorporated TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C. VIN POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TPS72015YZU) VBIAS POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY (TPS72015YZU) 100 100 IOUT = 350mA (VIN - VOUT) = 350mV 80 80 PSRR (dB) PSRR (dB) IOUT = 1mA 60 (VIN - VOUT) = 300mV 40 60 40 (VIN - VOUT) = 250mV IOUT = 350mA 20 20 (VIN - VOUT) = 0.5V (VBIAS - VOUT) = 1.4V 0 0 Output Spectral Noise Density (mV/ÖHz) 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M Frequency (Hz) Frequency (Hz) Figure 19. Figure 20. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY (TPS72015YZU) VIN INRUSH CURRENT VIN = 1.8V, VOUT = 1.3V, VBIAS = 2.7V, IOUT = 0mA 10 VOUT = 1.3V IIN-PEAK = 110mA 1 IIN 50mA/div 0.1 EN 500mV/div 200mV/div VOUT 0.01 100 1k 10k 20ms/div 100k Frequency (Hz) Figure 21. VIN Figure 22. VIN LINE TRANSIENT RESPONSE VIN = 1.6V to 2.0V, VOUT = 1.3V, VBIAS = 2.7V, VIN SLEW RATE = 1V/µs, IOUT = 350mA VIN INRUSH CURRENT = 1.8V, VOUT = 1.3V, VBIAS = 2.7V, IOUT = 350mA VOUT = 1.3V IIN-PEAK = 400mA 1mV/div VOUT IIN 200mA/div 2.0V EN 500mV/div 200mV/div 200mV/div VIN 1.6V VOUT 20ms/div 100ms/div Figure 23. Figure 24. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS720xx SBVS100D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), VBIAS = (VOUT + 1.4V) or 2.5V (whichever is greater); VIN = VOUT + 0.5V, IOUT = 1mA, VEN = 1.1V, COUT = 2.2µF, unless otherwise noted. Typical values are at TJ = +25°C. VBIAS LINE TRANSIENT RESPONSE VIN = 1.8V, VOUT = 1.3V, VBIAS = 2.7V to 3.3V, VBIAS SLEW RATE = 600m/µs, IOUT = 350mA 1mV/div VOUT LOAD TRANSIENT RESPONSE VIN = 1.8V, VOUT = 1.3V, VBIAS = 2.7V, tRISE = 1µs 10mV/div VOUT 3.3V 200mV/div 10 300mA VBIAS 2.7V 100mA/div IOUT 0mA 100ms/div 100ms/div Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 APPLICATION INFORMATION The TPS720xx belongs to a family of new generation LDO regulators that use innovative circuitry to achieve ultra-wide bandwidth and high loop gain, resulting in extremely high PSRR (up to 1MHz) at very low headroom (VIN – VOUT). The implementation of the BIAS pin on the TPS720xx vastly improves efficiency of low VOUT applications by allowing the use of a preregulated, low-voltage input supply. The TPS720xx supports a novel feature in which the output of the LDO regulates under light loads (<500µA) when the IN pin is left floating. The light-load drive current is sourced from VBIAS under this condition. This feature is particularly useful in power-saving applications where the dc/dc converter connected to the IN pin is disabled but the LDO is still required to regulate the voltage to a light load. These features, combined with low noise, low ground pin current, and ultra-small packaging, make this device ideal for portable applications. This family of regulators offers sub-bandgap output voltages, current limit and thermal protection, and is fully specified from –40°C to +125°C. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability on the IN pin, it is good analog design practice to connect a 0.1µF to 1.0µF low equivalent series resistance (ESR) capacitor across the IN pin input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is located close to the power source. If source impedance is not sufficiently low, a 0.1µF input capacitor may be necessary to ensure stability. The BIAS pin does not require an input capacitor because it does not source high currents. However, if source impedance is not sufficiently low, a small 0.1µF bypass capacitor is recommended. The TPS720xx is designed to be stable with standard ceramic capacitors with values of 2.2µF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 250mΩ. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the Copyright © 2008–2009, Texas Instruments Incorporated ground connection for the output capacitor should be connected directly to the GND pin of the device. High equivalent series resistance (ESR) capacitors may degrade PSRR. The BIAS pin draws very little current and can be routed as a signal (make sure to shield it from high-frequency coupling). INTERNAL CURRENT LIMIT The TPS720xx internal current limits help protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The NMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shut down is triggered and the device is turned off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details. The NMOS pass element in the TPS720xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current is recommended. INRUSH CURRENT LIMIT The TPS720xx family of LDO regulators implement a novel inrush current-limit circuit architecture: the current drawn through the IN pin is limited to a finite value. This IINRUSHLIMIT charges the output to its final voltage. All the current drawn through VIN goes to charge the output capacitance when the load is disconnected. The following equation shows the inrush current limit performed by the circuit: IINRUSHLIMIT(A) = COUT(µF) × 0.0454545(V/µs) + ILOAD(A) (1) Assuming a COUT of 2.2µF with the load disconnected (that is, ILOAD = 0) the IINRUSHLIMIT is calculated to be 100mA. The inrush current charges the LDO output capacitor. If the output of the LDO regulates to 1.3V, then the LDO charges the output capacitor to the final output value in approximately 28.6µs. Another consideration is when a load is connected to the output of an LDO. The connected load tries to steer a portion of the current away from VOUT. The TPS720xx inrush current-limit circuit employs a new technique that supplies not only the IINRUSHLIMIT, but also the additional current needed by the load. If ILOAD = 350mA, then the IINRUSHLIMIT calculates to be approximately 450mA (from Equation 1). Submit Documentation Feedback 11 TPS720xx SBVS100D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com SHUTDOWN MINIMUM LOAD The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to the IN pin. The TPS720xx is stable with no output load. Traditional LDOs suffer from low loop gain at very light output loads. The TPS720xx employs an innovative, low-current mode circuit under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. DROPOUT VOLTAGE The TPS720xx uses a NMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the NMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the NMOS pass element. VDO approximately scales with output current because the NMOS device behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 19 in the Typical Characteristics section. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. UNDERVOLTAGE LOCK-OUT (UVLO) The TPS720xx uses an undervoltage lock-out circuit on the BIAS pin to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are less than 50µs duration. OUTPUT REGULATION WITH IN PIN FLOATING The TPS720xx supports a novel feature in which the output of the LDO regulates under light loads when the IN pin is left floating. Under normal conditions, when the IN pin is connected to a power source, the BIAS pin draws only tens of milliamperes. However, when the IN pin is floating, an innovative circuit is used that allows a mximum current of 500µA to be drawn by the load through the BIAS pin, while maintaining the output in regulation. This feature is particularly useful in power-saving applications where a dc/dc converter connected to the IN pin is disabled, but the LDO is required to regulate the output voltage to a light load. Figure 27 shows an application example where a microcontroller is not turned off (to maintain the state of the internal memory), but where the regulated supply (shown as the TPS62xxx) is turned off to reduce power. In this case, the TPS720xx BIAS pin provides sufficient load current to maintain a regulated voltage to the microcontroller. 10mH 2.5V to 5.5V VIN IN SW TPS62xxx EN FB Control to turn on/off the dc/dc OUT TPS720xx 10mF EN GND BIAS 2.2mF GND Microcontroller Output of dc/dc is floating when the TPS62xxx EN pin is low Figure 27. Example of Floating IN Pin Regulation 12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated TPS720xx www.ti.com........................................................................................................................................................ SBVS100D – JUNE 2008 – REVISED AUGUST 2009 THERMAL INFORMATION POWER DISSIPATION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC lowand high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2: PD = (VIN – VOUT) × IOUT (2) PACKAGE MOUNTING Solder pad footprint recommendations for the TPS720xx are available from the Texas Instruments web site at www.ti.com. The internal protection circuitry of the TPS720xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS720xx into thermal shutdown degrades device reliability. 0,994 0,934 1,362 1,302 NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. Figure 28. YZU Wafer Chip-Scale Package Dimensions (in mm) Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS720xx SBVS100D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September, 2008) to Revision D ......................................................................................... Page • • 14 Added electrical specifications for DRV package .................................................................................................................. 3 Noted electrical specifications for YZU package ................................................................................................................... 3 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS72009YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 G3 TPS72009YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 G3 TPS720105DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODC TPS720105DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODC TPS720105YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 NM TPS720105YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 NM TPS72010DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAA TPS72010DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAA TPS720115DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SHP TPS720115DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SHP TPS72011DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PAR TPS72011DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 PAR TPS72011YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BQ TPS72011YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 BQ TPS72012DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAB TPS72012DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAB TPS72012YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 NN Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS72012YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 NN TPS72013YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FS TPS72013YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FS TPS72015DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAC TPS72015DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAC TPS72015YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FT TPS72015YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 FT TPS72017YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 GC TPS72017YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 GC TPS72018DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAD TPS72018DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 DAD TPS72018YZUR ACTIVE DSBGA YZU 5 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 GD TPS72018YZUT ACTIVE DSBGA YZU 5 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 GD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 7-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ TPS72009YZUR DSBGA 3000 180.0 8.4 YZU 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.07 1.42 0.74 4.0 8.0 Q1 TPS72009YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS720105DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS720105DRVR SON DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS720105DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS720105DRVT SON DRV 6 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS720105YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS720105YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS72010DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS72010DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS720115DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS720115DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS72011DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS72011DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS72011YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS72011YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS72012DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS72012DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Sep-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS72012YZUR DSBGA YZU 5 3000 180.0 8.4 TPS72012YZUT DSBGA YZU 5 250 180.0 8.4 TPS72013YZUR DSBGA YZU 5 3000 180.0 TPS72013YZUT DSBGA YZU 5 250 180.0 TPS72015DRVR SON DRV 6 3000 TPS72015DRVR SON DRV 6 TPS72015DRVT SON DRV 6 TPS72015DRVT SON DRV TPS72015YZUR DSBGA TPS72015YZUT DSBGA TPS72017YZUR DSBGA W Pin1 (mm) Quadrant 1.07 1.42 0.74 4.0 8.0 Q1 1.07 1.42 0.74 4.0 8.0 Q1 8.4 1.07 1.42 0.74 4.0 8.0 Q1 8.4 1.07 1.42 0.74 4.0 8.0 Q1 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS72017YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS72018DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS72018DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS72018YZUR DSBGA YZU 5 3000 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 TPS72018YZUT DSBGA YZU 5 250 180.0 8.4 1.07 1.42 0.74 4.0 8.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS72009YZUR DSBGA YZU 5 3000 182.0 182.0 17.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 7-Sep-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS72009YZUT DSBGA YZU 5 250 182.0 182.0 17.0 TPS720105DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS720105DRVR SON DRV 6 3000 210.0 185.0 35.0 TPS720105DRVT SON DRV 6 250 203.0 203.0 35.0 TPS720105DRVT SON DRV 6 250 210.0 185.0 35.0 TPS720105YZUR DSBGA YZU 5 3000 210.0 185.0 35.0 TPS720105YZUT DSBGA YZU 5 250 210.0 185.0 35.0 TPS72010DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS72010DRVT SON DRV 6 250 203.0 203.0 35.0 TPS720115DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS720115DRVT SON DRV 6 250 203.0 203.0 35.0 TPS72011DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS72011DRVT SON DRV 6 250 203.0 203.0 35.0 TPS72011YZUR DSBGA YZU 5 3000 182.0 182.0 17.0 TPS72011YZUT DSBGA YZU 5 250 182.0 182.0 17.0 TPS72012DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS72012DRVT SON DRV 6 250 203.0 203.0 35.0 TPS72012YZUR DSBGA YZU 5 3000 210.0 185.0 35.0 TPS72012YZUT DSBGA YZU 5 250 210.0 185.0 35.0 TPS72013YZUR DSBGA YZU 5 3000 210.0 185.0 35.0 TPS72013YZUT DSBGA YZU 5 250 210.0 185.0 35.0 TPS72015DRVR SON DRV 6 3000 210.0 185.0 35.0 TPS72015DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS72015DRVT SON DRV 6 250 210.0 185.0 35.0 TPS72015DRVT SON DRV 6 250 203.0 203.0 35.0 TPS72015YZUR DSBGA YZU 5 3000 210.0 185.0 35.0 TPS72015YZUT DSBGA YZU 5 250 210.0 185.0 35.0 TPS72017YZUR DSBGA YZU 5 3000 210.0 185.0 35.0 TPS72017YZUT DSBGA YZU 5 250 210.0 185.0 35.0 TPS72018DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS72018DRVT SON DRV 6 250 203.0 203.0 35.0 TPS72018YZUR DSBGA YZU 5 3000 210.0 185.0 35.0 TPS72018YZUT DSBGA YZU 5 250 210.0 185.0 35.0 Pack Materials-Page 3 D: Max = 1.362 mm, Min =1.302 mm E: Max = 0.994 mm, Min =0.934 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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