LTC1090 Single Chip 10-Bit Data Acquisition System U FEATURES ■ ■ ■ ■ ■ DESCRIPTIO Software Programmable Features: Unipolar/Bipolar Conversions 4 Differential/8 Single Ended Inputs MSB or LSB First Data Sequence Variable Data Word Length Built-In Sample and Hold Single Supply 5V, 10V or ±5V Operation Direct 4 Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports 30kHz Maximum Throughput Rate U KEY SPECIFICATIO S ■ ■ ■ ■ Resolution: 10 Bits Total Unadjusted Error (LTC1090A): ±1/2LSB Max Conversion Time: 22µs Supply Current: 2.5mA Max, 1.0mA Typ , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS is a trademark of Linear Technology Corp. The LTC®1090 is a data acquisition component which contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology to perform either 10-bit unipolar, or 9-bit plus sign bipolar A/D conversions. The 8-channel input multiplexer can be configured for either single ended or differential inputs (or combinations thereof). An on-chip sample and hold is included for all single ended input channels. The serial I/O is designed to be compatible with industry standard full duplex serial interfaces. It allows either MSB or LSB first data and automatically provides 2’s complement output coding in the bipolar mode. The output data word can be programmed for a length of 8, 10, 12 or 16 bits. This allows easy interface to shift registers and a variety of processors. The LTC1090A is specified with total unadjusted error (including the effects of offset, linearity and gain errors) less than ±0.5LSB. The LTC1090 is specified with offset and linearity less than ±0.5LSB but with a gain error limit of ±2LSB for applications where gain is adjustable or less critical. U TYPICAL APPLICATIO FOR 8051 CODE SEE APPLICATIONS INFORMATION SECTION LTC1090 MPU (e.g., 8051) Linearity Plot DIFFERENTIAL INPUT 1.0 5V BIPOLAR INPUT 0.5 ERROR (LSBs) 5V –5V T UNIPOLAR INPUTS DOUT P1.1 DIN P1.2 SCLK P1.3 CS P1.4 0.0 – 0.5 SERIAL DATA LINK –1.0 0 512 1024 OUTPUT CODE LTC1090 • TA02 (+) (–) – UNIPOLAR INPUT LTC1090 • TA01 –5V 1090fc 1 LTC1090 W W W AXI U U U W PACKAGE/ORDER I FOR ATIO U ABSOLUTE RATI GS (Notes 1 and 2) Supply Voltage (VCC) to GND or V – ................................ 12V Negative Supply Voltage (V –) ..................... – 6V to GND Voltage: Analog and Reference Inputs .................................... (V –) –0.3V to VCC 0.3V Digital Inputs ......................................... –0.3V to 12V Digital Outputs .............................. – 0.3V to VCC 0.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1090AC/LTC1090C ........................–40°C to 85°C LTC1090AM/LTC1090M (OBSOLETE) ...... –55°C to 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C TOP VIEW CH0 1 20 VCC CH1 2 19 ACLK CH2 3 18 SCLK CH3 4 17 DIN CH4 5 16 DOUT CH5 6 15 CS CH6 7 14 REF + CH7 8 13 REF – COM 9 12 V – DGND 10 ORDER PART NUMBER LTC1090ACN LTC1090CN LTC1090CSW 11 AGND SW PACKAGE 20-LEAD PLASTIC SO WIDE N PACKAGE 20-LEAD PDIP TJMAX = 150°C, θJA = 70°C/W TJMAX = 110°C, θJA = 90°C/W J PACKAGE 20-LEAD CERDIP TJMAX = 150°C θJA = 70° C/W LTC1090AMJ LTC1090MJ LTC1090ACJ LTC1090CJ OBSOLETE PACKAGE Consider the SW or N Package for Alternate Source LTC1090 • POI01 Consult LTC Marketing for parts specified with wider operating temperature ranges. U U U U WW RECO E DED OPERATI G CO DITIO S LTC1090/LTC1090A MIN MAX SYMBOL PARAMETER CONDITIONS VCC Positive Supply Voltage V – = 0V 4.5 10 V V– Negative Supply Voltage VCC = 5V – 5.5 0 V fSCLK Shift Clock Frequency VCC = 5V fACLK A/D Clock Frequency VCC = 5V tCYC Total Cycle Time See Operating Sequence thCS Hold Time, CS Low After Last SCLK↓ VCC = 5V thDI Hold Time, DIN After SCLK↑ tsuCS Setup Time CS↓ Before Clocking in First Address Bit (Note 9) tsuDI tWHACLK 25°C 85°C 125°C UNITS 0 1.0 MHz 0.01 0.05 0.25 2.0 2.0 2.0 MHz 10 SCLK + 48 ACLK Cycles 0 ns VCC = 5V 150 ns VCC = 5V 2 ACLK Cycles 1µs Setup Time, DIN Stable Before SCLK↑ VCC = 5V 400 ns ACLK High Time VCC = 5V 127 ns tWLACLK ACLK Low Time VCC = 5V 200 ns tWHCS CS High Time During Conversion VCC = 5V 44 ACLK Cycles 1090fc 2 LTC1090 W U U CO VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. (Note 3) MIN LTC1090A TYP CONDITIONS MAX UNITS Offset Error (Note 4) ● ±0.5 ±0.5 LSB Linearity Error (Notes 4 and 5) ● ±0.5 ±0.5 LSB Gain Error (Note 4) ● ±1.0 ±2.0 LSB Total Unadjusted Error VREF = 5.000V (Notes 4 and 6) ● ±1.0 Reference Input Resistance MAX LTC1090 TYP PARAMETER MIN LSB 10 10 kΩ (V –) – 0.05V to VCC 0.05V Analog and REF Input Range (Note 7) On Channel Leakage Current (Note 8) On Channel = 5V Off Channel = 0V ● 1 1 µA On Channel = 0V Off Channel = 5V ● –1 –1 µA On Channel = 5V Off Channel = 0V ● –1 –1 µA On Channel = 0V Off Channel = 5V ● 1 1 µA Off Channel Leakage Current (Note 8) V AC ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specification are TA = 25°C. (Note 3) MIN LTC1090/LTC1090A TYP MAX SYMBOL PARAMETER CONDITIONS tACC Delay Time From CS↓ to DOUT Data Valid (Note 9) 2 ACLK Cycles tSMPL Analog Input Sample Time See Operating Sequence 5 SCLK Cycles tCONV Conversion Time See Operating Sequence tdDO See Test Circuits ● tdis Delay Time, SCLK↓ to DOUT Data Valid Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● ten Delay Time, 2nd CLK↓ to DOUT Enabled See Test Circuits ● thDO Time Output Data Remains Valid After SCLK↓ tf DOUT Fall Time See Test Circuits ● 90 300 ns ns tr DOUT Rise Time See Test Circuits ● 60 300 ns ns CIN Input Capacitance Analog Inputs 44 ACLK Cycles 250 450 ns 140 300 ns ns 150 400 ns ns 50 Digital Inputs On Channel Off Channel UNITS 65 5 5 ns pF pF pF 1090fc 3 LTC1090 U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specification are TA = 25°C. (Note 3) MIN LTC1090/LTC1090A TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level lnput Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● IIH High Level lnput Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● –2.5 µA VOH High Level Output Voltage VCC = 4.75V, lO = 10µA VCC = 4.75V, lO = 360µA ● 2.0 V 0.8 2.4 UNITS 4.7 4.0 V V V VOL Low Level Output Voltage VCC = 4.75V, lO = 1.6mA ● 0.4 V IOZ Hi-Z Output Leakage VOUT = VCC, CS High VOUT = 0V, CS High ● ● 3 –3 µA µA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VCC 10 mA ICC Positive Supply Current CS High, REF + Open ● 1.0 2.5 mA IREF Reference Current VREF = 5V ● 0.5 1.0 mA I– Negative Supply Current CS High, V – = – 5V ● 1 50 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND and REF – wired together (unless otherwise noted). Note 3: VCC = 5V, VREF + = 5V, VREF – = 0V, V – = 0V for unipolar mode and –5V for bipolar mode, ACLK = 2.0MHz, SCLK = 0.5MHz unless otherwise specified. Note 4: These specs apply for both unipolar and bipolar modes. In bipolar mode, one LSB is equal to the bipolar input span (2VREF) divided by 1024. For example, when VREF = 5V, 1LSB (bipolar) = 2(5V)/1024 = 9.77mV. Note 5: Linearity error is specified between the actual end points of the A/D transfer curve. Note 6: Total unadjusted error includes offset, gain, linearity, multiplexer and hold step errors. Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below V – or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level reference or analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for inputs near full-scale. This spec allows 50mV forward bias of either diode. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading. Note 8: Channel leakage current is measured after the channel selection. Note 9: To minimize errors caused by noise at the chip select input, the internal circuitry waits for two ACLK falling edges after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock an address in or data out until the minimum chip select setup time has elapsed. 1090fc 4 LTC1090 TEST CIRCUITS On and Off Channel Leakage Current Voltage Waveforms for DOUT Delay Time, tdDO SCLK 5V 0.8V ION tdDO A ON CHANNELS 2.4V 0.4V DOUT IOFF A Voltage Waveforms for DOUT Rise and Fall Times, tr, tf OFF CHANNELS POLARITY 2.4V 0.4V DOUT LTC1090 • TC01 tf tr LTC1090 • TC02 Voltage Waveforms for ten and tdis 1 2 ACLK 2.0V CS DOUT WAVEFORM 1 (SEE NOTE 1) 90% 2.4V ten DOUT WAVEFORM 2 (SEE NOTE 2) tdis 0.4V 10% NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL LTC1090 • TC03 Load Circuit for tdis and ten 1.4V TEST POINT DOUT Load Circuit for tdDO, tr, and tf 3k 100pF 5V WAVEFORM 2 WAVEFORM 1 3k DOUT TEST POINT 100pF LTC1090 • TC04 LTC1090 • TC05 1090fc 5 LTC1090 U U U PI FU CTIO S # PIN FUNCTION DESCRIPTION 1-8 9 CH0 to CH7 COM Analog Inputs Common 10 11 12 13,14 15 16 17 18 19 20 DGND AGND V– REF –, REF+ CS DOUT DIN SCLK ACLK VCC Digital Ground Analog Ground Negative Supply Reference Inputs Chip Select Input Digital Data Output Data Input Shift Clock A/D Conversion Clock Positive Supply The analog inputs must be free of noise with respect to AGND. The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is usually tied to the analog ground plane. This is the ground for the internal logic. Tie to the ground plane. AGND should be tied directly to the analog ground plane. Tie V – to most negative potential in the circuit. (Ground in single supply applications.) The reference inputs must be kept free of noise with respect to AGND. A logic low on this input enables data transfer. The A/D conversion result is shifted out of this output. The A/D configuration word is shifted into this input. This clock synchronizes the serial data transfer. This clock controls the A/D conversion process. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. W BLOCK DIAGRA VCC DIN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 18 20 17 OUTPUT SHIFT REGISTER INPUT SHIFT REGISTER 1 2 3 4 5 6 7 8 9 SAMPLE AND HOLD 16 SCLK DOUT COMP 10-BIT SAR ANALOG INPUT MUX 10-BIT CAPACITIVE DAC 19 10 11 DGND AGND 12 V– 13 REF – 14 REF+ CONTROL AND TIMING 15 ACLK CS LTC1090 • BD01 1090fc 6 LTC1090 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage Supply Current vs Temperature 4 3 2 1.2 1.0 0.8 0.6 1 0 0.6 REF +OPEN ACLK = 2MHz CS = 5V VCC = 5V 0.4 4 5 9 6 7 8 SUPPLY VOLTAGE, VCC (V) 0.2 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) 10 LTC1090 • TPC01 OFFSET ERROR (LSBs = 6 8 7 VOS = 1mV 4 3 VOS = 0.5mV 0 0.5 LTC1090 • TPC03 1 3 4 2 REFERENCE VOLTAGE, VREF (V) 0 5 0.5 0 0 0.5 0.25 VREF = 4V ACLK = 2MHz CHANGE IN GAIN ERROR (LSBs) LINEARITY ERROR (LSBs) 0.5 1.0 0.75 0.5 0.25 9 6 7 8 SUPPLY VOLTAGE, VCC (V) 10 LTC1090 • TPC07 0 5 Change in Gain Error vs Supply Voltage VREF = 4V ACLK = 2MHz 0.75 1 3 4 2 REFERENCE VOLTAGE, VREF (V) LTC1090 • TPC06 1.25 5 1.0 Linearity Error vs Supply Voltage VREF = 4V ACLK = 2MHz VOS = 1.25mV AT VCC = 5V 4 VCC = 5V LTC1090 • TPC05 1.25 125 0.25 Offset Error vs Supply Voltage OFFSET ERROR (LSBs) 0 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) 0.75 LTC1090 • TPC04 0 0.1 1.25 VCC = 5V 1.0 0 0.2 1.0 5.0 REFERENCE VOLTAGE, VREF (V) 1.0 0.2 Change in Gain Error vs Reference Voltage 0.25 2 1 0.3 125 0.75 5 0.4 CHANGE IN GAIN ERROR (LSBs = 1 • VREF) 1024 1.25 LINEARITY ERROR (LSBs = 1 • VREF) 1024 1 •V ) 1024 REF 9 0.5 Linearity Error vs Reference Voltage VCC = 5V VREF = 5V LTC1090 • TPC02 Unadjusted Offset Error vs Reference Voltage 10 REFERENCE CURRENT, IREF (mA) REF +OPEN ACLK = 2MHz CS = VCC TA = 25°C 5 Reference Current vs Temperature 1.4 SUPPLY CURRENT, ICC (mA) SUPPLY CURRENT, ICC (mA) 6 4 5 9 6 7 8 SUPPLY VOLTAGE, VCC (V) 10 LTC1090 • TPC08 0.25 0 – 0.25 – 0.5 4 5 9 6 7 8 SUPPLY VOLTAGE, VCC (V) 10 LTC1090 • TPC09 1090fc 7 LTC1090 U W 0.6 VCC = 5V VREF = 5V ACLK = 2MHz 0.5 0.4 0.3 0.2 0.1 0 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) 125 0.6 VCC = 5V VREF = 5V ACLK = 2MHz 0.5 0.4 0.3 0.2 0.1 0 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) Maximum Conversion Clock Rate vs Temperature 3 2 1 VCC = 5V VREF = 5V 0 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) 4 3 2 1 0 125 –INPUT RFILTER + CFILTER ≥ 1µF 10k _ 1k 100 RSOURCE– 10 0 100 1k 5 4 3 2 1 4 5 10k RSOURCE – (Ω) 5 8 7 9 6 SUPPLY VOLTAGE, VCC (V) 10 LTC1090 • TPC15 Sample-and-Hold Acquisition Time vs Source Resistance S & H ACQUISITION TIME TO 0.1% (µs) +INPUT 2 VREF = 4V TA = 25°C 6 10 VIN MAXIMUM RFILTER** (Ω) 3 125 0 1 3 4 2 REFERENCE VOLTAGE, VREF (V) 0 100k VCC = 5V VREF = 5V TA = 25°C 10 0 50 100 –50 –25 25 75 0 AMBIENT TEMPERATURE, TA (°C) Maximum Filter Resistor vs Cycle Time 5 1 0.1 LTC1090 • TPC14 Maximum Conversion Clock Rate vs Source Resistance VIN 0.2 7 VCC = 5V TA = 25°C LTC1090 • TPC13 4 0.3 Maximum Conversion Clock Rate vs Supply Voltage MAXIMUM ACLK FREQUENCY* (MHz) MAXIMUM ACLK FREQUENCY* (MHz) MAXIMUM ACLK FREQUENCY* (MHz) 4 0.4 LTC1090 • TPC12 5 5 VCC = 5V VREF = 5V ACLK = 2MHz 0.5 Maximum Conversion Clock Rate vs Reference Voltage 6 MAXIMUM ACLK FREQUENCY* (MHz) 125 0.6 LTC1090 • TPC11 LTC1090 • TPC10 10 100 1000 CYCLE TIME, tCYC (µs) LTC1090 • TPC16 *MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 2MHz VALVE IS FIRST DETECTED. 8 Change in Gain Error vs Temperature Change in Linearity Error vs Temperature MAGNITUDE OF GAIN CHANGE, ∆GAIN (LSBs) Change in Offset Error vs Temperature MAGNITUDE OF LINEARITY CHANGE, ∆LINEARITY (LSBs) MAGNITUDE OF OFFSET CHANGE, ∆OFFSET (LSBs) TYPICAL PERFOR A CE CHARACTERISTICS 10k LTC1090 • TPC17 VREF = 5V VCC = 5V TA = 25°C 0 TO 5V INPUT STEP 1 RSOURCE+ VIN + _ 0.1 100 1k RSOURCE+ (Ω) 10k LTC1090 • TPC18 **MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALVE AT WHICH A 0.1LSB SHIFT CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0 IS FIRST DETECTED. 1090fc LTC1090 U W TYPICAL PERFOR A CE CHARACTERISTICS Digital Input Logic Threshold vs Supply Voltage Input Channel Leakage Current vs Temperature 1000 INPUT CHANNEL LEAKAGE CURRENT (nA) TA = 25°C 3 2 1 5 6 7 8 9 SUPPLY VOLTAGE, VCC (V) GUARANTEED 800 700 600 500 400 ON CHANNEL 300 200 OFF CHANNELS 100 0 4 LTC1090 NOISE = 200µV PEAK-TO-PEAK 900 PEAK-TO-PEAK NOISE ERROR (LSBs) 4 LOGIC THRESHOLD (V) Noise Error vs Reference Voltage 2.0 50 25 –50 –25 0 75 100 AMBIENT TEMPERATURE, TA (°C) 10 1.75 1.5 1.25 1.0 0.75 0.5 0.25 1 5 0.2 REFERENCE VOLTAGE, VREF (V) 125 LTC1090 • TPC21 LTC1090 • TPC20 LTC1090 • TPC19 U W U U APPLICATIO S I FOR ATIO The LTC1090 is a data acquisition component which contains the following functional blocks: 1. 10-bit successive approximation capacitive A/D converter DIGITAL CONSIDERATIONS 1. Serial Interface The LTC1090 communicates with microprocessors and other external circuitry via a synchronous, full duplex, four wire serial interface (see Operating Sequence). The shift clock (SCLK) synchronizes the data transfer with each bit being transmitted on the falling SCLK edge and captured on the rising SCLK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). 2. Analog multiplexer (MUX) 3. Sample and hold (S/H) 4. Synchronous, full duplex serial interface 5. Control and timing logic Operating Sequence (Example: Differential Inputs (CH3 to CH2), Bipolar, MSB First and 10-Bit Word Length) tCYC 1 5 8 SCLK 10 DON’T CARE tSMPL tCONV CS DIN SGL/ DIFF ODD/ SEL1 SEL0 UNI MSBF WL1 WL0 SIGN DOUT DON’T CARE B9 (SB) SHIFT CONFIGURATION WORD IN B8 B7 B6 B5 B4 B3 B2 SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B1 B0 LTC1090 • AI01 1090fc 9 LTC1090 U W U U APPLICATIO S I FOR ATIO Data transfer is initiated by a falling chip select (CS) signal. After the falling CS is recognized, an 8-bit input word is shifted into the DIN input which configures the LTC1090 for the next conversion. Simultaneously, the result of the previous conversion is output on the DOUT line. At the end of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is complete and the results will be available on the next data transfer cycle. As shown below, the result of a conversion is delayed by one CS cycle from the input word requesting it. DIN DIN Word 1 DIN Word 2 DIN Word 3 DOUT DOUT Word 0 DOUT Word 1 DOUT Word 2 Data Transfer tCONV A/D Conversion tCONV A/D Conversion Data Transfer LTC1090 • AI02 2. Input Data Word The LTC1090 8-bit input data word is clocked into the DIN input on the first eight rising SCLK edges after chip select is recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The eight bits of the input word are defined as follows: Unipolar/ Bipolar Data Input (DIN) Word: SGL/ DIFF ODD/ SIGN SELECT 1 MUX Address SELECT 0 UNI Multiplexer (MLIX) Address The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and – signs in the selected row of Table 1. Note that in differential mode (SGL/DIFF = O) measurements are limited to four adjacent input pairs with either polarity. In single ended mode, all input channels are measured with respect to COM. Figure 1 shows some examples of multiplexer assignments. Table 1. Multiplexer Channel Selection MUX ADDRESS SGL/ DIFF ODD SIGN 0 0 1 0 0 0 + – 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 Word Length MSBF MSB First/ LSB First WL1 WL0 LTC1090• AI03 DIFFERENTIAL CHANNEL SELECTION SELECT 1 0 – 3 + – 4 5 + – 6 7 + – – + + – + – MUX ADDRESS SGL/ ODD/ DIFF SIGN 2 + SINGLE ENDED CHANNEL SELECTION SELECT 1 0 0 + 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 2 3 4 5 6 7 COM – + – + – + – + – + – + – + – 1090fc 10 LTC1090 U W U U APPLICATIO S I FOR ATIO 4 Differential 8 Single Ended CHANNEL 0 1 2 3 4 5 6 7 CHANNEL 0,1 +( – ) –( + ) 2,3 +( – ) –( + ) 4,5 +( – ) –( + ) 6,7 +( – ) –( + ) Combinations of Differential and Single Ended CHANNEL + + + + + + + + 0,1 + – 2,3 – + 4 5 6 7 COM ( – ) + + + + COM ( – ) LTC1090 • AI04B LTC1090 • AI04A LTC1090 • AI04C Changing the MUX Assignment “On the Fly” 4,5 + – 6,7 + – – + 5,4 6 7 + + COM ( – ) COM (UNUSED) 2ND CONVERSION 1ST CONVERSION LTC1090 • AI04E LTC1090 • AI04D Figure 1. Examples of Multiplexer Options on the LTC1090 Unipolar/Bipolar (UNI) The fifth input bit (UNI) determines whether the conversion will be unipolar or bipolar. When UNI is a logical one, a unipolar conversion will be performed on the selected input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for each conversion type are shown in the figures below. Unipolar Transfer Curve (UNI = 1) 1111111111 1111111110 0000000001 0000000000 OV VREF – 2LSB 1LSB VREF VREF – 1LSB VIN LTC1090 • AI05 Bipolar Transfer Curve (UNI = 0) 0111111111 0111111110 –VREF +1LSB –VREF 0000000001 0000000000 1LSB VIN –1LSB 1111111111 1111111110 VREF – 2LSB VREF VREF – 1LSB –2LSB 1000000001 1000000000 LTC1090 • AI06 1090fc 11 LTC1090 U W U U APPLICATIO S I FOR ATIO Unipolar Output Code (UNI = 1) OUTPUT CODE INPUT VOLTAGE INPUT VOLTAGE (VREF = 5V) 1111111111 1111111110 • • • 0000000001 0000000000 VREF – 1LSB VREF – 2LSB • • • 1LSB 0V 4.9951V 4.9902V • • • 0.0049V 0V control the length of the present, not the next, DOUT word. WL1 and WL0 are never “don’t cares” and must be set for the correct DOUT word length even when a “dummy” DIN word is sent. On any transfer cycle, the word length should be made equal to the number of SCLK cycles sent by the MPU. Bipolar Output Code (UNI = 0) OUTPUT CODE INPUT VOLTAGE INPUT VOLTAGE (VREF = 5V) 0111111111 0111111110 • • • 0000000001 0000000000 1111111111 1111111110 • • • 1000000001 1000000000 VREF – 1LSB VREF – 2LSB • • • 1LSB 0V –1LSB –2LSB • • • – (VREF) + 1LSB – (VREF) 4.9902V 4.9805V • • • 0.0098V 0V –0.0098V –0.0195V • • • –4.9902V –5.000V MSB First/LSB First Format (MSBF) The output data of the LTC1090 is programmed for MSB first or LSB first sequence using the MSBF bit. For MSB first output data the input word clocked to the LTC1090 should always contain a logical one in the sixth bit location (MSBF bit). Likewise for LSB first output data, the input word clocked to the LTC1090 should always contain a zero in the MSBF bit location. The MSBF bit in a given DIN word will control the order of the next DOUT word. The MSBF bit affects only the order of the output data word. The order of the input word is unaffected by this bit. MSBF OUTPUT FORMAT 0 1 LSB First MSB First Word Length (WL1, WL0) The last two bits of the input word (WL1 and WL0) program the output data word length of the LTC1090. Word lengths of 8, 10, 12 or 16 bits can be selected according to the following table. The WL1 and WL0 bits in a given DIN word WL1 WL0 OUTPUT WORD LENGTH 0 0 1 1 0 1 0 1 8 Bits 10 Bits 12 Bits 16 Bits Figure 2 shows how the data output (DOUT) timing can be controlled with word length selection and MSB/LSB first format selection. 3. Deglitcher A deglitching circuit has been added to the Chip Select input of the LTC1090 to minimize the effects of errors caused by noise on that input. This circuit ignores changes in state on the CS input that are shorter in duration than 1 ACLK cycle. After a change of state on the CS input, the LTC1090 waits for two falling edges of the ACLK before recognizing a valid chip select. One indication of CS low recognition is the DOUT line becoming active (leaving the Hi-Z state). Note that the deglitching applies to both the rising and falling CS edges. ACLK CS DOUT HIGH Z VALID OUTPUT LOW CS RECOGNIZED INTERNALLY ACLK CS DOUT HIGH Z HIGH CS RECOGNIZED INTERNALLY LTC1090 • AI07 1090fc 12 LTC1090 U W U U APPLICATIO S I FOR ATIO 8-Bit Word Length t SMPL t CONV CS SCLK 1 8 (SB) DOUT MSB FIRST B9 B8 B7 B6 B5 B4 B3 B2 DOUT LSB FIRST B0 B1 B2 B3 B4 B5 B6 B7 THE LAST TWO BITS ARE TRUNCATED LTC1090 • AI08A 10-Bit Word Length t SMPL t CONV CS SCLK 10 1 (SB) DOUT MSB FIRST B9 B8 B7 B6 B5 B4 B3 B2 B1 DOUT LSB FIRST B0 B1 B2 B3 B4 B5 B6 B7 B8 B0 (SB) B9 LTC1090 • AI08B 12-Bit Word Length t CONV t SMPL CS SCLK 10 1 12 (SB) DOUT MSB FIRST B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 FILL ZEROES (SB) DOUT LSB FIRST B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 * * LTC1090 • AI08C 16-Bit Word Length t SMPL t CONV CS SCLK 1 16 10 (SB) DOUT MSB FIRST B9 B8 B7 B6 B5 B4 B3 B2 B1 DOUT LSB FIRST B0 B1 B2 B3 B4 B5 B6 B7 B8 FILL ZEROES B0 (SB) B9 * * * * * *IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROES. IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS * LTC1090 • AI08D Figure 2. Data Output (DOUT) Timing with Different Word Lengths 1090fc 13 LTC1090 U W U U APPLICATIO S I FOR ATIO 4. CS Low During Conversion In the normal mode of operation, CS is brought high during the conversion time (see Figure 3). The serial port ignores any SCLK activity while CS is high. The LTC1090 will also operate with CS low during the conversion. In this mode, SCLK must remain low during the conversion as shown in Figure 4. After the conversion is complete, the tSMPL SAMPLE ANALOG INPUT SHIFT MUX ADDRESS IN DOUT line will become active with the first output bit. Then the data transfer can begin as normal. 5. Microprocessor Interfaces The LTC1090 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous SHIFT RESULT OUT AND NEW ADDRESS IN 40 TO 44 ACLK CYCLES CS SCLK DIN DOUT SEL SEL SGL/ ODD/ 0 UNI MSBF WL1 WL0 1 DIFF SIGN B9 B8 B7 B6 B5 B4 B3 B2 SEL SGL/ ODD/ 1 SEL DIFF SIGN 0 DON’T CARE B1 B0 B9 B8 B7 B6 UNI MSBF WL1 WL0 B5 B4 B3 B2 B1 B0 LTC1090 • AI09 Figure 3. CS High During Conversion tSMPL SAMPLE ANALOG INPUT SHIFT MUX ADDRESS IN SHIFT RESULT OUT AND NEW ADDRESS IN 40 TO 44 ACLK CYCLES CS SCLK DIN SCLK MUST REMAIN LOW SEL SEL SGL/ ODD/ 0 UNI MSBF WL1 WL0 1 DIFF SIGN DOUT B9 B8 B7 B6 B5 B4 B3 B2 SEL SGL/ ODD/ 1 SEL DIFF SIGN 0 DON’T CARE B1 B0 B9 B8 B7 B6 UNI MSBF WL1 WL0 B5 B4 B3 B2 B1 B0 LTC1090 • AI10 Figure 4. CS Low During Conversion 1090fc 14 LTC1090 U W U U APPLICATIO S I FOR ATIO serial formats (see Table 2). If an MPU without a serial interface is used, then 4 of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1090. Included here are three serial interface examples and one example showing a parallel port programmed to form the serial interface. Table 2. Microprocessors with Hardware Serial Interfaces Compatible with the LTC1090** PART NUMBER Motorola MC6805S2, S3 MC68HC11 MC68HC05 RCA CDP68HC05 Hitachi HD6305 HD63705 HD6301 HD63701 HD6303 National Semiconductor COP400 Family COP800 Family NS8050U HPC16000 Family Texas Instruments TMS7002 TMS7042 TMS70C02 TMS70C42 TMS32011* TMS32020* TYPE OF INTERFACE National MICROWIRE (COP420) The COP420 transfers data MSB first and in 4-bit increments (nibbles). This is easily accommodated by setting the LTC1090 to MSB first format and 12-bit word length. The data output word is then received by the COP420 in three 4-bit blocks with the final two unused bits filled with zeroes by the LTC1090. Hardware and Software Interface to National Semiconductor COP420 Processor SPI SPI SPI ANALOG INPUTS SPI SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous MICROWIRE† MICROWIRE/PLUS† MICROWIRE/PLUS MICROWIRE/PLUS Serial Port Serial Port Serial Port Serial Port Serial Port Serial Port *Requires external hardware **Contact LTC Marketing for interface information for processors not on this list †MICROWIRE and MlCROWIRE/PLUS are trademarks of National Semiconductor Corp. Serial Port Microprocessors Most synchronous serial formats contain a shift clock (SCLK) and two data lines, one for transmitting and one for receiving. In most cases data bits are transmitted on the falling edge of the clock (SCLK) and captured on the rising edge. However, serial port formats vary among MPU manufacturers as to the smallest number of bits that can be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers). They also vary as to the order in which the bits are transmitted (LSB or MSB first). The following examples show how the LTC1090 accommodates these differences. COP420 LTC1090 CS GO SCLK SK DIN SO DOUT SI DOUT from LTC1090 stored in COP420 RAM Location A MSB* B9 B8 B7 B6 first 4 bits Location A + 1 B5 B4 B3 B2 second 4 bits LSB Location A + 2 B1 B0 B0 B0 third 4 bits LTC1090 • AI11 *B9 is MSB in unipolar or sign bit in bipolar MNEMONIC LEI SC OGI LDD XAS LDD NOP XAS XIS NOP XAS XIS RC NOP XAS XIS OGI LEI DESCRIPTION Enable SlO Set Carry flag G0 is set to (CS goes low) Load first 4 bits of DIN to ACC Swap ACC with SIO reg. Starts SK Clk Load 2nd 4 bits of DIN to ACC Timing Swap first 4 bits from A/D with ACC. SK continues. Put first 4 bits in RAM (location A) Timing Swap 2nd 4 bits from A/D with ACC. SK continues. Put 2nd 4 bits in RAM (location A + 1) Clear Carry Timing Swap 3rd 4 bits from A/D with ACC. SK off Put 3rd 4 bits in RAM (location A + 2) G0 is set to 1 (CS goes high) Disable SlO 1090fc 15 LTC1090 U W U U APPLICATIO S I FOR ATIO Motorola SPI (MC68HC05C4) Hitachi Synchronous SCI (HD63705) The MC68HC05C4 transfers data MSB first and in 8-bit increments. Programming the LTC1090 for MSB first format and 16-bit word length allows the 10-bit data output to be received by the MPU as two 8-bit bytes with the final 6 unused bits filled with zeroes by the LTC1090. The HD63705 transfers serial data in 8-bit increments, LSB first. To accommodate this, the LTC1090 is programmed for 16-bit word length and LSB first format. The 10-bit output data is received by the processor as two 8-bit bytes, LSB first. The LTC1090 fills the final 6 unused bits (after the MSB) with zeroes in unipolar mode and with the sign bit in bipolar mode. Hardware and Software Interface to Motorola MC68HC05C4 Processor Hardware and Software Interface to Hitachi HD63705 Processor LTC1090 MC68HCO5C4 CO CS ANALOG INPUTS LTC1090 SCK SCLK DIN MOSI DOUT MISO ANALOG INPUTS DOUT from LTC1090 stored in MC68HCO5C4 RAM B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 C0 SCLK CK DIN TX DOUT RX LSB byte 1 B7 B6 B5 B4 B3 B2 B1 B0 Location A LSB Location A + 1 CS DOUT from LTC1090 stored in HD63705 RAM MSB* Location A HD63705 0 0 0 0 0 0 *B9 is MSB in unipolar or sign bit in bipolar byte 1 Sign byte 2 Location A + 1 B9 B9 B9 B9 B9 B9 B9 B8 byte 2 LTC1090 • AI12 Bipolar LSB MNEMONIC BCLR n LDA STA ↑ NOP ↓ LDA LDA STA STA ↑ NOP ↓ BSET n LDA LDA STA DESCRIPTION C0 is cleared (CS goes Low) Load DIN for LTC1090 into ACC Load DIN from ACC to SPI data reg. Start SCK B7 B6 B5 B4 B3 B2 B1 B0 Location A Location A + 1 0 0 0 Unipolar 8 NOPs for timing Load contents of SPI status reg. into ACC Load LTC1090 DOUT from SPI data reg. into ACC (byte 1) Load LTC1090 DOUT into RAM (location A) Start next SPl cycle MNEMONIC 6 NOPs for timing ↑ NOP ↓ LDA C0 is set (CS goes high) Load contents of SPI status reg. into ACC Load LTC1090 DOUT from SPI data reg. into ACC (byte 2) Load LTC1090 DOUT into RAM (location A + 1) MSB 0 0 0 B9 B8 LDA BCLR n STA STA NOP BSET n LDA STA byte 1 byte 2 LTC1090 • AI13 DESCRIPTION Load DIN word for LTC1090 into ACC from RAM C0 cleared (CS goes low) Load DIN word for LTC1090 into SCI data reg. from ACC and start clocking data (LSB first) 6 NOPs for timing Load contents of SCI data reg. into ACC (byte 1) Start next SCI cycle Load LTC1090 DOUT word into RAM (Location A) Timing C0 set (CS goes high) Load contents of SCI data reg. into ACC (byte 2) Load LTC1090 DOUT word into RAM (Location A + 1) 1090fc 16 LTC1090 U W U U APPLICATIO S I FOR ATIO 8051 Code Parallel Port Microprocessors When interfacing the LTC1090 to an MPU which has a parallel port, the serial signals are created on the port with software. Three MPU port lines are programmed to create the CS, SCLK and DIN signals for the LTC1090. A fourth port line reads the DOUT line. An example is made of the Intel 8051/8052/80C252 family. LOOP: Hardware and Software Interface to Intel 8051 Processor LTC1090 ANALOG INPUTS 8051 DOUT P1.1 DIN P1.2 SCLK P1.3 CS P1.4 ACLK ALE DOUT from LTC1090 stored in 8051 RAM DELAY: MSB* R2 DESCRIPTION MOV PI,#02H Initialize port 1 (bit 1 is made an input) SCLK goes low CS goes high DIN word for the LTC1090 is placed in ACC. CS goes low Load counter Delay for deglitcher Read data bit into carry Rotate data bit into ACC Output DIN bit to LTC1090 SCLK goes high SCLK goes low Next bit Store MSBs in R2 Read data bit into carry CIear ACC Rotate data bit into ACC SCLK goes high SCLK goes low Read data bit into carry Rotate right into ACC Rotate right into ACC Store LSBs in R3 SCLK goes high SCLK goes low CS goes high Load counter Delay for LTC1090 to perform conversion Repeat program CLR P1.3 SETB P1.4 CONTINUE: MOV A,#0DH Intel 8051 To interface to the 8051, the LTC1090 is programmed for MSB first format and 10-bit word length. The 8051 generates CS, SCLK and DIN on three port lines and reads DOUT on the fourth. MNEMONIC CLR P1.4 MOV R4,#08 NOP MOV C, P1.1 RLC A MOV P1.2, C SETB P1.3 CLR P1.3 DJNZ R4, LOOP MOV R2, A MOV C, P1.1 CLR A RLC A SETB P1.3 CLR P1.3 MOV C, P1.1 RRC A RRC A MOV R3, A SETB P1.3 CLR P1.3 SETB P1.4 MOV R5,#07H DJNZ R5, DELAY AJMP CONTINUE B9 B8 B7 B6 B5 B4 B3 B2 LSB R3 B1 B0 0 0 0 0 0 0 *B9 is MSB in unipolar or sign bit in bipolar 2 1 0 OUTPUT PORT SERIAL DATA MPU 3-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1090s 3 3 3 LTC1090 8 CHANNELS CS 3 LTC1090 8 CHANNELS CS CS LTC1090 8 CHANNELS LTC1090 • AI14 Figure 5. Several LTC1090’s Sharing One 3-Wire Serial Interface 1090fc 17 LTC1090 U W U U APPLICATIO S I FOR ATIO 6. Sharing the Serial Interface The LTC1090 can share the same 3-wire serial interface with other peripheral components or other LTC1090s (see Figure 5). In this case, the CS signals decide which LTC1090 is being addressed by the MPU. VCC 4.7µF TANTALUM 1 20 ANALOG CONSIDERATIONS 1. Grounding The LTC1090 should be used with an analog ground plane and single point grounding techniques. Pin 11 (AGND) should be tied directly to this ground plane. Pin 20 (VCC) should be bypassed to the ground plane with a 4.7µF tantalum with leads as short as possible. Pin 12 (V –) should be bypassed with a 0.1µF ceramic disk. For single supply applications, V – can be tied to the ground plane. It is also recommended that pin 13 (REF –) and pin 9 (COM) be tied directly to the ground plane. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. Figure 6 shows an example of an ideal ground plane design for a two sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. V– ANALOG GROUND PLANE 10 11 0.1µF CERAMIC DISK LTC1090 • AI15 Figure 6. Example Ground Plane for the LTC1090 VERTICAL: 0.5mV/DIV Pin 10 (DGND) can also be tied directly to this ground plane because minimal digital noise is generated within the chip itself. HORIZONTAL: 10µs/DIV Figure 7. Poor VCC Bypassing. Noise and Ripple can Cause A/D Errors For good performance, VCC must be free of noise and ripple. Any changes in the VCC voltage with respect to analog ground during a conversion cycle can induce errors or noise in the output code. VCC noise and ripple can be kept below 1mV by bypassing the VCC pin directly to the analog ground plane with a 4.7µF tantalum with leads as short as possible. Figures 7 and 8 show the effects of good and poor VCC bypassing. VERTICAL: 0.5mV/DIV 2. Bypassing HORIZONTAL: 10µs/DIV Figure 8. Good VCC Bypassing Keeps Noise and Ripple on VCC Below 1mV 1090fc 18 LTC1090 U W U U APPLICATIO S I FOR ATIO 3. Analog Inputs “+” Input Settling Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1090 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. This input capacitor is switched onto the “+” input during the sample phase (tSMPL, see Figure 10). The sample phase starts at the 4th SCLK cycle and lasts until the falling edge of the last SCLK (the 8th, 10th, 12th or 16th SCLK cycle depending on the selected word length). The voltage on the “+” input must settle completely within this sample time. Minimizing RSOURCE+ and C1 will improve the input settling time. If large “+” input source resistance must be used, the sample time can be increased by using a slower SCLK frequency or selecting a longer word length. With the minimum possible sample time of 4µs, RSOURCE+ < 2k and C1 < 20pF will provide adequate settling. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. Source Resistance The analog inputs of the LTC1090 look like a 60pF capacitor (CIN) in series with a 500Ω resistor (RON) as shown in Figure 9. CIN gets switched between the selected “+” and “–” inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time. VIN+ RSOURCE+ “+” INPUT 4TH SCLK RON = 500Ω C1 VIN– RSOURCE– “–” INPUT CIN = 60pF LAST SCLK LTC1090 C2 LTC1090 • AI16 “–” Input Settling At the end of the sample phase the input capacitor switches to the “–” input and the conversion starts (see Figure 10). During the conversion, the “+” input voltage is effectively “held” by the sample and hold and will not affect the conversion result. However, it is critical that the “–” input voltage be free of noise and settle completely during the first four ACLK cycles of the conversion time. Minimizing RSOURCE– and C2 will improve settling time. If large “–” input source resistance must be used, the time allowed for settling can be extended by using a slower ACLK frequency. At the maximum ACLK rate of 2MHz, RSOURCE– < 1kΩ and C2 < 20pF will provide adequate settling. Figure 9. Analog Input Equivalent Circuit SAMPLE MUX ADDRESS SHIFTED IN HOLD “ + ” INPUT MUST SETTLE DURING THIS TIME t SMPL CS SCLK ACLK 1 2 3 4 LAST SCLK (8TH, 10TH, 12TH OR 16TH DEPENDING ON WORK LENGTH) 1 2 3 4 1ST BIT TEST “ – ” INPUT MUST SETTLE DURING THIS TIME “ + ” INPUT “ – ” INPUT LTC1090 • AI17 Figure 10. “+” and “–” Input Settling Windows 1090fc 19 LTC1090 U W U U APPLICATIO S I FOR ATIO Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 10). Again, the “+” and “–” input sampling times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006 and LT1013 single supply op amps can be made to settle well even with the minimum settling windows of 4µs (“+” input) and 2µs (“–” input) which occur at the maximum clock rates (ACLK = 2MHz and SCLK = 1MHz). Figures 11 and 12 show examples of adequate and poor op amp settling. eliminated by increasing the cycle time as shown in the typical curve of Maximum Filter Resistor vs Cycle Time. VIN RFILTER IDC “+” CFILTER LTC1090 “–” LTC1090 • AI18 Figure 13. RC Input Filtering VERTICAL: 5mV/DIV Input Leakage Current HORIZONTAL: 1µs/DIV Figure 11. Adequate Settling of Op Amp Driving Analog Input Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 1µA (at 125°C) flowing through a source resistance of 1kΩ will cause a voltage drop of 1mV or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of Input Channel Leakage Current vs Temperature). VERTICAL: 5mV/DIV Noise Coupling into Inputs HORIZONTAL: 20µs/DIV Figure 12. Poor Op Amp Settling can Cause A/D Errors RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 13. For large values of CF (e.g., 1µF), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately lDC = 60pF x VIN/tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 33µs, the input current equals 9µA at VIN = 5V. In this case, a filter resistor of 50Ω will cause 0.1LSB of full-scale error. If a larger filter resistor must be used, errors can be High source resistance input signals (>500Ω) are more sensitive to coupling from external sources. It is preferable to use channels near the center of the package (i.e., CH2 to CH7) for signals which have the highest output resistance because they are essentially shielded by the pins on the package ends (DGND and CH0). Grounding any unused inputs (especially the end pin, CH0) will also reduce outside coupling into high source resistances. 4. Sample-and-Hold Single Ended Inputs The LTC1090 provides a built-in sample and hold (S&H) function for all signals acquired in the single ended mode (COM pin grounded). This sample and hold allows the LTC1090 to convert rapidly varying signals (see typical curve of S&H Acquisition Time vs Source Resistance). The input voltage is sampled during the tSMPL time as shown in Figure 10. The sampling interval begins after the fourth 1090fc 20 LTC1090 U W U U APPLICATIO S I FOR ATIO MUX address bit is shifted in and continues during the remainder of the data transfer. On the falling edge of the final SCLK, the S&H goes into hold mode and the conversion begins. The voltage will be held on either the 8th, 10th, 12th or 16th falling edge of the SCLK depending on the word length selected. When driving the reference inputs, three things should be kept in mind: Differential Inputs 2. Transients on the reference inputs caused by the capacitive switching currents must settle completely during each bit test (each 4 ACLK cycles). Figures 15 and 16 show examples of both adequate and poor settling. Using a slower ACLK will allow more time for the reference to settle. However, even at the maximum ACLK rate of 2MHz most references and op amps can be made to settle within the 2µs bit time. With differential inputs or when the COM pin is not tied to ground, the A/D no longer converts just a single voltage but rather the difference between two voltages. In these cases, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 44 ACLK cycles. Therefore, a change in the “–” input voltage during this interval can “–” input this error would be: 1. The source resistance (ROUT) driving the reference inputs should be low (less than 1Ω) to prevent DC drops caused by the 1mA maximum reference current (IREF). 3. It is recommended that the REF – input be tied directly to the analog ground plane. If REF – is biased at a voltage other than ground, the voltage must not change during a conversion cycle. This voltage must also be free of noise and ripple with respect to analog ground. VERROR (MAX) = VPEAK x 2 x π x f(“–”) x 44/fACLK 5. Reference Inputs The voltage between the reference inputs of the LTC1090 defines the voltage span of the A/D converter. The reference inputs look primarily like a 10kΩ resistor but will have transient capacitive switching currents due to the switched capacitor conversion technique (see Figure 14). During each bit test of the conversion (every 4 ACLK cycles), a capacitive current spike will be generated on the reference pins by the A/D. These current spikes settle quickly and do not cause a problem. However, if slow settling circuitry is used to drive the reference inputs, care must be taken to insure that transients caused by these current spikes settle completely during each bit test of the conversion. REF + 14 ROUT VREF 10k TYP EVERY 4 ACLK CYCLES RON REF – 5pF – 30pF 13 LTC1090 LTC1090 • AI19 Figure 14. Reference Input Equivalent Circuit VERTICAL: 0.5mV/DIV Where f(“–”) is the frequency of the “–” input voltage, VPEAK is its peak amplitude and fACLK is the frequency of the ACLK. In most cases VERROR will not be significant. For a 60Hz signal on the “–” input to generate a 1/4LSB error (1.25mV) with the converter running at ACLK = 2MHz, its peak value would have to be 150mV. HORIZONTAL: 1µs/DIV Figure 15. Adequate Reference Settling 1090fc 21 LTC1090 U W U U VERTICAL: 0.5mV/DIV APPLICATIO S I FOR ATIO HORIZONTAL: 1µs/DIV Figure 16. Poor Reference Settling Can Cause A/D Errors 6. Reduced Reference Operation voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 0.5mV which is 0.1LSB with a 5V reference becomes 0.5LSB with a 1V reference and 2.5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “–” input to the LTC1090. The effective resolution of the LTC1090 can be increased by reducing the input span of the converter. The LTC1090 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of Linearity and Gain Error vs Reference Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low VREF values: Noise with Reduced VREF 1. Conversion speed (ACLK frequency) For operation with a 5V reference, the 200µV noise is only 0.04LSB peak-to-peak. In this case, the LTC1090 noise will contribute virtually no uncertainty to the output code. However, for reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1V reference, this same 200µV noise is 0.2LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 0.2LSB. If the reference is further reduced to 200mV, the 200µV noise becomes equal to one LSB and a stable code may be difficult to achieve. In this case averaging readings may be necessary. 2. Offset 3. Noise Conversion Speed with Reduced VREF With reduced reference voltages, the LSB step size is reduced and the LTC1090 internal comparator overdrive is reduced. With less overdrive, more time is required to perform a conversion. Therefore, the maximum ACLK frequency should be reduced when low values of VREF are used. This is shown in the typical curve of Maximum Conversion Clock Rate vs Reference Voltage. Offset with Reduced VREF The offset of the LTC1090 has a larger effect on the output code when the A/D is operated with reduced reference The total input referred noise of the LTC1090 can be reduced to approximately 200µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200µV of noise. This noise data was taken in a very clean setup. Any setup induced noise (noise or ripple on VCC, VREF, VIN or V –) will add to the internal noise. The lower the reference voltage to be used, the more critical it becomes to have a clean, noise-free setup. 1090fc 22 LTC1090 U TYPICAL APPLICATIO A “Quick Look” Circuit for the LTC1090 SNEAK-A-BITTM Users can get a quick look at the function and timing of the LTC1090 by using the following simple circuit. REF+ and DIN are tied to VCC selecting a 5V input span, CH7 as a single ended input, unipolar mode, MSB first format and 16-bit word length. ACLK and SCLK are tied together and driven by an external clock. CS is driven at 1/64 the clock rate by the CD4520 and DOUT outputs the data. All other pins are tied to a ground plane. The output data from the DOUT pin can be viewed on an oscilloscope which is set up to trigger on the falling edge of CS. The LTC1090’s unique ability to software select the polarity of the differential inputs and the output word length is used to achieve one more bit of resolution. Using the circuit below with two conversions and some software, a 2’s complement 10-bit + sign word is returned to memory inside the MPU. The MC68HC05C4 was chosen as an example; however, any processor could be used. Two 10-bit unipolar conversions are performed: the first over a 0 to 5V span and the second over a 0 to –5V span (by reversing the polarity of the inputs). The sign of the input is determined by which of the two spans contained it. Then the resulting number (ranging from –1023 to 1023 decimal) is converted to 2’s complement notation and stored in RAM. A “Quick Look” Circuit for the LTC1090 5V 4.7µF f/64 CH0 VCC CH1 ACLK CH2 SCLK EN RESET CH3 DIN Q1 Q4 CH4 DOUT Q2 CS Q3 CH6 REF + Q4 Q1 CH7 REF – RESET EN CH5 VIN LTC1090 COM DGND VDD CLK f V– Scope Trace of LTC1090 “Quick Look” Circuit Showing A/D Output of 0101010101 (155HEX) 0.1 Q3 LTC1090 Q2 VSS CS CLK DOUT AGND TO OSCILLOSCOPE CLOCK IN 1MHz MAX DEGLITCHER TIME LTC1090 • TA03 MSB (B9) LSB (B0) FILLS ZERO SNEAK-A-BIT Circuit 10µF LT1021-5 9V 2MHz CLOCK OTHER CHANNELS OR SNEAK-A-BIT INPUTS CH0 VCC CH1 ACLK CH2 SCLK CH3 DIN MOSI CH4 DOUT MISO CH5 VIN – 5V TO 5V MC68HC05C4 SCK LTC1090 CS CH6 REF + CH7 REF – COM V– DGND CO AGND 0.1µF –5V SNEAK-A-BIT is a trademark of Linear Technology Corp. LTC1090 • TA04 1090fc 23 LTC1090 U TYPICAL APPLICATIO Sneak-A-Bit Code for the LTC1090 Using the MC68HC05C4 SNEAK-A-BIT VIN 5V VIN MNEMONIC 5V ( + ) CH6 1ST CONVERSION 1024 STEPS ( – ) CH7 SOFTWARE 1ST CONVERSION VIN 0V 0V 2047 STEPS 0V 2ND CONVERSION 1024 STEPS ( – ) CH6 ( + ) CH7 –5V –5V 2ND CONVERSION SNEAK-A-BIT Code DOUT from LTC1090 in MC68HC05C4 RAM Sign Location $77 B10 B9 B8 B7 B6 B5 B4 B3 LSB B2 Location $87 B1 B0 filled with 0s DIN words for LTC1090 MSBF MUX Addr. UNI Word Length (ODD/SIGN) DIN 1 0 0 1 1 1 1 1 1 DIN 2 0 1 1 1 1 1 1 1 DIN 3 0 0 1 1 1 1 1 1 LTC1090 • TA05 Sneak-A-Bit Code for the LTC1090 Using the MC68HC05C4 MNEMONIC LDA STA LDA STA BSET JSR #$50 $0A #$FF $06 0, $02 READ–/+ JSR JSR JSR READ+/– READ–/+ CHK SIGN DESCRIPTION Configuration data for SPCR Load configuration data into $0A Configuration data for port C DDR Load configuration data into port C DDR Make sure CS is high Dummy read configures LTC1090 for next read Read CH6 with respect to CH7 Read CH7 with respect to CH6 Determines which reading has valid data, converts to 2’s complement and stores in RAM READ–/+: LDA JSR LDA STA LDA STA RTS READ+/–: LDA JSR LDA STA LDA STA RTS TRANSFER: BCLR STA LOOP 1: TST BPL LDA STA STA LOOP 2: TST BPL BSET LDA STA RTS CHK SIGN: LDA ORA BEQ CLC ROR ROR LDA STA LDA STA BRA MINUS: CLC ROR ROR COM COM LDA ADD STA CLRA ADC STA STA LDA STA END: RTS DESCRIPTION #$3F TRANSFER $60 $71 $61 $72 Load DIN word for LTC1090 into ACC Read LTC1090 routine Load MSBs from LTC1090 into ACC Store MSBs in $71 Load LSBs from LTC1090 into ACC Store LSBs in $72 Return #$7F Load DIN word for LTC1090 into ACC TRANSFER Read LTC1090 routine $60 Load MSBs from LTC1090 into ACC $73 Store MSBs in $73 $61 Load LSBs from LTC1090 into ACC $74 Store LSBs in $74 Return 0, $02 CS goes low $0C Load DIN into SPI. Start transfer $0B Test status of SPlF LOOP 1 Loop to previous instruction if not done $0C Load contents of SPI data reg into ACC $0C Start next cycle $60 Store MSBs in $60 $0B Test status of SPlF LOOP 2 Loop to previous instruction if not done 0, $02 CS goes high $0C Load contents of SPI data reg into ACC $61 Store LSBs in $61 Return $73 Load MSBs of +/– read into ACC $74 Or ACC (MSBs) with LSBs of +/– read MINUS If result is 0 goto minus Clear carry $73 Rotate right $73 through carry $74 Rotate right $74 through carry $73 Load MSBs of +/– read into ACC $77 Store MSBs in RAM location $77 $74 Load LSBs of +/– read into ACC $87 Store LSBs in RAM location $87 END Goto end of routine Clear carry $71 Shift MSBs of – /+ read right $72 Shift LSBs of – /+ read right $71 1’s complement of MSBs $72 1’s complement of LSBs $72 Load LSBs into ACC #$01 Add 1 to LSBs $72 Store ACC in $72 Clear ACC $71 Add with carry to MSBs. Result in ACC $71 Store ACC in $71 $77 Store MSBs in RAM location $77 $72 Load LSBs in ACC $87 Store LSBs in RAM location $87 Return 1090fc 24 LTC1090 U PACKAGE DESCRIPTIO J Package 20-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 1.060 (26.924) MAX CORNER LEADS OPTION (4 PLCS) 20 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 19 18 17 16 15 14 13 12 11 2 3 4 5 6 7 8 9 10 0.220 – 0.310 0.025 (5.588 – 7.874) (0.635) RAD TYP 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 1 0.005 (0.127) MIN 0.300 BSC (0.762 BSC) 0.200 (5.080) MAX 0.015 – 0.060 (0.381 – 1.524) 0.008 – 0.018 (0.203 – 0.457) 0° – 15° NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS 0.125 (3.175) MIN 0.045 – 0.065 (1.143 – 1.651) 0.014 – 0.026 (0.356 – 0.660) 0.100 (2.54) BSC J20 1298 OBSOLETE PACKAGE 1090fc 25 LTC1090 U PACKAGE DESCRIPTIO N Package 20-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 1.040* (26.416) MAX 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 +0.889 8.255 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.127) MIN *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 0.100 (2.54) BSC 0.018 ± 0.003 (0.457 ± 0.076) N20 1098 1090fc 26 LTC1090 U PACKAGE DESCRIPTIO SW Package 20-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) 0.496 – 0.512* (12.598 – 13.005) 20 19 18 17 16 15 14 13 12 11 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 1 2 3 4 5 6 7 8 9 0.093 – 0.104 (2.362 – 2.642) 10 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) BSC 0.014 – 0.019 (0.356 – 0.482) TYP 0.004 – 0.012 (0.102 – 0.305) S20 (WIDE) 1098 NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1090fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC1090 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1290 8-Channel Configurable, 5V, 12-Bit ADC Pin-Compatible with LTC1090 LTC1391 Serial-Controlled 8-to-1 Analog Multiplexer Low RON, Low Power, 16-Pin SO and SSOP Package LTC1594L/LTC1598L 4-/8-Channel, 3V Micropower 12-Bit ADC Low Power, Small Size LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADCs 5V, Programmable MUX and Sequencer LTC1852/LTC1853 10-Bit/12-Bit, 8-Channel, 400ksps ADCs 3V or 5V, Programmable MUX and Sequencer LTC2404/LTC2408 24-Bit, 4-/8-Channel, No Latency ∆ΣTM ADC 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2424/LTC2428 20-Bit, 4-/8-Channel, No Latency ∆Σ ADC 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408 No Latency ∆Σ is a trademark of Linear Technology Corporation. 1090fc 28 Linear Technology Corporation LW/TP 0902 1K REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 1990