LTC1283
3V Single Chip 10-Bit Data
Acquisition System
U
DESCRIPTIO
FEATURES
■
■
■
■
■
Single Supply 3.3V or ±3.3V Operation
Software Programmable Features:
Unipolar/Bipolar Conversions
4 Differential/8 Single-Ended Inputs
MSB- or LSB-First Data Sequence
Variable Data Word Length
Built-In Sample-and-Hold
Direct 4-Wire Interface to Most MPU Serial Ports
and all MPU Parallel Ports
15kHz Maximum Throughput Rate
U
KEY SPECIFICATIO S
■
■
■
■
■
■
■
Minimum Guaranteed Supply Voltage: 3V
Resolution: 10 Bits
Offset Error: ±0.5LSB Max
Linearity Error: ±0.5LSB Max
Gain Error (LTC1283A): ±1LSB Max
Conversion Time: 44µs
Supply Current: 350µA Max, 150µA Typ
The LTC1283 is a 3V data acquisition component which
contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology
to perform either 10-bit unipolar, or 9-bit plus sign bipolar
A/D conversions. The 8-channel input multiplexer can be
configured for either single-ended or differential inputs (or
combinations thereof). An on-chip sample-and-hold is
included for all single-ended input channels.
The serial I/O is designed to be compatible with industrystandard full-duplex serial interfaces. It allows either MSBor LSB-first data and automatically provides 2’s complement output coding in the bipolar mode. The output data
word can be programmed for a length of 8-, 10-, 12-, or
16-bit. This allows easy interface to shift registers and a
variety of processors.
Both the LTC1283A and LTC1283 are specified with offset
and linearity errors less than ±0.5LSB. The LTC1283A has
a gain error limit of ±1LSB. The 1283 is specified with a
gain error limit of ±2LSB for applications where gain is
adjustable or less critcial.
LTCMOS is a trademark of Linear Technology Corp.
UO
TYPICAL APPLICATI
4.7µF
Linearity Plot
FOR 83CL410 CODE SEE
APPLICATIONS INFORMATION SECTION
3V
1.0
MPU
(e.g., 83CL410)
LTC1283
DIFFERENTIAL
INPUT
0.5
ERROR (LSBs)
3V
BIPOLAR
INPUT
–3V
3V
UNIPOLAR
INPUTS
T
DOUT
P1.1
DIN
P1.2
SCLK
P1.3
0
–0.5
P1.4
CS
SERIAL DATA LINK
– 1.0
0
512
1024
OUTPUT CODE
LTC1283 • TA02
(+)
(–)
–3V
–UNIPOLAR
INPUT
LTC1283 • TA01
1
LTC1283
W W
W
AXI U
U
ABSOLUTE
RATI GS (Notes 1 and 2)
Supply Voltage (VCC) to GND or V – ......................... 12V
Voltage
Analog and Reference
Inputs ................................. (V –) –0.3V to VCC + 0.3V
Digital Inputs......................................... –0.3V to 12V
Digital Outputs ........................... –0.3V to VCC + 0.3V
Negative Supply Voltage (V–) ..................... –6V to GND
Power Dissipation.............................................. 500mW
Operating Temperature
LTC1283AC, LTC1283C ......................... 0°C to 70°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CH0
1
20 VCC
CH1
2
19 ACLK
CH2
3
18 SCLK
CH3
4
17 DIN
CH4
5
CH5
6
CH6
CH7
COM
ORDER PART
NUMBER
TOP VIEW
CH0 1
20 VCC
CH1 2
19 ACLK
CH2 3
18 SCLK
CH3 4
17 DIN
16 DOUT
CH4 5
16 DOUT
15 CS
CH5 6
15 CS
7
14 REF +
CH6 7
14 REF +
8
13 REF –
CH7 8
13 REF –
COM 9
12 V –
9
12
DGND 10
LTC1283ACN
LTC1283CN
V–
11 AGND
DGND 10
ORDER PART
NUMBER
LTC1283ACS
LTC1283CS
11 AGND
N PACKAGE
20-LEAD PLASTIC DIP
S PACKAGE
20-LEAD PLASTIC SOL
TJ MAX = 150°C, θJA = 100°C/W
TJ MAX = 150°C, θJA = 130°C/W
Consult factory for Industrial and Military grade parts
U
U
U WW
SYMBOL
U
RECO
E DED OPERATI G CO DITIO S
LTC1283/LTC1283A
MIN
TYP
MAX
PARAMETER
CONDITIONS
VCC
Positive Supply Voltage
V – = 0V
3.0
3.6
V
V–
Negative Supply Voltage
VCC = 3.3V
– 3.6
0
V
fSCLK
Shift Clock Frequency
VCC = 3V
0
500
kHz
fACLK
A/D Clock Frequency
VCC = 3V
TA ≤ 25°C
TA ≤ 70°C
0.01
0.05
1.00
1.00
MHz
MHz
tCYC
Total Cycle Time
See Operating Sequence
thCS
Hold Time, CS Low After Last SCLK↓
VCC = 3V
thDI
Hold Time, DIN After SCLK↑
tsuCS
Setup Time CS↓ Before Clocking in First Address Bit (Note 8)
tsuDI
10 SCLK +
48 ACLK
UNITS
Cycles
0
ns
VCC = 3V
200
ns
VCC = 3V
2 ACLK Cycles
+ 1µs
Setup Time, DIN Stable Before SCLK↑
VCC = 3V
400
ns
tWHACLK
ACLK High Time
VCC = 3V
250
ns
tWLACLK
ACLK Low Time
VCC = 3V
400
ns
tWHCS
CS High Time During Conversion
VCC = 3V
44
ACLK
Cycles
2
LTC1283
U
U W
CO VERTER A D ULTIPLEXER CHARACTERISTICS (Note 3)
LTC1283
TYP
MAX
UNITS
±0.5
±0.5
LSB
●
±0.5
±0.5
LSB
●
±1.0
±2.0
LSB
●
10
10
Bits
PARAMETER
CONDITIONS
MIN
Offset Error
(Note 4)
●
Linearity Error
(Notes 4 and 5)
Gain Error
(Note 4)
Minimum Resolution for Which No
Missing Codes are Guaranteed
LTC1283A
TYP
MAX
Reference Input Resistance
MIN
10
10
(V –) – 0.05V to V
kΩ
Analog and REF Input Range
(Note 6)
On Channel Leakage Current
(Note 7)
On Channel = 3V
Off Channel = 0V
●
1
1
µA
On Channel = 0V
Off Channel = 3V
●
–1
–1
µA
On Channel = 3V
Off Channel = 0V
●
–1
–1
µA
On Channel = 0V
Off Channel = 3V
●
1
1
µA
LTC1283/LTC1283A
MIN
TYP
MAX
UNITS
Off Channel Leakage Current
(Note 7)
CC
V
+ 0.05V
AC CHARACTERISTICS (Note 3)
SYMBOL
PARAMETER
CONDITIONS
tACC
Delay Time From CS↓ to DOUT Data Valid
(Note 8)
2
ACLK Cycles
tSMPL
Analog Input Sample Time
See Operating Sequence
5
SCLK Cycles
tCONV
Conversion Time
See Operating Sequence
44
ACLK Cycles
tdDO
Delay Time, SCLK↓ to DOUT Data Valid
See Test Circuts
●
400
900
ns
tdis
Delay Time, CS↑ to DOUT Hi-Z
See Test Circuits
●
240
500
ns
ten
Delay Time, 2nd CLK↓ to DOUT Enabled
See Test Circuits
●
300
800
ns
thDO
Time Output Data Remains Valid After SCLK↓
tf
DOUT Fall Time
See Test Circuits
●
90
300
ns
tr
DOUT Rise Time
See Test Circuits
●
80
300
ns
CIN
Input Capacitance
Analog Inputs On Channel
Off Channel
Digital Inputs
75
ns
65
5
5
pF
pF
pF
U
DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3)
LTC1283/LTC1283A
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VCC = 3.6V
●
VIL
Low Level Input Voltage
VCC = 3V
●
IIH
High Level Input Current
VIN = VCC
IIL
Low Level Input Current
VIN = 0V
VOH
High Level Output Voltage
VCC = 3V, IO = – 20µA
IO = – 200µA
●
VCC = 3V, IO = 20µA
IO = 400µA
●
VOL
Low Level Output Voltage
1.7
UNITS
V
0.45
V
●
2.5
µA
●
– 2.5
µA
2.6
2.0
2.8
0.05
0.10
V
V
0.30
V
V
3
LTC1283
U
DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3)
LTC1283/LTC1283A
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
IOZ
Hi-Z Output Leakage
VOUT = VCC, CS High
VOUT = 0V, CS High
ISOURCE
Output Source Current
VOUT = 0V
– 4.5
mA
ISINK
Output Sink Current
VOUT = VCC
4.5
mA
ICC
Positive Supply Current
CS High, REF + Open
●
150
IREF
Reference Current
VREF = 2.5V
●
250
500
µA
I–
Negative Supply Current
CS High, V – = – 3V
●
–1
– 50
µA
The ● denotes specifications which apply over the operating temperature
range; all other limits and typicals TA = 25°C.
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND
and REF – wired together (unless otherwise noted).
Note 3: VCC = 3V, VREF+ = 2.5V, VREF– = 0V, V – = 0V for unipolar mode
and – 3V for bipolar mode, ACLK = 1MHz, SCLK = 0.25MHz unless
otherwise specified.
Note 4: These specifications apply for both unipolar and bipolar modes. In
bipolar mode, one LSB is equal to the bipolar input span (2VREF) divided
by 1024. For example, when VREF = 2.5V, 1LSB (bipolar) = 2(2.5V)/1024 =
4.88mV.
Note 5: Linearity error is the deviation from ideal of the slope between the
two end points of the transfer curve.
UNITS
µA
µA
3
–3
●
●
µA
350
Note 6: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode drop
below V – or one diode drop above VCC. Be careful during testing at low
VCC levels, as high level reference or analog inputs can cause this input
diode to conduct, especially at elevated temperatures, and cause errors for
inputs near full scale. This spec allows 50mV forward bias of either diode.
This means that as long as the reference or analog input does not exceed
the supply voltage by more than 50mV, the output code will be correct.
Note 7: Channel leakage current is measured after the channel selection.
Note 8: To minimize errors caused by noise at the chip select input, the
internal circuitry waits for two ACLK falling edges after a chip select falling
edge is detected before responding to control input signals. Therefore, no
attempt should be made to clock an address in or data out until the
minimum chip select setup time has elapsed.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Temperature
500
REF + OPEN
ACLK = 500kHz
VCC = CS = 3V
1
× VREF)
1024
400
100
300
OFFSET ERROR (LSBs =
150
200
100
50
0
50
25
0
75 100
–50 –25
AMBIENT TEMPERATURE (°C)
125
LTC1283 • G01
4
10
VCC = 3V
VREF = 2.5V
IREF (µA)
SUPPLY CURRENT, ICC (µA)
250
200
Unadjusted Offset Error
vs Reference Voltage
Reference Current vs Temperature
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LTC1283 • G02
VCC = 3V
ACLK = 500kHz
9
8
7
6
5
4
3
2
1
0
0
0.5
1.5
2.0
1.0
REFERENCE VOLTAGE (V)
2.5
LTC1283 • G03
LTC1283
U W
Change in Full-Scale Error
vs Reference Voltage
Linearity Error
vs Reference Voltage
1.0
1.0
0.8
0.7
LINEARITY ERROR (LSBs =
CHANGE IN GAIN ERROR (LSB)
0.9
1
× VREF)
1024
VCC = 3V
ACLK = 500kHz
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1.5
2.0
1.0
REFERENCE VOLTAGE (V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
VCC = 3V
ACLK = 500kHz
0.5
1.5
2.0
1.0
REFERENCE VOLTAGE (V)
0
Change in Linearity Error
vs Temperature
0.3
0.2
0.1
0
50
25
0
75 100
–50 –25
AMBIENT TEMPERATURE (°C)
125
0.2
0.1
0
50
25
0
75 100
–50 –25
AMBIENT TEMPERATURE (°C)
0.3
0.2
0.1
0
–50 –25
50
25
0
75
TEMPERATURE (°C)
1500
500
250
0
2.5
1.0
0.75
0.5
0.25
–25
75 100
0
50
25
AMBIENT TEMPERATURE (˚C)
125
LTC1283 • G09
Maximum Filter Resistor
vs Cycle Time
100k
VCC = 3V
VCC = 3V
RFILTER
+
VIN
1250
CFILTER ≥ 1µF
1000
750
VIN
+ INPUT
500
– INPUT
250
10k
–
1k
100
RSOURCE–
0
1.0
1.5
2.0
REFERENCE VOLTAGE (V)
1.25
0
–50
125
MAXIMUM RFILTER** (Ω)
MAXIMUM ACLK FREQUENCY* (kHz)
750
100
1.5
Maximum Conversion Clock Rate
vs Source Resistance
VCC = 3V
1000
125
VCC = 3V
VREF = 2.5V
1.75
LTC1283 • G08
1500
MAXIMUM ACLK FREQUENCY* (kHz)
0.3
2.0
VCC = 3V
VREF = 2.5V
ACLK = 500kHz
0.4
Maximum Conversion Clock Rate
vs Reference Voltage
0.5
0.4
Maximum Conversion Clock Rate
vs Temperature
0.5
LTC1283 • G07
1250
VCC = 3V
VREF = 2.5V
ACLK = 500kHz
LTC1283 • G06
MAXIMUM ACLK FREQUENCY* (MHz)
VCC = 3V
VREF = 2.5V
ACLK = 500kHz
0
0.5
Change in Gain Error
vs Temperature
0.5
0.4
Change in Offset Error
vs Temperature
LTC1283 • G05
MAGNITUDE OF GAIN CHANGE, ∆ GAIN (LSB)
MAGNITUDE OF LINEARITY CHANGE, ∆ LINEARITY (LSB)
LTC1283 • G04
2.5
MAGNITUDE OF OFFSET CHANGE, ∆ OFFSET (LSB)
TYPICAL PERFOR A CE CHARACTERISTICS
10
1
100
RSOURCE (kΩ)
LTC1283 • G10
*Maximum ACLK frequency represents the ACLK frequency at which a 0.1LSB shift in the error at
any code transition from its 100kHz value is first detected.
LTC1283 • G11
10
10
100
1000
10000
CYCLE TIME (µs)
LTC1283 • G12
**Maximum RFILTER represents the filter resistor value at which a 0.1LSB change in full-scale error
from its value at RFILTER = 0 is first detected.
5
LTC1283
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Noise Error
vs Reference Voltage
1000
VCC = 3V
VREF = 2.5V
TA = 25°C
0V TO 2.5V INPUT STEP
4 V
IN
+
RSOURCE
+
3
–
2
1
0.1
1
10
RSOURCE (kΩ)
1.2
VCC = 3V
VREF = 2.5V
GUARANTEED
PEAK-TO-PEAK NOISE ERROR (LSB )
10
9
8
7
6
5
Input Channel Leakage Current
vs Temperature
INPUT CHANNEL LEAKAGE CURRENT (nA)
S&H ACQUISITION TIME TO 0.1% (µs)
Sample-and-Hold Acquisition
Time vs Source Resistance
100
10
ON
CHANNEL
1
OFF
CHANNEL
0.1
0.01
75 100
–50 –25
0
25
50
AMBIENT TEMPERATURE (°C)
LTC1283 • G13
VCC = 3V
ACLK = 500kHz
1.0
0.8
LTC1283 NOISE = 200µVP-P
0.6
0.4
0.2
0
125
0
0.5
1.0
1.5
2.0
REFERENCE VOLTAGE (V)
LTC1283 • G14
LTC1283 • G15
U
U
U
PI FU CTIO S
#
PIN
FUNCTION
DESCRIPTION
1-8
9
CH0-CH7
COM
Analog Inputs
Common
10
11
12
13, 14
15
16
17
18
19
20
DGND
AGND
V–
REF –, REF +
CS
DOUT
DIN
SCLK
ACLK
VCC
Digital Ground
Analog Ground
Negative Supply
Reference Inputs
Chip Select Input
Digital Data Output
Data Input
Shift Clock
A/D Conversion Clock
Positive Supply
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single-ended inputs. It must be
free of noise and is usually tied to the analog ground plane.
This is the ground for the internal logic. Tie to the ground plane.
AGND should be tied directly to the analog ground plane.
Tie V – to most negative potential in the circuit. (Ground in single supply applications.)
The reference inputs must be kept free of noise with respect to AGND.
A logic low on this input enables data transfer.
The A/D conversion result is shifted out of this output.
The A/D configuration word is shifted into this input.
This clock synchronizes the serial data transfer.
This clock controls the A/D conversion process.
This supply must be kept free of noise and ripple by bypassing directly to the analog
ground plane.
W
BLOCK DIAGRA
VCC
DIN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
6
18
20
INPUT
SHIFT
REGISTER
17
OUTPUT
SHIFT
REGISTER
16
SCLK
DOUT
1
SAMPLEANDHOLD
2
3
COMP
4
5
ANALOG
INPUT MUX
10-BIT
SAR
6
10-BIT
CAPACITIVE
DAC
7
8
9
19
10
11
DGND
AGND
12
V–
13
REF –
14
REF+
2.5
CONTROL
AND
TIMING
15
ACLK
CS
LTC1283 BD
LTC1283
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO
On and Off Channel Leakage Current
3V
SCLK
ION
A
0.6V
ON CHANNEL
tdDO
IOFF
2.0V
A
DOUT
0.6V
OFF
CHANNELS
LTC1283 TC02
POLARITY
LTC1283 TC01
Load Circuit for tdDO, tr, tf and ten
Voltage Waveform for DOUT Rise and Fall Times, tr and tf
1.5V
2.0V
DOUT
3k
DOUT
0.6V
TEST POINT
tr
tf
100pF
LTC1283 TC03
LTC1283 TC06
Load Circuit for tdis
TEST POINT
3V WAVEFORM 2
3k
DOUT
WAVEFORM 1
100pF
LTC1283 TC05
Voltage Waveforms for ten and tdis
1
2
ACLK
2.0V
CS
DOUT
WAVEFORM 1
(SEE NOTE 1)
2.0V
ten
DOUT
WAVEFORM 2
(SEE NOTE 2)
90%
tdis
0.6V
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT
IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT
IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1283 TC04
7
LTC1283
W
U
U
UO
APPLICATI
S I FOR ATIO
The LTC1283 is a 3V data acquisition component which
contains the following functional blocks:
previous conversion is output on the DOUT line. At the end
of the data exchange the requested conversion begins
and CS should be brought high. After tCONV, the conversion is complete and the results will be available on the
next data transfer cycle. As shown below, the result of
a conversion is delayed by one CS cycle from the input
word requesting it.
1. 10-bit successive approximation capacitive
A/D converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S&H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIN
DIN WORD 1
DIN WORD 2
DIN WORD 3
DOUT
DOUT WORD 0
DOUT WORD 1
DOUT WORD 2
DIGITAL CONSIDERATIONS
DATA
TRANSFER
tCONV
A/D
CONVERSION
tCONV
A/D
CONVERSION
DATA
TRANSFER
LTC1283 • AI02
1. Serial Interface
2. Input Data Word
The LTC1283 communicates with microprocessors and
other external circuitry via a synchronous, full duplex, 4wire serial interface (see Operating Sequence). The shift
clock (SCLK) synchronizes the data transfer with each bit
being transmitted on the falling SCLK edge and captured
on the rising SCLK edge in both transmitting and receiving
systems. The data is transmitted and received simultaneously (full duplex).
The LTC1283 8-bit input data word is clocked into the DIN
input on the first eight rising SCLK edges after chip select
is recognized. Further inputs on the DIN pin are then
ignored until the next CS cycle. The eight bits of the input
word are defined as follows:
UNIPOLAR/
BIPOLAR
DATA INPUT (DIN) WORD:
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the DIN input which configures the LTC1283
for the next conversion. Simultaneously, the result of the
SGL/
DIFF
ODD/
SIGN
SELECT
1
SELECT
0
UNI
WORD
LENGTH
MSBF
WL1
MSB-FIRST/
LSB-FIRST
MUX ADDRESS
WL0
LTC1283 • AI03
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 10-Bit Word Length)
tCYC
1
2
3
4
5
6
7
8
SCLK
9
10
DON’T CARE
tSMPL
tCONV
CS
DIN
ODD/
SEL
SGL/ SIGN SEL 0
WL0
MSBF
WL1
UNI
DIFF
1
DON’T CARE
B9
(SB)
DOUT
SHIFT CONFIGURATION
WORD IN
B8
B7
B6
B5
B4
B3
B2
B1
B0
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
LTC1283 • AI01
8
LTC1283
W
U
U
UO
APPLICATI
S I FOR ATIO
Multiplexer (MUX) Address
The first four bits of the input word assign the MUX
configuration for the requested conversion. For a given
channel selection, the converter will measure the voltage
between the two channels indicted by the + and – signs in
the selected row of Table 1. Note that in differential mode
(SGL/DIFF = 0) measurements are limited to four adjacent
input pairs with either polarity. In single-ended mode, all
input channels are measured with respect to COM. Figure
1 shows some examples of multiplexer assignments.
Table 1. Multiplexer Channel Selection
MUX ADDRESS
SELECT
0DD/
0
SIGN 1
0
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
SGL/
DIFF
0
0
0
0
0
0
0
0
DIFFERENTIAL CHANNEL SELECTION
0
+
1
–
2
+
3
5
4
0,1
{
2,3
{
4,5
{
6,7
{
7
–
–
+
+
–
–
+
–
+
+
–
–
4 Differential
CHANNEL
6
+
MUX ADDRESS
0DD/ SELECT
SIGN 1
0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
8 Single-Ended
CHANNEL
0
1
2
3
4
5
6
7
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
+ (–)
– (+)
SINGLE-ENDED CHANNEL SELECTION
SGL/
DIFF
0
+
1
2
3
4
5
6
+
+
+
+
+
+
7 COM
–
–
–
–
–
–
–
–
+
Combinations of Differential and Single-Ended
CHANNEL
+
+
+
+
+
+
+
+
0,1
{
+
–
2,3
{
–
+
+
+
+
+
4
5
6
7
COM (–)
COM (–)
Changing the MUX Assignment “On the Fly”
4,5
{
6,7
{
+
–
+
–
COM (UNUSED)
1ST CONVERSION
5,4
{
–
+
6
7
{
+
+
COM (–)
LTC1283 • F01
2ND CONVERSION
Figure 1. Examples of Multiplexer Options on the LTC1283
9
LTC1283
W
U
U
UO
APPLICATI
S I FOR ATIO
Unipolar/Bipolar (UNI)
input voltage. When UNI is a logical zero, a bipolar conversion will result. The input span and code assignment for
each conversion type are shown in the figures below.
The fifth input bit (UNI) determines whether the conversion will be unipolar or bipolar. When UNI is a logical one,
a unipolar conversion will be performed on the selected
Unipolar Transfer Curve (UNI = 1)
Unipolar Output Code (UNI = 1)
1111111111
1111111110
•
•
•
0000000001
0000000000
VIN
0V
1LSB
VREF – 2LSB
VREF
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 2.5V)
1111111111
1111111110
•
•
•
0000000001
0000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
2.4976V
2.4951V
•
•
•
0.0024V
0V
VREF – 1LSB
LTC1283 AI06
LTC1283 AI04
Bipolar Transfer Curve (UNI = 0)
0111111111
0111111110
1LSB
–VREF + 1LSB
–VREF
0000000001
0000000000
VIN
VREF – 2LSB
1111111111
VREF
1111111110
VREF – 1LSB
–1LSB
–2LSB
1000000001
LTC1283 AI05
1000000000
Bipolar Output Code (UNI = 0)
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 2.5V)
0111111111
0111111110
•
•
•
0000000001
0000000000
1111111111
1111111110
•
•
•
1000000001
1000000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
–1LSB
–2LSB
•
•
•
–(VREF) + 1LSB
– (VREF)
2.4951V
2.4902V
•
•
•
0.0049V
0V
–0.0049V
–0.0098V
•
•
•
–2.4951V
–2.5000V
LTC1283 AI07
10
LTC1283
U
W
U
UO
APPLICATI
S I FOR ATIO
MSB-First/LSB-First Format (MSBF)
The output data of the LTC1283 is programmed for MSBfirst or LSB-first sequence using the MSBF bit. For MSBfirst output data the input word clocked to the LTC1283
should always contain a logical one in the sixth bit location
(MSBF bit). Likewise for LSB-first output data, the input
word clocked to the LTC1283 should always contain a zero
in the MSBF bit location. The MSBF bit in a given DIN word
will control the order of the next DOUT word. The MSBF bit
affects only the order of the output data word. The order
of the input word is unaffected by this bit.
1 ACLK cycle. After a change of state on the CS input, the
LTC1283 waits for two falling edges of the ACLK before
recognizing a valid chip select. One indication of CS low
recognition is the DOUT line becoming active (leaving the
Hi-Z state). Note that the deglitching applies to both the
rising and falling CS edges.
ACLK
CS
DOUT
HI-Z
OUTPUT FORMAT
LSB-First
MSB-First
MSBF
0
1
VALID OUTPUT
LOW CS RECOGINZED INTERNALLY
LTC1283 AI08
ACLK
Word Length (WL1, WL0)
The last two bits of the input word (WL1 and WL0)
program the output data word length of the LTC1283.
Word lengths of 8-, 10-, 12- or 16-bit can be selected
according to the following table. The WL1 and WL0 bits in
a given DIN word control the length of the present, not the
next, DOUT word. WL1 and WL2 are never “don’t cares”
and must be set for the correct DOUT word length even
when a “dummy” DIN word is sent. On any transfer cycle,
the word length should be made equal to the number of
SCLK cycles sent by the MPU.
WL1
0
0
1
1
WL0
0
1
0
1
OUTPUT WORD LENGTH
8 Bits
10 Bits
12 Bits
16 Bits
LTC1283 • AI09
Figure 2 shows how the data output (DOUT) timing can be
controlled with word length selection and MSB/LSB-first
format selection.
3. Deglitcher
A deglitching circuit has been added to the chip select
input of the LTC1283 to minimize the effects of errors
caused by noise on that input. This circuit ignores changes
in state on the CS input that are shorter in duration than
CS
DOUT
VALID OUTPUT
HI-Z
HIGH CS RECOGNIZED INTERNALLY
LTC1283 • AI10
4. CS Low During Conversion
In the normal mode of operation, CS is brought high
during the conversion time (see Figure 3). The serial port
ignores any SCLK activity while CS is high. The LTC1283
will also operate with CS low during the conversion. In this
mode, SCLK must remain low during the conversion as
shown in Figure 4. After the conversion is complete, the
DOUT line will become active with the first output bit. Then
the data transfer can begin as normal.
5. Microprocessor Interfaces
The LTC1283 can interface directly (without external hardware) to most popular microprocessor (MPU) synchronous serial formats (see Table 2). If an MPU without a
serial interface is used, then four of the MPU’s parallel port
lines can be programmed to form the serial link to the
LTC1283. Included here are three serial interface examples and one example showing a parallel port programmed to form the serial interface.
11
LTC1283
W
U
U
UO
APPLICATI
S I FOR ATIO
8-Bit Word Length
tSMPL
tCONV
CS
SCLK
1
8
(SB)
DOUT
MSB-FIRST
B9
B8
B7
B6
B5
B4
B3
B2
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
THE LAST TWO BITS
ARE TRUNCATED
10-Bit Word Length
tSMPL
tCONV
CS
SCLK
10
1
(SB)
DOUT
MSB-FIRST
B8
B9
B7
B6
B5
B4
B3
B2
B1
B0
(SB)
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
12-Bit Word Length
tSMPL
tCONV
CS
1
SCLK
10
(SB)
DOUT
MSB-FIRST
B9
B8
B7
B6
B5
B4
B3
B2
B1
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
B8
12
FILL
ZEROES
B0
(SB)
B9
*
*
16-Bit Word Length
tSMPL
tCONV
CS
SCLK
1
10
16
(SB)
DOUT
MSB-FIRST
B9
B8
B7
B6
B5
B4
B3
B2
B1
DOUT
LSB-FIRST
B0
B1
B2
B3
B4
B5
B6
B7
B8
FILL
ZEROES
B0
(SB)
B9
*
*
*
*
* IN UNIPOLAR MODE, THESE BITS ARE FILLED WITH ZEROES.
IN BIPOLAR MODE, THE SIGN BIT IS EXTENDED INTO THESE LOCATIONS.
Figure 2. Data Output (DOUT) Timing with Different Word Lengths
12
*
*
LTC1283 • F02
LTC1283
W
U
U
UO
APPLICATI
S I FOR ATIO
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
40 TO 44
ACLK CYCLES
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK
DIN
DOUT
SGL/
SEL SEL
DIFF ODD/ 1
0 UNI MSBF WL1 WL0
SIGN
B9
B8
B7
B6
B5
B4
B3
B2
DON’T CARE
B1
SGL/
SEL
DIFF ODD/ 1 SEL UNI MSBF WL1 WL0
0
SIGN
B0
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1283 • F03
Figure 3. CS High During Conversion
SHIFT
MUX ADDRESS
IN
tSMPL
SAMPLE ANALOG
INPUT
40 TO 44
ACLK CYCLES
SHIFT RESULT OUT
AND NEW ADDRESS IN
CS
SCLK MUST REMAIN LOW
SCLK
DIN
DOUT
SGL/
SEL SEL
DIFF ODD/ 1
0 UNI MSBF WL1 WL0
SIGN
B9
B8
B7
B6
B5
B4
B3
B2
DON’T CARE
B1
B0
SGL/
SEL
DIFF ODD/ 1 SEL UNI MSBF WL1 WL0
0
SIGN
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1283 • F04
Figure 4. CS Low During Conversion
Table 2. 3V Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1283*
PART NUMBER
TYPE OF INTERFACE
Motorola
MC68HC11
MC68HC05
SPI
SPI
RCA
CDP68HC05
SPI
National Semiconductor
COP800 Family
HPC16000 Family
MICROWIRE/PLUS†
MICROWIRE/PLUS†
Texas Instruments
TMS70C02
TMS70C42
Serial Port
Serial Port
Serial Port Microprocessors
Most synchronous serial formats contain a shift clock
(SCLK) and two data lines, one for transmitting and one for
receiving. In most cases data bits are transmitted on the
falling edge of the clock (SCLK) and captured on the rising
edge. However, serial port formats vary among MPU
manufacturers as to the smallest number of bits that can
be sent in one group (e.g., 4-bit, 8-bit or 16-bit transfers).
They also vary as to the order in which the bits are
transmitted (LSB- or MSB-first). The following examples
show how the LTC1283 accommodates these differences.
National MICROWIRE (COP820C)
*Contact factory for interface information for processors not on this list
†
MICROWIRE/PLUS is a trademark of National Semiconductor Corp.
The COP820C transfers data MSB-first and in 8-bit increments. This is easily accommodated by setting the LTC1283
to MSB-first format and 10-bit word length. The data
output word is then received by the COP820C in one 8-bit
block and one 2-bit block.
13
LTC1283
U
W
U
UO
APPLICATI
S I FOR ATIO
Hardware and Software Interface to National Semiconductor
COP820C Processor
LTC1283
ANALOG
INPUTS
•
•
•
•
DOUT from LTC1283 stored in COP820C RAM
MSB*
COP820C
CS
G1
SCLK
SK
DIN
SO
DOUT
9
8
7
6
5
4
3
2
BYTE 1
X
X
X
X
X
X
BYTE 2
LSB
1
SI
0
*B9 is MSB in unipolar or sign bit in bipolar
LTC1283 • AI12
LTC1283 • AI11
MNEMONIC
COMMENTS
MNEMONIC
COMMENTS
LD (F0)←0D
LD (D5)←32
LD (EE)←8
LD (B)←D4
LD (A)←(F0)
RBIT 1
X (A)←→(E9)
LD (B)←EF
SBIT 2
↑
NOP
↓
LOAD 0D INTO F0 (DIN)
CONFIGURE PORT G
CONFIGURE CONTROL REG.
PORT G DATA REG. INTO B
LOAD DIN INTO ACC
G1 RESET (CS GOES LOW)
LOAD DIN INTO SHIFT REG.
LOAD PSW REG. ADDR IN B
TRANSFER BEGINS
X(A)←→(E9)
SBIT 2
X (A)←→(F3)
RBIT 2
LD (B)←D4
SBIT 1
X (A)←→(E9)
RC
RRCA
RRCA
RRCA
X (A)←→(F4)
LOAD DOUT INTO ACC
TRANSFER CONTINUES
LOAD DOUT IN ADDR F3
STOP TRANSFER
PUT PORT G ADDR IN B
G1 SET (CS GOES HIGH)
LOAD DOUT INTO ACC
CLEAR CARRY
SHIFT RIGHT THRU CARRY
SHIFT RIGHT THRU CARRY
SHIFT RIGHT THRU CARRY
LOAD DOUT IN ADDR F4
15 NOPs FOR TIMING
Motorola SPI (MC68HC05C4, MC68HC11)
The MC68HC05C4 and MC68HC11 transfer data MSBfirst and in 8-bit increments. Programming the LTC1283
for MSB-first format and 16-bit word length allows the 10-
bit data output to be received by the MPU as two 8-bit
bytes with the final 6 unused bits filled with zeroes by the
LTC1283.
Hardware and Software Interface to Motorola MC68HC05C4 and
MC68HC11 Processors
DOUT from LTC1283 stored in MC68HC05C4 or MC68HC11 RAM
LTC1283
CS
ANALOG
INPUTS
•
•
•
•
SCLK
DIN
DOUT
MC68HC05C4
MC68HC11
MSB*
LOCATION A B9
C0
SCK
B8
B7
B6
B5
B4
B3
B2
BYTE 1
0
0
0
0
0
0
BYTE 2
LSB
MOSI
LOCATION A + 1 B1
B0
*B9 is MSB in unipolar or sign bit in bipolar
MISO
LTC1283 • AI14
LTC1283 • AI13
MNEMONIC
COMMENTS
MNEMONIC
COMMENTS
BCLR n
LDA
STA
↑
NOP
↓
LDA
LDA
C0 IS CLEARED (CS GOES LOW)
LOAD DIN FOR LTC1283 INTO ACC
LOAD DIN FROM ACC TO SPI DATA REG. START SCK
STA
↑
NOP
↓
BSET n
LDA
LDA
START NEXT SPI CYCLE
STA
14
8 NOPs FOR TIMING
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LOAD LTC1283 DOUT FROM SPI DATA REG.
INTO ACC (BYTE 1)
LOAD LTC1283 DOUT INTO RAM (LOCATION A)
STA
6 NOPs FOR TIMING
CO IS SET (CS GOES HIGH)
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LOAD LTC1283 DOUT FROM SPI DATA REG.
INT ACC (BYTE 2)
LOAD LTC1283 INTO RAM (LOCATION A +1)
LTC1283
U
W
U
UO
APPLICATI
S I FOR ATIO
Texas Instruments TMS70C42
The TMS70C42 transfers serial data in 8-bit increments,
LSB-first. To accommodate this, the LTC1283 is programmed for 16-bit word length and LSB-first format. The
10-bit output data is received by the processor as two
8-bit bytes, LSB-first. The LTC1283 fills the final 6 unused
bits (after the MSB) with zeroes.
Hardware and Software Interface to TI TMS70C42 Processor
DOUT from LTC1283 stored in TMS70C42 RAM
LTC1283
CS
ANALOG
INPUTS
7
AO
SCLK
•
•
•
•
LSB
TMS70C42
SCLK
DIN
TXD
DOUT
RXD
6
5
4
3
2
0
0
1
0
0
BYTE 1
8
BYTE 2
MSB
FILL WITH ZEROES
0
0
0
9
LTC1283 • AI16
LTC1283 • AI15
LABEL
MNEMONIC
DESCRIPTION
START
DINT
MOVP
MOVP
MOV
LDSP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOV
CALL
MOV
MOV
ANDP
MOVP
DISABLES ALL INTERRUPTS
DISABLE INTERRUPT FLAGS
DISABLE INTERRUPT FLAGS
ADDRESS OF STACK
PUT ADDRESS INTO POINTER
CONFIGURE PORT A
ENABLE Tx BY SETTING B3 = 1
RESET THE SERIAL PORT
CONFIGURE THE SERIAL PORT
TURN START BIT OFF
ENABLE THE SERIAL PORT
SET SCLK RATE (TIMER 3)
START TIMER
LOAD DIN WORD IN A
ROUTINE THAT SHIFTS DATA
PUT FIRST 8 LSBs IN R5
PUT MSBs IN R6
A0 CLEARED (CS GOES LOW)
PUT DIN INTO TXBUF
LOOP
SXTNBIT
% > 2A, P0
% > 02, P16
% > 60, B
% > DF, P5
% > 08, P6
% > 40, P21
% > 0C, P20
% > 00, P24
% > 00, P21
% > 00, P23
% > C0, P24
% > DF, A
SXTNBIT
B, R5
A, R6
% > FE, P4
A, P26
LABEL
WAIT1
WAIT2
MNEMONIC
DESCRIPTION
MOVP
MOVP
MOVP
MOVP
MOV
DJNZ
NOP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOV
DJNZ
NOP
MOVP
ORP
RETS
SCLK OFF (TIMER 3 DISABLED)
ENABLE SERIAL PORT
SCLK ON (TRANSFER BEGINS)
TXEN GOES LOW
LOAD COUNTER
LOOP WHILE SHIFT OCCURS
DELAY
PUT DOUT IN B
LOAD TXBUF
SCLK OFF (TIMER 3 DISABLE)
ENABLE SERIAL PORT
SCLK ON (TRANSFER BEGINS)
TXEN GOES LOW
LOAD COUNTER
LOOP WHILE SHIFT OCCURS
DELAY
PUT DOUT IN A
A0 SET (CS GOES HIGH)
RETURN TO MAIN PROGRAM
% > 40, P24
% > 17, P21
% > C0, P24
% > 16, P21
% > 02, A
A, WAIT1
P25, B
A, P26
% > 40, P24
% > 17, P21
% > C0, P24
% > 16, P21
% > 02, A
A, WAIT2
P25, A
% > 01, P4
Parallel Port Microprocessors
Signetics 83CL410
When interfacing the LTC1283 to an MPU which has a
parallel port, the serial signals are created on the port with
software. Three MPU port lines are programmed to create
the CS, SCLK and DIN signals for the LTC1283. A fourth
port line reads the DOUT line. An example is made of the
Signetics 83CL410.
To interface to the 83CL410, (a 3V version of the 80C51)
the LTC1283 is programmed for MSB-first format and 10bit word length. The 83CL410 generates CS, SCLK and DIN
on three port lines and reads DOUT on the fourth.
DOUT from LTC1283 stored in 83CL410 RAM
Hardware and Software Interface to Signetics 83CL410 Processor
LTC1283
DOUT
ANALOG
INPUTS
•
•
•
•
•
•
•
•
83CL410
MSB*
R2
B9
R3
B1
P1.2
SCLK
P1.3
CS
P1.4
ACLK
ALE
B7
B6
B5
B4
B3
B2
0
0
0
0
0
0
LSB
P1.1
DIN
B8
B2
*B9 IS MSB IN UNIPOLAR OR
SIGN BIT IN BIPOLAR
LTC1283 • AI18
LTC1283 • AI17
15
LTC1283
W
U
U
UO
APPLICATI
S I FOR ATIO
83CL410 Code
MNEMONIC
DESCRIPTION
MOV P1, #02H
CLR P1.3
SETB P1.4
CONTINUE: MOV A, #0DH
LOOP:
CLR P1.4
MOV R4, #08
NOP
MOV C, P1.1
RLC A
MOV P1.2, C
SETB P1.3
CLR P1.3
DJNZ R4, LOOP
MOV R2, A
MNEMONIC
INITIALIZE PORT 1 (BIT 1 IS MADE AN
INPUT)
SCLK GOES LOW
CS GOES LOW
DIN WORD FOR THE LTC1283 IS PLACED
IN ACC
CS GOES LOW
LOAD COUNTER
DELAY FOR DEGLITCHER
READ DATA BIT INTO CARRY
ROTATE DATA BIT INTO ACC
OUTPUT DIN BIT TO LTC1283
SCLK GOES HIGH
SCLK GOES LOW
NEXT BIT
STORE MSBs IN R2
6. Sharing the Serial Interface
The LTC1283 can share the same 3-wire serial interface
with other peripheral components or other LTC1283s (see
Figure 5). In this case, the CS signals decide which
LTC1283 is being addressed by the MPU.
ANALOG CONSIDERATIONS
1. Grounding
The LTC1283 should be used with an analog ground plane
and single point grounding techniques.
Pin 11 (AGND) should be tied directly to this ground plane.
Pin 10 (DGND) can also be tied directly to this ground
plane because minimal digital noise is generated within
the chip itself.
Pin 20 (VCC) should be bypassed to the ground plane with
a 4.7µF tantalum with leads as short as possible. Pin 12
2
1
DELAY:
DESCRIPTION
MOV C, P1.1
CLR A
RLC A
SETB P1.3
CLR P1.3
MOV C, P1.1
RRC A
RRC A
MOV R3, A
SETB P1.3
CLR P1.3
SETB P1.4
MOV R5, #07H
DJNZ R5, DELAY
AJMP CONTINUE
READ DATA BIT INTO CARRY
CLEAR ACC
ROTATE DATA BIT INTO ACC
SCLK GOES HIGH
SCLK GOES LOW
READ DATA BIT IN CARRY
ROTATE RIGHT INTO ACC
ROTATE RIGHT INTO ACC
STORE LSBs IN R3
SCLK GOES HIGH
SCLK GOES LOW
CS GOES HIGH
LOAD COUNTER
DELAY FOR LTC1283 TO PERFORM
CONVERSION
REPEAT PROGRAM
(V –) should be bypassed with a 0.1µF ceramic disk. For
single supply applications, V – can be tied to the ground
plane.
It is also recommended that pin 13 (REF –) and pin 9 (COM)
be tied directly to the ground plane. All analog inputs
should be referenced directly to the single point ground.
Digital inputs and outputs should be shielded from and/or
routed away from the reference and analog circuitry.
Figure 6 shows an example of an ideal ground plane design
for a two-sided board. Of course this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
2. Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce errors
0
OUTPUT PORT
SERIAL DATA
MPU
3-WIRE SERIAL
INTERFACE TO OTHER
PERIPHERALS OR LTC1283s
3
3
3
3
CS
LTC1283
CS
LTC1283
CS
LTC1283
8 CHANNELS
8 CHANNELS
8 CHANNELS
Figure 5. Several LTC1283s Sharing One 3-Wire Serial Interface
16
LTC1283 • F05
LTC1283
W
U
U
UO
APPLICATI
S I FOR ATIO
VCC
ANALOG
GROUND
PLANE
VERTICAL: 0.5mV/DIV
4.7µF
TANTALUM
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
V–
10
11
0.1µF
CERAMIC
DISK
HORIZONTAL: 10µs/DIV
Figure 7. Poor VCC Bypassing. Noise and Ripple
can Cause A/D Errors
LTC1283 • F06
or noise in the output code. VCC noise and ripple can be
kept below 1mV by bypassing the VCC pin directly to the
analog ground plane with a 4.7µF tantalum with leads as
short as possible. Figures 7 and 8 show the effects of good
and poor VCC bypassing.
VERTICAL: 0.5mV/DIV
Figure 6. Example Ground Plane for the LTC1283
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1283 have
capacitive switching input current spikes. These current
spikes settle quickly and do not cause a problem.
However, if large source resistances are used or if slow
settling op amps drive the inputs, care must be taken to
insure that the transients caused by the current spikes
settle completely before the conversion begins.
Source Resistance
The analog inputs of the LTC1283 look like 65pF capacitor
(CIN) in series with a 500Ω resistor (RON) as shown in
Figure 9. CIN gets switched between the selected “+” and
“–” inputs once during each conversion cycle. Large
external source resistors and capacitances will slow the
settling of the inputs. It is important that the overall RC
time constants be short enough to allow the analog inputs
to completely settle within the allowed time.
HORIZONTAL: 10µs/DIV
Figure 8. Good VCC Bypassing Keeps Noise and Ripple
on VCC Below 1mV
VIN +
VIN
–
RSOURCE +
RSOURCE –
“+”
INPUT
LTC1283
C1
4TH SCLK
RON = 500Ω
“–”
INPUT
LAST SCLK
CIN =
65pF
C2
LTC1283 • F09
Figure 9. Analog Input Equivalent Circuit
17
LTC1283
W
U
UO
S I FOR ATIO
SAMPLE
MUX ADDRESS
SHIFTED IN
ACLK
“+” INPUT
MUST SETTLE
DURING THIS TIME
tSMPL
HOLD
•••
CS
SCLK
U
APPLICATI
1
2
3
4
LAST SCLK (8TH, 10TH, 12TH OR 16TH DEPENDING ON WORD LENGTH)
•••
•••
1
2
3
4
•••
1ST BIT TEST
“–” INPUT MUST SETTLE
DURING THIS TIME
“+” INPUT
“–” INPUT
LTC1283 • F10
Figure 10. “+” and “–” Input Settling Windows
“+” Input Settling
Input Op Amps
This input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 10). The sample
phase starts at the 4th SCLK cycle and lasts until the falling
edge of the last SCLK (the 8th, 10th, 12th or 16th SCLK
cycle depending on the selected word length). The voltage
on the “+” input must settle completely within this sample
time. Minimizing RSOURCE+ and C1 will improve the input
settling time. If large “+” input source resistance must be
used, the sample time can be increased by using a slower
SCLK frequency or selecting a longer word length. With
the minimum possible sample time of 8µs, RSOURCE+ < 2k
and C1 < 20pF will provide adequate settling.
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommodate slower op amps. Most op amps including the LT1006
and LT1013 single supply op amps can be made to settle
well even with the minimum settling windows of 8µs (“+”
input) and 4µs (“–” input) which occur at the maximum
clock rates (ACLK = 1MHz and SCLK = 0.5MHz). Figures 11
and 12 show examples of adequate and poor op amp
settling.
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 10).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage be free of noise and settle completely during the
first four ACLK cycles of the conversion time. Minimizing
RSOURCE– and C2 will improve settling time. If large “–”
input source resistance must be used, the time allowed for
settling can be extended by using a slower ACLK frequency. At the maximum ACLK rate of 1MHz, RSOURCE–
< 1k and C2 < 20pF will provide adequate settling.
18
VERTICAL: 5mV/DIV
“–” Input Settling
HORIZONTAL: 1µs/DIV
Figure 11. Adequate Settling of Op Amp Driving Analog Input
LTC1283
U
W
U
UO
APPLICATI
S I FOR ATIO
VERTICAL: 5mV/DIV
leakage specification of 1µA (at 125°C) flowing through a
source resistance of 1k will cause a voltage drop of 1mV
or 0.4LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
curve of Input Channel Leakage Current vs Temperature).
Noise Coupling into Inputs
HORIZONTAL: 1µs/DIV
Figure 12. Poor Op Amp Settling Can Cause A/D Errors
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 13. For large values of CF (e.g., 1µF), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with small
resistor and large capacitor to prevent DC drops across
the resistor. The magnitude of the DC current is approximately IDC = 65pF × VIN /tCYC and is roughly proportional
to VIN. When running at the minimum cycle time of 68µs,
the input current equals 2.5µA at VIN = 2.5V. In this case,
a filter resistor of 100Ω will cause 0.1LSB of full-scale
error. If a larger filter resistor must be used, errors can be
eliminated by increasing the cycle time as shown in the
typical curve Maximum Filter Resistor vs Cycle Time.
RFILTER
IDC
“+”
VIN
CFILTER
High source resistance input signals (>500Ω) are more
sensitive to coupling from external sources. It is preferable to use channels near the center of the package (i.e.,
CH2-CH7) for signals which have the highest output
resistance because they are essentially shielded by the
pins of the package ends (DGND and CH0). Grounding any
unused inputs (especially the end pin, CH0) will also
reduce outside coupling into high source resistances.
4. Sample-and-Hold
Single-Ended Inputs
The LTC1283 provides a built-in sample-and-hold (S&H)
function for all signals acquired in the single-ended mode
(COM pin grounded). This sample-and-hold allows the
LTC1283 to convert rapidly varying signals (see typical
curve of S&H Acquisition Time vs Source Resistance). The
input voltage is sampled during the tSMPL time as shown
in Figure 10. The sampling interval begins after the fourth
MUX address bit is shifted in and continues during the
remainder of the data transfer. On the falling edge of the
final SCLK, the S&H goes into hold mode and the conversion begins. The voltage will be held on either the 8th,
10th, 12th or 16th falling edge of the SCLK depending on
the word length selected.
LTC1283
Differential Inputs
“–”
LTC1283 • F13
Figure 13. RC Input Filtering
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
With differential inputs, or when the COM pin is not tied to
ground, the A/D no longer converts just a single voltage
but rather the difference between two voltages. In these
cases, the voltage on the selected “+” input is still sampled
and held and therefore may be rapidly time varying just as
in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise
and ripple throughout the conversion time. Otherwise, the
19
LTC1283
U
W
U
UO
S I FOR ATIO
VERROR (MAX) = VPEAK × 2 × π × f(“–”) × 44/fACLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fACLK is the frequency of
the ACLK. In most cases VERROR will not be significant. For
a 60Hz signal on the “–” input to generate a 1/4LSB error
(0.61mV) with the converter running at ACLK = 1MHz, its
peak value would have to be 38mV.
5. Reference Inputs
The voltage between the reference inputs of the LTC1283
defines the voltage span of the A/D converter. The reference inputs look primarily like a 10k resistor but will have
transient capacitive switching currents due to the switchedcapacitor conversion technique (see Figure 14). During
each bit test of the conversion (every 4 ACLK cycles), a
capacitive current spike will be generated on the reference
pins by the A/D. These current spikes settle quickly and do
not cause a problem. However, if slow settling circuitry is
used to drive the reference inputs, care must be taken to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
REF+
14
ROUT
VREF
10k
TYP
REF –
13
LTC1283
EVERY 4 ACLK CYCLES
RON
5pF TO 30pF
show examples of both adequate and poor settling.
Using a slower ACLK will allow more time for the reference to settle. However, even at the maximum ACLK rate
of 1MHz most references and op amps can be made to
settle within the 4µs bit time.
3. It is recommended that the REF – input be tied directly to
the analog ground plane. If REF – is biased at a voltage
other than ground, the voltage must not change during a
conversion cycle. This voltage must also be free of noise
and ripple with respect to analog ground.
VERTICAL: 0.5mV/DIV
differencing operation may not be performed accurately.
The conversion time is 44 ACLK cycles. Therefore, a
change in the “–” input voltage during this interval can
cause conversion errors. For a sinusoidal voltage on the
“–” input this error would be:
HORIZONTAL: 1µs/DIV
Figure 15. Adequate Reference Settling
VERTICAL: 0.5mV/DIV
APPLICATI
LTC1283 • F14
Figure 14. Reference Input Equivalent Circuit
When driving the reference inputs, three things should be
kept in mind:
1. The source resistance (ROUT) driving the reference
inputs should be low (less than 1Ω) to prevent DC drops
caused by the 300µA maximum reference current (IREF).
2. Transients on the reference inputs caused by the capacitive switching currents must settle completely during
each bit test (each 4 ACLK cycles). Figures 15 and 16
20
HORIZONTAL: 1µs/DIV
Figure 16. Poor Reference Settling Can Cause A/D Errors
6. Reduced Reference Operation
The effective resolution to the LTC1283 can be increased by
reducing the input span of the converter. The LTC1283
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Linearity and Gain
Error vs Reference Voltage). However, care must be taken
LTC1283
U
W
U
UO
APPLICATI
S I FOR ATIO
when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. The following factors
must be considered when operating at low VREF values.
1. Conversion speed (ACLK frequency)
2. Offset
3. Noise
Conversion Speed with Reduced VREF
With reduced reference voltages, the LSB step size is
reduced and the LTC1283 internal comparator overdrive
is reduced. With less overdrive, more time is required to
perform a conversion. Therefore, the maximum ACLK
frequency should be reduced when low values of VREF are
used. This is shown in the typical curve of Maximum
Conversion Clock Rate vs Reference Voltage.
Offset with Reduced VREF
The offset of the LTC1283 has a larger effect on the output
code when the A/D is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The typical curve of Unadjusted Offset Error vs
Reference Voltage shows how offset in LSBs is related to
reference voltage for a typical value of VOS. For example,
a VOS of 0.5mV which is 0.2LSB with a 2.5V reference
becomes 0.5LSB with a 1V reference and 2.5LSBs with a
0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input to the LTC1283.
Noise with Reduced VREF
The total input referred noise of the LTC1283 can be
reduced to approximately 200µV peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This noise
is insignificant with a 2.5V reference but will become a
larger fraction of an LSB as the size of the LSB is reduced.
The typical curve of Noise Error vs Reference Voltage
shows the LSB contribution of this 200µV of noise.
For operation with a 2.5V reference, the 200µV noise is only
0.08LSB peak-to-peak. In this case, the LTC1283 noise will
contribute virtually no uncertainty to the output code.
However, for reduced references, the noise may become a
significant fraction of an LSB and cause undesirable jitter in
the output code. For example, with a 1V reference, this same
200µV noise is 0.2LSB peak-to-peak. This will reduce the
range of input voltages over which a stable output code can
be achieved by 0.2LSB. If the reference is further reduced to
200mV, the 200µV noise becomes equal to one LSB and a
stable code may be difficult to achieve. In this case averaging readings may be necessary.
This noise data was taken in a very clean setup. Any setup
induced noise (noise or ripple on VCC, VREF, VIN or V –) will
add to the internal noise. The lower the reference voltage to
be used, the more critical it becomes to have a clean, noisefree setup.
A “Quick Look” Circuit for the LTC1283
Users can get a quick look at the function and timing of the
LTC1283 by using the following simple circuit. REF + and
DIN are tied to VCC selecting a 3V input span, CH7 as a
single-ended input, unipolar mode, MSB-first format and
16-bit word length. ACLK and SCLK are tied together and
driven by an external clock. CS is driven at 1/64 the clock
rate by the CD4520 and DOUT outputs the data. All other
pins are tied to a ground plane. The output data from the
DOUT pin can be viewed on an oscilloscope which is set up
to trigger on the falling edge of CS.
Scope Trace of LTC1283 “Quick Look” Circuit
Showing A/D Output of 0101010101 (155HEX)
CS
DOUT
DEGLITCHER
TIME
MSB
(B9)
LSB
(B0)
FILLS
ZEROES
VERTICAL: 1V/DIV, HORIZONTAL: 5µs/DIV
21
LTC1283
UO
TYPICAL APPLICATI
S
A “Quick Look” Circuit for the LTC1283
3V
4.7µF
f/64
CHO
VCC
CH1
ACLK
CH2
SCLK
VDD
EN
DIN
Q1
CH4
DOUT
Q2
CS
Q3
Q2
CH6
REF +
Q4
Q1
CH7
REF –
RESET
COM
V–
LTC1283
0.1µF
RESET
CH3
CH5
VIN
CLK
f
Q4
CD4520
VSS
Q3
LTC1283 • TA03
EN
CLK
AGND
{
DGND
CLOCK IN
500kHz MAX
TO
OSCILLOSCOPE
SNEAK-A-BITTM
The LTC1283’s unique ability to software select the polarity of the differential inputs and the output word length is
used to achieve one more bit of resolution. Using the
circuit below with two conversions and some software, a
2’s complement 10-bit + sign word is returned to memory
inside the MPU. The MC68HC05C4 was chosen as an
example; however, any processor could be used.
SNEAK-A-BIT Code
SNEAK-A-BIT Circuit
10µF
SIGN
LOCATION $77 B10 B9
CHO
VCC
CH1
ACLK
CH2
SCLK
CH3
DIN
MOSI
CH4
DOUT
MISO
CH5
VIN
–3V TO 3V
LTC1283
MC68HC05C4
SCK
REF +
CH7
REF –
COM
V–
B7
B6
B5
B4
B3
B2
B1
B0
FILLED WITH 0’s
LTC1283 • TA07
DIN Words for LTC1283
MSBF
LTC1283 • TA05
MUX ADDR.
UNI
WORD
LENGTH
(ODD/SIGN)
AGND
0.1µF
–3V
SNEAK-A-BIT is a trademark of Linear Technology Corp.
B8
LSB
LOCATION $87
CO
CS
CH6
DGND
22
DOUT from LTC1283 in MC68HC05C4
1MHz
CLOCK
3V
OTHER
CHANNELS
OR
SNEAK-A-BIT
INPUTS
Two 10-bit unipolar conversions are performed: the first
over a 0V to 3V span and the second over a 0V to – 3V span
(by reversing the polarity of the inputs). The sign of the
input is determined by which of the two spans contain it.
Then the resulting number (ranging from – 1023 to 1023
decimal) is converted to 2’s complement notation and
stored in RAM.
DIN 1
0
0
1
1
1
1
1
1
DIN 2
0
1
1
1
1
1
1
1
DIN 3
0
0
1
1
1
1
1
1
LTC1283 • TA08
LTC1283
UO
TYPICAL APPLICATI
S
Sneak-A-Bit Code for the LTC1283 Using the MC68HC05C4
MNEMONIC
LDA
STA
LDA
STA
DESCRIPTION
#$50
$0A
#$FF
$06
CONFIGURATION DATA FOR SPCR
LOAD CONFIGURATION DATA INTO $0A
CONFIGURATION DATA FOR PORT C DDR
LOAD CONFIGURATION DATA INTO PORT
C DDR
BSET 0, $02
MAKE SURE CS IS HIGH
JSR READ –/+ DUMMY READ CONFIGURES LTC1283 FOR
NEXT READ
JSR READ +/– READ CH6 WITH RESPECT TO CH7
JSR READ –/+ READ CH7 WITH RESPECT TO CH6
JSR CHK SIGN DETERMINES WHICH READING HAS VALID
DATA, CONVERTS TO 2’s COMPLEMENT
AND STORES IN RAM
READ – / +: LDA #$3F
LOAD DIN WORD FOR LTC1283 INTO ACC
JSR TRANSFER READ LTC1283 ROUTINE
LDA $60
LOAD MSBs FROM LTC1283 INTO ACC
STA $71
STORE MSBs IN $71
LDA $61
LOAD LSBs FROM LTC1283 INTO ACC
STA $72
STORE LSBs IN $72
RTS
RETURN
Read + / –: LDA #$7F
LOAD DIN WORD FOR LTC1283 INTO ACC
JSR TRANSFER READ LTC1283 ROUTINE
LDA $60
LOAD MSBs FROM LTC1283 INTO ACC
STA $73
STORE MSBs IN $73
LDA $61
LOAD LSBs FROM LTC1283 INTO ACC
STA $74
STORE LSBs IN $74
RTS
RETURN
TRANSFER: BCLR 0, $02
CS GOES LOW
STA $0C
LOAD DIN INTO SPI. START TRANSFER
LOOP 1:
TST $0B
TEST STATUS OF SPIF
BPL LOOP 1
LOOP TO PREVIOUS INSTRUCTION IF NOT
DONE
LDA $0C
LOAD CONTENTS OF SPI DATA REG. INTO
ACC
STA $0C
START NEXT CYCLE
STA $60
STORE MSBs IN $60
MNEMONIC
LOOP 2:
TST
BPL
$0B
LOOP 2
BSET 0, $02
LDA $0C
STA
RTS
CHK SIGN: LDA
ORA
BEQ
CLC
ROR
ROR
LDA
STA
LDA
STA
BRA
MINUS:
CLC
ROR
ROR
COM
COM
LDA
ADD
STA
CLRA
ADC
END:
STA
STA
LDA
STA
RTS
$61
$73
$74
MINUS
$73
$74
$73
$77
$74
$87
END
$71
$72
$71
$72
$72
#$01
$72
$71
$71
$77
$72
$87
DESCRIPTION
TEST STATUS OF SPIF
LOOP TO PREVIOUS INSTRUCTION IF NOT
DONE
CS GOES HIGH
LOAD CONTENTS OF SPI DATA REG. INTO
ACC
STORE LSBs IN $61
RETURN
LOAD MSBs OF +/– READ INTO ACC
OR ACC (MSBs) WITH LSBs OF +/– read
IF RESULT IS 0 GOTO MINUS
CLEAR CARRY
ROTATE RIGHT $73 THROUGH CARRY
ROTATE RIGHT $74 THROUGH CARRY
LOAD MSBs OF +/– READ INTO ACC
STORE MSBs IN RAM LOCATION $77
LOAD LSBs OF +/– READ INTO ACC
STORE LSBs IN RAM LOCATION $87
GOTO END OF ROUTINE
CLEAR CARRY
SHIFT MSBs OF –/+ READ RIGHT
SHIFT LSBs –/+ READ RIGHT
1’s COMPLEMENT OF MSBs
1’s COMPLEMENT OF LSBs
LOAD LSBs INTO ACC
ADD 1 TO LSBs
STORE ACC IN $72
CLEAR ACC
ADD WITH CARRY TO MSBs. RESULT IN
ACC
STORE ACC IN $71
STORE MSBs IN RAM LOCATION $77
LOAD LSBs IN ACC
STORE LSBs IN RAM LOCATION $87
RETURN
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
23
LTC1283
U
PACKAGE DESCRIPTIO
Dimensions are in inches (millimeters) unless otherwise noted.
N Package
20-Lead Plastic DIP
1.040
(26.416)
MAX
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
0.260 ± 0.010
(6.604 ± 0.254)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
0.015
(0.381)
MIN
0.065
(1.651)
TYP
+0.025
0.325 –0.015
8.255
+0.635
–0.381
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
)
0.125
(3.175)
MIN
0.065 ± 0.015
(1.651 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N20 0592
S Package
20-Lead Plastic SOL
0.496 – 0.512
(12.598 – 13.005)
20
19
18
17
16
15
14
13
12
11
0.394 – 0.419
(10.007 – 10.643)
SEE NOTE
1
2
3
4
5
6
7
8
9
10
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.037 – 0.045
(0.940 – 1.143)
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
SEE NOTE
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
0.004 – 0.012
(0.102 – 0.305)
SOL20 0392
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
24
Linear Technology Corporation
LT/GP 0294 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1994