LTC1655 16-Bit Rail-to-Rail Micropower DAC in SO-8 Package U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1655 is a rail-to-rail voltage output, 16-bit digital-to-analog converter (DAC) in an SO-8 package. It includes an output buffer and a reference. The 3-wire serial interface is compatible with SPI/QSPI and MICROWIRETM protocols. The CLK input has a Schmitt trigger that allows direct optocoupler interface. 16-Bit Monotonicity Over Temperature Deglitched Rail-to-Rail Voltage Output SO-8 Package 5V Single Supply Operation ICC(TYP): 600µA Internal Reference Maximum DNL Error: 1LSB Power-On Reset 3-Wire Cascadable Serial Interface Low Cost The LTC1655 has an onboard 2.048V reference that can be overdriven to a higher voltage. The output swings from 0V to 4.096V when using the internal reference. The typical power dissipation is 3.0mW on a single 5V supply. U APPLICATIO S ■ ■ ■ ■ The LTC1655 is pin compatible with Linear Technology’s 12-bit VOUT DAC family, allowing an easy upgrade path. It is the only buffered 16-bit DAC in an SO-8 package and it includes an onboard reference for stand alone performance. Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. U TYPICAL APPLICATIO Functional Block Diagram: 16-Bit Rail-to-Rail DAC 4.5V TO 5.5V 2.048V 8 VCC 3 CS/LD 1.0 REF 0.8 16-BIT SHIFT REG AND DAC LATCH 0.6 16 16-BIT DAC + – VOUT 7 RAIL-TO-RAIL VOLTAGE OUTPUT (0V TO 4.096V) 4 DOUT TO OTHER DACS DNL ERROR (LSB) µP 6 REF 2 DIN 1 CLK Differential Nonlinearity vs Input Code 0.4 0.2 0 – 0.2 – 0.4 – 0.6 – 0.8 POWER-ON RESET GND 5 – 1.0 1655 TA01 0 16384 32768 CODE 49152 65535 1655 TA02 1 LTC1655 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO (Note 1) VCC to GND .............................................. – 0.5V to 7.5V TTL Input Voltage .................................... – 0.5V to 7.5V VOUT, REF ....................................... – 0.5V to VCC + 0.5V Maximum Junction Temperature ......................... 125°C Operating Temperature Range LTC1655C .............................................. 0°C to 70°C LTC1655I........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW 8 VCC DIN 2 7 VOUT CS/LD 3 6 REF DOUT 4 5 GND CLK 1 N8 PACKAGE 8-LEAD PDIP S8 PACKAGE 8-LEAD PLASTIC SO LTC1655CN8 LTC1655IN8 LTC1655CS8 LTC1655IS8 S8 PART MARKING TJMAX = 125°C, θJA = 100°C/W (N8) TJMAX = 125°C, θJA = 150°C/W (S8) 1655 1655I Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded, REF unloaded, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC Resolution ● 16 Bits Monotonicity ● 16 Bits DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) ● ±0.3 ±1.0 LSB INL Integral Nonlinearity REF = 2.2V (External) (Note 2) ● ±8 ±20 LSB ZSE Zero Scale Error 3 mV VOS Offset Error VOSTC Offset Error Tempco Gain Error ● Measured at Code 200, REF = 2.2V (External) 0 ±0.5 ● ±3 ±5 REF = 2.2V (External) ±5 ● Gain Error Drift mV µV/°C ±16 0.5 LSB ppm/°C Power Supply VCC Positive Supply Voltage For Specified Performance ● ICC Supply Current 4.5V ≤ VCC ≤ 5.5V (Note 4) ● Short-Circuit Current Low VOUT Shorted to GND Short-Circuit Current High Output Impedance to GND Output Line Regulation 4.5 5.5 V 600 1200 µA ● 70 120 mA VOUT Shorted to VCC ● 80 140 mA Input Code = 0 ● 40 120 Ω Input Code = 65535, VCC = 4.5V to 5.5V, with Internal Reference ● ±3 mV/V Voltage Output Slew Rate (Note 3) ● Voltage Output Settling Time (Note 3) to 0.0015% (16-Bit Settling Time) (Note 3) to 0.012% (13-Bit Settling Time) Op Amp DC Performance AC Performance Digital Feedthrough Midscale Glitch Impulse 2 DAC Switch Between 8000 and 7FFF ±0.3 ±0.7 V/µs 20 10 µs µs 0.3 nV -s 12 nV-s LTC1655 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded, REF unloaded, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital I/O VIH Digital Input High Voltage ● 2.4 V VIL Digital Input Low Voltage ● VOH Digital Output High Voltage IOUT = – 1mA, DOUT Only ● VOL Digital Output Low Voltage IOUT = 1mA, DOUT Only ● 0.4 V ILEAK Digital Input Leakage VIN = GND to VCC ● ±10 µA CIN Digital Input Capacitance (Note 6) 10 pF t1 DIN Valid to CLK Setup VCC = 5V ● t2 DIN Valid to CLK Hold VCC = 5V ● 0 ns t3 CLK High Time VCC = 5V (Note 6) ● 40 ns t4 CLK Low Time VCC = 5V (Note 6) ● 40 ns t5 CS/LD Pulse Width VCC = 5V (Note 6) ● 50 ns t6 LSB CLK to CS/LD VCC = 5V (Note 6) ● 40 ns t7 CS/LD Low to CLK VCC = 5V (Note 6) ● 20 ns t8 DOUT Output Delay VCC = 5V, CLOAD = 15pF ● 0 t9 CLK Low to CS/LD Low VCC = 5V (Note 6) ● 20 ● 2.036 0.8 V VCC – 1 V Switching 40 ns 120 ns ns Reference Output Reference Output Voltage Reference Input Range (Notes 5, 6) Reference Output Tempco Reference Input Resistance 2.048 2.2 2.060 V VCC /2 V 5 REF Overdriven to 2.2V Reference Short-Circuit Current ● ● 8.5 ppm/°C 13 40 kΩ 100 mA Reference Output Line Regulation VCC = 4.5V to 5.5V ● ±1.5 mV/V Reference Load Regulation IOUT = 100µA ● 0.5 mV Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity is defined from code 128 to code 65535 (full scale). See Applications Information. Note 3: DAC switched between all 1s and code 400. Note 4: Digital inputs at 0V or VCC. Note 5: Reference can be overdriven (see Applications Information). Note 6: Guaranteed by design. Not subject to test. 3 LTC1655 U W TYPICAL PERFORMANCE CHARACTERISTICS Minimum Supply Headroom for Full Output Swing vs Load Current Integral Nonlinearity 1.0 5 0.8 4 INTEGRAL NONLINEARITY (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 1.2 2 1 0 –1 –2 –3 –0.8 125°C 0.6 25°C 0.4 –55°C 0.2 –5 0 16,384 49,152 32,768 DIGITAL INPUT CODE 65,535 16,384 49,152 32,768 DIGITAL INPUT CODE 0 1655 G01 0 65,535 0 10 5 LOAD CURRENT (mA) 1655 G02 Minimum Output Voltage vs Output Sink Current 15 1655 F03 Full-Scale Voltage vs Temperature Offset vs Temperature 4.10 1.0 1.0 CODE: ALL 0’s 0.8 0.6 125°C 0.4 25°C –55°C 0.6 0.4 4.09 OFFSET (mV) 0.8 FULL-SCALE VOLTAGE (V) OUTPUT PULL-DOWN VOLTAGE (V) 0.8 –4 –1.0 4.08 0.2 0 –0.2 –0.4 –0.6 0.2 –0.8 0 0 10 5 OUTPUT SINK CURRENT (mA) 15 4.07 –55 –25 95 5 35 65 TEMPERATURE (°C) 125 Supply Current vs Logic Input Voltage –10 80 35 TEMPERATURE (°C) 700 3.0 680 SUPPLY CURRENT (µA) 2.6 2.2 1.8 1.4 1.0 660 VCC = 5.5V 640 620 600 0.6 0.2 0 1 3 4 2 LOGIC INPUT VOLTAGE (V) 5 1655 G07 580 –55 –35 –15 125 1655 G06 Supply Current vs Temperature 3.4 SUPPLY CURRENT (mA) –1.0 –55 1655 G05 1655 F04 4 ∆VOUT < 1LSB VOUT = 4.096V CODE: ALL 1’s 1.0 3 VCC – VOUT (V) DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity VCC = 5V VCC = 4.5V 5 25 45 65 85 105 125 TEMPERATURE (°C) 1655 G08 LTC1655 U U U PIN FUNCTIONS CLK (Pin 1): The TTL Level Input for the Serial Interface Clock. GND (Pin 5): Ground. REF (Pin 6): Reference. Output of the internal reference is 2.048V. There is a gain of two from this pin to the output. The reference can be overdriven from 2.2V to VCC/2. When tied to VCC/2, the output will swing from GND to VCC. The output can only swing to within its offset specification of VCC (see Applications Information). DIN (Pin 2): The TTL Level Input for the Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock and is loaded MSB first. The LTC1655 requires a 16-bit word. CS/LD (Pin 3): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. VOUT (Pin 7): Deglitched Rail-to-Rail Voltage Output. VOUT clears to 0V on power-up. VCC (Pin 8): Positive Supply Input. 4.5V ≤ VCC ≤ 5.5V. Requires a bypass capacitor to ground. DOUT (Pin 4): Output of the Shift Register. Becomes valid on the rising edge of the serial clock and swings from GND to VCC. WU W TI I G DIAGRA t1 t9 t2 t7 CLK DIN 1 D15 MSB 2 D14 t6 t3 t4 15 3 D13 D1 16 D0 LSB t5 CS/LD t8 DOUT D15 PREVIOUS WORD D14 PREVIOUS WORD D13 PREVIOUS WORD D0 PREVIOUS WORD D15 CURRENT WORD 1655 TD 5 LTC1655 U U DEFI ITIO S Differential Nonlinearity (DNL): The difference between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (∆VOUT – LSB)/LSB Where ∆VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Gain Error (GE): The difference between the full-scale output of a DAC from its ideal full-scale value after offset error has been adjusted. Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code that guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT – VOS – (VFS – VOS)(code/65535)]/LSB Where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = 2VREF/65536 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero. U OPERATIO Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The input word must be 16 bits wide. the chips, then the CS/LD signal is pulled high to update all of them simultaneously. The shift register and DAC register are cleared to all 0s on power-up. Voltage Output The buffered output of the 16-bit shift register is available on the DOUT pin which swings from GND to VCC. The LTC1655 rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 400mV of the positive supply voltage or ground. The output stage is equipped with a deglitcher that gives a midscale glitch of 12nV-s. At power-up, output stage clears to 0V. Multiple LTC1655s may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip while the clock and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40Ω when driving a load to the rails. The output can drive 1000pF without going into oscillation. 6 LTC1655 U W U U APPLICATIONS INFORMATION Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 1b. error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 1c. No full-scale limiting can occur if VREF is less than (VCC – FSE)/2. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Similarly, limiting can occur near full scale when the REF pin is tied to VCC /2. If VREF = VCC /2 and the DAC full-scale VCC VREF = VCC /2 POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VCC VREF = VCC /2 OUTPUT VOLTAGE 0 32768 INPUT CODE (a) 65535 OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1655 F01 Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC /2 7 LTC1655 U TYPICAL APPLICATIONS This circuit shows how to use an LTC1655 to make an optoisolated digitally controlled 4mA to 20mA process controller. The controller circuitry, including the optoisolation, is powered by the loop voltage that can have a wide range of 6V to 30V. The 2.048V reference output of the LTC1655 is used for the 4mA offset current and VOUT is used for the digitally controlled 0mA to 16mA current. RS is a sense resistor and the op amp modulates the transistor Q1 to provide the 4mA to 20mA current through this resistor. The potentiometers allow for offset and fullscale adjustment. The control circuitry dissipates well under the 4mA budget at zero scale. An Isolated 4mA to 20mA Process Controller VLOOP 6V TO 30V LT ®1121-5 IN OUT 1µF CLK FROM OPTOISOLATED INPUTS VCC DIN VREF LTC1655 VOUT 150k 1% 20k 75k 1% 5k + LT®1077 CS/LD 3k CLK DIN CS/LD 8 500Ω 10k 4N28 Q1 2N3440 – RS 10Ω 5V OPTOISOLATORS 1k IOUT CLK DIN CS/LD 1655 TA03 LTC1655 U TYPICAL APPLICATIONS This circuit shows how to make a bipolar output 16-bit DAC with a wide output swing using an LTC1655 and an LT1077. R1 and R2 resistively divide down the LTC1655 output and an offset is summed in using the LTC1655 onboard 2.048V reference and R3 and R4. R5 ensures that the onboard reference is always sourcing current and never has to sink any current even when VOUT is at full scale. The LT1077 output will have a wide bipolar output swing of – 4.096V to 4.096V as shown in the figure below. With this output swing 1LSB = 125µV. A Wide Swing, Bipolar Output 16-Bit DAC 5V 0.1µF VCC CLK µP DIN CS/LD VOUT LTC1655 GND R1 100k 1% VREF 5V + R2 200k 1% TRANSFER CURVE 4.096 VOUT 0 32768 65535 R3 100k 1% DIN LT1077 VOUT: (2)(DIN)(4.096) – 4.096V 65536 – R4 – 5V 200k 1% 1655 TA05 R5 100k 1% – 4.096 9 LTC1655 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.400* (10.160) MAX 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 10 0.130 ± 0.005 (3.302 ± 0.127) 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 ± 0.003 (0.457 ± 0.076) N8 1197 LTC1655 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 0996 11 LTC1655 U TYPICAL APPLICATION This circuit shows a digitally programmable current source from an external voltage source using an external op amp, an LT1077 and an NPN transistor (2N3440). Any digital word from 0 to 65535 is loaded into the LTC1655 and its output correspondingly swings from 0V to 4.096V. In the configuration shown, R1, R2 resistively divide down the LTC1655 output voltage. This divided voltage will be forced across the resistor RA. If RA is chosen to be 205Ω, the output current will range from 0mA at zero scale to 10mA at full scale. The minimum voltage for VS is determined by the load resistor RL and Q1’s VCESAT voltage. With a load resistor of 50Ω, the voltage source can be as low as 3.3V. Digitally Programmable Current Source 5V VS + 3.3V TO 100V FOR RL ≤ 50Ω 0.1µF VCC CLK µP DIN RL LTC1655 VOUT CS/LD GND R1 100k 1% + LT1077 – R2 100k 1% Q1 2N3440 (DIN)(4.096) 1 • (65536)(RA) 2 ≈ 0mA TO 10mA IOUT = RA 205Ω 1% 1655 TA04 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1257 Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446/ LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1448 Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450/ LTC1450L Single 12-Bit VOUT DACs with Parallel Interface LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1451 Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin 5V, Low Power Complete VOUT DAC in SO-8 Package LTC1452 Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC1453 Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454/ LTC1454L Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458/ LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1650 Single 16-Bit VOUT Industrial DAC in 16-Pin SO, VCC = ±5V DAC, Output Swing ±4.5V Low Power, Deglitched, 4-Quadrant Mulitplying VOUT LTC1658 Single Rail-to-Rail 14-Bit VOUT DAC in 8-Pin MSOP, VCC = 2.7V to 5.5V Low Power, Multiplying VOUT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1659 Single Rail-to-Rail 12-Bit VOUT DAC in 8-Pin MSOP, VCC = 2.7V to 5.5V Low Power, Multiplying VOUT DAC in MS8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC 12 Linear Technology Corporation 1655f LT/TP 0399 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998