LINER LTC2152-14

Electrical Specifications Subject to Change
LTC2152-14/
LTC2151-14/LTC2150-14
14-Bit 250Msps/
210Msps/170Msps ADCs
FEATURES
DESCRIPTION
n
n
n
n
n
n
n
n
n
n
n
The LTC®2152-14/LTC2151-14/LTC2150-14 are 250Msps/
210Msps/170Msps 14-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 70dB SNR and 90dB
spurious free dynamic range (SFDR). The latency is only
five clock cycles.
n
70dB SNR
90dB SFDR
Low Power: 338mW/316mW/290mW Total
Single 1.8V Supply
DDR LVDS Outputs
Easy-to-Drive 1.5VP-P Input Range
1.25GHz Full Power Bandwidth S/H
Optional Clock Duty Cycle Stabilizer
Low Power Sleep and Nap Modes
Serial SPI Port for Configuration
Pin Compatible with 12-Bit Versions
40-Pin (6mm × 6mm) QFN Package
DC specs include ±0.85LSB INL (typ), ±0.25LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 1.82LSBRMS.
The digital outputs are Double-Data Rate (DDR) LVDS.
The ENC+ and ENC– inputs can be driven differentially with
a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional
clock duty cycle stabilizer allows high performance at full
speed for a wide range of clock duty cycles.
APPLICATIONS
Communications
Cellular Basestations
n Software Defined Radios
n Medical Imaging
n High Definition Video
n Testing and Measurement Instruments
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
VDD
0
OVDD
CLOCK
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
D12_13
•
•
•
D0_1
OGND
CLOCK/DUTY
CYCLE
CONTROL
–20
DDR
LVDS
AMPLITUDE (dBFS)
ANALOG
INPUT
14-BIT
PIPELINED
ADC
–40
–60
–80
–100
21521014 TA01a
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21521014 TA01b
21521014p
1
LTC2152-14/
LTC2151-14/LTC2150-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
D10_11–
D10_11+
D12_13–
D12_13+
GND
SDO
SDI
SCK
CS
PAR/SER
TOP VIEW
40 39 38 37 36 35 34 33 32 31
VDD 1
30 OVDD
VDD 2
29 D8_9+
GND 3
28 D8_9–
AIN+ 4
27 CLKOUT+
AIN– 5
26 CLKOUT –
GND
41
GND 6
25 D6_7+
SENSE 7
24 D6_7–
VREF 8
23 D4_5+
VCM 9
22 D4_5–
GND 10
21 OGND
OVDD
D2_3+
D2_3–
D0_1+
D0_1–
OF +
OF –
GND
ENC–
11 12 13 14 15 16 17 18 19 20
ENC+
Supply Voltage
VDD, OVDD................................................. –0.3V to 2V
Analog Input Voltage
AINA/B+, AINA/B –, PAR/SER,
SENSE (Note 3)......................... –0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC– (Note 3)................. –0.3V to (VDD + 3.9V)
CS, SDI, SCK (Note 4)............... –0.3V to (VDD + 0.3V)
SDO (Note 4).............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2152C, LTC2151C, LTC2150C.............. 0°C to 70°C
LTC2152I, LTC2151I, LTC2150I.............–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, θJA = 33°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2152CUP-14#PBF
LTC2152CUP-14#TRPBF
LTC2152-14
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2152IUP-14#PBF
LTC2152IUP-14#TRPBF
LTC2152-14
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
LTC2151CUP-14#PBF
LTC2151CUP-14#TRPBF
LTC2151-14
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2151IUP-14#PBF
LTC2151IUP-14#TRPBF
LTC2151-14
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
LTC2150CUP-14#PBF
LTC2150CUP-14#TRPBF
LTC2150-14
40-Lead (6mm × 6mm) Plastic QFN
0°C to 70°C
LTC2150IUP-14#PBF
LTC2150IUP-14#TRPBF
LTC2150-14
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
21521014p
2
LTC2152-14/
LTC2151-14/LTC2150-14
CONVERTER
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
l
Integral Linearity Error
Differential Analog Input (Note 6) l
Differential Linearity Error
Differential Analog Input
Offset Error
Gain Error
LTC2152-14
TYP MAX
MIN
14
LTC2151-14
TYP MAX
LTC2150-14
MIN
TYP MAX
14
UNITS
14
Bits
–3.7
±0.85
3.7
–3.8
±1
3.8
–3.8
±1
3.8
LSB
l
–1
±0.5
1
–1
±0.5
1
–1
±0.5
1
LSB
(Note 7)
l
–15
±5
15
–15
±5
15
–15
±3
15
External Reference
l
Offset Drift
mV
±1
±1
±1
%FS
±20
±20
±20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Transition Noise
External Reference
1.85
1.8
1.8
LSBRMS
ANALOG
INPUT
The
l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
l
VCM – 20mV
VCM
VCM + 20mV
V
External Reference Mode
l
1.200
1.250
1.300
V
Analog Input Leakage Current
0 < AIN+, AIN– < VDD
l
–1
1
µA
SENSE Input Leakage Current
1.2V < SENSE < 1.3V
l
–1
1
µA
IIN3
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–1
1
µA
tAP
Sample-and-Hold Acquisition Delay Time
1
tJITTER
Sample-and-Hold Acquisition Delay Jitter
0.15
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
VSENSE
External Reference Mode
IIN1
IIN2
MAX
UNITS
1.5
VP-P
ns
psRMS
75
dB
1250
MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
70MHz Input
140MHz Input
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
MIN
l
l
l
l
LTC2152-14
TYP MAX
TBD
70
69.7
69
TBD
90
85
80
TBD
95
95
85
TBD
69.9
69.4
68.8
MIN
LTC2151-14
TYP MAX
TBD
70
69.7
69
TBD
90
85
80
TBD
95
95
85
TBD
69.9
69.4
68.8
LTC2150-14
MIN
TYP MAX
UNITS
70
69.7
69
dBFS
dBFS
dBFS
90
85
80
dBFS
dBFS
dBFS
TBD
98
95
85
dBFS
dBFS
dBFS
TBD
69.9
69.4
68.8
dBFS
dBFS
dBFS
TBD
TBD
21521014p
3
LTC2152-14/
LTC2151-14/LTC2150-14
INTERNAL
REFERENCE CHARACTERISTICS l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.444 •
VDD – 15mV
0.444 •
VDD
0.444 •
VDD + 15mV
VCM Output Temperature Drift
UNITS
V
±37
VCM Output Resistance
–1mA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
ppm/°C
4
1.225
Ω
1.250
VREF Output Temperature Drift
1.275
V
±30
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
ppm/°C
7
Ω
0.6
mV/V
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
VDD
Analog Supply Voltage
(Note 9)
l
1.7
OVDD
Output Supply Voltage
LVDS Mode (Note 9)
l
1.7
IVDD
Analog Supply Current
IOVDD
Digital Supply Current
PDISS
Power Dissipation
MIN
LTC2152-14
TYP MAX
MIN
1.8
1.9
1.7
1.8
1.9
1.7
LTC2151-14
TYP MAX
LTC2150-14
MIN
TYP MAX
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.8
1.9
UNITS
V
V
l
160
149
135
mA
1.75mA LVDS Mode
3.5mA LVDS Mode
l
28
47
27
45
26
44
mA
mA
1.75mA LVDS Mode
3.5mA LVDS Mode
l
338
372
316
249
290
322
mW
mW
PSLEEP
Nap Mode Power
Clocked at fS(MAX)
113.5
106.2
97.2
mW
PNAP
Sleep Mode Power
Clocked at fS(MAX)
<2
<2
<2
mW
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1
1.9
V
1.5
V
V
1.9
V
ENCODE INPUTS (ENC+, ENC– )
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
l
0.2
1.2
VIN
Input Voltage Range
ENC+, ENC– to GND
RIN
Input Resistance
(See Figure 2)
10
kΩ
CIN
Input Capacitance
(Note 8)
2
pF
DIGITAL INPUTS (CS, SDI, SCK)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 1.8V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
µA
3
pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
200
l
–10
Ω
10
4
µA
pF
21521014p
4
LTC2152-14/
LTC2151-14/LTC2150-14
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
DIGITAL DATA OUTPUTS
CONDITIONS
VOD
Differential Output Voltage
VOS
Common Mode Output Voltage
RTERM
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OVDD = 1.8V
l
l
l
l
MIN
TYP
MAX
UNITS
247
125
1.125
1.125
350
175
1.250
1.250
100
454
250
1.375
1.375
mV
mV
V
V
Ω
TIMING
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
fS
tL
PARAMETER
Sampling Frequency
ENC Low Time (Note 8)
tH
ENC High Time (Note 8)
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
l
l
l
MIN
10
1.9
1.9
1.9
1.9
LTC2152-14
TYP MAX
250
2
50
2
50
2
50
2
50
MIN
10
2.26
1.5
2.26
1.5
LTC2151-14
TYP MAX
210
2.38
50
2.38
50
2.38
50
2.38
50
LTC2150-14
MIN
TYP MAX
10
170
2.79 2.94
50
1.5
2.94
50
2.79 2.94
50
1.5
2.94
50
UNITS
MHz
ns
ns
ns
ns
DIGITAL DATA OUTPUTS
LTC215X-14
MIN
SYMBOL
tD
PARAMETER
ENC to Data Delay
CONDITIONS
CL = 5pF
l
tC
ENC to CLKOUT Delay
CL = 5pF
l
tSKEW
DATA to CLKOUT Skew
tD – tC
l
Pipeline Latency
TYP
MAX
1.7
2
2.3
ns
1.3
1.6
2
ns
0.3
0.4
0.55
ns
5
5
UNITS
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
CS to SCK Set-Up Time
tH
Write Mode, CSDO = 20pF
Readback Mode RPULLUP = 2k, CSDO = 20pF
l
40
250
5
ns
ns
ns
SCK to CS Hold Time
l
5
ns
tDS
SDI Set-Up Time
l
5
ns
tDH
SDI Hold Time
l
5
tDO
SCK Falling to SDO Valid
Readback Mode RPULLUP = 2k, CSDO = 20pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
l
ns
125
ns
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 250MHz (LTC2152),
210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential
ENC+/ENC– = 2VP-P sine wave, input range = 1.5VP-P with differential
drive, unless otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111
in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
21521014p
5
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-14: Integral Nonlinearity
(INL)
LTC2152-14: Differential Nonlinearity
(DNL)
LTC2152-14: 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
0
2.0
0.4
1.5
–20
0.5
0
–0.5
–1.0
0
–0.2
–60
–80
–0.4
0
4096
8192
12288
OUTPUT CODE
16384
0
4096
8192
12288
OUTPUT CODE
21521014 G01
16384
–120
LTC2152-14: 32K Point FFT,
fIN = 122MHz, –1dBFS, 250Msps
–20
–20
–40
–60
–80
–100
–100
–120
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
–80
0
20
40
60
80
100
FREQUENCY (MHz)
120
–120
0
20
40
60
80
100
FREQUENCY (MHz)
–40
–60
–80
120
–120
0
20
40
60
80
100
FREQUENCY (MHz)
21521014 G05
LTC2152-14: 32K Point FFT,
fIN = 229MHz, –1dBFS, 250Msps
0
0
–20
–20
–40
–60
–80
–100
120
21521014 G06
LTC2152-14: 32K Point FFT,
fIN = 381MHz, –1dBFS, 250Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
120
–100
21521014 G04
–120
40
60
80
100
FREQUENCY (MHz)
LTC2152-14: 32K Point FFT,
fIN = 171MHz, –1dBFS, 250Msps
0
–60
20
21521014 G03
0
–40
0
21521014 G02
LTC2152-14: 32K Point FFT,
fIN = 70MHz, –1dBFS, 250Msps
AMPLITUDE (dBFS)
–40
–100
–1.5
–2.0
0.2
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
–40
–60
–80
–100
0
20
40
60
80
100
FREQUENCY (MHz)
120
21521014 G07
–120
0
20
40
60
80
100
FREQUENCY (MHz)
120
21521014 G08
21521014p
6
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-14: 32K Point FFT, fIN =
907MHz, –1dBFS, 250Msps
LTC2152-14: 32K Point FFT, fIN =
571MHz, –1dBFS, 250MHz
0
0
–20
–20
–20
–40
–60
–80
–40
–60
–80
–100
–100
–120
AMPLITUDE (dBFS)
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
LTC2152-14: 32K Point FFT, fIN =
421MHz, –1dBFS, 250MHz
0
20
–120
40
60
80
100 120
INPUT FREQUENCY (MHz) 21521014 G09
LTC2152-14: 32K Point 2-Tone
FFT, fIN = 70.5MHz and 69.5MHz,
250Msps
–20
0
20
100 120
40
60
80
INPUT FREQUENCY (MHz) 21521014 G10
–120
4000
50
3500
45
IOVDD (mA)
COUNT
AMPLITUDE (dBFS)
2000
1500
40
60
80
100 120
INPUT FREQUENCY (MHz) 21521014 G12
0
8196
8200
8208
8204
OUTPUT CODE
35
30
LVDS CURRENT
1.75mA
8212
8216
15
0
50
100
150
200
SAMPLE RATE (Msps)
250
21521014 G14
215210 G13
LTC2152-14: SFDR vs Input
Level, fIN = 70MHz, 1.5V Range,
250Msps
170
120
160
100
SFDR (dBFS)
150
140
dBc
60
40
120
20
0
50
100
150
200
SAMPLE RATE (Msps)
250
21521014 G15
dBFS
80
130
110
LVDS CURRENT
3.5mA
20
LTC2152-14: IVDD vs Sample
Rate, 15MHz Sine Wave Input,
–1dBFS
IVDD (mA)
20
40
60
80
100 120
INPUT FREQUENCY (MHz) 21521014 G11
25
500
0
20
40
1000
–120
0
LTC2152-14: IOVDD vs Sample
Rate, 15MHz Sine Wave Input,
–1dBFS
2500
–100
–80
–100
3000
–40
–80
–60
LTC2152-14: Shorted Input
Histogram
0
–60
–40
0
–80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE (dBFS)
0
21521014 G16
21521014p
7
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2152-14: SFDR vs Input
Frequency, –1dBFS, 1.5V Range,
250Msps
LTC2152-14: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 250Msps
20
0
50
–10
dBc
–20
40
–30
30
–40
20
–50
80
70
SFDR (dBFS)
60
–50
–40 –30 –20
AMPLITUDE (dBFS)
–10
50
40
20
10
–70
–60
60
30
–60
10
0
90
10
dBFS
INPUT LEVEL (dBc)
SNR (dBFS)
70
0
0
21521014 G17
21521014 G18
LTC2152-14: SNR vs Input
Frequency, –1dBFS, 1.5V Range,
250Msps
LTC2152-14: Frequency Response
–0.5
75
–1.0
70
–1.5
FS AMPLITUDE (–1dB)
SNR (dBFS)
65
60
55
50
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
–5.5
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21521014 G19
–6.0
100
1000
INPUT FREQUENCY (MHz)
21521014 G20
21521014p
8
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2151-14: Integral Nonlinearity
INL
LTC2151-14: Differential Nonlinearity
DNL
LTC2151-14: 32K Point FFT,
fIN = 15MHz, –1dBFS, 210Msps
0
2.0
0.4
1.5
–20
0.5
0
–0.5
–1.0
0
4096
8192
12288
OUTPUT CODE
0
16384
4096
21521014 G21
LTC2151-14: 32K Point FFT,
fIN = 71MHz, –1dBFS, 210Msps
0
8192
12288
OUTPUT CODE
16384
–80
–120
–40
–60
–80
40
60
80
FREQUENCY (MHz)
100
–60
–80
–40
–60
–80
–100
0
20
21521014 G24
40
60
80
FREQUENCY (MHz)
LTC2151-14: 32K Point FFT,
fIN = 227MHz, –1dBFS, 210Msps
0
0
–20
–20
–40
–60
–80
–120
100
0
20
21521014 G25
40
60
80
FREQUENCY (MHz)
100
21521014 G26
LTC2151-14: 32K Point FFT,
fIN = 379MHz, –1dBFS, 210Msps
–40
–60
–80
–100
–100
–120
100
21521014 G23
–20
–40
–120
40
60
80
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
20
AMPLITUDE (dBFS)
0
20
LTC2151-14: 32K Point FFT,
fIN = 171MHz, –1dBFS, 210Msps
LTC2151-14: 32K Point FFT,
fIN = 101MHz, –1dBFS, 210Msps
–100
–100
0
21521014 G22
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–60
–0.4
–20
–120
–0.2
AMPLITUDE (dBFS)
0
0
–40
–100
–1.5
–2.0
0.2
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
0
20
40
60
80
FREQUENCY (MHz)
100
21521014 G27
–120
0
20
40
60
80
FREQUENCY (MHz)
100
21521014 G28
21521014p
9
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
0
0
–20
–20
AMPLITUDE (dBFS)
0
LTC2151-14: 32K Point FFT,
fIN = 907MHz, –1dBFS, 210Msps
LTC2151-14: 32K Point FFT,
fIN = 571MHz, –1dBFS, 210Msps
LTC2151-14: 32K Point FFT,
fIN = 417MHz, –1dBFS, 210Msps
–40
–60
–80
20
40
60
80
FREQUENCY (MHz)
–120
100
0
20
21521014 G29
LTC2151-14: 32K Point 2-Tone FFT,
fIN = 70.5 and 69.5MHz, 210Msps
–20
40
60
80
FREQUENCY (MHz)
100
–120
4000
50
3500
45
IOVDD (mA)
COUNT
AMPLITUDE (dBFS)
2000
1500
20
40
60
80
FREQUENCY (MHz)
100
0
8196
8200
8208
8204
OUTPUT CODE
21521014 G32
8212
30
LVDS CURRENT
1.75mA
8216
15
0
50
100
150
200
SAMPLE RATE (Msps)
250
21521014 G34
215210 G33
LTC2151-14: SFDR vs Input Level,
fIN = 71MHz, 1.5V Range, 210Msps
170
120
160
100
SFDR (dBFS)
150
IVDD (mA)
35
20
LTC2151-14: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
140
130
dBFS
80
60
dBc
40
120
110
100
21521014 G31
LVDS CURRENT
3.5mA
25
500
0
40
60
80
FREQUENCY (MHz)
40
1000
–120
20
LTC2151-14: IOVDD vs Sample
Rate, 15MHz Sine Wave Input,
–1dBFS
2500
–100
0
21521014 G30
3000
–40
–80
–80
LTC2151-14: Shorted Input
Histogram
0
–60
–60
–100
–100
0
–40
20
0
50
100
150
200
SAMPLE RATE (Msps)
250
21521014 G35
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE (dBFS)
0
21521014 G36
21521014p
10
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2151-14: SNR vs Input
Level, fIN = 71MHz, 1.5V Range,
210Msps
LTC2151-14: SFDR vs Input Level,
–1dBFS, 1.5V Range, 210Msps
20
0
50
–10
dBc
–20
40
–30
30
–40
20
–50
80
70
SFDR (dBFS)
60
–50
–40 –30 –20
AMPLITUDE (dBFS)
–10
50
40
20
10
–70
–60
60
30
–60
10
0
90
10
dBFS
INPUT LEVEL (dBc)
SNR (dBFS)
70
0
0
21521014 G37
21521014 G38
LTC2151-14: SNR vs Input Level,
–1dBFS, 1.5V Range, 210Msps
LTC2151-14: Frequency Response
–0.5
75
–1.0
70
–1.5
FS AMPLITUDE (–1dB)
SNR (dBFS)
65
60
55
50
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
–5.5
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21521014 G39
–6.0
100
1000
INPUT FREQUENCY (MHz)
21521014 G40
21521014p
11
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2150-14: Differential
Nonlinearity DNL
LTC2150-14: Integral Nonlinearity INL
0
2.0
0.4
1.5
–20
0.5
0
–0.5
–1.0
0.2
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
1.0
0
–0.2
–40
–60
–80
–100
–1.5
–2.0
LTC2150-14: 32K Point FFT,
fIN = 15MHz, –1dBFS, 170Msps
–0.4
0
4096
8192
12288
OUTPUT CODE
0
16384
0
4096
21521014 G41
8192
12288
OUTPUT CODE
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–60
–80
–100
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
30 40 50 60
FREQUENCY (MHz)
70
80
21521014 G43
LTC2150-14: 32K Point FFT,
fIN = 121MHz, –1dBFS, 170Msps
–40
–60
–80
–120
0
10
20
21521014 G44
0
0
–20
–20
–40
–60
–80
30 40 50 60
FREQUENCY (MHz)
70
80
21521014 G45
LTC2150-14: 32K Point FFT,
fIN = 225MHz, –1dBFS, 170Msps
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
20
–100
LTC2150-14: 32K Point FFT,
fIN = 176MHz, –1dBFS, 170Msps
–40
–60
–80
–100
–100
–120
10
–20
–40
–120
0
21521014 G42
LTC2150-14: 32K Point FFT,
fIN = 70MHz, –1dBFS, 170Msps
–20
–120
16384
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
21521014 G46
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
21521014 G47
21521014p
12
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
0
–60
–80
–100
0
–40
–60
–80
–100
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
0
10
20
21521014 G49
30 40 50 60
FREQUENCY (MHz)
70
80
21521014 G50
LTC2150-14: Shorted Input
Histogram
0
AMPLITUDE (dBFS)
–80
–80
–120
80
4000
3500
–20
–60
–60
LTC2150-14: 32K Point 2-Tone FFT,
fIN = 70.5 and 69.5MHz, 170Msps
LTC2150-14: 32K Point FFT,
fIN = 907MHz, –1dBFS, 170Msps
–40
–40
–100
21521014 G48
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
–40
–120
0
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
LTC2150-14: 32K Point FFT,
fIN = 571MHz, –1dBFS, 170Msps
LTC2150-14: 32K Point FFT,
fIN = 420MHz, –1dBFS, 170Msps
3000
–40
2500
COUNT
0
LTC2150-14: 32K Point FFT,
fIN = 380MHz, –1dBFS, 170Msps
–60
2000
1500
–80
1000
–100
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
–120
500
0
10
21521014 G51
20 30 40 50 60 70
INPUT FREQUENCY (MHz)
0
8196
80
8200
21521014 G52
8208
8204
OUTPUT CODE
8212
8216
215210 G53
LTC2150-14: IVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
LTC2150-14: IOVDD vs Sample Rate,
15MHz Sine Wave Input, –1dBFS
50
160
LVDS CURRENT
3.5mA
45
150
40
140
35
30
IVDD (mA)
0
IOVDD (mA)
–120
–100
LVDS CURRENT
1.75mA
25
120
20
15
130
110
0
50
100
150
200
SAMPLE RATE (Msps)
250
21521014 G54
0
50
100
150
200
SAMPLE RATE (Msps)
250
21521014 G55
21521014p
13
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL PERFORMANCE CHARACTERISTICS
20
70
dBFS
SNR (dBFS)
SFDR (dBFS)
dBc
60
40
60
0
50
–10
dBc
–20
40
–30
30
–40
20
20
–50
–60
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
AMPLITUDE (dBFS)
0
0
–70
–60
–50
21521014 G56
–40 –30 –20
AMPLITUDE (dBFS)
–10
21521014 G57
LTC2150-14: SNR vs Input
Frequency, –1dBFS, 1.5V Range,
170Msps
60
50
40
30
20
10
0
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21521014 G58
–0.5
–1.0
70
–1.5
FS AMPLITUDE (–1dB)
65
SNR (dBFS)
70
LTC2150-14: Frequency Response
75
60
55
50
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
45
40
0
80
INPUT LEVEL (dBc)
80
90
10
dBFS
SFDR (dBFS)
120
100
LTC2150-14: SFDR vs Input
Frequency, –1dBFS, 1.5V Range,
170Msps
LTC2150-14: SNR vs Input Level,
fIN = 70MHz, 1.5V Range, 170Msps
LTC2150-14: SFDR vs Input Level,
fIN = 70MHz, 1.5V Range, 170Msps
–5.5
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
21521014 G59
–6.0
100
1000
INPUT FREQUENCY (MHz)
21521014 G60
21521014p
14
LTC2152-14/
LTC2151-14/LTC2150-14
PIN FUNCTIONS
VDD (Pins 1, 2): 1.8V Analog Power Supply. Bypass to
ground with 0.1µF ceramic capacitor. Pins 1, 2 can share
a bypass capacitor.
GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC
Power Ground. The exposed pad must be soldered to the
PCB ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN– (Pin 5): Negative Differential Analog Input.
SENSE (Pin 7): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±0.75V
input range. An external reference between 1.2V and 1.3V
applied to SENSE selects an input range of ±0.6 × VSENSE.
VREF (Pin 8): Reference Voltage Output. Bypass to ground
with a 2.2µF ceramic capacitor. Nominally 1.25V.
VCM (Pin 9): Common Mode Bias Output; nominally equal
to 0.8V. VCM should be used to bias the common mode of
the analog inputs. Bypass to ground with a 0.1µF ceramic
capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
OVDD (Pins 20, 30): 1.8V Output Driver Supply. Bypass
to ground with a 0.1µF ceramic capacitor.
OGND (Pin 21): LVDS Driver Ground.
SDO (Pin 36): In serial programming mode, (PAR/SER =
0V), SDO is the optional serial interface data output. Data
on SDO is read back from the mode control registers and
can be latched on the falling edge of SCK. SDO is an opendrain N-channel MOSFET output that requires an external
2k pull-up resistor from 1.8V to 3.3V. If readback from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected.
SDI (Pin 37): In serial programming mode, (PAR/SER
= 0V), SDI is the serial interface data input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
VDD), SDI selects 3.5mA or 1.75mA LVDS output current
(see Table 2).
SCK (Pin 38): In serial programming mode, (PAR/SER
= 0V), SCK is the serial interface clock input. In parallel
programming mode (PAR/SER = VDD), SCK controls the
sleep mode (see Table 2).
CS (Pin 39): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When CS is
low, SCK is enabled for shifting data on SDI into the mode
control registers. In parallel programming mode (PAR/
SER = VDD), CS controls the clock duty cycle stabilizer
(see Table 2).
PAR/SER (Pin 40): Programming Mode Selection Pin.
Connect to ground to enable the serial programming
mode. CS, SCK, SDI and SDO become a serial interface
that control the A/D operating modes. Connect to VDD to
enable the parallel programming mode where CS, SCK and
SDI become parallel logic inputs that control a reduced
set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not
be driven by a logic signal.
21521014p
15
LTC2152-14/
LTC2151-14/LTC2150-14
PIN FUNCTIONS
CLKOUT –/CLKOUT+ (Pins 26/27): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
LVDS Outputs (DDR LVDS)
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OF–/OF+ (Pins 14/15): Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
This underflow is valid only when CLKOUT+ is low. In the
second half clock cycle, the overflow is set to 0.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 16/17, 18/19,
22/23, 24/25, 28/29, 31/32, 33/34): Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
FUNCTIONAL BLOCK DIAGRAM
VDD
OVDD
ANALOG
INPUT
14-BIT
PIPELINED
ADC
S/H
VCM
0.1µF
CORRECTION
LOGIC
OUTPUT
DRIVERS
VCM
BUFFER
D12_13
•
•
•
D0_1
LVDS
OGND
BUFFER
GND
CLOCK
CLOCK/DUTY
CYCLE CONTROL
CS
SCK
SDI
SDO
PAR/SER
SPI
VREF
2.2µF
1.25V
REFERENCE
GND
SENSE
GND
RANGE
SELECT
21521014 F01
Figure 1. Functional Block Diagram
21521014p
16
LTC2152-14/
LTC2151-14/LTC2150-14
TIMING DIAGRAMS
Double-Data Rate Output Timing, All Outputs Are Differential LVDS
N
tAP
N+3
N+2
N+1
tL
tH
ENC–
ENC+
CLKOUT +
CLKOUT –
D0_1–
D0_1+
D12_13–
D12_13+
OF –
OF +
tC
D0N-5
D1N-5
D0N-4
D1N-4
D0N-3
D1N-3
D12N-5
D13N-5
D12N-4
D13N-4
D12N-3
D13N-3
OFN-5
INVALID
OFN-4
INVALID
OFN-3
INVALID
tD
tSKEW
21521014 TD01
21521014p
17
LTC2152-14/
LTC2151-14/LTC2150-14
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
21521014 TD02
21521014p
18
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
CONVERTER OPERATION
INPUT DRIVE CIRCUITS
The LTC2152-14/LTC2151-14/LTC2150-14 are 14-bit
250Msps/210Msps/170Msps A/D converters that
are powered by a single 1.8V supply. The analog
inputs must be driven differentially. The encode inputs should be driven differentially for optimal performance. The digital outputs are double-data rate
LVDS. Additional features can be chosen by programming
the mode control registers through a serial SPI port.
Input Filtering
ANALOG INPUT
Transformer-Coupled Circuits
The analog inputs is a differential CMOS sample-andhold circuit (Figure 2). It must be driven differentially
around a common mode voltage set by the VCM output
pin, which is nominally 0.8V. The inputs should swing
from VCM – 0.375V to VCM + 0.375V. There should be a
180° phase difference between the inputs.
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and also
limits wide band noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Figure 3 shows the analog input being driven by an RF
transformer with the common mode supplied through a
pair of resistors via the VCM pin.
At higher input frequencies a transmission line balun
transformer (Figures 4 and 5) has better balance, resulting
in lower A/D distortion.
10Ω
VCM
0.1µF
0.1µF
LTC2152-14
IN
VDD
AIN+
RON
20Ω
5Ω
T1
1:1
4.7Ω
0.1µF
4.7Ω
2pF
VDD
AIN–
RON
20Ω
AIN+
25Ω
2pF
25Ω
5Ω
LTC2152-14
10pF
AIN–
T1: MACOM ETC1-1T
2pF
21521014 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
2pF
VDD
10Ω
1.2V
VCM
0.1µF
0.1µF
MABA
007159000000
IN
10k
ENC+
T2
1:1
LTC2152-14
4.7Ω
AIN+
45Ω
T1
ENC–
0.1µF
T1
45Ω
0.1µF
4.7Ω
100Ω
AIN–
21521014 F02
Figure 2. Equivalent Input Circuit for Differential Input Clock
T1: MACOM ETC1-1-13
21521014 F04
Figure 4. Recommended Front-End Circuit for
Input Frequencies from 15MHz to 150MHz
21521014p
19
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
Amplifier Circuits
VCM
AIN+
AIN–
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
3 and 5) should convert the signal to differential before
driving the A/D. The A/D cannot be driven single-ended.
LTC2152-14
4.7Ω
MABA
007159000000
IN
Figure 6 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
0.1µF
10Ω
0.1µF
45Ω
T1
0.1µF
100Ω
45Ω
0.1µF
4.7Ω
21521014 F05
T1: MACOM ETC1-1-13
Figure 5. Recommended Front-End Circuit for
Input Frequencies from 150MHz Up to 900MHz
Reference
The LTC2152-14/LTC2151-14/LTC2150-14 has an internal
1.25V voltage reference. For a 1.5V input range with internal reference, connect SENSE to VDD. For a 1.5V input
range with an external reference, apply a 1.25V reference
voltage to SENSE (Figure 7).
50Ω
50Ω
VCM
Encode Input
LTC2152-14
3pF
0.1µF
4.7Ω
+ +
INPUT
0.1µF
0.1µF
4.7Ω
– –
3pF
AIN+
AIN–
3pF
21521014 F06
Figure 6. Front-End Circuit Using a High
Speed Differential Amplifier
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
LTC2152-14
1.25V
5Ω
VREF
1.2V
2.2µF
SCALER/
BUFFER
SENSE
VDD
ADC
REFERENCE
SENSE
DETECTOR
10k
ENC–
21521014 F07
Figure 7. Reference Circuit
ENC+
21521014 F08
Figure 8. Equivalent Encode Input Circuit
21521014p
20
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
the encode inputs directly. Otherwise, a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
exceed VDD +0.1V or go below –0.1V.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
Clock Duty Cycle Stabilizer
DIGITAL OUTPUTS
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
via SPI Register A2 (see SPI Control Register) or by CS
in parallel programming mode.
The digital outputs are double-data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are seven LVDS output pairs (D0_1+/
D0_1– through D12_13–/D12_13+). Overflow (OF+/OF–)
and the data output clock (CLKOUT+/CLKOUT–) each have
an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage.
LTC2152-14
VDD
1.2V
0.1µF
10k
50Ω
T1
100Ω
0.1µF
50Ω
21521014 F09
0.1µF
T1: MACOM ETC1-1-13
Figure 9. Sinusoidal Encode Drive
LTC2152-14
VDD
1.2V
0.1µF
PECL OR
LVDS INPUT
ENC+
10k
100Ω
0.1µF
ENC–
21521014 F10
Figure 10. PECL or LVDS Encode Drive
21521014p
21
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors
should be located as close as possible to the LVDS receiver.
Overflow Bit
The outputs are powered by OVDD and OGND, which are
isolated from the A/D core power and ground.
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overflow bit has the same pipeline latency as the
data bits.
Programmable LVDS Output Current
The OF is valid when CLKOUT+ is low.
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 3). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor
can be enabled by serially programming mode control
register A3. The internal termination helps absorb any
reflections caused by imperfect termination at the
receiver. When the internal termination is enabled, the
output driver current is doubled to maintain the same
output voltage swing.
Phase Shifting the Output Clock
To allow adequate set-up and hold time when latching the
output data, the CLKOUT+ signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
Alternatively, the ADC can also phase shift the CLKOUT+/
CLKOUT– signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature, the clock
duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combination of these two features enables phase shifts of 45° up
to 315° (Figure 11).
ENC+
D0-D13, OF
CLKOUT+
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
CLKPHASE1
CLKPHASE0
0°
0
0
0
45°
0
0
1
90°
0
1
0
135°
0
1
1
180°
1
0
0
225°
1
0
1
270°
1
1
0
315°
1
1
1
21521014 F11
Figure 11. Phase Shifting CLKOUT
21521014p
22
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
DATA FORMAT
CLKOUT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
OF
OF
D13
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
CLKOUT
D13/D0
D12
(1.5V Range)
OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>0.75 V
1
11 1111 1111 1111
01 1111 1111 1111
+0.75V
0
11 1111 1111 1111
01 1111 1111 1111
+0.749908V
0
11 1111 1111 1110
01 1111 1111 1110
+0.0000915V
0
10 0000 0000 0001
00 0000 0000 0001
+0.000000V
0
10 0000 0000 0000
00 0000 0000 0000
–0.0000915V
0
01 1111 1111 1111
11 1111 1111 1111
–0.0001831V
0
01 1111 1111 1110
11 1111 1111 1110
–0.7499084V
0
00 0000 0000 0001
10 0000 0000 0001
–0.75V
0
00 0000 0000 0000
10 0000 0000 0000
< –0.75V
1
00 0000 0000 0000
10 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off-chip, these unwanted
tones can be randomized, which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclusive‑OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled
by serially programming mode control register A4.
D12/D0
•
•
•
RANDOMIZER
ON
D1
D1/D0
D0
D0
21521014 F12
Figure 12. Functional Equivalent of Digital Output Randomizer
PC BOARD
CLKOUT FPGA
OF
D13/D0
LTC215X-14
D13
D12/D0
D1/D0
D0
•
•
•
D12
D1
D0
21521014 F13
Figure 13. Unrandomizing for Randomized
Digital Output Signal
21521014p
23
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
Alternate Bit Polarity
Power-Down Modes
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11, D13) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The A/D may be placed in a power-down mode to conserve
power. In sleep mode, the entire A/D converter is powered
down, resulting in < 2mW power consumption. If the encode input signal is not disabled, the power consumption
will be higher (up to 2mW at 250Msps). Sleep mode is
enabled by mode control register A1 (serial programming
mode), or by SCK (parallel programming mode).
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output randomizer—either both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
In serial programming mode it is also possible to disable
channel B while leaving channel A in normal operation.
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF .
For the suggested values in Figure 1, the A/D will stabilize after 0.1ms + 2500 • tp where tp is the period of the
sampling clock.
Digital Output Test Patterns
Nap Mode
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes (activate by setting
DTESTON) that force the A/D data outputs (OF, D13 to
D0) to known values:
All 0s: All outputs are 0
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wakeup. Recovering from nap mode requires at least 100
clock cycles. Wake-up time from nap mode is guaranteed
only if the clock is kept running, otherwise power-down,
wake-up time conditions apply. Nap mode is enabled by
power-down register A1 in the serial programming mode.
Alternating: Outputs change from all 1s to all 0s on
alternating samples
DEVICE PROGRAMMING MODES
All 1s: All outputs are 1
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs, including OF and CLKOUT, are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
The operating modes of the LTC215X-14 can be programmed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
21521014p
24
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Power-Down Control Bit
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is necessary to
write 1 in register A0 (Bit D7). After the reset is complete,
Bit D7 is automatically set back to zero.
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
SDI
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored. The data transfer ends when CS is taken high again.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed. Table  3 shows a map of the mode control registers.
GROUNDING AND BYPASSING
The LTC215X-14 requires a printed circuit board with a
clean unbroken ground plane in the first layer beneath the
ADC. A multilayer board with an internal ground plane is
recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, OVDD, VCM and VREF pins. Bypass capacitors
must be located as close to the pins as possible. Size
0402 ceramic capacitors are recommended. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The analog inputs, encode signals and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the LTC215X-14 is transferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad must
be soldered to a large grounded pad on the PC board. This
pad should be connected to the internal ground planes by
an array of vias.
21521014p
25
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An “X” indicates an unused bit.
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
X
X
X
X
X
X
RESET
Bit 7
Software Reset Bit
0 = Not Used
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused
Unused Bit Read Back as 0
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
SLEEP
NAP
0
0
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode
Bit 1-0
Must be set to 0 at all times
Unused Bit Read Back as 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
Unused Bit Read Back as 0
21521014p
26
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
X
X
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
Bits 4-2
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
Bit 0
OUTOFF
Digital Output Mode Control Bits
0 = LVDS DDR
1 = LVDS Tristate (High Impedance)
Unused Bit Read Back as 0
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
OUTTEST2
D6
D5
D4
D3
D2
D1
D0
OUTTEST1
OUTTEST0
ABP
X
DTESTON
RAND
TWOSCOMP
Bits 7-5
OUTTEST2:OUTTEST0
Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111
100 = Checkerboard Output Pattern. OF, D13-D0 alternate between 010 1010 1010 1010 and 101 0101 0101 0101
Bit 4
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3
Must be set to 0 at all times
Bit 2
DTESTON
Enable digital patterns (Bits 7-5)
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Bit 1
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 0
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Unused Bit Read Back as 0
21521014p
27
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
215210 F14
Silkscreen Top
Inner Layer 1 GND
215210 F15
Inner Layer 2
215210 F16
Inner Layer 3
215210 F17
21521014p
28
LTC2152-14/
LTC2151-14/LTC2150-14
APPLICATIONS INFORMATION
215210 F18
Inner Layer 4
215210 F19
Inner Layer 5
215210 F20
Bottom Layer 6
21521014p
29
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL APPLICATIONS
REGULATED 1.8V
C10
1µF
+
C11
47µF
1210
VDD OVDD
L5
BEAD
C12
0.1µF
C34
0.1µF
C35
0.1µF
SDO
SDI
SCK
CS
PAR/SER
D12_13+
D12_13–
D10_11+
D10_11–
L4
BEAD
PAR/SER
CS
SCK
SDI
SDO
GND
D12_13+
D12_13–
D10_11+
D10_11–
VDD
AINA+
AINA–
C13
2.2µF
R14
10Ω
R19
10Ω
R9, 1k
R16
100Ω
SENSE
C16
2.2µF
VDD
VDD
GND
AINA+
AINA–
GND
SENSE
VREF
VCM
GND
GND
10Ω
1
2
3
4
5
6
7
8
9
10
41
30
29
28
27
26
25
24
23
22
21
LTC2152
OVDD
D8_9+
D8_9–
CLKOUT+
CLKOUT –
D6_7+
D6_7–
D4_5+
D4_5–
OGND
OVDD
D8_9+
D8_9–
CLKOUT+
CLKOUT –
D6_7+
D6_7 –
D4_5+
D4_5–
CLK+
CLK–
GND
OF –
OF +
D0_1–
D0_1+
D2_3–
D2_3+
OVDD
SENSE
0.1µF
40
39
38
37
36
35
34
33
32
31
TP3
11
12
13
14
15
16
17
18
19
20
0.2µF
C21
0.1µF
OF –
OF +
D0_1–
D0_1+
D2_3–
D2_3+
0.1µF
0.1µF
+
CLK
OVDD
0.1µF
CLK–
21521014 TA02
21521014p
30
LTC2152-14/
LTC2151-14/LTC2150-14
PACKAGE DESCRIPTION
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 0.05
6.50 0.05
5.10 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 0.10
(4 SIDES)
0.75 0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 ¥ 45
CHAMFER
4.42 0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
21521014p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC2152-14/
LTC2151-14/LTC2150-14
TYPICAL APPLICATION
LTC2152-14 32K Point FFT,
fIN = 15MHz, –1dBFS, 250Msps
VDD
0
OVDD
ANALOG
INPUT
CLOCK
14-BIT
PIPELINED
ADC
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
DDR
LVDS
AMPLITUDE (dBFS)
–20
D12_13
•
•
•
D0_1
–40
–60
–80
–100
–120
21521014 TA03a
0
20
40
60
80
100
FREQUENCY (MHz)
120
21521014 TA03b
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Amplifier
Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise
Figure, 4mm × 4mm QFN-24
LTC6420-20
1.8GHz Dual Low Noise, Low Distortion Differential ADC
Drivers for 300MHz IF
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per
Amplifier, 3mm × 4mm QFN-20
Amplifiers/Filters
Receiver Subsystems
LTM9002
14-Bit Dual Channel IF/Baseband Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
21521014p
32 Linear Technology Corporation
LT 0311 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2011