LINER LTC2208IUP-14

LTC2208-14
14-Bit, 130Msps ADC
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FEATURES
DESCRIPTIO
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The LTC®2208-14 is a 130Msps, sampling 14-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals with input frequencies up to
700MHz. The input range of the ADC can be optimized
with the PGA front end.
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Sample Rate: 130Msps
77.1dBFS Noise Floor
98dB SFDR
SFDR >81dB at 250MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.32W
Clock Duty Cycle Stabilizer
Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit)
64-Pin (9mm × 9mm) QFN Package
The LTC2208-14 is perfect for demanding communications
applications, with AC performance that includes 77.1dBFS
Noise Floor and 98dB spurious free dynamic range (SFDR).
Ultralow jitter of 70fsRMS allows undersampling of high
input frequencies with excellent noise performance.
Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL
(no missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
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APPLICATIO S
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Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
3.3V
32k Point FFT, fIN = 15.11MHz,
–1dB, PGA = 0, RAND “On”,
Dither “OFF”
SENSE
2.2µF
AIN+
1.25V
COMMON MODE
BIAS VOLTAGE
0.5V TO 3.6V
0
0.1µF
–10
+
ANALOG
INPUT
AIN–
OVDD
INTERNAL ADC
REFERENCE
GENERATOR
14-BIT
PIPELINED
ADC CORE
S/H
AMP
–
OF
CLKOUT
D13
•
•
•
D0
OUTPUT
DRIVERS
CORRECTION
LOGIC AND
SHIFT REGISTER
–20
–30
AMPLITUDE (dBFS)
VCM
CMOS
OR
LVDS
OGND
–40
–50
–60
–70
–80
–90
CLOCK/DUTY
CYCLE
CONTROL
VDD
GND
ENC +
ENC –
0.1µF
3.3V
–100
0.1µF
–110
–120
0.1µF
0
220814 TA01
PGA
SHDN
DITH
MODE
LVDS
RAND
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G05
ADC CONTROL INPUTS
220814f
1
LTC2208-14
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W W
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
OVDD = VDD (Notes 1 and 2)
TOP VIEW
64 PGA
63 RAND
62 MODE
61 LVDS
60 OF+/0FA
59 OF–/DA13
58 D13+/DA12
57 D13–/DA11
56 D12+/DA10
55 D12–/DA9
54 D11+/DA8
53 D11–/DA7
52 D10+/DA6
51 D10–/DA5
50 OGND
49 OVDD
Supply Voltage (VDD) ................................... –0.3V to 4V
Digital Output Ground Voltage (OGND)........ –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................–0.3V to (OVDD + 0.3V)
Power Dissipation............................................ 2000mW
Operating Temperature Range
LTC2208C-14 ........................................... 0°C to 70°C
LTC2208I-14 ........................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V
SENSE 1
GND 2
VCM 3
GND 4
VDD 5
VDD 6
GND 7
AIN+ 8
AIN– 9
GND 10
GND 11
ENC+ 12
ENC– 13
GND 14
VDD 15
VDD 16
48 D9+/DA4
47 D9–/DA3
46 D8+/DA2
45 D8–/DA1
44 D7 +/DA0
43 D7 –/DNC
42 D6+/DNC
41 D6–/CLKOUTA
40 CLKOUT+/CLKOUTB
39 CLKOUT–/OFB
38 D5+_ /DB13
37 D5 /DB12
36 D4+/DB11
35 D4–/DB10
34 D3+/DB9
33 D3–/DB8
VDD 17
GND 18
SHDN 19
DITH 20
NC 21
NC 22
DNC/DB0 23
DNC/DB1 24
D0–/DB2 25
D0+/DB3 26
D1–/DB4 27
D1+/DB5 28
D2–/DB6 29
D2+/DB7 30
OGND 31
OVDD 32
65
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB BOARD
TJMAX = 125°C, θJA = 20°C/W
ORDER PART
NUMBER
UP PART
MARKING*
LTC2208CUP-14
LTC2208IUP-14
LTC2208UP-14
LTC2208UP-14
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Drift
Gain Error
Full-Scale Drift
Differential Analog Input (Note 5)
Differential Analog Input
(Note 6)
●
External Reference
Internal Reference
External Reference
External Reference
●
Transition Noise
MIN
●
●
TYP
MAX
UNITS
±1
±0.2
±2
±10
±0.2
±30
±15
0.8
±1.5
±0.5
±10.8
LSB
LSB
mV
μV/°C
%FS
±2.3
ppm/°C
ppm/°C
LSBRMS
220814f
2
LTC2208-14
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A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
VIN
VIN, CM
IIN
ISENSE
IMODE
ILVDS
CIN
PARAMETER
Analog Input Range (AIN+ – AIN–)
Analog Input Common Mode
Analog Input Leakage Current
SENSE Input Leakage Current
MODE Pin Pull-Down Current to GND
LVDS Pin Pull-Down Current to GND
Analog Input Capacitance
tAP
Sample-and-Hold
Acquisition Delay Time
Sample-and-Hold
Acquisition Delay Time Jitter
Analog Input
Common Mode Rejection Ratio
Full Power Bandwidth
tJITTER
CMRR
BW-3dB
CONDITIONS
3.135V ≤ VDD ≤ 3.465V
Differential Input (Note 7)
0V ≤ AIN+, AIN– ≤ VDD
0V ≤ SENSE ≤ VDD
MIN
10
10
6.5
1.8
1.0
UNITS
VP-P
V
µA
µA
µA
µA
pF
pF
ns
70
fs RMS
1V < (AIN+ = AIN–) <1.5V
80
dB
RS < 25Ω
700
MHz
●
●
●
1
–1
–3
Sample Mode ENC+ < ENC–
Hold Mode ENC+ > ENC–
TYP
1.5 or 2.25
1.25
MAX
1.5
1
3
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
SNR
SFDR
PARAMETER
Signal-to-Noise Ratio
Spurious Free
Dynamic Range
2nd or 3rd Harmonic
CONDITIONS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0) TA = 25°C
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) TA = 25°C
140MHz Input (1.5V Range, PGA = 1)
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA =1 )
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
MIN
●
75.7
75.4
●
73.5
73.3
●
84
●
81.5
TYP
77.1
74.9
77.0
77.0
74.9
76.9
74.8
76.4
74.6
74.6
75.0
73.6
98
98
96
98
90
93
85
95
76
81
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
220814f
3
LTC2208-14
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
SYMBOL
SFDR
S/(N+D)
PARAMETER
Spurious Free
Dynamic Range
4th Harmonic
or Higher
Signal-to-Noise
Plus Distortion Ratio
CONDITIONS
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0) TA = 25°C
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1) TA = 25°C
140MHz Input (1.5V Range, PGA = 1)
MIN
●
87
●
85
●
75.4
75.1
●
73.4
73.0
●
95
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
SFDR
Spurious Free Dynamic Range
at –25dBFS
Dither “OFF”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
SFDR
Spurious Free Dynamic Range
at –25dBFS
Dither “ON”
5MHz Input (2.25V Range, PGA = 0)
5MHz Input (1.5V Range, PGA = 1)
30MHz Input (2.25V Range, PGA = 0)
30MHz Input (1.5V Range, PGA = 1)
70MHz Input (2.25V Range, PGA = 0)
70MHz Input (1.5V Range, PGA = 1)
140MHz Input (2.25V Range, PGA = 0)
140MHz Input (1.5V Range, PGA = 1)
250MHz Input (2.25V Range, PGA = 0)
250MHz Input (1.5V Range, PGA = 1)
TYP
100
100
100
100
100
100
95
95
90
90
77.0
74.8
MAX
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
76.9
76.9
74.7
76.6
74.6
76.3
74.5
74.5
73.6
72.9
105
105
105
105
105
105
100
100
100
100
115
115
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
110
110
110
110
107
107
105
105
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
220814f
4
LTC2208-14
COMMON MODE BIAS CHARACTERISTICS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
VCM Output Voltage
VCM Output Tempco
VCM Line Regulation
CONDITIONS
IOUT = 0
IOUT = 0
3.135V ≤ VDD ≤ 3.465V
VCM Output Resistance
| IOUT | ≤ 1mA
MIN
1.15
TYP
1.25
40
1
MAX
1.35
UNITS
V
ppm/°C
mV/ V
Ω
2
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
ENCODE INPUTS (ENC+, ENC–)
Differential Input Voltage
VID
VICM
Common Mode Input Voltage
CONDITIONS
RIN
(See Figure 2)
(Note 7)
Input Resistance
CIN
Input Capacitance
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
LOGIC OUTPUTS (CMOS MODE)
OVDD = 3.3V
VOH
High Level Output Voltage
VOL
ISOURCE
ISINK
OVDD = 2.5V
VOH
VOL
OVDD = 1.8V
VOH
VOL
Low Level Output Voltage
MIN
●
(Note 7)
Internally Set
Externally Set (Note 7)
VDD = 3.3V
MAX
0.2
1.6
1.2
●
VDD = 3.3V
VDD = 3.3V
VIN = 0V to VDD
(Note 7)
VDD = 3.3V
TYP
3.0
kΩ
pF
0.8
±10
1.5
V
V
µA
pF
3.299
3.29
0.01
0.10
–50
50
0.4
V
V
V
V
mA
mA
2
●
3.1
V
V
V
6
3
●
IO = –10µA
IO = –200µA ●
IO = 160µA
IO = 1.6mA
●
UNITS
Output Source Current
Output Sink Current
VOUT = 0V
VOUT = 3.3V
High Level Output Voltage
Low Level Output Voltage
VDD = 3.3V
VDD = 3.3V
IO = –200µA
IO = 1.60mA
2.49
0.1
High Level Output Voltage
VDD = 3.3V
IO = –200µA
1.79
V
VDD = 3.3V
IO = 1.60mA
0.1
V
Low Level Output Voltage
LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS
VOD
Differential Output Voltage
VOS
Output Common Mode Voltage
LOW POWER LVDS
VOD
Differential Ouptut Voltage
VOS
Output Common Mode Voltage
100Ω Differential Load
100Ω Differential Load
●
100Ω Differential Load
100Ω Differential Load
●
●
●
V
V
247
1.125
350
1.2
454
1.375
mV
V
125
1.125
175
1.2
250
1.375
mV
V
220814f
5
LTC2208-14
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
VDD
Analog Supply Voltage
PSHDN
Shutdown Power
STANDARD LVDS OUTPUT MODE
OVDD
Output Supply Voltage
IVDD
Analog Supply Current
IOVDD
Output Supply Current
PDIS
Power Dissipation
LOW POWER LVDS OUTPUT MODE
OVDD
Output Supply Voltage
IVDD
Analog Supply Current
IOVDD
Output Supply Current
PDIS
Power Dissipation
CMOS OUTPUT MODE
OVDD
Output Supply Voltage
IVDD
Analog Supply Current
PDIS
Power Dissipation
CONDITIONS
(Note 8)
SHDN = VDD
●
MIN
3.135
TYP
3.3
0.2
MAX
3.465
UNITS
V
mW
(Note 8)
●
3
3.3
401
71
1498
3.6
470
90
1782
V
mA
mA
mW
3
3.3
401
40
1356
3.6
470
50
1650
V
mA
mA
mW
401
1320
3.6
470
1551
V
mA
mW
●
●
●
(Note 8)
●
●
●
●
(Note 8)
●
0.5
●
●
WU
TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fS
tL
PARAMETER
Sampling Frequency
ENC Low Time
CONDITIONS
(Note 8)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
tH
ENC High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
(Note 7)
(Note 7)
(tC-tD) (Note 7)
●
(Note 7)
(Note 7)
(tC-tD) (Note 7)
Full Rate CMOS
Demuxed
●
tAP
Sample-and-Hold Aperture Delay
LVDS OUTPUT MODE (STANDARD and LOW POWER)
tD
ENC to DATA Delay
tC
ENC to CLKOUT Delay
DATA to CLKOUT Skew
tSKEW
tRISE
Output Rise Time
tFALL
Output Fall Time
Data Latency
Data Latency
CMOS OUTPUT MODE
tD
ENC to DATA Delay
tC
ENC to CLKOUT Delay
tSKEW
DATA to CLKOUT Skew
Data Latency
Data Latency
●
●
●
●
●
●
●
MIN
1
3.65
2.6
3.65
2.6
TYP
3.846
3.846
3.846
3.846
–1
MAX
130
1000
1000
1000
1000
UNITS
MHz
ns
ns
ns
ns
ns
1.3
1.3
–0.6
2.5
2.5
0
0.5
0.5
7
3.8
3.8
0.6
ns
ns
ns
ns
ns
Cycles
1.3
1.3
–0.6
2.7
2.7
0
7
7
4.0
4.0
0.6
ns
ns
ns
Cycles
Cycles
220814f
6
LTC2208-14
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/
ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P
with differential drive (PGA = 0), unless otherwise specified.
Note 5: Integral nonlinearity is defined as the deviation of a code from a “best
fit straight line” to the transfer curve. The deviation is measured from the
center of the quantization band.
Note 6: Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in
2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
WU
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TI I G DIAGRA
LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
tAP
ANALOG
INPUT
N+1
N+4
N
N+3
N+2
tH
tL
–
ENC
ENC+
tD
N–7
D0-D13, OF
CLKOUT+
CLKOUT –
N–6
N–5
N–4
N–3
tC
220814 TD01
220814f
7
LTC2208-14
W
UW
TI I G DIAGRA S
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+1
N+4
N
N+3
N+2
tH
tL
ENC–
ENC+
tD
N–7
DA0-DA13, OFA
N–6
N–5
N–4
N–3
tC
CLKOUTA
CLKOUTB
HIGH IMPEDANCE
DB0-DB13, OFB
220814 TD02
Demultiplexed CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+1
N
N+4
N+2
N+3
tH
tL
ENC–
ENC+
tD
DA0-DA13, OFA
N–8
N–6
N–4
N–7
N–5
N–3
tD
DB0-DB13, OFB
tC
CLKOUTA
CLKOUTB
220814 TD03
220814f
8
LTC2208-14
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TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity (DNL)
vs Output Code
1.0
0.5
0.8
0.4
0.6
0.3
0.4
0.2
0.2
0
–0.2
–0.4
200000
0.1
150000
0
–0.1
100000
–0.2
–0.6
–0.3
–0.8
–0.4
–1.0
50000
–0.5
0
4096
12288
8192
OUTPUT CODE
0
16384
4096
12288
8192
OUTPUT CODE
220814 G01
0
8176
16384
32k Point FFT, fIN = 15.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
–120
0
60
10
40
30
20
50
FREQUENCY (MHz)
0
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
0
–50
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G07
60
–40
–90
0
40
30
20
50
FREQUENCY (MHz)
32k Point 2-Tone FFT, fIN =
20.14MHz and 14.25MHz, –25dBFS,
PGA = 0, RAND = “On”, Dither “Off”
–10
–40
10
220814 G06
32k Point 2-Tone FFT, fIN =
20.14MHz and 14.25MHz, –7dBFS,
PGA = 0, RAND = “On”, Dither “Off”
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
60
220814 G05
220814 G04
128k Point FFT, fIN = 15.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “On”
8186
–40
–90
0
8184
128k Point FFT, fIN = 15.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “Off”
0
–50
8182
8180
OUTPUT CODE
220814 G03
–10
–40
8178
220814 G01
32k Point FFT, fIN = 5.21MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
AMPLITUDE (dBFS)
AC Grounded Input Histogram
250000
COUNT
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity (INL)
vs Output Code
–120
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G08
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G09
220814f
9
LTC2208-14
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SFDR vs Input Level, fIN = 15.1MHz,
PGA = 0, RAND = “On”, Dither “Off”
32k Point FFT, fIN = 30.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
SFDR vs Input Level, fIN = 15.1MHz,
PGA = 0, RAND = “On”, Dither “On”
0
120
120
–10
80
60
40
–30
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
–20
100
100
80
60
40
–50
–60
–70
–80
–90
–100
20
20
–40
–110
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
0
60
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G13
220814 G14
128k Point FFT, fIN = 70.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “Off”
128k Point FFT, fIN = 70.11MHz,
–40dBFS, PGA = 0, RAND = “On”,
Dither “On”
–120
0
0
–10
–20
–20
–20
–30
–30
–30
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G16
60
–40
–90
0
40
30
20
50
FREQUENCY (MHz)
32k Point FFT, fIN = 70.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
0
–40
10
220814 G15
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
60
32k Point FFT, fIN = 70.11MHz,
–10dBFS, PGA = 0, RAND = “On”,
Dither “Off”
0
–50
40
30
20
50
FREQUENCY (MHz)
220814 G12
32k Point FFT, fIN = 70.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
–10
–40
10
220814 G11
220814 G10
32k Point FFT, fIN = 30.11MHz,
–25dBFS, PGA = 0, RAND = “On”,
Dither “On”
AMPLITUDE (dBFS)
–120
0
–120
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G17
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G18
220814f
10
LTC2208-14
U W
TYPICAL PERFOR A CE CHARACTERISTICS
SFDR vs Input Level, fIN = 70.2MHz,
PGA = 0, RAND = “On”, Dither “Off”
32k Point 2-Tone FFT, fIN = 67.2MHz
and 74.4MHz, –7dBFS, PGA = 0,
RAND = “On”, Dither “Off”
SFDR vs Input Level, fIN = 70.2MHz,
PGA = 0, RAND = “On”, Dither “On”
120
0
120
–10
–20
100
80
60
40
20
–30
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
100
80
60
40
–40
–50
–60
–70
–80
–90
–100
20
–110
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220814 G19
0
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
0
10
40
30
20
50
FREQUENCY (MHz)
–120
0
60
220814 G22
10
40
30
20
50
FREQUENCY (MHz)
0
60
10
40
30
20
50
FREQUENCY (MHz)
220814 G23
SFDR vs Input Level, fIN = 140.1MHz,
PGA = 1, RAND = “On”, Dither “Off”
60
220814 G24
32k Point FFT, fIN = 170.1MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
SFDR vs Input Level, fIN = 140.1MHz,
PGA = 1, RAND = “On”, Dither “On”
0
120
120
60
32k Point FFT, fIN = 140.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
0
–50
40
30
20
50
FREQUENCY (MHz)
220814 G21
32k Point FFT, fIN = 140.11MHz,
–1dBFS, PGA = 0, RAND = “On”,
Dither “Off”
–10
–40
10
220814 G20
32k Point 2-Tone FFT, fIN = 67.2MHz
and 74.4MHz, –15dBFS, PGA = 0,
RAND = “On”, Dither “Off”
AMPLITUDE (dBFS)
–120
0
–10
80
60
40
–30
AMPLITUDE (dBFS)
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)
–20
100
100
80
60
40
–50
–60
–70
–80
–90
–100
20
20
–40
–110
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
220814 G25
0
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
–120
0
220814 G26
0
10
40
30
20
50
FREQUENCY (MHz)
60
220814 G27
220814f
11
LTC2208-14
U W
TYPICAL PERFOR A CE CHARACTERISTICS
32k Point FFT, fIN = 250.11MHz,
–10dBFS, PGA = 1, RAND = “On”,
Dither “Off”
32k Point FFT, fIN = 380.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
32k Point FFT, fIN = 250.11MHz,
–1dBFS, PGA = 1, RAND = “On”,
Dither “Off”
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
0
10
40
30
20
50
FREQUENCY (MHz)
–120
0
60
10
40
30
20
50
FREQUENCY (MHz)
32k Point FFT, fIN = 380.11MHz,
–10dBFS, PGA = 1, RAND = “On”,
Dither “Off”
–10
–30
100
–40
95
–70
–80
77
76
90
85
PGA = 0
75
74
PGA = 1
80
73
–90
75
–100
72
70
–110
–120
0
10
40
30
20
50
FREQUENCY (MHz)
71
65
60
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
220814 G31
105
105
100
100
90
85
80
SNR
300
220814 G33
IVDD vs Sample Rate,
fIN = 5.1MHz, –1dBfs
470
450
SFDR
VDD = 3.47V
430
95
IVDD (mA)
SNR AND SFDR (dBFS)
110
95
200
100
INPUT FREQUENCY (MHz)
0
220814 G32
110
SFDR
300
SNR and SFDR vs Supply Voltage
(VDD), fIN = 5.1MHz, –1dBFS
SNR and SFDR vs Sample Rate
fIN = 5.1MHz, –1dBFS
SNR AND SFDR (dBFS)
PGA = 0
PGA = 1
SNR (dBFS)
SFDR (dBc)
AMPLITUDE (dBFS)
78
105
–20
60
SNR vs Input Frequency
110
–60
40
30
20
50
FREQUENCY (MHz)
220814 G30
SFDR (HD2 and HD3)
vs Input Frequency
0
–50
10
220814 G29
220814 G28
90
85
80
VDD = 3.3V
410
VDD = 3.13V
390
SNR
370
75
75
70
0
60
0
25
50 75 100 125 150 175 200
SAMPLE RATE (Msps)
220814 G34
70
2.8
350
3.2
3.4
3.0
SUPPLY VOLTAGE (V)
3.6
220814 G35
0
20
40 60 80 100 120 140 160
SAMPLE RATE (Msps)
220814 G36
220814f
12
LTC2208-14
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Gain Error Drift vs Temperature,
Internal Reference, Drift from 25°C
SNR and SFDR vs Duty Cycle
Gain Error Drift vs Temperature,
External Reference, Drift from 25°C
0.08
0.2
110
0.06
0.1
SFDR DCS ON
0.04
90
80
SNR DCS ON
0
–0.1
–0.2
–0.3
0.02
0
–0.02
–0.04
–0.06
–0.08
70
–0.4
SNR DCS OFF
30
50
40
60
70
–0.10
–0.5
–50 –30
DUTY CYCLE (%)
30
50
–10 10
TEMPERATURE (°C)
70
90
–0.12
–50
–30
30
–10 10
50
TEMPERATURE (°C)
220814 G38
220814 G37
Input Offset Voltage Drift vs
Temperature, Drift from 25°C
70
90
220814 G39
SNR and SFDR vs Input Common
Mode Voltage
100
0.24
SFDR
0.20
SNR (dBFS) AND SFDR (dBc)
60
GAIN ERROR DRIFT (%)
GAIN ERROR DRIFT (%)
SFDR DCS OFF
INPUT OFFSET VOLTAGE (mV)
SFDR AND SNR (dBFS)
100
0.15
0.10
0.05
90
80
SNR
70
0
–0.05
–50 –30
30
50
–10 10
TEMPERATURE (°C)
70
90
220814 G40
60
0.50
0.75 1.00 1.25 1.50 1.75
INPUT COMMON MODE VOLTAGE (V)
2.00
220814 G41
220814f
13
LTC2208-14
U
U
U
PI FU CTIO S
For CMOS Mode. Full Rate or Demultiplexed
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
VCM (Pin 3): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 0.1µF ceramic chip capacitors.
AIN+ (Pin 8): Positive Differential Analog Input.
AIN– (Pin 9): Negative Differential Analog Input.
ENC+ (Pin 12): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.
OFB (Pin 39): Over/Under Flow Digital Output for the B
Bus. OFB is high when an over or under flow has occurred
on the B bus. This pin goes to high impedance state in full
rate CMOS mode.
CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle
at the sample rate in full rate CMOS mode or at 1/2 the
sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.
CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA
will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.
DNC (Pins 42, 43): Do Not Connect in CMOS Mode.
DA0-DA13 (Pins 44-48 and 51-59): Digital Outputs, A Bus.
DA13 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.
OFA (Pin 60): Over/Under Flow Digital Output for the A
Bus. OFA is high when an over or under flow has occurred
on the A bus.
ENC– (Pin 13): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC –.
Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1µF capacitor for a single-ended
Encode signal.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.
NC (Pins 21, 22): No Connect.
DB0-DB13 (Pins 23-30 and 33-38): Digital Outputs, B Bus.
DB13 is the MSB. Active in demultiplexed mode. The B bus
is in high impedance state in full rate CMOS mode.
OGND (Pins 31 and 50): Output Driver Ground.
OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with O.1µF capacitor.
RAND (Pin 63): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
220814f
14
LTC2208-14
U
U
U
PI FU CTIO S
PGA (Pin 64): Programmable Gain Amplifier Control Pin. Low
selects a front-end gain of 1, input range of 2.25VP-P. High
selects a front-end gain of 1.5, input range of 1.5VP-P.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package must be soldered to
ground.
For LVDS Mode. Standard or Low Power
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground.
VCM (Pin 3): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum
of 2.2µF. Ceramic chip capacitors are recommended.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 0.1µF ceramic chip capacitors.
AIN + (Pin 8): Positive Differential Analog Input.
AIN – (Pin 9): Negative Differential Analog Input.
ENC + (Pin 12): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC+.
Internally biased to 1.6V through a 6.2kΩ resistor. Output
data can be latched on the rising edge of ENC+.
ENC – (Pin 13): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC –.
Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1µF capacitor for a single-ended
Encode signal.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are set in
high impedance state.
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal dither.
Refer to Internal Dither section of the data sheet for details
on dither operation.
NC (Pins 21, 22): No Connect.
NC (Pins 23, 24): Do Not Connect in LVDS Mode.
D0–/D0+ to D13–/D13+ (Pins 25-30, 33-38, 41-48 and
51-58): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS receiver.
D13+/D13– is the MSB.
OGND (Pins 31 and 50): Output Driver Ground.
OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1µF capacitor.
CLKOUT–/CLKOUT + (Pins 39 and 40): LVDS Data Valid
0utput. Latch data on the rising edge of CLKOUT +, falling
edge of CLKOUT –.
OF–/OF+ (Pins 59 and 60): Over/Under Flow Digital Output
OF is high when an over or under flow has occurred.
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connecting LVDS to VDD selects Standard LVDS mode.
MODE (Pin 62): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 63): Digital Output Randomization Selection Pin.
RAND low results in normal operation. RAND high selects
D1-D13 to be EXCLUSIVE-ORed with D0 (the LSB). The
output can be decoded by again applying an XOR operation
between the LSB and all other bits. The mode of operation
reduces the effects of digital output interference.
PGA (Pin 64): Programmable Gain Amplifier Control Pin. Low
selects a front-end gain of 1, input range of 2.25VP-P. High
selects a front-end gain of 1.5, input range of 1.5VP-P.
GND (Exposed Pad Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package must be soldered to ground.
220814f
15
LTC2208-14
W
BLOCK DIAGRA
AIN+
VDD
INPUT
S/H
AIN–
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
GND
DITHER
SIGNAL
GENERATOR
CORRECTION LOGIC
AND
SHIFT REGISTER
ADC CLOCKS
RANGE
SELECT
OVDD
SENSE
PGA
VCM
BUFFER
ADC
REFERENCE
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
VOLTAGE
REFERENCE
OGND
ENC+
ENC–
SHDN PGA RAND M0DE LVDS
CLKOUT+
CLKOUT–
OF+
OF–
D13+
D13–
D0+
D0–
220814 F01
DITH
Figure 1. Functional Block Diagram
220814f
16
LTC2208-14
U
OPERATIO
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components, except the
first five harmonics.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = –20Log
(V
2
2
)
+ V32 + V42 + ...VN2 / V12
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second
through nth harmonics.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
defined as the ratio of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
Spurious Free Dynamic Range (SFDR)
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
Full Power Bandwidth
The Full Power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC + equals the ENC– voltage
to the instant that the input signal is held by the sampleand-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from convertion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
220814f
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CONVERTER OPERATION
The LTC2208-14 is a CMOS pipelined multistep converter
with a front-end PGA. As shown in Figure 1, the converter
has five pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2208-14 has two phases of operation, determined
by the state of the differential ENC+/ENC – input pins. For
brevity, the text will refer to ENC+ greater than ENC – as
ENC high and ENC+ less than ENC – as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplifier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifier which
drives the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fifth stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
18
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2208-14
CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors
(CSAMPLE) through NMOS transitors. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
LTC2208-14
VDD
RPARASITIC
3Ω
AIN+
RON
20Ω
CPARASITIC
1.8pF
VDD
RPARASITIC
3Ω
AIN–
CSAMPLE
4.9pF
RON
20Ω
CSAMPLE
4.9pF
CPARASITIC
1.8pF
VDD
1.6V
6k
ENC+
ENC–
6k
1.6V
2208 F02
Figure 2. Equivalent Input Circuit
220814f
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input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 3) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with 2.2µF or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the dynamic performance of the LTC2208-14 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC the
sample and hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F encode); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
provide isolation from ADC S/H switching. The LTC2208-14
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC filter.
Figures 3, 4a and 4b show three examples of input RC
filtering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well
as noise coupled from the digital circuitry. The LTC220814 does not require any input filter to achieve data sheet
specifications; however, no filtering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2208-14 being driven by an RF
transformer with a center-tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50Ω can reduce
the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Center-tapped transformers provide a convenient means
of DC biasing the secondary; however, they often show
poor balance at high input frequencies, resulting in large
2nd order harmonics.
VCM
2.2µF
5Ω
T1
8.2pF
35Ω
Input Filtering
A first order RC low pass filter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
LTC2208-14
8.2pF
0.1µF
10Ω
INPUT DRIVE CIRCUITS
5Ω AIN+
10Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
35Ω
5Ω AIN–
8.2pF
220814 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer. Recommended for Input
Frequencies from 5MHz to 100MHz
220814f
19
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Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has
much better high frequency response and balance than
flux coupled center tap transformers. Coupling capacitors
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure
4b shows the same circuit with components suitable for
higher input frequencies.
VCM
2.2µF
0.1µF
0.1µF
5Ω AIN+
10Ω
ANALOG
INPUT
T1
1:1
25Ω
0.1µF
25Ω
10Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
LTC2208-14
4.7pF
4.7pF
5Ω AIN–
4.7pF
220814 F04a
Reference Operation
Figure 6 shows the LTC2208-14 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain
amplifier and control circuit. The LTC2208-14 has three
modes of reference operation: Internal Reference, 1.25V
external reference or 2.5V external reference. To use the
internal reference, tie the SENSE pin to VDD. To use an
external reference, simply apply either a 1.25V or 2.5V
reference voltage to the SENSE input pin. Both 1.25V
and 2.5V applied to SENSE will result in a full scale range
of 2.25VP-P (PGA = 0). A 1.25V output, VCM is provided
for a common mode bias for input drive circuitry. An
external bypass capacitor is required for the VCM output.
This provides a high frequency low impedance path to
ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
stable without this capacitor. The minimum value required
for stability is 2.2µF.
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
VCM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
VCM
ANALOG
INPUT
2.2µF
0.1µF
5Ω
ANALOG
INPUT
25Ω
0.1µF
T1
1:1
0.1µF
25Ω
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2µF
AIN+
+
2.2pF
AIN+
25Ω
LTC2208-14
12pF
+
CM
LTC2208-14
–
2.2pF
5Ω
2.2µF
–
25Ω
AMPLIFIER = LTC6600-20,
LT1993, ETC.
AIN–
AIN–
12pF
220814 F05
Figure 5. DC Coupled Input with Differential Amplifier
220814 F04b
Figure 4b. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 250MHz to 500MHz
Direct Coupled Circuits
Figure 5 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifiers tend to have
high noise. As a result, the SNR will be degraded unless
the noise bandwidth is limited prior to the ADC input.
TIE TO VDD TO USE
INTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
RANGE
SELECT
AND GAIN
CONTROL
INTERNAL
ADC
REFERENCE
SENSE
PGA
2.5V
BANDGAP
REFERENCE
VCM
BUFFER
1.25V
2.2µF
220814 F06
Figure 6. Reference Circuit
220814f
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The internal programmable gain amplifier provides the
internal reference voltage for the ADC. This amplifier has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1µF ceramic capacitor.
VCM
1.25V
2.2µF
3.3V
1µF
2
LT1461-2.5
4
6
SENSE
LTC2208-14
In applications where jitter is critical (high input frequencies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fixed frequency sinusoidal
signal, filter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to 3V. Each input may be driven from ground to VDD for
single-ended drive.
2.2µF
LTC2208-14
VDD
220814 F07
TO INTERNAL
ADC CLOCK
DRIVERS
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
VDD
PGA Pin
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25VP-P; PGA
= 1 selects an input range of 1.5VP-P. The 2.25V input range
has the best SNR; however, the distortion will be higher for
input frequencies above 100MHz. For applications with high
input frequencies, the low input range will have improved
distortion; however, the SNR will be approximately 1.8dB
worse. See the typical performance curves section.
1.6V
6k
ENC+
VDD 1.6V
6k
ENC–
220814 F08a
Figure 8a. Equivalent Encode Input Circuit
Driving the Encode Inputs
The noise performance of the LTC2208-14 can depend on
the encode signal quality as much as on the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
0.1µF
ENC+
T1
50Ω
100Ω
0.1µF
50Ω
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
LTC2208-14
8.2pF
ENC–
220814 F08b
Figure 8b. Transformer Driven Encode
220814f
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ENC+
VTHRESHOLD = 1.6V
1.6V ENC– LTC2208-14
0.1µF
220814 F09
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
DIGITAL OUTPUTS
Digital Output Modes
3.3V
MC100LVELT22
3.3V
130Ω
Q0
130Ω
ENC+
D0
ENC– LTC2208-14
Q0
83Ω
The lower limit of the LTC2208-14 sample rate is determined
by droop of the sample and hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2208-14 is 1Msps.
83Ω
220814 F10
Figure 10. ENC Drive Using a CMOS to PECL Translator
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2208-14 is 130Msps.
For the ADC to operate properly the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 3.65ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3VDD or 2/3VDD using external resistors.
The LTC2208-14 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can
be used to set the 1/3VDD and 2/3VDD logic levels. Table 1
shows the logic states for the LVDS pin.
Table 1. LVDS Pin Function
LVDS
0V(GND)
1/3VDD
2/3VDD
VDD
Digital Output Mode
Full-Rate CMOS
Demultiplexed CMOS
Low Power LVDS
LVDS
Digital Output Buffers (CMOS Modes)
Figure 11 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
buffer is powered by OVDD and OGND, isolated from the
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
output appear as 50Ω to external circuitry and eliminates
the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2208-14 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as a ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
220814f
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output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
LTC2208-14
OVDD
VDD
0.5V
TO 3.6V
VDD
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OGND
2208 F11
Figure 11. Equivalent Circuit for a Digital Output Buffer
Digital Output Buffers (LVDS Modes)
Figure 12 shows an equivalent circuit for an LVDS output
pair. A 3.5mA current is steered from OUT+ to OUT– or
vice versa, which creates a ±350mV differential voltage
across the 100Ω termination resistor at the LVDS receiver.
A feedback loop regulates the common mode output voltage to 1.20V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
resistor, even if the signal is not used (such as OF+/OF– or
CLKOUT+/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew, all LVDS PC board traces
should have about the same length.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in ±175mV at the LVDS
receiver’s 100Ω termination resistor. The output common mode voltage is 1.20V, the same as standard LVDS
Mode.
Data Format
The LTC2208-14 parallel digital output can be selected
for offset binary or 2’s complement format. The format
is selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An
external resistor divider can be used to set the 1/3VDD
and 2/3VDD logic levels. Table 2 shows the logic states
for the MODE pin.
Table 2. MODE Pin Function
MODE
0(GND)
1/3VDD
2/3VDD
VDD
Output Format
Clock Duty
Cycle Stabilizer
Offset Binary
Offset Binary
2’s Complement
2’s Complement
Off
On
On
Off
OVDD
3.3V
LTC2208-14
0.1µF
3.5mA
VDD
VDD
OVDD
43Ω
DATA
FROM
LATCH
PREDRIVER
LOGIC
10k
10k
OVDD
100Ω
LVDS
RECEIVER
43Ω
1.20V
+
–
OGND
2208-14 F12
Figure 12. Equivalent Output Buffer in LVDS Mode
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Overflow Bit
An overflow output bit (OF) indicates when the converter
is over-ranged or under-ranged. In CMOS mode, a logic
high on the OFA pin indicates an overflow or underflow on
the A data bus, while a logic high on the OFB pin indicates
an overflow on the B data bus. In LVDS mode, a differential logic high on OF+/OF– pins indicates an overflow
or underflow.
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output Randomizer function is active
when the RAND pin is high.
CLKOUT
CLKOUT
OF
OF
Output Clock
The ADC has a delayed version of the encode input available as a digital output, CLKOUT. The CLKOUT pin can
be used to synchronize the converter data to the digital
system. This is necessary when using a sinusoidal encode. In both CMOS modes, A bus data will be updated
as CLKOUTA falls and CLKOUTB rises. In demultiplexed
CMOS mode the B bus data will be updated as CLKOUTA
falls and CLKOUTB rises.
D13
In Full Rate CMOS Mode, only the A data bus is active;
data may be latched on the rising edge of CLKOUTA or
the falling edge of CLKOUTB.
D1
In demultiplexed CMOS mode CLKOUTA and CLKOUTB
will toggle at 1/2 the frequency of the encode signal. Both
the A bus and the B bus may be latched on the rising edge
of CLKOUTA or the falling edge of CLKOUTB.
D13/D0
D12
D2
RAND = HIGH,
RANDOMIZER
ENABLED
D12/D0
•
•
•
D2/D0
D1/D0
RAND
D0
D0
220814 F13
Figure 13. Functional Equivalent of Digital Output Randomizer
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise floor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply. In CMOS mode OVDD can be powered with
any logic voltage up to the 3.6V. OGND can be powered
with any voltage from ground up to 1V and must be less
than OVDD. The logic outputs will swing between OGND
and OVDD. In LVDS Mode, OVDD should be connected to
a 3.3V supply and OGND should be connected to GND.
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Internal Dither
PC BOARD
FPGA
The LTC2208-14 is a 14-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones.
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
mode can be enabled to randomize the input location on
the ADC transfer curve, resulting in improved SFDR for
low signal levels.
CLKOUT
OF
D13/D0
D13
D12/D0
As shown in Figure 15, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
the noise floor of the ADC, as compared to the noise floor
with dither off.
D12
•
•
•
LTC2208-14
D2/D0
D2
D1/D0
D1
D0
D0
220814 F14
Figure 14. Derandomizing a Randomized Digital Output
LTC2208-14
AIN+
ANALOG
INPUT
AIN–
14-BIT
PIPELINED
ADC CORE
S/H
AMP
CLOCK/DUTY
CYCLE
CONTROL
PRECISION
DAC
DIGITAL
SUMMATION
CLKOUT
OF
D13
•
•
•
D0
OUTPUT
DRIVERS
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
220814 F15
ENC +
ENC –
DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit
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Grounding and Bypassing
The LTC2208-14 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTC2208-14 has been optimized for a flowthrough layout
so that the interaction between inputs and digital outputs
is minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated
as much as possible. In particular, care should be taken
not to run any digital track alongside an analog signal
track or underneath the ADC.
High quality ceramic bypass capacitors should be used
at the VDD, VCM, and OVDD pins. Bypass capacitors must
be located as close to the pins as possible. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2208-14 differential inputs should run parallel
and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2208-14 is transferred from the die through the bottom-side exposed pad.
For good electrical and thermal performance, the exposed
pad must be soldered to a large grounded pad on the PC
board. It is critical that the exposed pad and all ground
pins are connected to a ground plane of sufficient area
with as many vias as possible.
220814f
26
LTC2208-14
U
PACKAGE DESCRIPTIO
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
7.15 ±0.05
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
9 .00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.115
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
7.15 ± 0.10
(4-SIDES)
0.25 ± 0.05
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
(UP64) QFN 1003
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
220814f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2208-14
RELATED PARTS
PART NUMBER
LTC1747
LTC1748
LTC1749
LTC1750
LT1993-2
LTC2202
LTC2203
LTC2204
LTC2205
LTC2206
LTC2207
LTC2208
LTC2220
LTC2220-1
LTC2249
LTC2250
LTC2251
LTC2252
LTC2253
LTC2254
LTC2255
LTC2299
LT5512
LT5514
LT5522
DESCRIPTION
12-Bit, 80MSPS ADC
14-Bit, 80Msps ADC
12-Bit, 80Msps Wideband ADC
14-Bit, 80Msps Wideband ADC
High Speed Differential Op Amp
16-Bit, 10MSPS ADC
16-Bit, 25MSPS ADC
16-Bit, 40Msps ADC
16-Bit, 65Msps ADC
16-Bit, 80Msps ADC
16-Bit, 105Msps ADC
16-Bit, 130Msps ADC
12-Bit, 170Msps ADC
12-Bit, 185Msps ADC
14-Bit, 65Msps ADC
10-Bit, 105Msps ADC
10-Bit, 125Msps ADC
12-Bit, 105Msps ADC
12-Bit, 125Msps ADC
14-Bit, 105Msps ADC
14-Bit, 125Msps ADC
Dual 14-Bit, 80Msps ADC
DC-3GHz High Signal Level
Downconverting Mixer
Ultralow Distortion IF Amplifier/ADC
Driver with Digitally Controlled Gain
600MHz to 2.7GHz High Linearity
Downconverting Mixer
COMMENTS
72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
Up to 500MHz IF Undersampling, 87dB SFDR
Up to 500MHz IF Undersampling, 90dB SFDR
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
140mW, 81.6dB SNR, 100dB SFDR
220mW, 81.6dB SNR, 100dB SFDR
480mW, 79.1dB SNR, 100dB SFDR
610mW, 79dB SNR, 100dB SFDR
725mW, 77.9dB SNR, 100dB SFDR
900mW, 77.9dB SNR, 100dB SFDR
1250mW, 77.7dB SNR, 100dB SFDR
890mW, 67.5dB SNR, 9mm x 9mm QFN Package
910mW, 67.5dB SNR, 9mm x 9mm QFN Package
230mW, 73dB SNR, 5mm x 5mm QFN Package
320mW, 61.6dB SNR, 5mm x 5mm QFN Package
395mW, 61.6dB SNR, 5mm x 5mm QFN Package
320mW, 70.2dB SNR, 5mm x 5mm QFN Package
395mW, 70.2dB SNR, 5mm x 5mm QFN Package
320mW, 72.5dB SNR, 5mm x 5mm QFN Package
395mW, 72.4dB SNR, 5mm x 5mm QFN Package
445mW, 73dB SNR, 9mm x 9mm QFN Package
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
220814f
28 Linear Technology Corporation
LT 0406 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
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FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006