LTC3677-3 Highly Integrated Portable Product PMIC Description Features Full Featured Li-Ion/Polymer Charger/PowerPath™ Controller with Instant-On Operation n Triple Adjustable High Efficiency Step-Down Switching Regulators (800mA, 500mA, 500mA IOUT) n I2C Adjustable SW Slew Rates for EMI Reduction n High Temperature Battery Voltage Reduction Improves Safety and Reliability n Overvoltage Protection Controller for USB (V BUS)/Wall Inputs Provide Protection to 30V n 1.5A Maximum Charge Current with Thermal Limiting n Battery Float Voltage:4.2V n Pushbutton ON/OFF Control with System Reset n Dual 150mA Current Limited LDOs n Start-Up Timing Compatible with SiRF Atlas IV Processor n Small 4mm × 7mm 44-Pin QFN Package n Applications PNDs, DMB/DVB-H, Digital/Satellite Radio, Media Players n Portable Industrial/Medical Products n Other USB-Based Handheld Products n The LTC®3677-3 is a highly integrated power management IC for single-cell Li-Ion/Polymer battery applications. It includes a PowerPath manager with automatic load prioritization, a battery charger, an ideal diode, input overvoltage protection and numerous other internal protection features. The LTC3677-3 is designed to accurately charge from current limited supplies such as USB by automatically reducing charge current such that the sum of the load current and the charge current does not exceed the programmed input current limit (100mA or 500mA modes). The LTC3677-3 reduces the battery voltage at elevated temperatures to improve safety and reliability. The three step-down switching regulators and two LDOs provide a wide range of available supplies. The LTC3677-3 also includes a pushbutton input to control power sequencing and system reset. The LTC3677-3 has pushbutton timing and sequencing designed to support the SiRF Atlas IV processor. The LTC3677-3 is available in a low profile 4mm × 7mm × 0.75mm 44-pin QFN package. L, LT, LTC, LTM, Linear Technology, PowerPath, Burst Mode and the Linear logo are registered trademarks and Bat-Track and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6522118, 6700364, 7511390, 5481178, 6580258. Other patents pending. Typical Application High Temperature BAT Discharge 5V ADAPTER OPTIONAL USB 200 100mA/500mA 1000mA VNTC < VTOO_HOT 180 VBUS = 0V VOUT CHARGE PB 140 CC/CV CHARGER LTC3677-3 2 160 0V I2C PORT PUSHBUTTON CONTROL + NTC 0.8V to 3.6V/150mA 0.8V to 3.6V/150mA DUAL LDO REGULATORS TRIPLE HIGH EFFICIENCY STEP-DOWN SWITCHING REGULATORS SINGLE-CELL Li-Ion 0.8V to 3.6V/800mA 0.8V to 3.6V/500mA 0.8V to 3.6V/500mA 36773 TA01a IBAT (mA) OVERVOLTAGE PROTECTION 120 100 80 60 40 20 0 3.8 3.9 4.0 VBAT (V) 4.1 4.2 36773 TA01b 36773f LTC3677-3 Table of Contents Features............................................................................................................................. 1 Applications........................................................................................................................ 1 Typical Application................................................................................................................ 1 Description......................................................................................................................... 1 Absolute Maximum Ratings...................................................................................................... 3 Order Information.................................................................................................................. 3 Pin Configuration.................................................................................................................. 3 Electrical Characteristics......................................................................................................... 4 Typical Performance Characteristics..........................................................................................10 Pin Functions......................................................................................................................15 Block Diagram.....................................................................................................................18 Operation..........................................................................................................................19 PowerPath OPERATION......................................................................................................................................... 19 Low Dropout Linear Regulator Operation.............................................................................................................. 27 Step-Down Switching Regulator Operation............................................................................................................ 28 I2C Operation......................................................................................................................................................... 32 Pushbutton Interface Operation............................................................................................................................. 36 Layout and Thermal Considerations...................................................................................................................... 40 Typical Application...............................................................................................................42 Package Description.............................................................................................................43 Typical Application...............................................................................................................44 Related Parts......................................................................................................................44 36773f LTC3677-3 Pin Configuration VBUS, VOUT , VIN12, VIN3, VINLDO1, VINLDO2, WALL t < 1ms and Duty Cycle < 1%.................... –0.3V to 7V Steady State............................................. –0.3V to 6V CHRG, BAT, PWR_ON, EXTPWR, PBSTAT, PGOOD, FB1, FB2, FB3, LDO1, LDO1_FB, LDO2, LDO2_FB, DVCC, SCL, SDA, EN3.................. –0.3V to 6V NTC, PROG, CLPROG, ON, ILIM0, ILIM1 (Note 4)............................................ –0.3V to VCC + 0.3V IVBUS, IVOUT , IBAT, Continuous (Note 16)......................2A ISW3, Continuous (Note 16).................................. 850mA ISW2, ISW1, Continuous (Note 16)......................... 600mA ILDO1, ILDO2, Continuous (Note 16)...................... 200mA ICHRG , IACPR , IEXTPWR , IPBSTAT, IPGOOD...................75mA IOVSENS...................................................................10mA ICLPROG, IPROG..........................................................2mA Operating Junction Temperature Range (Note 2)................................................–40°C to 85°C Maximum Junction Temperature............................110°C Storage Temperature Range................... –65°C to 125°C TOP VIEW 44 CHRG 43 CLPROG 42 EXTPWR 41 ACPR 40 VBUS 39 VOUT 38 BAT (Notes 1, 2, 3) ILIM0 1 ILIM1 2 NC 3 WALL 4 SW3 5 VIN3 6 FB3 7 OVSENS 8 NC 9 DVCC 10 SDA 11 SCL 12 OVGATE 13 PWR_ON 14 ON 15 45 GND 37 IDGATE 36 PROG 35 NTC 34 NTCBIAS 33 SW1 32 VIN12 31 SW2 30 VINLD02 29 LDO2 28 LDO1 27 VINLDO1 26 FB1 25 FB2 24 LDO2_FB 23 LDO1_FB PBSTAT 16 EN3 17 NC 18 NC 19 NC 20 PGOOD 21 NC 22 Absolute Maximum Ratings UFF PACKAGE 44-LEAD (7mm s 4mm) PLASTIC QFN TJMAX = 110°C, θJA = 45°C/W EXPOSED PAD (PIN 45) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3677EUFF-3#PBF LTC3677EUFF-3#TRPBF 36773 44-Lead (4mm × 7mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 36773f LTC3677-3 Electrical Characteristics Power Manager. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V, WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Power Supply VBUS Input Supply Voltage 4.35 IBUS_LIM Total Input Current (Note 5) ILIM0 = 5V, ILIM1 = 5V (1x Mode) ILIM0 = 0V, ILIM1 = 0V (5x Mode) ILIM0 = 0V, ILIM1 = 5V (10x Mode) IBUSQ Input Quiescent Current, POFF State 1x, 5x, 10x Modes ILIM0 = 5V, ILIM1 = 0V (Suspend Mode) hCLPROG Ratio of Measured VBUS Current to CLPROG Program Current VCLPROG CLPROG Servo Voltage in Current Limit 1x Mode 5x Mode 10x Mode VUVLO VBUS Undervoltage Lockout Rising Threshold Falling Threshold VDUVLO RON_ILIM l l l 80 450 900 3.5 5.5 V 90 475 950 100 500 1000 mA mA mA 0.42 0.05 0.1 mA mA 1000 mA/mA 0.2 1.0 2.0 V V V 3.8 3.7 3.9 V V VBUS to VOUT Differential Undervoltage Rising Threshold Lockout Falling Threshold 50 –50 100 mV mV Input Current Limit Power FET On-Resistance (Between VBUS and VOUT) 200 mΩ Battery Charger VFLOAT VBAT Regulated Output Voltage LTC3677-3 LTC3677-3, 0 ≤ TJ ≤ 85°C 4.179 4.165 4.200 4.200 4.221 4.235 V V ICHG Constant-Current Mode Charge Current RPROG = 1k, Input Current Limit = 2A IC Not in Thermal Limit RPROG = 2k, Input Current Limit = 1A RPROG = 5k, Input Current Limit = 0.4A 950 465 180 1000 500 200 1050 535 220 mA mA mA IBATQ_OFF Battery-Drain Current, POFF State, Buck3 Disabled, No Load (Note 14) VBAT = 4.3V, Charger Time Out VBUS = 0V 6 55 27 100 µA µA IBATQ_ON Battery-Drain Current, PON State, Buck3 Enabled (Notes 10, 14) VBUS = 0V, IOUT = 0µA, No Load On Supplies, Burst Mode® Operation 130 200 µA VPROG,CHG PROG Pin Servo Voltage VBAT > VTRKL 1.000 V VPROG,TRKL PROG Pin Servo Voltage in Trickle Charge VBAT < VTRKL 0.100 V hPROG Ratio of IBAT to PROG Pin Current 1000 mA/mA ITRKL Trickle Charge Current VBAT < VTRKL 40 50 60 mA VTRKL Trickle Charge Rising Threshold Trickle Charge Falling Threshold VBAT Rising VBAT Falling 2.5 2.9 2.75 3.0 V V ∆VRECHRG Recharge Battery Threshold Voltage Threshold Voltage Relative to VFLOAT –75 –100 –125 mV tTERM Safety Timer Termination Period Timer Starts when VBAT = VFLOAT – 50mV 3.2 4 4.8 Hour tBADBAT Bad Battery Termination Time VBAT < VTRKL 0.4 0.5 0.6 Hour hC/10 End-of-Charge Indication Current Ratio (Note 6) 0.085 0.1 0.11 mA/mA RON_CHG Battery Charger Power FET On-Resistance (Between VOUT and BAT) 200 mΩ TLIM Junction Temperature in ConstantTemperature Mode 110 °C l l l 36773f LTC3677-3 Electrical Characteristics Power Manager. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VBUS = 5V, VBAT = 3.8V, ILIM0 = ILIM1 = 5V, WALL = 0V, VINLDO2 = VINLOD1 = VIN12 = VIN3 = VOUT, RPROG = 2k, RCLPROG = 2.1k, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NTC, Battery Discharge Protection VCOLD Cold Temperature Fault Threshold Voltage Rising NTC Voltage Hysteresis 75 76 1.3 77 %VNTCBIAS %VNTCBIAS VHOT Hot Temperature Fault Threshold Voltage Falling NTC Voltage Hysteresis 34 35 1.3 36 %VNTCBIAS %VNTCBIAS VTOO_HOT NTC Discharge Threshold Voltage Falling NTC Voltage Hysteresis 24.5 25.5 50 26.5 %VNTCBIAS mV INTC NTC Leakage Current VNTC = VBUS = 5V –50 IBAT2HOT BAT Discharge Current VBAT = 4.1V, NTC < VTOO_HOT 170 mA VBAT2HOT BAT Discharge Threshold IBAT < 0.1mA, NTC < VTOO_HOT 3.9 V VFWD Forward Voltage Detection IOUT = 10mA RDROPOUT Diode On-Resistance, Dropout IOUT = 200mA 200 mΩ IMAX Diode Current Limit (Note 7) 3.6 A 50 nA Ideal Diode 5 15 25 mV Overvoltage Protection VOVCUTOFF Overvoltage Protection Threshold Rising Threshold, ROVSENS = 6.2k 6.10 VOVGATE OVGATE Output Voltage Input Below VOVCUTOFF Input Above VOVCUTOFF IOVSENSQ OVSENS Quiescent Current VOVSENS = 5V 40 µA tRISE OVGATE Time to Reach Regulation COVGATE = 1nF 2.5 ms 6.35 1.88 • VOVSENS 0 6.70 12 V V V Wall Adapter and High Voltage Buck Output Control VACPR ACPR Pin Output High Voltage ACPR Pin Output Low Voltage IACPR = 0.1mA IACPR = 1mA VOUT – 0.3 VOUT 0 0.3 V V VW Absolute Wall Input Threshold Voltage VWALL Rising VWALL Falling 3.1 4.3 3.2 4.45 V V ∆VW Differential Wall Input Threshold Voltage VWALL – VBAT Falling VWALL – VBAT Rising 0 25 75 100 mV mV IQWALL Wall Operating Quiescent Current IWALL + IVOUT , IBAT = 0mA, WALL = VOUT = 5V 440 µA Logic (ILIM0, ILIM1 and CHRG) VIL Input Low Voltage ILIM0, ILIM1 VIH Input High Voltage ILIM0, ILIM1 IPD Static Pull-Down Current ILIM0, ILIM1; VPIN = 1V VCHRG CHRG Pin Output Low Voltage ICHRG = 10mA ICHRG CHRG Pin Input Current VBAT = 4.5V, VCHRG = 5V 0.4 1.2 V V 2 µA 0.15 0.4 V 0 1 µA 36773f LTC3677-3 Electrical Characteristics I2C Interface. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. DVCC = 3.3V, VOUT = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP DVCC Input Supply Voltage IDVCC DVCC Supply Current VDVCC,UVLO DVCC UVLO 1.0 VIH Input High Voltage 50 VIL Input Low Voltage IIH Input High Leakage Current SDA = SCL = DVCC = 5.5V –1 1 µA IIL Input Low Leakage Current SDA = SCL = 0V, DVCC = 5.5V –1 1 µA VOL SDA Output Low Voltage ISDA = 3mA 0.4 V 400 kHz 1.6 SCL = 400kHz SCL = SDA = 0kHz 30 MAX UNITS 5.5 V 10 1 µA µA 70 %DVCC V 50 %DVCC Timing Characteristics (Note 8) (All Values Are Referenced to VIH and VIL) fSCL SCL Clock Frequency tLOW Low Period of the SCL Clock 1.3 µs tHIGH High Period of the SCL Clock 0.6 µs tBUF Bus Free Time Between Stop and Start Condition 1.3 µs tHD,STA Hold Time After (Repeated) Start Condition 0.6 µs tSU,STA Set-Up Time for a Repeated Start Condition 0.6 µs tSU,STO Stop Condition Set-Up Time 0.6 tHD,DATO Output Data Hold Time tHD,DATI Input Data Hold Time tSU,DAT Data Set-Up Time tSP Input Spike Suppression Pulse Width 0 µs 900 ns 0 ns 100 ns 50 ns 36773f LTC3677-3 Electrical Characteristics Step-Down Switching Regulators. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VOUT = VIN12 = VIN3 = 3.8V, all regulators enabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Step-Down Switching Regulators (Buck1, Buck2 and Buck3) VIN12, VIN3 Input Supply Voltage (Note 9) VOUT UVLO VOUT Falling VOUT Rising VIN12 and VIN3 Connected to VOUT Through Low Impedance. Switching Regulators Are Disabled Below VOUT UVLO 2.5 fOSC Oscillator Frequency 1.91 l 2.7 5.5 V 2.7 2.8 2.9 V V 2.25 2.59 MHz 800mA Step-Down Switching Regulator 3 (Buck3-Enabled via EN3, Disabled in PDN and POFF States) IVIN3Q Pulse-Skipping Mode Input Current (Note 10) 100 Burst Mode Operation Input Current (Note 10) 20 µA 35 µA Shutdown Input Current EN3 = 0 ILIM3 Peak P-Channel MOSFET Current Limit (Note 7) VFB3 Feedback Voltage Pulse-Skipping Mode Burst Mode Operation IFB3 FB3 Input Current (Note 10) –0.05 D3 Max Duty Cycle FB3 = 0V 100 RP3 RDS(ON) of P-Channel MOSFET 0.3 Ω RN3 RDS(ON) of N-Channel MOSFET 0.4 Ω RSW3_PD SW3 Pull-Down in Shutdown VIL,EN3 EN3 Input Low Voltage VIH,EN3 EN3 Input High Voltage l l 0.01 1 µA 1000 1400 1700 mA 0.78 0.78 0.8 0.8 0.82 0.824 V V 0.05 µA EN3 = 0 % 10 kΩ 0.4 1.2 V V 500mA Step-Down Switching Regulator 2 (Buck2-Pushbutton Enabled, Third in Sequence) IVIN12Q Pulse-Skipping Mode Input Current (Note 10) 100 Burst Mode Operation Input Current (Note 10) 20 Shutdown Input Current POFF State 0.01 1 µA ILIM2 Peak P-Channel MOSFET Current Limit (Note 7) 650 900 1200 mA VFB2 Feedback Voltage Pulse-Skipping Mode Burst Mode Operation 0.78 0.78 0.8 0.8 0.82 0.824 V V IFB2 FB2 Input Current (Note 10) –0.05 0.05 µA D2 Max Duty Cycle FB2 = 0V 100 RP2 RDS(ON) of P-Channel MOSFET ISW2 = 100mA 0.6 RN2 RDS(ON) of N-Channel MOSFET ISW2 = –100mA 0.6 Ω RSW2_PD SW2 Pull-Down in Shutdown POFF State 10 kΩ 100 µA l l µA µA % Ω 500mA Step-Down Switching Regulator 1 (Buck1-Pushbutton Enabled, Second in Sequence) IVIN12Q Pulse-Skipping Mode Input Current (Note 10) Burst Mode Operation Input Current (Note 10) 20 Shutdown Input Current µA 0.01 1 µA 650 900 1200 mA 0.78 0.78 0.8 0.8 0.82 0.824 V V 0.05 µA ILIM1 Peak P-Channel MOSFET Current Limit (Note 7) VFB1 Feedback Voltage Pulse-Skipping Mode Burst Mode Operation IFB1 FB1 Input Current (Note 10) –0.05 D1 Max Duty Cycle FB1 = 0V 100 RP1 RDS(ON) of P-Channel MOSFET ISW1 = 100mA 0.6 Ω RN1 RDS(ON) of N-Channel MOSFET ISW1 = –100mA 0.6 Ω RSW1_PD SW1 Pull-Down in Shutdown POFF State 10 kΩ l l % 36773f LTC3677-3 Electrical Characteristics LDO Regulators. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VINLDO1 = VINLDO2 = VOUT = 3.8V, LDO1 and LDO2 enabled unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LDO Regulator 1 (LDO1-Always On) VINLDO1 Input Voltage Range VINLDO1 ≤ VOUT + 0.3V VOUT_UVLO VOUT Falling VOUT Rising LDO1 Is Disabled Below VOUT UVLO VLDO1_FB LDO1_FB Regulated Feedback Voltage ILDO1 = 1mA LDO1_FB Line Regulation (Note 11) ILDO1 = 1mA, VIN = 1.65V to 5.5V LDO1_FB Load Regulation (Note 11) ILDO1 = 1mA to 150mA l l 1.65 5.5 V 2.5 2.7 2.8 2.9 V V 0.78 0.8 0.82 mV/V 5 µV/mA ILDO1_OC Available Output Current ILDO1_SC Short-Circuit Output Current (Note 7) VDROP1 Dropout Voltage (Note 12) ILDO1 = 150mA, VINLDO1 = 3.6V ILDO1 = 150mA, VINLDO1 = 2.5V ILDO1 = 75mA, VINLDO1 = 1.8V 160 200 170 RLDO1_PD Output Pull-Down Resistance in Shutdown LDO1 Disabled 10 ILDO_FB1 LDO_FB1 Input Current l V 0.4 150 mA 270 –50 mA 260 320 280 mV mV mV kΩ 50 nA LDO Regulator 2 (LDO2-Pushbutton Enabled, First in Sequence) VINLDO2 Input Voltage Range VINLDO2 ≤ VOUT + 0.3V VOUT_UVLO VOUT Falling VOUT Rising LDO2 is Disabled Below VOUT UVLO VLDO2_FB LDO2_FB Regulated Output Voltage ILDO2 = 1mA LDO2_FB Line Regulation (Note 11) ILDO2 = 1mA, VIN = 1.65V to 5.5V LDO2_FB Load Regulation (Note 11) ILDO2 = 1mA to 150mA l l 1.65 5.5 V 2.5 2.7 2.8 2.9 V V 0.78 0.8 0.82 mV/V 5 µV/mA ILDO2_OC Available Output Current ILDO2_SC Short-Circuit Output Current (Note 7) VDROP2 Dropout Voltage (Note 12) ILDO2 = 150mA, VINLDO2 = 3.6V ILDO2 = 150mA, VINLDO2 = 2.5V ILDO1 = 75mA, VINLDO1 = 1.8V 160 200 170 RLDO2_PD Output Pull-Down Resistance in Shutdown LDO2 Disabled 14 ILDO_FB2 LDO_FB2 Input Current l 150 mA 270 –50 V 0.4 mA 260 320 280 mV mV mV kΩ 50 nA 36773f LTC3677-3 Electrical Characteristics Pushbutton Controller. The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TJ = 25°C. VOUT = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Pushbutton Pin (ON) VOUT Pushbutton Operating Supply Range (Note 9) VOUT UVLO VOUT Falling VOUT Rising Pushbutton is Disabled Below VOUT UVLO VON_TH ON Threshold Rising ON Threshold Falling ION ON Input Current l VON = VOUT VON = 0V 2.7 5.5 V 2.5 2.7 2.8 2.9 V V 0.4 0.8 0.7 1.2 V V –1 –4 –9 1 –14 μA μA 0.4 0.8 0.7 1.2 V V Power-On Input Pin (PWR_ON) VPWR_ON PWR_ON Threshold Rising PWR_ON Threshold Falling IPWR_ON PWR_ON Input Current VPWR_ON = 3V –1 –1 1 μA Status Output Pins (PBSTAT, EXTPWR, PGOOD) IPBSTAT PBSTAT Output High Leakage Current VPBSTAT = 3V 1 μA VPBSTAT PBSTAT Output Low Voltage IPBSTAT = 3mA 0.1 0.4 V IEXTPWR EXTPWR Pin Input Current VEXTPWR = 3V 0 1 μA VEXTPWR EXTPWR Pin Output Low Voltage IEXTPWR = 2mA 0.15 0.4 V IPGOOD PGOOD Output High Leakage Current VPGOOD = 3V 1 μA VPGOOD PGOOD Output Low Voltage IPGOOD = 3mA 0.1 VTHPGOOD PGOOD Threshold Voltage (Note 13) –8 % 50 ms PBSTAT Low > tPBSTAT_PW 900 μs 50 ms 50 ms –1 0.4 V Pushbutton Timing Parameters tON_PBSTAT1 ON Low Time to PBSTAT Low tON_PBSTAT2 ON High to PBSTAT High tPBSTAT_PW PBSTAT Minimum Pulse Width tON_PUP ON Low Time for Power-Up tON_RST ON Low to PGOOD Reset Low tON_RST_PW PGOOD Reset Low Pulse Width tPUP_PDN Minimum Time from Power Up to Down 1 Seconds tPDN_PUP Minimum Time from Power Down to Up 1 Seconds tPWR_ONH PWR_ON High to Power-Up 50 ms tPWR_ONL PWR_ON Low to Power-Down 50 ms tPWR_ONBK1 PWR_ON Power-Up Blanking PWR_ON Low Recognized from Power-Up 1 Seconds tPWR_ONBK2 PWR_ON Power-Down Blanking PWR_ON High Recognized from Power-Down 1 Seconds tPGOODH From Regulation to PGOOD High Buck1, 2 and LDO1 Within PGOOD Threshold 230 tPGOODL Bucks Disabled to PGOOD Low Bucks Disabled tLDO2_BK1 LDO2 Enable to Buck Enable 40 12 14 16.5 1.8 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3677-3 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. Note that the maximum Seconds ms ms 44 12.5 14.5 µs 17.5 ms ambient temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: This IC includes over temperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 110°C when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. 36773f LTC3677-3 Electrical Characteristics Note 4: VCC is the greater of VBUS, VOUT or BAT. Note 5: Total input current is the sum of quiescent current, IBUSQ, and measured current given by VCLPROG/RCLPROG • (hCLPROG + 1). Note 6: hC/10 is expressed as a fraction of measured full charge current with indicated PROG resistor. Note 7: The current limit features of this part are intended to protect the IC from short term or intermittent fault conditions. Continuous operation above the maximum specified pin current rating may result in device degradation or failure. Note 8: The serial port is tested at rated operating frequency. Timing parameters are tested and/or guaranteed by design. Note 9: VOUT not in UVLO. Note 10: Buck FB high, not switching. Note 11: Measured with the LDO running unity gain with output tied to feedback pin. Note 12: Dropout voltage is the minimum input to output voltage differential needed for an LDO to maintain regulation at a specified output current. When an LDO is in dropout, its output voltage will be equal to VIN – VDROP . Note 13: PGOOD threshold is expressed as a percentage difference from the Buck1, Buck2 and LDO1 regulation voltages. The threshold is measured from Buck1, Buck2 and LDO1 output rising. Note 14: The IBATQ specifications represent the total battery load assuming VINLDO1, VINLDO2, VIN12 and VIN3 are tied directly to VOUT . Note 15: Long-term current density rating for the part. Typical Performance Characteristics TJ = 25°C unless otherwise specified Input Supply Current vs Temperature 0.7 0.10 VBUS = 5V 1x MODE 450 VBUS = 5V 350 NO LOAD ON ALL SUPPLIES VBAT = 3.8V VBUS = 0V 300 IVBUS (mA) 0.5 0.4 0.3 0.06 0.04 250 200 150 0.2 50 0 50 75 25 TEMPERATURE (°C) 100 125 36773 G01 0 –50 ALL SUPPLIES ENABLED Burst Mode OPERATION 100 0.02 0.1 0 –50 –25 ALL SUPPLIES ENABLED PULSE-SKIPPING MODE 400 0.08 0.6 IVBUS (mA) Battery-Drain Current vs Temperature IBAT (µA) 0.8 Input Supply Current vs Temperature (Suspend Mode) –25 50 25 0 75 TEMPERATURE (°C) 100 125 36773 G02 0 –50 ALL SUPPLIES DISABLED EXCEPT LDO1 –25 50 25 0 75 TEMPERATURE (°C) 100 125 36773 G03 36773f 10 LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified 10x MODE 240 700 220 600 RON (mΩ) IVBUS (mA) 800 5x MODE 500 120 1x MODE 100 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 0 –50 125 6 4.24 5 4.22 4 300 3 200 SAFETY TIMER 2 TERMINATION C/10 IBAT 5 6 0 4.10 4.18 0 200 400 600 IBAT (mA) 2.8 4.04 –50 –25 1000 800 3.2 3.6 VBAT (V) VBAT = 3.2V 36773 G10 0 125 36773 G09 30 VBAT = 3.6V VBAT = 4.2V VFWD (V) 4.4 100 VBAT = 3.8V VBUS = 0V TA = 25°C 35 25 20 15 10 0.05 4.0 50 75 25 TEMPERATURE (°C) Forward Voltage vs Ideal Diode Current (with Si2333DS External FET) 40 VBUS = 0V TA = 25°C 0 357734 G08 0.10 VBUS = 5V 10x MODE RPROG = 2k RCLPROG = 2k 2.4 4.12 4.06 0.15 FALLING VBAT 2.0 4.14 4.10 0.20 100 4.16 4.08 0.25 RISING VBAT 357734 G06 4.20 Forward Voltage vs Ideal Diode Current (No External FET) 500 125 IBAT = 2mA 4.22 36773 G07 600 200 4.24 VBUS = 5V 10x MODE 4.14 4.12 100 Battery Regulation (Float) Voltage vs Temperature 4.16 1 50 25 75 0 TEMPERATURE (°C) 36773 G05 4.18 IBAT vs VBAT 300 0 –50 –25 125 100 4.20 VFLOAT (V) 400 VBAT AND VCHRG (V) VBAT 400 50 25 0 75 TEMPERATURE (°C) Battery Float Voltage Load Regulation CHRG 3 4 TIME (HOUR) –25 36773 G04 600 1450mAhr CELL 100 VBUS = 5V RPROG = 2k RCLPROG = 2k 0 0 2 1 VBUS = 5V 10x MODE RPROG = 2k 100 100 Battery Current and Voltage vs Time 500 300 200 140 200 IBAT (mA) 400 VBUS = 5.5V 160 300 IBAT (mA) VBUS = 4.5V VBUS = 5V 180 400 Charge Current vs Temperature (Thermal Regulation) 500 260 900 0 600 IOUT = 400mA 280 IBAT (mA) 1000 300 VBUS = 5V RCLPROG = 2.1k VBAT (V) 1100 Input RON vs Temperature VFWD (mV) 1200 Input Current Limit vs Temperature 5 0 0.2 0.4 0.6 IBAT (A) 0.8 1.0 1.2 36773 G11 0 0 0.2 0.4 0.6 IBAT (A) 0.8 1.0 36773 G12 36773f 11 LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified Input Disconnect Waveform Input Connect Waveform Switching from 1x to 5x Mode VBUS 5V/DIV VBUS 5V/DIV VOUT 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV IBUS 0.5A/DIV IBUS 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k 36773 G13 1ms/DIV ILIM0/ILIM1 5V/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k Switching from Suspend Mode to 5x Mode 36773 G14 1ms/DIV VBAT = 3.75V IOUT = 50mA RCLPROG = 2k RPROG = 2k WALL Connect Waveform WALL 5V/DIV WALL 5V/DIV VOUT 5V/DIV IBUS 0.5A/DIV VOUT 5V/DIV IWALL 0.5A/DIV VOUT 5V/DIV IWALL 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV IBAT 0.5A/DIV 36773 G16 100µs/DIV VBAT = 3.75V IOUT = 100mA RPROG = 2k 36773 G17 1ms/DIV Oscillator Frequency vs Temperature 100 VBAT = 3.75V IOUT = 100mA RPROG = 2k Burst Mode 90 OPERATION 2.6 80 2.5 70 VOUT = 5V 2.3 2.2 VOUT = 3.8V 2.1 1ms/DIV PULSE-SKIPPING 60 50 40 30 2.0 20 VOUT1 = 3.3V 1.9 10 VIN12 = 3.8V VIN12 = 5V 1.8 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 36773 G19 36773 G18 Step-Down Switching Regulator 1 3.3V Output Efficiency vs IOUT1 2.7 EFFICIENCY (%) FREQUENCY (MHz) 2.8 2.4 36773 G15 WALL Disconnect Waveform ILIM0 5V/DIV VBAT = 3.75V IOUT = 100mA RCLPROG = 2k RPROG = 2k ILIM1 = 5V 1ms/DIV 0 0.01 0.1 1 10 IOUT (mA) 100 1000 36773 G20 36773f 12 LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified EFFICIENCY (%) 80 100 90 Burst Mode OPERATION PULSE-SKIPPING 60 50 40 60 VOUT2 = 1.8V 20 10 VIN12 = 3.8V VIN12 = 5V 0 0.01 0.1 1 10 IOUT (mA) 100 1000 900 500mA BUCK 800 IOUT3 700 600 500 –50 –25 5mA 0 50 75 25 TEMPERATURE (°C) 100 125 36773 G24 SWITCH IMPEDANCE (Ω) 0.8 VINX = 3.2V 0.7 0.6 500mA NMOS 500mA PMOS 0.5 0.4 800mA PMOS 0.3 0 –50 0.85 0.84 0.84 0.83 0.83 0 25 50 75 TEMPERATURE (°C) 100 125 36773 G27 1000 36773 G23 0.81 0.80 0.79 0.75 0.1 36773 G26 VOUT1 = 3.3V 50µs/DIV IOUT1 = 30mA VOUT2 = 1.8V IOUT2 = 20mA VOUT3 = 1.2V VOUT = VBAT = 3.8V 0.82 Burst Mode OPERATION PULSE-SKIPPING Burst Mode OPERATION 0.81 0.80 0.79 PULSE-SKIPPING 0.78 0.77 VIN3 = 3.8V VIN3 = 5V 0.76 –25 5mA 0.85 0.77 0.1 100 500mA Step-Down Switching Regulator Feedback Voltage vs Output Current 0.78 800mA NMOS 0.2 1 10 IOUT (mA) 500mA 36773 G25 VOUT1 = 3.3V 50µs/DIV IOUT1 = 10mA VOUT2 = 1.8V IOUT2 = 20mA VOUT3 = 1.2V VOUT = VBAT = 3.8V 0.82 FEEDBACK (V) 0.9 IOUT3 800mA Step-Down Switching Regulator Feedback Voltage vs Output Current Step-Down Switching Regulator Switch Impedance vs Temperature 0.1 VOUT1 50mV/DIV (AC) VOUT2 50mV/DIV (AC) VOUT3 100mV/DIV (AC) 500mA VINx = 3.8V VINx = 5V VOUT3 = 2.5V VIN3 = 3.8V VIN3 = 5V Step-Down Switching Regulator Output Transient (Pulse-Skipping) FEEDBACK (V) SHORT-CIRCUIT CURRENT (mA) 1100 30 0 0.01 1000 VOUT1 50mV/DIV (AC) VOUT2 50mV/DIV (AC) VOUT3 100mV/DIV (AC) 800mA BUCK 1200 40 10 1500 1300 50 Step-Down Switching Regulator Output Transient (Burst Mode Operation) Step-Down Switching Regulator Short-Circuit Current vs Temperature PULSE-SKIPPING 60 36773 G22 36773 G21 1400 70 20 VOUT3 = 1.2V VIN3 = 3.8V VIN3 = 5V 10 1000 Burst Mode OPERATION 80 40 20 100 90 PULSE-SKIPPING 50 30 1 10 IOUT (mA) 100 70 30 0.1 Step-Down Switching Regulator 3 2.5V Output Efficiency Burst Mode OPERATION 80 70 0 0.01 Step-Down Switching Regulator 3 1.2V Output Efficiency vs IOUT3 EFFICIENCY (%) 90 EFFICIENCY (%) 100 Step-Down Switching Regulator 2 1.8V Output Efficiency vs IOUT2 1 10 IOUT (mA) 100 1000 357732 G29 VIN12 = 3.8V VIN12 = 5V 0.76 0.75 0.1 1 10 IOUT (mA) 100 1000 36773 G29 36773f 13 LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified Step-Down Switching Regulator 3 Soft-Start and Shutdown OVP Connection Waveform VOUT1 100mV/DIV (AC) 2V VBUS 5V/DIV VOUT3 1V 0V OVGATE 5V/DIV 400mA IL3 200mA 0mA VOUT1 = 1.8V IOUT1 = 100mA ROUT3 = 3Ω 36773 G30 50µs/DIV OVP INPUT VOLTAGE 0V TO 5V STEP 5V/DIV OVP Protection Waveform 36773 G31 500µs/DIV OVP Reconnection Waveform VBUS 5V/DIV VBUS 5V/DIV OVGATE 5V/DIV OVP INPUT VOLTAGE 5V TO 10V STEP 5V/DIV 36773 G32 500µs/DIV OVGATE 5V/DIV OVP INPUT VOLTAGE 10V TO 5V STEP 5V/DIV Rising Overvoltage Threshold vs Temperature OVSENS Quiescent Current vs Temperature 6.280 VOVSENS = 5V 35 6.275 OPV THRESHOLD (V) QUIESCENT CURRENT (µA) 37 33 31 29 27 –40 36773 G33 500µs/DIV 6.270 6.265 6.260 –15 35 10 TEMPERATURE (°C) 60 85 36773 G34 6.255 –40 –15 35 10 TEMPERATURE (°C) 60 85 36773 G35 36773f 14 LTC3677-3 Typical Performance Characteristics TJ = 25°C unless otherwise specified OVGATE vs OVSENS LDO Load Step Too Hot BAT Discharge 200 12 OVSENS CONNECTED TO INPUT THROUGH 10 6.2k RESISTOR VNTC < VTOO_HOT 180 VBUS = 0V LDO1 50mV/DIV (AC) 160 140 LDO2 20mV/DIV (AC) 6 4 IOUT1 2 0 IBAT (mA) OVGATE (V) 8 0 2 4 6 INPUT VOLTAGE (V) 8 20 0 CURRENT (mA) BATTERY DISCHARGE CURRENT (mA) 400 125 VBUS = 0V 75 50 60 70 90 100 80 TEMPERATURE (°C) 4.0 VBAT (V) 4.1 4.2 36773 G38 IIN ILOAD 300 IBAT (CHARGING) 200 100 VBAT = 4.1V VNTC < VTOO_HOT 5x MODE IVOUT = 0mA 25 0 RPROG = 2k RCLPROG = 2k 500 VBUS = 5V 50 3.9 Input and Battery Current vs Output Current 600 100 3.8 36773 G36 200 150 80 40 36773 G37 LDO1 = 1.2V 20µs/DIV LDO2 = 2.5V ILDO2 = 40mA VOUT = VBAT = 3.8V Battery Discharge vs Temperature 175 100 60 100mA 5mA 120 0 110 120 36773 G39 –100 IBAT (DISCHARGING) WALL = 0V 0 100 200 400 300 IOUT (mA) 500 600 36773 G40 Pin Functions ILIM0, ILIM1 (Pins 1, 2): Input Current Control Pins. ILIM0 and ILIM1 control the input current limit. See Table 1 in the USB PowerPath Controller section. Both pins are pulled low by a weak current sink. SW3 (Pin 5): Power Transmission (Switch) Pin for StepDown Switching Regulator 3 (Buck3). NC (Pins 3, 9, 18, 19, 20, 22): No Connect. This pin has no function and may be floated or connected to ground. FB3 (Pin 7): Feedback Input for Step-Down Switching Regulator 3 (Buck3). This pin servos to a fixed voltage of 0.8V when the control loop is complete. WALL (Pin 4): Wall Adapter Present Input. Pulling this pin above 4.3V will disconnect the power path from VBUS to VOUT. The ACPR pin will also be pulled low to indicate that a wall adapter has been detected. VIN3 (Pin 6): Power Input for Step-Down Switching Regulator 3. This pin should be connected to VOUT. OVSENSE (Pin 8): Overvoltage Protection Sense Input. OVSENSE should be connected through a 6.2k resistor to the input power connector and the drain of an external 36773f 15 LTC3677-3 Pin Functions N-channel MOSFET pass transistor. When the voltage on this pin exceeds a preset level, the OVGATE pin will be pulled to GND to disable the pass transistor and protect downstream circuitry. DVCC (Pin 10): Supply Voltage for I2C Lines. This pin sets the logic reference level of the LTC3677-3. A UVLO circuit on the DVCC pin forces all registers to all 0s whenever DVCC is <1V. Bypass to GND with a 0.1µF capacitor. SDA (Pin 11): I2C Data Input. Serial data is shifted one bit per clock to control the LTC3677-3. The logic level for SDA is referenced to DVCC. I2C SCL (Pin 12): Clock Input. The logic level for SCL is referenced to DVCC. value. There is a 230ms delay from all regulators reaching regulation and PGOOD going high. LDO1_FB (Pin 23): Feedback Voltage Input for Low Dropout Linear Regulator 1 (LDO1). LDO1 output voltage is set using an external resistor divider between LDO1 and LDO1_FB. LDO2_FB (Pin 24): Feedback Voltage Input for Low Dropout Linear Regulator 2 (LDO2). LDO2 output voltage is set using an external resistor divider between LDO2 and LDO2_FB. FB2 (Pin 25): Feedback Input for Step-Down Switching Regulator 2 (Buck2). This pin servos to a fixed voltage of 0.8V when the control loop is complete. OVGATE (Pin 13): Overvoltage Protection Gate Output. Connect OVGATE to the gate pin of an external N-channel MOSFET pass transistor. The source of the transistor should be connected to VBUS and the drain should be connected to the product’s DC input connector. In the absence of an overvoltage condition, this pin is connected to an internal charge pump capable of creating sufficient overdrive to fully enhance this transistor. If an overvoltage condition is detected, OVGATE is brought rapidly to GND to prevent damage. OVGATE works in conjunction with OVSENSE to provide this protection. FB1 (Pin 26): Feedback Input for Step-Down Switching Regulator 1 (Buck1). This pin servos to a fixed voltage of 0.8V when the control loop is complete. PWR_ON (Pin 14): Logic Input Used to Keep Buck1, Buck2 and LDO2 Enabled After Power-Up. May also be used to enable regulators directly (sequence = LDO2 → Buck1 → Buck2). See the Pushbutton Interface Operation section for more information. LDO2 (Pin 29): Output of Low Dropout Linear Regulator 2. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor. ON (Pin 15): Pushbutton Input. A weak internal pull-up forces ON high when left floating. A normally open pushbutton is connected from ON to ground to force a low state on this pin. PBSTAT (Pin 16): Open-drain output is a debounced and buffered version of ON to be used for processor interrupts. EN3 (Pin 17): Enable Pin for Step-Down Switching Regulator 3 (Buck3). PGOOD (Pin 21): Open-Drain Output. PGOOD indicates that Buck1, Buck2 and LDO1 are within 8% of final regulation VINLDO1 (Pin 27): Input Supply of Low Dropout Linear Regulator 1 (LDO1). This pin should be bypassed to ground with a 1µF or greater ceramic capacitor. LDO1 (Pin 28): Output of Low Dropout Linear Regulator 1. LDO1 is an always-on LDO and will be enabled whenever the part is not in VOUT UVLO. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor. VINLDO2 (Pin 30): Input Supply of Low Dropout Linear Regulator 2 (LDO2). This pin should be bypassed to ground with a 1µF or greater ceramic capacitor. SW2 (Pin 31): Power Transmission (Switch) Pin for StepDown Switching Regulator 2 (Buck2). VIN12 (Pin 32): Power Input for Step-Down Switching Regulators 1 and 2. This pin will generally be connected to VOUT. SW1 (Pin 33): Power Transmission (Switch) Pin for StepDown Switching Regulator 1 (Buck1). NTCBIAS (Pin 34): Output Bias Voltage for NTC. A resistor from this pin to the NTC pin will bias the NTC thermistor. 36773f 16 LTC3677-3 Pin Functions NTC (Pin 35): The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the battery’s temperature is out of range, charging is paused until it drops back into range. A low drift bias resistor is required from NTCBIAS to NTC and a thermistor is required from NTC to ground. PROG (Pin 36): Charge Current Program and Charge Current Monitor Pin. Connecting a resistor from PROG to ground programs the charge current: ICHG = 1000 V A RPROG ( ) If sufficient input power is available in constant-current mode, this pin servos to 1V. The voltage on this pin always represents the actual charge current. IDGATE (Pin 37): Ideal Diode Gate Connection. This pin controls the gate of an optional external P-channel MOSFET transistor used to supplement the internal ideal diode. The source of the P-channel MOSFET should be connected to VOUT and the drain should be connected to BAT. It is important to maintain high impedance on this pin and minimize all leakage paths. BAT (Pin 38): Single-Cell Li-Ion Battery Pin. Depending on available power and load, a Li-Ion battery on BAT will either deliver system power to VOUT through the ideal diode or be charged from the battery charger. VOUT (Pin 39): Output Voltage of the PowerPath Controller and Input Voltage of the Battery Charger. The majority of the portable product should be powered from VOUT. The LTC3677-3 will partition the available power between the external load on VOUT and the internal battery charger. Priority is given to the external load and any extra power is used to charge the battery. An ideal diode from BAT to VOUT ensures that VOUT is powered even if the load exceeds the allotted input current from VBUS or if the VBUS power source is removed. VOUT should be bypassed with a low impedance multilayer ceramic capacitor. VBUS (Pin 40): USB Input Voltage. VBUS will usually be connected to the USB port of a computer or a DC output wall adapter. VBUS should be bypassed with a low impedance multilayer ceramic capacitor. ACPR (Pin 41): Wall Adapter Present Output (Active Low). A low on this pin indicates that the wall adapter input comparator has had its input pulled above its input threshold (typically 4.3V). This pin can be used to drive the gate of an external P-channel MOSFET to provide power to VOUT from a power source other than a USB port. EXTPWR (Pin 42): External Power Present Output (Active Low, Open-Drain Output). A low on this pin indicates that external power is present at either the VBUS or WALL input. For EXTPWR to signal VBUS present, VBUS must exceed the VBUS undervoltage lockout threshold. For EXTPWR to signal WALL present, WALL must exceed the absolute and differential WALL input thresholds. The EXTPWR signal is independent of the ILIM1 and ILIM0 pins. Thus, it is possible to have the input current limit circuitry in suspend with EXTPWR showing a valid charging level on VBUS. CLPROG (Pin 43): Input Current Program and Input Current Monitor Pin. A resistor from CLPROG to ground determines the upper limit of the current drawn from the VBUS pin (i.e., the input current limit). A precise fraction of the input current, hCLPROG, is sent to the CLPROG pin. The input PowerPath delivers current until the CLPROG pin reaches 2V (10x mode), 1V (5x mode) or 0.2V (1x mode). Therefore, the current drawn from VBUS will be limited to an amount given by hCLPROG and RCLPROG. In USB applications the resistor RCLPROG should be set to no less than 2.1k. CHRG (Pin 44): Open-Drain Charge Status Output. The CHRG pin indicates the status of the battery charger. If CHRG is high then the charger is near the float voltage (charge current less than 1/10th programmed charge current) or charging is complete and charger is disabled. A low on CHRG indicates that the charger is enabled. For more information see the Charge Status Indication section. GND (Exposed Pad Pin 45): The exposed package pad is ground and must be soldered to PCB ground for electrical contact and rated thermal performance. 36773f 17 LTC3677-3 Block Diagram 8 13 OVSENS OVERVOLTAGE PROTECTON 40 43 34 35 42 OVGATE EXTERNAL POWER DETECT 44 INPUT CURRENT LIMIT CLPROG NTCBIAS BATTERY TEMP MONITOR 15 16 17 10 11 12 21 WALL DETECT NTC CC/CV CHARGER IDEAL DIODE OVERTEMP BATTERY SAFETY DISCHARGER – + + – 15mV IDGATE BAT PROG UVLO ILIM LOGIC EN CHRG 14ms RISING DELAY CHARGE STATUS 14 ACPR VOUT ILIM1 2 41 WALL VBUS ILIM0 1 4 EXTPWR 0.8V 150mA LDO2 – + PUSHBUTTON INPUT ON PBSTAT 0.8V + – DVCC EN 500mA, 2.25MHz BUCK REGULATOR 2 I2C SDA LOGIC SCL 0.8V PGOOD + – EN 800mA, 2.25MHz BUCK REGULATOR 3 0.8V NC 3, 9, 18, 19, 20, 22 ENB PG 150mA LDO1 GND 45 + – 0.8V SW1 SW2 FB2 PG 230ms FALLING DELAY VIN12 FB1 PG EN3 LDO2 LDO2_FB EN 500mA, 2.25MHz BUCK REGULATOR 1 PWR_ON VINLD02 VIN3 SW3 FB3 – + VINLD01 LDO1 LDO1_FB 39 37 38 36 30 29 24 32 33 26 31 25 6 5 7 27 28 23 36773 BD 36773f 18 LTC3677-3 Operation PowerPath OPERATION Introduction The LTC3677-3 is highly integrated power management IC that includes the following features: – PowerPath controller – Battery charger – Ideal diode – Input overvoltage protection – Pushbutton controller – Three step-down switching regulators – Two low dropout linear regulators Designed specifically for USB applications, the PowerPath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current does not violate the USB average input current specification. The ideal diode from BAT to VOUT guarantees that ample power is always available to VOUT even if there is insufficient or absent power at VBUS. The LTC3677-3 also has the ability to receive power from a wall adapter or other non-current-limited power source. Such a power supply can be connected to the VOUT pin of the LTC3677-3 through an external device such as a power Schottky or FET, as shown in Figure 1. The LTC3677-3 has the unique ability to use the output, which is powered by an external supply, to charge the battery while providing power to the load. A comparator on the WALL pin is configured to detect the presence of the wall adapter and shut off the connection to the USB. This prevents reverse conduction from VOUT to VBUS when a wall adapter is present. The LTC3677-3 also includes a pushbutton input to control the power sequencing of two synchronous step-down switching regulators (Buck1 and Buck2), a low dropout regulator (LDO2) and system reset. The three 2.25MHz constant-frequency current mode step-down switching regulators provide 500mA, 500mA and 800mA each and FROM AC ADAPTER 4 FROM USB WALL 4.3V (RISING) 3.2V (FALLING) ACPR + – + – 40 – + VBUS 75mV (RISING) 25mV (FALLING) ENABLE VOUT VOUT 41 39 SYSTEM LOAD USB CURRENT LIMIT IDEAL DIODE CONSTANT-CURRENT CONSTANT-VOLTAGE BATTERY CHARGER – + + – IDGATE OPTIONAL EXTERNAL IDEAL DIODE PMOS 37 15mV BAT BAT 38 36773 F01 + Li-Ion Figure 1. Simplified PowerPath Block Diagram 36773f 19 LTC3677-3 OPERATION support 100% duty cycle operation as well as operating in Burst Mode operation for high efficiency at light load. No external compensation components are required for the switching regulators. The two low dropout regulators can output up to 150mA. All regulators can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory or other logic circuitry. The input current limit is programmed by the ILIM0 and ILIM1 pins. The LTC3677-3 can be configured to limit input current to one of several possible settings as well as be deactivated (USB suspend). The input current limit will be set by the appropriate servo voltage and the resistor on CLPROG according to the following expression: IVBUS = IBUSQ + IVBUS = IBUSQ + USB PowerPath Controller The input current limit and charge control circuits of the LTC3677-3 is designed to limit input current as well as control battery charge current as a function of IVOUT . VOUT drives the combination of the external load, the three step-down switching regulators, two LDOs and the battery charger. If the combined load does not exceed the programmed input current limit, VOUT will be connected to VBUS through an internal 200mΩ P-channel MOSFET. If the combined load at VOUT exceeds the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satisfied while maintaining the programmed input current. Even if the battery charge current is set to exceed the allowable USB current, the average input current USB specification will not be violated. Furthermore, load current at VOUT will always be prioritized and only excess available current will be used to charge the battery. The current out of the CLPROG pin is a fraction (1/hCLPROG) of the VBUS current. When a programming resistor is connected from CLPROG to GND, the voltage on CLPROG represents the input current: IVBUS = IBUSQ + IVBUS = IBUSQ + 0.2V RCLPROG 1V RCLPROG 2V RCLPROG ( ) ( ) • hCLPROG 1x Mode • hCLPROG 5x Mode ( • hCLPROG 10 x Mode ) Under worst-case conditions, the USB specification for average input current will not be violated with an RCLPROG resistor of 2.1k or greater. Table 1 shows the available settings for the ILIM0 and ILIM1 pins: Table 1. Controlled Input Current Limit ILIM1 ILIM0 IBUS(LIM) 1 1 100mA (1x) 1 0 1A (10x) 0 1 Suspend 0 0 500mA (5x) Notice that when ILIM0 is low and ILIM1 is high, the input current limit is set to a higher current limit for increased charging and current availability at VOUT . This mode is typically used when there is a higher power, non-USB source available at the VBUS pin. VCLPROG •h RCLPROG CLPROG where IBUSQ and hCLPROG are given in the Electrical Characteristics table. 36773f 20 LTC3677-3 OPERATION Ideal Diode from BAT to VOUT The LTC3677-3 has an internal ideal diode as well as a controller for an optional external ideal diode. Both the internal and the external ideal diodes respond quickly whenever VOUT drops below BAT. If the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diodes. Furthermore, if power to VBUS (USB) or VOUT (external wall power or high voltage regulator) is removed, then all of the application power will be provided by the battery via the ideal diodes. The ideal diodes are fast enough to keep VOUT from dropping significantly below VBAT with just the recommended output capacitor (see Figure 2). The ideal diode consists of a precision amplifier that enables an on-chip P-channel MOSFET whenever the voltage at VOUT is approximately 15mV (VFWD) below the voltage at BAT. The resistance of the internal ideal diode is approximately 200mΩ. If this is sufficient for the application, then no external components are necessary. However, if lower resistance is needed, an external P-channel MOSFET can be added from BAT to VOUT . The IDGATE pin of the LTC3677-3 drives the gate of the external P-channel MOSFET for automatic ideal diode control. The source of the MOSFET should be connected to VOUT and the drain should be connected to BAT. Capable of driving a 1nF load, the IDGATE pin can control an external P-channel MOSFET having extremely low on-resistance. VOUT 3.8V 0 –500mA IVOUT LOAD 1.The WALL pin voltage must exceed approximately 4.3V. 2.The WALL pin voltage must be greater than 75mV above the BAT pin voltage. The input power path (between VBUS and VOUT) is re- enabled and the ACPR pin is pulled high when either of the following conditions is met: 1.The WALL pin voltage falls to within 25mV of the BAT pin voltage. 2.The WALL pin voltage falls below 3.2V. Suspend Mode 3.6V IBAT The WALL input pin can be used to identify the presence of an external power source (particularly one that is not subject to a fixed current limit like the USB VBUS input). Typically, such a power supply would be a 5V wall adapter output or the low voltage output of a high voltage buck regulator. When the wall adapter output (or buck regulator output) is connected directly to the WALL pin, and the voltage exceeds the WALL pin threshold, the USB power path (from VBUS to VOUT) will be disconnected. Furthermore, the ACPR pin will be pulled low. In order for the presence of an external power supply to be acknowledged, both of the following conditions must be satisfied: Each of these thresholds is suitably filtered in time to prevent transient glitches on the WALL pin from falsely triggering an event. 4.0V 500mA Using the WALL Pin to Detect the Presence of an External Power Source CHARGE DISCHARGE 1A 0A VBAT = 3.8V VBUS = 5V 5x MODE COUT = 10µF 10µs/DIV 36773 F02 When ILIM0 is pulled high and ILIM1 is pulled low the LTC3677-3 enters suspend mode to comply with the USB specification. In this mode, the power path between VBUS and VOUT is put in a high impedance state to reduce the VBUS input current to 50μA. If no other power source is available to drive WALL and VOUT , the system load connected to VOUT is supplied through the ideal diodes connected to BAT. Figure 2. Ideal Diode Transient Response 36773f 21 LTC3677-3 OPERATION VBUS Undervoltage Lockout (UVLO) and Undervoltage Current Limit (UVCL) An internal undervoltage lockout circuit monitors VBUS and keeps the input current limit circuitry off until VBUS rises above the rising UVLO threshold (3.8V) and at least 50mV above VOUT . Hysteresis on the UVLO turns off the input current limit if VBUS drops below 3.7V or 50mV below VOUT . When this happens, system power at VOUT will be drawn from the battery via the ideal diode. To minimize the possibility of oscillation in and out of UVLO when using resistive input supplies, the input current limit is reduced as VBUS falls below 4.45V (typ). Battery Charger The LTC3677-3 includes a constant-current/constant- voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery voltage is below VTRKL, typically 2.85V, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. If the low voltage persists for more than 1/2 hour, the battery charger automatically terminates. Once the battery voltage is above 2.85V, the battery charger begins charging in full power constant-current mode. The current delivered to the battery will try to reach 1000V/RPROG. Depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. The external load will always be prioritized over the battery charge current. The USB current limit programming will always be observed and only additional current will be available to charge the battery. When system loads are light, battery charge current will be maximized. Charge Termination The battery charger has a built-in safety timer. When the battery voltage approaches the float voltage, the charge current begins to decrease as the LTC3677-3 enters constant-voltage mode. Once the battery charger detects that it has entered constant-voltage mode, the four hour safety timer is started. After the safety timer expires, charging of the battery will terminate and no more current will be delivered. Automatic Recharge After the battery charger terminates, it will remain off drawing only microamperes of current from the battery. If the portable product remains in this state long enough, the battery will eventually self discharge. To ensure that the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below VRECHRG (typically 4.1V for LTC3677-3). In the event that the safety timer is running when the battery voltage falls below VRECHRG, the timer will reset back to zero. To prevent brief excursions below VRECHRG from resetting the safety timer, the battery voltage must be below VRECHRG for more than 1.3ms. The charge cycle and safety timer will also restart if the VBUS UVLO cycles low and then high (e.g., VBUS, is removed and then replaced). Charge Current The charge current is programmed using a single resistor from PROG to ground. 1/1000th of the battery charge current is delivered to PROG which will attempt to servo to 1.000V. Thus, the battery charge current will try to reach 1000 times the current in the PROG pin. The program resistor and the charge current are calculated using the following equations: RPROG = 1000 V 1000 V , ICHG = ICHG RPROG 36773f 22 LTC3677-3 OPERATION In either the constant-current or constant-voltage charging modes, the PROG pin voltage will be proportional to the actual charge current delivered to the battery. Therefore, the actual charge current can be determined at any time by monitoring the PROG pin voltage and using the following equation: IBAT = VPROG • 1000 RPROG In many cases, the actual battery charge current, IBAT , will be lower than ICHG due to limited input current available and prioritization with the system load drawn from VOUT . Thermal Regulation To prevent thermal damage to the IC or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110°C. Thermal regulation protects the LTC3677-3 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the LTC3677-3 or external components. The benefit of the LTC3677-3 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. Charge Status Indication The CHRG pin indicates the status of the battery charger. An open-drain output, the CHRG pin can drive an indicator LED through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. When charging begins, CHRG is pulled low and remains low for the duration of a normal charge cycle. When charging is complete, i.e., the charger enters constant-voltage mode and the charge current has dropped to one-tenth of the programmed value, the CHRG pin is released (high impedance). The CHRG pin does not respond to the C/10 threshold if the LTC3677‑3 is in input current limit. This prevents false end-of-charge indications due to insufficient power available to the battery charger. Even though charging is stopped during an NTC fault the CHRG pin will stay low indicating that charging is not complete. Battery Charger Stability Considerations The LTC3677-3’s battery charger contains both a constantvoltage and a constant-current control loop. The constantvoltage loop is stable without any compensation when a battery is connected with low impedance leads. Excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1µF from BAT to GND. Furthermore, a 4.7µF capacitor in series with a 0.2Ω to 1Ω resistor from BAT to GND is required to keep ripple voltage low when the battery is disconnected. High value, low ESR multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. Ceramic capacitors up to 22µF may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2Ω to 1Ω of series resistance. In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the additional pole created by any PROG pin capacitance, capacitance on this pin must be kept to a minimum. With no additional capacitance on the PROG pin, the battery charger is stable with program resistor values as high as 25k. However, additional capacitance on this node reduces the maximum allowed program resistor. The pole frequency at the PROG pin should be kept above 100kHz. Therefore, if the PROG pin has a parasitic capacitance, CPROG, the following equation should be used to calculate the maximum resistance value for RPROG: RPROG ≤ 1 2π • 100kHz • CPROG NTC Thermistor and Battery Voltage Reduction The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery pack. To use this feature connect the NTC thermistor, RNTC, between the NTC pin and ground and a bias resistor, RNOM, from NTCBIAS to NTC. RNOM should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at 25°C (R25). The LTC3677-3 will 36773f 23 LTC3677-3 OPERATION pause charging when the resistance of the NTC thermistor drops to 0.54 times the value of R25 or approximately 54k (for a Vishay curve 1 thermistor, this corresponds to approximately 40°C). If the battery charger is in constantvoltage (float) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. As the temperature drops, the resistance of the NTC thermistor rises. The LTC3677-3 is also designed to pause charging when the value of the NTC thermistor increases to 3.25 times the value of R25. For a Vishay curve 1 thermistor this resistance, 325k, corresponds to approximately 0°C. The hot and cold comparators each have approximately 3°C of hysteresis to prevent oscillation about the trip point. The typical NTC circuit is shown in Figure 3. When the charger is disabled an internal watchdog timer samples the NTC thermistor for about 150µs every 150ms and will enable the battery monitoring circuitry if the battery temperature exceeds the NTC TOO_HOT threshold. If adding a capacitor to the NTC pin for filtering the time constant must be much less than 150µs so that the NTC pin can settle to its final value during the sampling period. A time constant less than 10µs is recommended. Once the battery monitoring circuitry is enabled it will remain enabled and monitoring the battery voltage until the battery temperature falls back below the discharge temperature threshold. The battery discharge circuitry is only enabled if the battery voltage is greater than the battery discharge threshold. To improve safety and reliability the battery voltage is reduced when the battery temperature becomes excessively high. When the resistance of the NTC thermistor drops to about 0.35 times the value of R25 or approximately 35k (for a Vishay curve 1 thermistor, this corresponds to approximately 50°C) the NTC enables circuitry to monitor the battery voltage. If the battery voltage is above the battery discharge threshold (about 3.9V) then the battery discharge circuitry is enabled and draws about 140mA from the battery when VBUS = 0V and about 180mA when VBUS = 5V. The battery discharge current is disabled below the battery discharge threshold. Alternate NTC Thermistors and Biasing NTCBIAS The upper and lower temperature thresholds can be adjusted by either a modification of the bias resistor value NTC BLOCK 34 0.76 • NTCBIAS LTC3677-3 – TOO_COLD 35 + RNTC 100k – 0.35 • NTCBIAS 0.26 • NTCBIAS TOO_HOT + + – BATTERY OVERTEMP 36773 F03 RNOM 100k NTC The LTC3677-3 provides temperature qualified charging if a grounded thermistor and a bias resistor are connected to NTC. By using a bias resistor whose value is equal to the room temperature resistance of the thermistor (R25) the upper and lower temperatures are pre-programmed to approximately 40°C and 0°C, respectively (assuming a Vishay curve 1 thermistor). Figure 3. Typical NTC Thermistor Circuit 36773f 24 LTC3677-3 OPERATION or by adding a second adjustment resistor to the circuit. If only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. The other trip point will be determined by the characteristics of the thermistor. Using the bias resistor in addition to an adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. Examples of each technique are given below. NTC thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. The Vishay-Dale thermistor NTHS0603N011-N1003F, used in the following examples, has a nominal value of 100k and follows the Vishay curve 1 resistance-temperature characteristic. In the explanation below, the following notation is used. R25 = Value of the thermistor at 25°C RNTC|COLD = Value of thermistor at the cold trip point RNTC|HOT = Value of the thermistor at the hot trip point rCOLD = Ratio of RNTC|COLD to R25 rHOT = Ratio of RNTC|HOT to R25 RNOM = Primary thermistor bias resistor (see Figure 3) R1 = Optional temperature range adjustment resistor (see Figure 4) The trip points for the LTC3677-3’s temperature qualification are internally programmed at 0.35 • VNTC for the hot threshold and 0.76 • VNTC for the cold threshold. Therefore, the hot trip point is set when: RNTC|HOT RNOM + RNTC|HOT • NTCBIAS = 0.35 • NTCBIAS Solving these equations for RNTC|COLD and RNTC|HOT results in the following: RNTC|HOT = 0.538 • RNOM and RNTC|COLD = 3.17 • RNOM By setting RNOM equal to R25, the above equations result in rHOT = 0.538 and rCOLD = 3.17. Referencing these ratios to the Vishay resistance-temperature curve 1 chart gives a hot trip point of about 40°C and a cold trip point of about 0°C. The difference between the hot and cold trip points is approximately 40°C. By using a bias resistor, RNOM, different in value from R25, the hot and cold trip points can be moved in either direction. The temperature span will change somewhat due to the nonlinear behavior of the thermistor. The following equations can be used to easily calculate a new value for the bias resistor: r RNOM = HOT • R25 0.538 rCOLD • R25 3.17 where rHOT and rCOLD are the resistance ratios at the desired hot and cold trip points. Note that these equations RNOM = NTCBIAS NTC BLOCK 34 RNOM 105k NTC 0.76 • NTCBIAS – TOO_COLD + 35 R1 12.7k RNTC 100k LTC3677-3 – 0.35 • NTCBIAS TOO_HOT + and the cold trip point is set when: RNOM + RNTC|COLD • NTCBIAS = 0.76 • NTCBIAS 0.26 • NTCBIAS + – BATTERY OVERTEMP 36773 F04 RNTC|COLD Figure 4. NTC Thermistor Circuit with Additional Bias Resistor 36773f 25 LTC3677-3 OPERATION are linked. Therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the IC. Consider an example where a 60°C hot trip point is desired. From the Vishay curve 1 R-T characteristics, rHOT is 0.2488 at 60°C. Using the above equation, RNOM should be set to 46.4k. With this value of RNOM, the cold trip point is about 16°C. Notice that the span is now 44°C rather than the previous 40°C. This is due to the decrease in temperature gain of the thermistor as absolute temperature increases. The upper and lower temperature trip points can be independently programmed by using an additional bias resistor as shown in Figure 4. The following formulas can be used to compute the values of RNOM and R1: r –r RNOM = COLD HOT • R25 2.714 R1 = 0.536 • RNOM – rHOT • R25 For example, to set the trip points to 0°C and 45°C with a Vishay curve 1 thermistor choose: RNOM = 3.266 – 0.4368 • 100k = 104.2k 2.714 the nearest 1% value is 105k. R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k the nearest 1% value is 12.7k. The final solution is shown in Figure 4 and results in an upper trip point of 45°C and a lower trip point of 0°C. Overvoltage Protection (OVP) The LTC3677-3 can protect itself from the inadvertent application of excessive voltage to VBUS or WALL with just two external components: an N-channel MOSFET and a 6.2k resistor. The maximum safe overvoltage magnitude will be determined by the choice of the external N-channel MOSFET and its associated drain breakdown voltage. The overvoltage protection module consists of two pins. The first, OVSENS, is used to measure the externally applied voltage through an external resistor. The second, OVGATE, is an output used to drive the gate pin of an external FET. The voltage at OVSENS will be lower than the OVP input voltage by (IOVSENS • 6.2kΩ) due to the OVP circuit’s quiescent current. The OVP input will be 200mV to 400mV higher than OVSENS under normal operating conditions. When OVSENS is below 6V, an internal charge pump will drive OVGATE to approximately 1.88 • OVSENS. This will enhance the N-channel MOSFET and provide a low impedance connection to VBUS or WALL which will, in turn, power the LTC3677-3. If OVSENS should rise above 6V (6.35V OVP input) due to a fault or use of an incorrect wall adapter, OVGATE will be pulled to GND, disabling the external FET to protect downstream circuitry. When the voltage drops below 6V again, the external FET will be re-enabled. In an overvoltage condition, the OVSENS pin will be clamped at 6V. The external 6.2k resistor must be sized appropriately to dissipate the resultant power. For example, a 1/10W 6.2k resistor can have at most √PMAX • 6.2k = 24V applied across its terminals. With the 6V at OVSENS, the maximum overvoltage magnitude that this resistor can withstand is 30V. A 1/4W 6.2k resistor raises this value to 45V. The charge pump output on OVGATE has limited output drive capability. Care must be taken to avoid leakage on this pin, as it may adversely affect operation. 36773f 26 LTC3677-3 OPERATION Dual Input Overvoltage Protection Reverse Input Voltage Protection It is possible to protect both VBUS and WALL from overvoltage damage with several additional components, as shown in Figure 5. Schottky diodes D1 and D2 pass the larger of V1 and V2 to R1 and OVSENS. If either V1 or V2 exceeds 6V plus VF(SCHOTTKY), OVGATE will be pulled to GND and both the WALL and USB inputs will be protected. Each input is protected up to the drain-source breakdown, BVDSS, of MN1 and MN2. R1 must also be rated for the power dissipated during maximum overvoltage. See the Overvoltage Protection section for an explanation of this calculation. Table 2 shows some N-channel MOSFETs that maybe suitable for overvoltage protection. The LTC3677-3 can also be easily protected against the application of reverse voltage as shown in Figure 6. D1 and R1 are necessary to limit the maximum VGS seen by MP1 during positive overvoltage events. D1’s breakdown voltage must be safely below MP1’s BVGS. The circuit shown in Figure 6 offers forward voltage protection up to MN1’s BVDSS and reverse voltage protection up to MP1’s BVDSS. Table 2. Recommended Overvoltage FETs N-CHANNEL MOSFET BVDSS RON PACKAGE Si1472DH 30V 82mΩ SC70-6 Si2302ADS 20V 60mΩ SOT-23 Si2306BDS 30V 65mΩ SOT-23 Si2316BDS 30V 80mΩ SOT-23 IRLML2502 20V 35mΩ SOT-23 MN1 V1 OVGATE D2 D1 MN2 C1 MP1 MN1 C1 D1 R1 500k R2 6.2k VBUS LTC3677-3 OVGATE OVSENS D1: 5.6V ZENER MP1: Si2323 DS, BVDSS = 20V VBUS POSITIVE PROTECTION UP TO BVDSS OF MN1 VBUS NEGATIVE PROTECTION UP TO BVDSS OF MP1 36773 F06 Figure 6. Dual Polarity Voltage Protection Low Dropout Linear Regulator Operation WALL LTC3677-3 V2 USB/WALL ADAPTER VBUS R1 OVSENS 36773 F05 Figure 5. Dual Input Overvoltage Protection LDO Operation and Voltage Programming The LTC3677-3 contains two 150mA adjustable output LDO regulators. The first LDO (LDO1) is always on and will be enabled whenever VOUT is greater than VOUT UVLO. The second LDO (LDO2) is controlled by the pushbutton and is the first supply to sequence up in response to pushbutton application. Both LDOs are disabled when VOUT is less than VOUT UVLO and LDO2 is further disabled when the pushbutton circuity is in the power down or power off states. Both LDOs contain a soft-start function to limit inrush current when enabled. The soft-start function works by ramping up the LDO reference over a 200µs period (typical) when the LDO is enabled. When disabled all LDO circuitry is powered off leaving only a few nanoamps of leakage current on the LDO supply. Both LDO outputs are individually pulled to ground through internal resistors when disabled. 36773f 27 LTC3677-3 OPERATION The power good status bits of LDO1 and LDO2 are available in I2C through the read-back registers PGLDO[1] and PGLDO[2] for LDO1 and LDO2 respectively. The power good comparators for both LDOs are sampled when the I2C port receives the correct I2C read address. Figure 7 shows the LDO application circuit. The full-scale output voltage for each LDO is programmed using a resistor divider from the LDO output (LDO1 or LDO2) connected to the feedback pins (LDO1_FB or LDO2_FB) such that: R1 VLDOx = 0.8 V • +1 R2 For stability, each LDO output must be bypassed to ground with a minimum 1μF ceramic capacitor (COUT). VINLDOx LDOxEN 0 MP 1 LDOx LDOx_FB 0.8V GND R1 COUT LDOx OUTPUT R2 36773 F07 Figure 7. LDO Application Circuit Step-Down Switching Regulator Operation Introduction The LTC3677-3 includes three 2.25MHz constant-frequency current mode step-down switching regulators providing 500mA, 500mA and 800mA each. All step-down switching regulators can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory or other logic circuitry. All step-down switching regulators support 100% duty cycle operation (low dropout mode) when the input voltage drops very close to the output voltage and are also capable of Burst Mode operation for highest efficiencies at light loads. Burst Mode operation is individually selectable for each step-down switching regulator through the I2C register bits BK1BRST, BK2BRST and BK3BRST. The step-down switching regulators also include soft-start to limit inrush current when powering on, short-circuit current protection, and switch node slew limiting circuitry to reduce EMI radiation. No external compensation components are required for the switching regulators. Switching regulators 1 and 2 (Buck1 and Buck2) are sequenced up and down together through the pushbutton interface (see the Pushbutton Interface section for more information), while Buck3 has an individual enable pin (EN3) that is active when the pushbutton is in the power-up or power-on states. Buck3 is disabled in the power down and power off states. It is recommended that the step-down switching regulator input supplies (VIN12 and VIN3) be connected to the system supply pin (VOUT). This is recommended because the undervoltage lockout circuit on the VOUT pin (VOUT UVLO) disables the step-down switching regulators when the VOUT voltage drops below the VOUT UVLO threshold. If driving the step-down switching regulator input supplies from a voltage other than VOUT the regulators should not be operated outside the specified operating range as operation is not guaranteed beyond this range. Output Voltage Programming Figure 8 shows the step-down switching regulator application circuit. The full-scale output voltage for each step-down switching regulator is programmed using a resistor divider from the step-down switching regulator output connected to the feedback pins (FB1, FB2 and FB3) such that: R1 VOUTx = 0.8 V • +1 R2 VIN EN MODE PWM SLEW CONTROL MP SWx MN L CFB VOUTx R1 COUT FBx 0.8V GND R2 36773 F08 Figure 8. Step-Down Switching Regulator Application Circuit 36773f 28 LTC3677-3 OPERATION Typical values for R1 are in the range of 40k to 1M. The capacitor CFB cancels the pole created by feedback resistors and the input capacitance of the FB pin and also helps to improve transient response for output voltages much greater than 0.8V. A variety of capacitor sizes can be used for CFB but a value of 10pF is recommended for most applications. Experimentation with capacitor sizes between 2pF and 22pF may yield improved transient response. Operating Modes The step-down switching regulators include two possible operating modes to meet the noise/power needs of a variety of applications. In pulse-skipping mode, an internal latch is set at the start of every cycle, which turns on the main P-channel MOSFET switch. During each cycle, a current comparator compares the peak inductor current to the output of an error amplifier. The output of the current comparator resets the internal latch, which causes the main P-channel MOSFET switch to turn off and the N-channel MOSFET synchronous rectifier to turn on. The N-channel MOSFET synchronous rectifier turns off at the end of the 2.25MHz cycle or if the current through the N-channel MOSFET synchronous rectifier drops to zero. Using this method of operation, the error amplifier adjusts the peak inductor current to deliver the required output power. All necessary compensation is internal to the step-down switching regulator requiring only a single ceramic output capacitor for stability. At light loads in pulse-skipping mode, the inductor current may reach zero on each pulse which will turn off the N-channel MOSFET synchronous rectifier. In this case, the switch node (SW1, SW2 or SW3) goes high impedance and the switch node voltage will ring. This is discontinuous operation, and is normal behavior for a switching regulator. At very light loads in pulse-skipping mode, the step-down switching regulators will automatically skip pulses as needed to maintain output regulation. At high duty cycle (VOUTX approaching VINX) it is possible for the inductor current to reverse at light loads causing the stepped down switching regulator to operate continuously. When operating continuously, regulation and low noise output voltage are maintained, but input operating current will increase to a few milliamps. In Burst Mode operation, the step-down switching regulators automatically switch between fixed frequency PWM operation and hysteretic control as a function of the load current. At light loads the step-down switching regulators control the inductor current directly and use a hysteretic control loop to minimize both noise and switching losses. While operating in Burst Mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. The step-down switching regulator then goes into sleep mode, during which the output capacitor provides the load current. In sleep mode, most of the switching regulator’s circuitry is powered down, helping conserve battery power. When the output voltage drops below a pre-determined value, the step-down switching regulator circuitry is powered on and another burst cycle begins. The sleep time decreases as the load current increases. Beyond a certain load current point (about 1/4 rated output load current) the step-down switching regulators will switch to a low noise constant-frequency PWM mode of operation, much the same as pulse-skipping operation at high loads. For applications that can tolerate some output ripple at low output currents, Burst Mode operation provides better efficiency than pulse-skipping at light loads. The step-down switching regulators allow mode transition on-the-fly, providing seamless transition between modes even under load. This allows the user to switch back and forth between modes to reduce output ripple or increase low current efficiency as needed. Burst Mode operation is individually selectable for each step-down switching regulator through the I2C register bits BK1BRST, BK2BRST and BK3BRST. Shutdown The step-down switching regulators (Buck1, Buck2 and Buck3) are shut down when the pushbutton circuitry is in the power-down or power-off state. Step-down switching regulator 3 (Buck3) can also be shut down by bringing the EN3 input low. In shutdown all circuitry in the step-down switching regulator is disconnected from the switching regulator input supply leaving only a few nanoamps of leakage current. The step-down switching regulator outputs are individually pulled to ground through internal 10k resistors on the switch pin (SW1, SW2 or SW3) when in shutdown. 36773f 29 LTC3677-3 OPERATION Dropout Operation Slew Rate Control It is possible for a step-down switching regulator’s input voltage to approach its programmed output voltage (e.g., a battery voltage of 3.4V with a programmed output voltage of 3.3V). When this happens, the P-Channel MOSFET switch duty cycle increases until it is turned on continuously at 100%. In this dropout condition, the respective output voltage equals the regulator’s input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. The step-down switching regulators contain patented circuitry to limit the slew rate of the switch node (SW1, SW2 and SW3). This new circuitry is designed to transition the switch node over a period of a few nanoseconds, significantly reducing radiated EMI and conducted supply noise while maintaining high efficiency. Since slowing the slew rate of the switch nodes causes efficiency loss, the slew rate of the step-down switching regulators is adjustable via the I2C registers SLEWCTL1 and SLEWCTL2. This allows the user to optimize efficiency or EMI as necessary with four different slew rate settings. The power up default is the fastest slew rate (highest efficiency) setting. Figures 9 and 10 show the efficiency and power loss graph for Buck3 programmed for 1.2V and 2.5V outputs. Note that the power loss curves remain fairly constant for both graphs yet changing the slew rate has a larger effect on the 1.2V output efficiency. This is mainly because for a given output current the 2.5V output is delivering more than 2x the power than the 1.2V output. Efficiency will always decrease and show more variation to slew rate as the programmed output voltage is decreased. Soft-Start Operation Soft-start is accomplished by gradually increasing the peak inductor current for each step-down switching regulator over a 500μs period. This allows each output to rise slowly, helping minimize inrush current required to charge up the switching regulator output capacitor. A soft-start cycle occurs whenever a given switching regulator is enabled. A soft-start cycle is not triggered by changing operating modes. This allows seamless output transition when actively changing between operating modes. 100 1000 100 90 90 60 10 50 Burst Mode OPERATION VIN = 3.8V SW[1:0] = 00 01 10 11 40 30 20 10 0.1 1 10 IOUT3 (µA) 100 1 80 0.1 0.001 1000 36773 F09 Figure 9. VOUT3 (1.2V) Efficiency and Power Loss vs IOUT3 100 70 60 10 50 Burst Mode OPERATION VIN = 3.8V SW[1:0] = 00 01 10 11 40 30 20 10 0 0.01 0.1 10 1 IOUT3 (µA) 100 1 POWER LOSS (mW) 70 EFFICIENCY (%) 100 POWER LOSS (mW) EFFICIENCY (%) 80 0 0.01 1000 0.1 0.01 1000 36773 F10 Figure 10. VOUT3 (2.5V) Efficiency and Power Loss vs IOUT3 36773f 30 LTC3677-3 OPERATION Low Supply Operation An undervoltage lockout circuit on VOUT (VOUT UVLO) shuts down the step-down switching regulators when VOUT drops below about 2.7V. It is recommended that the stepdown switching regulator input supplies (VIN12, VIN3) be connected to the power path output (VOUT) directly. This UVLO prevents the step-down switching regulators from operating at low supply voltages where loss of regulation or other undesirable operation may occur. If driving the step-down switching regulator input supplies from a voltage other than the VOUT pin, the regulators should not be operated outside the specified operating range as operation is not guaranteed beyond this range. Inductor Selection Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. The step-down switching regulators are designed to work with inductors in the range of 2.2μH to 10μH. For most applications a 4.7μH inductor is suggested for step-down switching regulators providing up to 500mA of output current while a 3.3μH inductor is suggested for step-down switching regulators providing up to 800mA. Larger value inductors reduce ripple current, which improves output ripple voltage. Lower value inductors result in higher ripple current and improved transient response time, but will reduce the available output current. To maximize efficiency, choose an inductor with a low DC resistance. For a 1.2V output, efficiency is reduced about 2% for 100mΩ series resistance at 400mA load current, and about 2% for 300mΩ series resistance at 100mA load current. Choose an inductor with a DC current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. If output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the step-down converters. Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or Permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. Inductors that are very thin or have a very small volume typically have much higher core and DCR losses, and will not give the best efficiency. The Table 3. Recommended Inductors for Step-Down Switching Regulators L (μH) MAX IDC (A) MAX DCR (Ω) SIZE in mm (L × W × H) DB318C D312C DE2812C 4.7 3.3 4.7 3.3 4.7 3.3 1.07 1.20 0.79 0.90 1.15 1.37 0.1 0.07 0.24 0.20 0.13* 0.105* 3.8 × 3.8 × 1.8 3.8 × 3.8 × 1.8 3.6 × 3.6 × 1.2 3.6 × 3.6 × 1.2 3.0 × 2.8 × 1.2 3.0 × 2.8 × 1.2 Toko www.toko.com CDRH3D16 CDRH2D11 CLS4D09 4.7 3.3 4.7 3.3 4.7 0.9 1.1 0.5 0.6 0.75 0.11 0.085 0.17 0.123 0.19 4 × 4 × 1.8 4 × 4 × 1.8 3.2 × 3.2 × 1.2 3.2 × 3.2 × 1.2 4.9 × 4.9 × 1 Sumida www.sumida.com SD3118 SD3112 SD12 SD10 4.7 3.3 4.7 3.3 4.7 3.3 4.7 3.3 1.3 1.59 0.8 0.97 1.29 1.42 1.08 1.31 0.162 0.113 0.246 0.165 0.117* 0.104* 0.153* 0.108* 3.1 × 3.1 × 1.8 3.1 × 3.1 × 1.8 3.1 × 3.1 × 1.2 3.1 × 3.1 × 1.2 5.2 × 5.2 × 1.2 5.2 × 5.2 × 1.2 5.2 × 5.2 × 1.0 5.2 × 5.2 × 1.0 Cooper www.cooperet.com LPS3015 4.7 3.3 1.1 1.3 0.2 0.13 3.0 × 3.0 × 1.5 3.0 × 3.0 × 1.5 Coil Craft www.coilcraft.com INDUCTOR TYPE *Typical DCR MANUFACTURER 36773f 31 LTC3677-3 OPERATION choice of which style inductor to use often depends more on the price versus size, performance, and any radiated EMI requirements than on what the step-down switching regulators requires to operate. The inductor value also has an effect on Burst Mode operation. Lower inductor values will cause Burst Mode switching frequency to increase. Table 3 shows several inductors that work well with the step-down switching regulators. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors. Input/Output Capacitor Selection Low ESR (equivalent series resistance) ceramic capacitors should be used at both step-down switching regulator outputs as well as at each step-down switching regulator input supply. Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. A 10μF output capacitor is sufficient for the step-down switching regulator outputs. For good transient response and stability the output capacitor for step-down switching regulators should retain at least 4μF of capacitance over operating temperature and bias voltage. Each switching regulator input supply should be bypassed with a 2.2μF capacitor. Consult with capacitor manufacturers for detailed information on their selection and specifications of ceramic capacitors. Many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. Table 4 shows a list of several ceramic capacitor manufacturers. Table 4. Ceramic Capacitor Manufacturers AVX www.avxcorp.com Murata www.murata.com Taiyo Yuden www.t-yuden.com Vishay Siliconix www.vishay.com TDK www.tdk.com I2C Operation I2C Interface The LTC3677-3 may communicate with a bus master using the standard I2C 2-wire interface. The timing diagram in Figure 11 shows the relationship of the signals on the bus. The two bus lines, SDA and SCL, must be HIGH when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. The LTC3677-3 is both a slave receiver and slave transmitter. The I2C control signals, SDA and SCL are scaled internally to the DVCC supply. DVCC should be connected to the same power supply as the bus pull-up resistors. The I2C port has an undervoltage lockout on the DVCC pin. When DVCC is below approximately 1V, the I2C serial port is cleared and registers are set to the default configuration of all zeros. I2C Bus Speed The I2C port is designed to be operated at speeds of up to 400kHz. It has built-in timing delays to ensure correct operation when addressed from an I2C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted. I2C START and STOP Conditions A bus master signals the beginning of communications by transmitting a START condition. A START condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The master may transmit either the slave write or the slave read address. Once data is written to the LTC3677-3, the master may transmit a STOP condition which commands the LTC3677-3 to act upon its new command set. A STOP condition is sent by the master by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is then free for communication with another I2C device. I2C Byte Format Each byte sent to or received from the LTC3677-3 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. The data should be sent to the LTC3677-3 most significant bit (MSB) first. 36773f 32 LTC3677-3 OPERATION ADDRESS DATA BYTE A WR A7 0 0 0 1 0 0 1 0 SDA 0 0 0 1 0 0 1 0 ACK SCL 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 DATA BYTE B A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 START STOP ACK 1 2 3 4 5 6 7 8 9 ACK 1 2 3 4 5 6 7 8 9 SDA tSU, DAT tLOW tSU, STA tHD, DAT tBUF tSU, STO tHD, STA SCL tHIGH tHD, STA START CONDITION tr tSP tf REPEATED START CONDITION STOP CONDITION START CONDITION 36773 F11 Figure 11. I2C Timing Diagram I2C Acknowledge I2C Slave Address The acknowledge signal is used for handshaking between the master and the slave. When the LTC3677-3 is written to (write address), it acknowledges its write address as well as the subsequent two data bytes. When read from (read address), the LTC3677-3 acknowledges its read address only. The bus master should acknowledge receipt of information from the LTC3677-3. The LTC3677-3 responds to a 7-bit address which has been factory programmed to b’0001001[R/W]’. The LSB of the address byte, known as the read/write bit, should be 0 when writing data to the LTC3677-3 and 1 when reading data from it. Considering the address an 8-bit word, then the write address is 0x12 and the read address is 0x13. The LTC3677-3 will acknowledge both its read and write address. An acknowledge (active LOW) generated by the LTC3677-3 lets the master know that the latest byte of information was received. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock cycle. The LTC3677-3 pulls down the SDA line during the write acknowledge clock pulse so that it is a stable LOW during the HIGH period of this clock pulse. When the LTC3677-3 is read from, it releases the SDA line so that the master may acknowledge receipt of the data. Since the LTC3677-3 only transmits one byte of data, a master not acknowledging the data sent by the LTC3677-3 has no I2C specific consequence on the operation of the I2C port. I2C Sub-Addressed Writing The LTC3677-3 has one command register for control input. It is accessed by the I2C port via a sub-addressed writing system. Each write cycle of the LTC3677-3 consists of exactly three bytes. The first byte is always the LTC3677-3’s write address. The second byte represents the LTC3677-3’s sub-address. The sub-address is a pointer which directs the subsequent data byte within the LTC3677-3. The third byte consists of the data to be written to the location pointed to by the sub-address. The LTC3677-3 contains control registers at only sub-address location 0x00. Subaddresses outside 0x00 should not be written to as they access functionality not available in the LTC3677-3. 36773f 33 LTC3677-3 OPERATION I2C Bus Write Operation The master initiates communication with the LTC3677-3 with a START condition and the LTC3677-3’s write address. If the address matches that of the LTC3677-3, the LTC3677-3 returns an acknowledge. The master should then deliver the sub-address. Again the LTC3677-3 acknowledges and the cycle is repeated for the data byte. The data byte is transferred to an internal holding latch upon the return of its acknowledge by the LTC3677-3. This procedure must be repeated for each sub-address that requires new data. After one or more cycles of [ADDRESS][SUB-ADDRESS][DATA], the master may terminate the communication with a STOP condition. Alternatively, a REPEAT-START condition can be initiated by the master and another chip on the I2C bus can be addressed. This cycle can continue indefinitely and the LTC3677-3 will remember the last input of valid data that it received. Once all chips on the bus have been addressed and sent valid data, a global STOP can be sent and the LTC3677-3 will update its command latches with the data that it received. I2C Bus Read Operation The bus master reads the status of the LTC3677-3 with a START condition followed by the LTC3677-3 read address. If the read address matches that of the LTC3677-3, the LTC3677-3 returns an acknowledge. Following the acknowledgement of their read address, the LTC3677-3 returns one bit of status information for each of the next 8 clock cycles. A STOP command is not required for the bus read operation. I2C Input Data There is one byte of data that can be written to on the LTC3677-3. The byte is accessed through the sub-address 0x00. At first power application (VBUS, WALL or BAT) all bits default to 0. Additionally, all bits are cleared to 0 when DVCC drops below its undervoltage lock out or if the pushbutton enters the power down (PDN) state. Table 5 shows the byte of data that can be written to at sub-address 0x00. This byte of data is referred to as the buck control register. Table 5. Buck Control Register BUCK CONTROL REGISTER ADDRESS: 00010010 SUB-ADDRESS: 00000000 BIT NAME FUNCTION B0 N/A Not Used—No Effect On Operation B1 N/A Not Used—No Effect On Operation B2 BK1BRST Buck1 Burst Mode Enable B3 BK2BRST Buck2 Burst Mode Enable B4 BK3BRST Buck2 Burst Mode Enable B5 SLEWCTL1 B6 SLEWCTL2 Buck SW Slew Rate: 00 = 1ns, 01 = 2ns, 10 = 4ns, 11 = 8ns B7 N/A Not Used—No Effect On Operation Bits B2, B3, and B4 set the operating modes of the stepdown switching regulators (bucks). Writing a 1 to any of these three registers will put that respective buck converter in the high efficiency Burst Mode operation, while a 0 will enable the low noise pulse-skipping mode of operation. The B5 and B6 bits adjust the slew rate of all SW pins together so they all slew at the same rate. It is recommended that the fastest slew rate (B6:B5 = 00) be used unless EMI is an issue in the application as slower slew rates cause reduced efficiency. I2C Output Data One status byte may be read from the LTC3677-3, as shown in Table 6. A 1 read back in the any of the bit posi- 36773f 34 LTC3677-3 OPERATION tions indicates that the condition is true. For example, 1 read back from bit A3 indicate that LDO1 is enabled and regulating correctly. A status read from the LTC3677-3 captures the status information when the LTC3677-3 acknowledge its read address. Table 6. I2C READ Register STATUS REGISTER ADDRESS: 00010011 SUB-ADDRESS: None BIT NAME FUNCTION A0 CHARGE Charge Status (1 = Charging) A1 STAT[0] A2 STAT[1] STAT[1:0]; 00 = No Fault 01 = TOO COLD/HOT 10 = BATTERY OVERTEMP 11 = BATTERY FAULT A3 PGLDO[1] LDO1 Power Good A4 PGLDO[2] LDO2 Power Good A5 PGBCK[1] Buck1 Power Good A6 PGBCK[2] Buck2 Power Good A7 PGBCK[3] Buck3 Power Good Bit A7 shows the power good status of Buck3. A 1 indicates that Buck3 is enabled and is regulating correctly. A 0 indicates that either Buck3 is not enabled, or that the Buck3 is enabled, but is out of regulation by more than 8%. Bit A6 shows the power good status of Buck2. A 1 indicates that Buck2 is enabled and is regulating correctly. A 0 indicates that either Buck2 is not enabled, or that the Buck2 is enabled, but is out of regulation by more than 8%. Bit A5 shows the power good status of Buck1. A 1 indicates that Buck1 is enabled and is regulating correctly. A 0 indicates that either Buck1 is not enabled, or that the Buck1 is enabled, but is out of regulation by more than 8%. Bit A4 shows the power good status of LDO2. A 1 indicates that LDO2 is enabled and is regulating correctly. A 0 indi- cates that either LDO2 is not enabled, or that the LDO2 is enabled, but is out of regulation by more than 8%. Bit A3 shows the power good status of LDO1. A 1 indicates that LDO1 is enabled and is regulating correctly. A 0 indicates that either LDO1 is not enabled, or that the LDO1 is enabled, but is out of regulation by more than 8%. Bits A2 and A1 indicate the fault status of the charger measurement circuit and are decoded in Table 6. The too cold/hot state indicates that the thermistor temperature is out of the valid charging range (either below 0°C or above 40°C for a curve 1 thermistor) and that charging has paused until the battery returns to valid charging temperature. The battery overtemperature state indicates that the battery’s thermistor has reached a critical temperature (about 50°C for a curve 1 thermistor) and that long-term battery capacity may be seriously compromised if the condition persists. The battery fault state indicates that an attempt was made to charge a low battery (typically < 2.85V) but that the low voltage condition persisted for more than 1/2 hour. In this case charging has terminated. Bit A0 indicates the status of the battery charger. A 1 indicates that the charger is enabled and is in the constant-current charge state. In this case the battery is being charged unless the NTC thermistor is outside its valid charge range in which case charging is temporarily suspended but not complete. Charging will continue once the battery has returned to a valid charging temperature. A 0 in bit A0 indicates that charger has reached end-ofcharge (hC/10) and is near VFLOAT or that charging has been terminated. Charging can be terminated by reaching the end of the charge timer or by a battery fault as described previously. 36773f 35 LTC3677-3 OPERATION Pushbutton Interface Operation PBSTAT Operation State Diagram/Operation PBSTAT goes LOW 50ms after the initial pushbutton application (ON LOW) and will stay low for 50ms minimum. PBSTAT will go HIGH coincident with ON going HIGH unless ON goes HIGH before the 50ms minimum LOW time. Figure 13 shows the LTC3677-3 pushbutton state diagram. Upon first application of power (VBUS, WALL or BAT) an internal power-on reset (POR) signal places the pushbutton circuitry into the power-off (POFF) state. The following events cause the state machine to transition out of POFF into the power-up (PUP) state: 1) ON input LOW for 50ms (PB50MS) 2) PWR_ON input going HIGH (PWR_ON) Upon entering the PUP state, the pushbutton circuitry will sequence up LDO2, Buck1 and Buck2 in that order. One second after entering the PUP state, the pushbutton circuitry will transition into the power-on (PON) state. Note that the PWR_ON input must be brought HIGH before entering the PON state if the part is to remain in the PON state. Buck3 can be enabled through the EN3 input once the pushbutton is in the PUP or PON states. PWR_ON going LOW, or VOUT dropping to its undervoltage lockout (VOUT UVLO) threshold will cause the state machine to leave the PON state and enter the power-down (PDN) state. The PDN state resets the I2C registers as well as disables Buck1, Buck2 and LDO2 together. Buck3 is also disabled in the PDN and POFF states. The one second delay before leaving the power-down state allows the supplies to power down completely before they can be re-enabled. PB50ms + PWR_ON POR PUP 1SEC POFF PON UVLO + PWR_ON 1SEC PDN 35773 F13 Figure 12. Pushbutton State Diagram Hard Reset and PGOOD Operation The hard reset event is generated by pressing and holding the pushbutton (ON input LOW) for 14 seconds. For a valid hard reset event to occur the initial pushbutton application must start in the PUP or PON state. This avoids causing a hard reset from occurring if the user hangs on the pushbutton during initial power-up. If a valid hard reset event is present then the PGOOD output will transition LOW for about 1.8ms to allow the microprocessor to reset. The hard reset event does not affect the operating state or regulator operation. The PGOOD pin is an open-drain output used to indicate that Buck1, Buck2 and LDO1 are enabled and have reached their final regulation voltage. A 230ms delay is included from the time Buck1, Buck2 and LDO1 reach 92% of their regulation value to allow a system controller ample time to reset itself. PGOOD is an open-drain output and requires a pull-up resistor to an appropriate power source. Optimally the pull-up resistor is connected to the output of Buck1, Buck2 or LDO2 so that power is not dissipated while the regulators are disabled. Pushbutton Operation and VOUT UVLO As stated earlier VOUT dropping to its UVLO threshold will cause the pushbutton to leave the power-on state and enter the power-down state, thus powering down Buck1, Buck2, Buck3 and LDO2. Additionally, LDO1 is disabled when in UVLO. Thus, all LTC3677-3 supplies are disabled and remain disabled as long as the VOUT UVLO condition exists. It is not possible to power up any of the LTC3677-3 generated supplies while VOUT is below the VOUT UVLO threshold. 36773f 36 LTC3677-3 OPERATION Power-Up via Pushbutton Timing Power-Up via PWR_ON Timing The timing diagram, Figure 13, shows the LTC3677-3 powering up through application of the external pushbutton. For this example the pushbutton circuitry starts in the POFF state with VOUT not in UVLO and Buck1, Buck2 and LDO2 disabled. Pushbutton application (ON LOW) for 50ms transitions the pushbutton circuitry into the PUP state which sequences up LDO2, Buck1 and Buck2 in that order. PWR_ON must be driven HIGH before the 1 second PUP period is over to keep supplies up. If PWR_ON is LOW or goes LOW after the 1 second PUP period Buck1, Buck2, and LDO2 will be shut down together. PGOOD is asserted once Buck1, Buck2 and LDO1 are within 8% of their regulation voltage for 230ms. The timing diagram, Figure 14, shows the LTC3677-3 powering up by driving PWR_ON HIGH. For this example the pushbutton circuitry starts in the POFF state with VOUT not in UVLO and Buck1, Buck2 and LDO2 disabled. 50ms after PWR_ON goes HIGH the pushbutton circuitry transitions into the PUP state which sequences up LDO2, Buck1 and Buck2 in that order. PWR_ON must be driven high before the 1 second PUP period is over to keep supplies up. If PWR_ON is LOW or goes LOW after the 1 second PUP period Buck1, Buck2 and LDO2 will be shut down together. PGOOD is asserted once Buck1, Buck2 and LD01 are within 8% of their regulation voltage for 230ms. Buck3 can be enabled and disabled at any time via EN3 once in the PUP or PON states. The PWR_ON input can be driven via a μP/μC or by one of the sequenced outputs through a high impedance (100kΩ typ). PBSTAT goes LOW 50ms after the initial pushbutton application and will stay LOW for 50ms minimum. PBSTAT will go HIGH coincident with ON going HIGH unless ON goes HIGH before the 50ms minimum LOW time. VOUT UVLO Powering up via PWR_ON is useful for applications containing an always on microcontroller. This allows the microcontroller to power the application up and down for house keeping and other activities outside the user’s control. VOUT UVLO ON (PB) ON (PB) 50ms PBSTAT PBSTAT 1 SEC LDO2 PWR_ON 14ms BUCK1 50ms LDO2 14ms BUCK2 BUCK1 230ms PGOOD 1 SEC PWR_ON STATE Buck3 can be enabled and disabled at any time via EN3 once in the PUP or PON states. BUCK2 230ms PGOOD POFF PUP PON 36773 F13 Figure 13. Power-Up via Pushbutton STATE 36773 F14 POFF PUP PON Figure 14. Power-Up via PWR_ON 36773f 37 LTC3677-3 OPERATION Power Down via Pushbutton Timing VOUT UVLO Power-Down Timing The timing diagram, Figure 15, shows the LTC3677-3 powering down by μC/μP control. For this example the pushbutton circuitry starts in the PON state with VOUT not in UVLO and Buck1, Buck2 and LDO2 enabled. In this case the pushbutton is applied (ON LOW) for at least 50ms, which generates a low impedance on the PBSTAT output. After receiving the PBSTAT the μC/μP will drive the PWR_ON input LOW. 50ms after PWR_ON goes LOW the pushbutton circuitry will enter the PDN state. Buck1, Buck2 and LDO2 are disabled together upon entering the PDN state. After entering the PDN state, a 1 second wait time is initiated before entering the POFF state. During this 1 second time ON and PWR_ON inputs are ignored to allow all LTC3677-3 generated supplies to go LOW. If VOUT drops below the VOUT UVLO threshold, the pushbutton circuitry will transition from the PON state to the PDN state. Buck1, Buck2 and LDO2 are disabled together upon entering the PDN state. After entering the PDN state, a 1 second wait time is initiated before entering the POFF state. During this 1 second time ON and PWR_ON inputs are ignored to allow all LTC3677-3 generated supplies to go LOW. Upon entering the PDN state Buck3 is disabled and the I2C registers are cleared. Holding ON LOW through the 1 second power-down period will not cause a power-up event at end of the 1 second period. The ON input must be brought HIGH following the power-down event and then go LOW again to establish a valid power-up event. Upon entering the PDN state the Buck3 is disabled and the I2C registers are cleared. LDO1 is also disabled by the VOUT UVLO and stays disabled as long as the VOUT UVLO condition remains. Note that it is not possible to sequence any of the supplies up while the VOUT UVLO condition exists. LDO1 will be re-enabled when the VOUT UVLO condition is removed. The other supplies will remain disabled until a valid power-up pushbutton event takes place. VOUT UVLO VOUT UVLO 1 SEC 1 SEC ON (PB) ON (PB) LDO1 50ms PBSTAT µC/µP CONTROL PBSTAT PWR_ON PWR_ON 50ms BUCK1 BUCK1 BUCK2 BUCK2 LDO2 LDO2 PGOOD STATE PON PDN POFF 36773 F15 Figure 15. Power-Down via Pushbutton PGOOD STATE PON PDN POFF 36773 F16 Figure 16. VOUT UVLO Power-Down 36773f 38 LTC3677-3 OPERATION Hard Reset Timing Power-Up Sequencing Hard reset provides a way to reset the μC/μP in case of a software lockup. To initiate a hard reset, the pushbutton is pressed (ON LOW) and held for greater than 14 seconds. Once the hard reset time is exceeded the PGOOD input will go LOW for 1.8ms which resets the μC/μP. Operation of the enabled supplies is not effected by the hard reset event. All enabled supplies should remain in regulation and operating correctly assuming specified operating conditions are met (i.e., no shorted supplies, etc). Figure 18 shows the actual power-up sequencing of the LTC3677-3. Buck1, Buck2 and LDO2 are all initially disabled (0V). Once the pushbutton has been applied (ON LOW) for 50ms PBSTAT goes LOW and LDO2 is enabled. Once enabled, LDO2 slews up and enters regulation. The actual slew rate is controlled by the soft-start function of LDO2 which ramps the LDO reference up over a 200µs period typically. After a 14ms delay from LDO2 being enabled, Buck1 is enabled and slews up into regulation. When Buck1 is within about 8% of final regulation, Buck2 is enabled and slews up into regulation. The bucks also have a softstart function to limit inrush current at start-up. 230ms after Buck2 is within 8% of final regulation, the PGOOD output will go high impedance (not shown in Figure 18). The regulators in Figure 18 are slewing up with nominal output capacitors and no load. Adding a load or increasing output capacitance on any of the outputs will reduce the slew rate and lengthen the time it takes the regulator to get into regulation. There are only two methods to power down the LTC3677-3 supplies: 1) PWR_ON goes LOW; 2) VOUT drops below the VOUT UVLO threshold. If the μC/μP controls shutdown by bringing PWR_ON LOW, it is possible that the application can hang with all supplies enabled if the μC/μP fails to reset correctly on hard reset. In this case the battery will continue to be drained until VOUT drops below the VOUT UVLO threshold, or the user intervenes to shut down the application manually. The application can be shut down manually by removing the battery and any external supplies, or by providing a suicide button that will bring PWR_ON LOW when pressed. VOUT UVLO >14 SEC ON (PB) 50ms PBSTAT PWR_ON BUCK1 BUCK2 LDO1 14 SEC PGOOD STATE 1 PBSTAT 0 LDO2 1V/DIV 0V BUCK1 1V/DIV 0V BUCK2 2V/DIV 0V 2ms/DIV 36773 F18 36773 F17 1.8ms PON Figure 18. Power-Up Sequencing Figure 17. Hard Reset Timing 36773f 39 LTC3677-3 OPERATION Layout and Thermal Considerations Printed Circuit Board Power Dissipation In order to be able to deliver maximum charge current under all conditions, it is critical that the exposed ground pad on the backside of the LTC3677-3 package be soldered to a ground plane on the board. Correctly soldered to 2500mm2 ground plane on a double-sided 1oz copper board the LTC3677-3 has a thermal resistance (θJA) of approximately 45°C/W. Failure to make good thermal contact between the exposed pad on the backside of the package and a adequately sized ground plane will result in thermal resistances far greater than 45°C/W. The conditions that cause the LTC3677-3 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the part. For high charge currents with a wall adapter applied to VOUT , the LTC3677-3 power dissipation is approximately: PD = (VOUT – BAT) • IBAT + PDREGS where PD is the total power dissipated, VOUT is the supply voltage, BAT is the battery voltage and IBAT is the battery charge current. PDREGS is the sum of power dissipated onchip by the step-down switching, and LDO regulators. The power dissipated by a step-down switching regulator can be estimated as follows: ( PD(SWx ) = OUTx • IOUTx ) 100 – Eff • 100 where OUTx is the programmed output voltage, IOUTx is the load current and Eff is the % efficiency which can be measured or looked up on an efficiency table for the programmed output voltage. The power dissipated on chip by a LDO regulator can be estimated as follows: PDLDOx = (VINLDOx – LDOx) • ILDOx where LDOx is the programmed output voltage, VINLDOx is the LDO supply voltage and ILDOx is the LDO output load current. Note that if the LDO supply is connected to one of the buck output, then its supply current must be added to the buck regulator load current for calculating the buck power loss. Thus the power dissipated by all regulators is: PDREGS = PDSW1 + PDSW2 + PDSW3 + PDLDO1 + PDLDO2 It is not necessary to perform any worst-case power dissipation scenarios because the LTC3677-3 will automatically reduce the charge current to maintain the die temperature at approximately 110°C. However, the approximate ambient temperature at which the thermal feedback begins to protect the IC is: TA = 110°C – PD • θJA Example: Consider the LTC3677-3 operating from a wall adapter with 5V (VOUT) providing 1A (IBAT) to charge a Li-Ion battery at 3.3V (BAT). Also assume PDREGS = 0.3W, so the total power dissipation is: PD = (5V – 3.3V) • 1A + 0.3W = 2W The ambient temperature above which the LTC3677-3 begins to reduce the 1A charge current, is approximately TA = 110°C – 2W • 45°C/W = 20°C The LTC3677-3 can be used above 20°C, but the charge current will be reduced below 1A. The charge current at a given ambient temperature can be approximated by: PD = Thus: 110°C – TA = VOUT – BAT • IBAT + PD(REGS) θJA ( ) (110°C – TA ) θJA – PD(REGS) I = BAT VOUT – BAT 36773f 40 LTC3677-3 OPERATION Consider the previous example with an ambient temperature of 55°C. The charge current will be reduced to approximately: 110°C – 55°C – 0.3W 45°C/W IBAT = 5V – 3.3V IBAT = 1.22 – 0.3W = 542mA 1.7 V Printed Circuit Board Layout When laying out the printed circuit board, the following list should be followed to ensure proper operation of the LTC3677-3: 1.The exposed pad of the package (Pin 45) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2.The step-down switching regulator input supply pins (VIN12 and VIN3) and their respective decoupling capacitors should be kept as short as possible. The GND side of these capacitors should connect directly to the ground plane of the part. These capacitors provide the AC current to the internal power MOSFETs and their drivers. It’s important to minimizing inductance from these capacitors to the pins of the LTC3677-3. Connect VIN12 and VIN3 to VOUT through a short low impedance trace. 3.The switching power traces connecting SW1, SW2, and SW3 to their respective inductors should be minimized to reduce radiated EMI and parasitic coupling. Due to the large voltage swing of the switching nodes, sensitive nodes such as the feedback nodes (FBx and LDOx_FB) should be kept far away or shielded from the switching nodes or poor performance could result. 4.Connections between the step-down switching regulator inductors and their respective output capacitors should be kept as short as possible. The GND side of the output capacitors should connect directly to the thermal ground plane of the part. 5.Keep the buck feedback pin traces (FB1, FB2, and FB3) as short as possible. Minimize any parasitic capacitance between the feedback traces and any switching node (i.e., SW1, SW2, SW3, and logic signals). If necessary shield the feedback nodes with a GND trace. 6.Connections between the LTC3677-3 power path pins (VBUS and VOUT) and their respective decoupling capacitors should be kept as short as possible. The GND side of these capacitors should connect directly to the ground plane of the part. 36773f 41 LTC3677-3 Typical Application 5V WALL ADAPTER 4 13 8 40 USB WALL ACPR OVGATE OVSENSE 2.1k 43 PROG CLPROG 10 DVCC 11 SDA 12 SCL 499k µC/µP VIN12 LTC3677-3 36 DVCC SDA SCL 499k EXTPWR PBSTAT PWR_ON 30 VINLDO2 27 VINLDO1 39 VOUT VBUS 10µF 2k Si2333DS 41 VIN3 10µF 2.2µF 32 6 2.2µF 44 CHRG 37 IDGATE 38 BAT 34 100k NTCBIAS 35 NTC 499k 42 EXTPWR 16 PBSTAT 14 PWR_ON NC VOUT SYSTEM LOAD 20µF 1k Si2333DS (OPT) + BAT Li-Ion 100k NTC 3, 9, 18 ,19, 20, 22 KILL EN3 RST ILIM0 ILIM1 PUSHBUTTON 17 EN3 1 ILIM0 2 ILIM1 15 VLDO1 3.3V 150mA VLDO2 1.4V 150mA 28 1µF 324k 1.02M 23 29 1µF 464k 348k 24 SW1 FB1 33 SW2 LDO1_FB FB2 SW3 LDO2 LDO2_FB FB3 PGOOD 10pF 26 ON LDO1 4.7µH 31 649k 10µF 4.7µH 10pF 25 5 806k 1.02M 324k 10µF 3.3µH 10pF 7 232k 464k 10µF VOUT1 1.8V 500mA VOUT2 3.3V 500mA VOUT3 1.2V 800mA 21 GND 45 100k 36773 TA02 36773f 42 LTC3677-3 Package Description UFF Package Variation: UFFMA UFFMA Package 44-Lead Plastic QFN (4mm × 7mm) 44-Lead Plastic QFN (4mm s 7mm) (Reference LTC DWG # 05-08-1762 Rev Ø) (Reference LTC DWG # 05-08-1762 Rev Ø) 1.48 ±0.05 0.70 ±0.05 4.50 ±0.05 3.10 ±0.05 2.40 REF 1.70 ±0.05 2.56 ±0.05 2.02 ±0.05 2.76 ±0.05 2.64 ±0.05 0.98 ±0.05 PACKAGE OUTLINE 0.20 ±0.05 5.60 REF 6.10 ±0.05 7.50 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p0.10 0.75 p0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 2.40 REF 43 0.00 – 0.05 44 0.40 p0.10 1 2 PIN 1 TOP MARK (SEE NOTE 6) 2.64 ±0.10 2.56 ±0.10 7.00 p0.10 5.60 REF 1.70 ±0.10 2.76 ±0.10 R = 0.10 TYP 0.74 ±0.10 R = 0.10 TYP 0.74 ±0.10 (UFF44MA) QFN REF Ø 1107 0.200 REF R = 0.10 TYP 0.98 ±0.10 0.20 p0.05 0.40 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 36773f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 43 LTC3677-3 Typical application Si2333DS 5V WALL ADAPTER Si2306BDS D3 5.6V 4 R1 500k 13 6.2k 8 OPTIONAL OVERVOLTAGE/ REVERSE VOLTAGE PROTECTION 40 10µF 2k 36 2.1k 43 10 11 12 DVCC SDA SCL 499k 499k EXTPWR PBSTAT PWR_ON VINLDO1 OVSENSE VOUT USB µC/µP WALL ACPR OVGATE Si2333DS 41 39 10µF 2.2µF 32 VBUS VIN12 2.2µF LTC3677-3 6 VIN3 44 CHRG 37 PROG IDGATE 38 BAT CLPROG 34 100k NTCBIAS 35 DVCC NTC SDA SCL 499k 42 EXTPWR 16 PBSTAT 14 PWR_ON NC VOUT SYSTEM LOAD 20µF 30 1k Si2333DS (OPT) + BAT Li-Ion 100k NTC 3, 9, 18 ,19, 20, 22 KILL EN3 ILIM0 ILIM1 RST PUSHBUTTON 17 EN3 1 ILIM0 2 ILIM1 15 VLDO1 2.5V 150mA VLDO2 1.0V 150mA 28 1µF 470k 1.00M 23 29 1µF 464k 115k 24 SW1 FB1 VINLDO2 ON SW2 LDO1 LDO1_FB FB2 SW3 LDO2 LDO2_FB FB3 GND PGOOD 33 4.7µH 10pF 26 1.02M 324k 10µF VOUT1 3.3V 500mA 30 31 4.7µH 10pF 25 5 806k 649k 10µF 3.3µH 10pF 7 402k 649k 10µF VOUT2 1.8V 500mA VOUT3 1.3V 800mA 21 45 100k 36773 TA03 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC3556 High Efficiency USB Power Manager Plus Dual Buck Plus Buck-Boost DC/DC PMIC Two 400mA Synchronous Buck Regulators, One 1A Buck-Boost Regulator, 4mm × 5mm QFN28 Package. LTC3557/ LTC3557-1 USB Power Manager with Li-Ion/Polymer Linear Power Manager and Three Buck Regulators, 4mm × 4mm QFN28 Package, Charger and Triple Synchronous Buck Converter LTC3557-1 Version Has 4.1V Float Voltage. LTC3577/ LTC3577-1 Highly Integrated Protable/Navigation PMIC Linear Power Manager and Three Buck Regulators, 10-LED Boost Regulator, 2× 150mA LDOs, 4mm × 7mm QFN44 Package, LTC3577-1 Version Has 4.1V Float Voltage. 36773f 44 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 0310 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2010