LINEAR LTC3556

LTC3556
High Efficiency USB Power
Manager with Dual Buck
and Buck-Boost DC/DCs
DESCRIPTION
FEATURES
POWER MANAGER
n High Efﬁciency Switching PowerPathTM Controller
with Bat-TrackTM Adaptive Output Control
n Programmable USB or Wall Current Limit
(100mA/500mA/1A)
n Full Featured Li-Ion/Polymer Battery Charger
n Instant-On Operation with a Discharged Battery
n 1.5A Maximum Charge Current
n Internal 180mΩ Ideal Diode Plus External Ideal Diode
Controller Powers Load in Battery Mode
n Low No-Load I when Powered from BAT (<30μA)
Q
DC/DCs
n Dual High Efﬁciency Buck DC/DCs (400mA/400mA I
OUT)
n High Efﬁciency Buck-Boost DC/DC (1A I
)
OUT
n All Regulators Operate at 2.25MHz
n Dynamic Voltage Scaling on Two Buck Outputs
n I2C Control of Enables, Mode, Two V
OUT Settings
n ENALL Pin with Power-Up Sequence Control
n Low No-Load Quiescent Current: 20μA Each
APPLICATIONS
n
n
The LTC®3556 is a highly integrated power management
and battery charger IC for Li-Ion/Polymer battery applications. It includes a high efﬁciency current limited switching
PowerPath manager with automatic load prioritization, a
battery charger, an ideal diode, and three synchronous
switching regulators (two bucks and one buck-boost).
Designed speciﬁcally for USB applications, the LTC3556’s
switching power manager automatically limits input current to a maximum of either 100mA or 500mA for USB
applications or 1A for adapter-powered applications.
The LTC3556’s switching input stage transmits nearly all of
the 2.5W available from the USB port to the system load
with minimal power wasted as heat. This feature allows
the LTC3556 to provide more power to the application and
eases the constraint of thermal budgeting in small spaces.
The two buck regulators can provide up to 400mA each
and the buck-boost can deliver 1A.
The LTC3556 is available in the low proﬁle 28-pin (4mm
× 5mm × 0.75mm) QFN surface mount package.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. PowerPath
and Bat-Track are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 6522118 and 6404251.
HDD-Based MP3 Players, PDAs, GPS, PMPs
Other USB-Based Handheld Products
TYPICAL APPLICATION
Battery Charge Current
vs Battery Voltage
High Efﬁciency PowerPath Manager, Dual Buck, Buck-Boost and LDO
TO OTHER
LOADS
USB COMPLIANT
STEP-DOWN
REGULATOR
700
CC/CV
BATTERY
CHARGER
OPTIONAL
0V
+
CHARGE
T
Li-Ion
LTC3556
ALWAYS ON LDO
DUAL HIGH EFFICIENCY
BUCKS
ENALL
HIGH EFFICIENCY
BUCK-BOOST
SEQ
I2C
3
I2C PORT
BATTERY CHARGE CURRENT
600
1
2
3
3.3V/25mA
0.8V TO 3.6V/400mA
0.8V TO 3.6V/400mA
2.5V to 3.3V/1A
PGOODALL
RTC/LOW
POWER LOGIC
CHARGE CURRENT (mA)
USB/WALL
4.5V TO 5.5V
500mA USB CURRENT LIMIT
400
300
200
100
MEMORY
CORE
μP
EXTRA CURRENT
FOR FASTER CHARGING
500
VBUS = 5V
5X MODE
BATTERY CHARGER PROGRAMMED FOR 1A
0
2.8
3
3.2 3.4 3.6
3.8
BATTERY VOLTAGE (V)
4
4.2
3556 TA01b
HDD/IO
3556 TA01
3556f
1
LTC3556
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
BAT
VOUT
SW
VBUS
TOP VIEW
SEQ
ENALL
VBUS (Transient) t < 1ms, Duty Cycle < 1% .. –0.3V to 7V
VIN1, VIN2, VIN3, VBUS (Static), DVCC,
FB1, FB2, NTC, BAT, ENALL, SCL, SDA,
PGOODALL, CHRG ....................................... –0.3V to 6V
SEQ ....................–0.3V to Lesser of 6V or (VOUT + 0.3V)
FB3, VC3 .............. –0.3V to Lesser of 6V or (VIN3 + 0.3V)
ICLPROG ....................................................................3mA
IPGOODALL, ICHRG ....................................................50mA
IPROG ........................................................................2mA
ILDO3V3 ...................................................................30mA
ISW1, ISW2 ............................................................600mA
ISW, IBAT, IVOUT.............................................................2A
ISWAB3, ISWCD3, IVOUT3 .............................................2.5A
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range................... –65°C to 125°C
28 27 26 25 24 23
LDO3V3 1
22 GATE
CLPROG 2
21 CHRG
NTC 3
20 PROG
SW1 4
19 SW2
29
VIN1 5
18 VIN2
FB1 6
17 FB2
FB3 7
16 SDA
VC3 8
15 PGOODALL
SWCD3
SCL
VOUT3
VIN3
DVCC
SWAB3
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm s 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3556EUFD#PBF
LTC3556EUFD#TRPBF
3556
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PowerPath Switching Regulator
VBUS
Input Supply Voltage
4.35
IBUSLIM
Total Input Current
1x Mode, VOUT = BAT
5x Mode, VOUT = BAT
10x Mode, VOUT = BAT
Suspend Mode, VOUT = BAT
IVBUSQ
VBUS Quiescent Current
1x Mode, IOUT = 0mA
5x Mode, IOUT = 0mA
10x Mode, IOUT = 0mA
Suspend Mode, IOUT = 0mA
7
15
15
0.044
mA
mA
mA
mA
hCLPROG (Note 4)
Ratio of Measured VBUS Current to
CLPROG Program Current
1x Mode
5x Mode
10x Mode
Suspend Mode
224
1133
2140
11.3
mA/mA
mA/mA
mA/mA
mA/mA
l
l
l
l
87
436
800
0.31
5.5
95
460
860
0.38
100
500
1000
0.50
V
mA
mA
mA
mA
3556f
2
LTC3556
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
IOUT(POWERPATH)
VOUT Current Available Before Loading 1x Mode, BAT = 3.3V
BAT
5x Mode, BAT = 3.3V
10x Mode, BAT = 3.3V
Suspend Mode
135
672
1251
0.32
mA
mA
mA
mA
VCLPROG
CLPROG Servo Voltage in Current
Limit
1x, 5x, 10x Modes
Suspend Mode
1.188
100
V
mV
VUVLO_VBUS
VBUS Undervoltage Lockout
Rising Threshold
Falling Threshold
3.95
TYP
4.30
4.00
MAX
4.35
V
V
VUVLO_VBUS-BAT
VBUS to BAT Differential Undervoltage
Lockout
Rising Threshold
Falling Threshold
VOUT
VOUT Voltage
1x, 5x, 10x Modes, 0V < BAT < 4.2V,
IOUT = 0mA, Battery Charger Off
3.4
BAT +
0.3
4.7
V
USB Suspend Mode, IOUT = 250μA
4.5
4.6
4.7
V
1.8
2.25
2.7
MHz
fOSC
200
50
UNITS
l
Switching Frequency
mV
mV
RPMOS_POWERPATH PMOS On-Resistance
0.18
Ω
RNMOS_POWERPATH NMOS On-Resistance
0.30
Ω
2
3
A
A
IPEAK_POWERPATH
Peak Switch Current Limit
1x, 5x Modes
10x Mode
Battery Charger
VFLOAT
BAT Regulated Output Voltage
ICHG
Constant Current Mode Charge
Current
IBAT
Battery Drain Current
VPROG
PROG Pin Servo Voltage
VPROG_TRKL
PROG Pin Servo Voltage in Trickle
Charge
VC/10
C/10 Threshold Voltage at PROG
l
RPROG = 5k
VBUS > VUVLO, Battery Charger Off, IOUT = 0μA
VBUS = 0V, IOUT = 0μA (Ideal Diode Mode)
4.179
4.165
4.200
4.200
4.221
4.235
V
V
980
185
1022
204
1065
223
mA
mA
2
3.5
27
5
38
μA
μA
BAT < VTRKL
hPROG
Ratio of IBAT to PROG Pin Current
ITRKL
Trickle Charge Current
BAT < VTRKL
VTRKL
Trickle Charge Threshold Voltage
BAT Rising
ΔVTRKL
Trickle Charge Hysteresis Voltage
VRECHRG
Recharge Battery Threshold Voltage
Threshold Voltage Relative to VFLOAT
2.7
1.000
V
0.100
V
100
mV
1022
mA/mA
100
mA
2.85
3.0
135
–75
–100
V
mV
–125
mV
tTERM
Safety Timer Termination
Timer Starts When BAT = VFLOAT
3.3
4
5
Hour
tBADBAT
Bad Battery Termination Time
BAT < VTRKL
0.42
0.5
0.63
Hour
hC/10
End of Charge Indication Current Ratio (Note 5)
0.088
0.1
0.112
mA/mA
VCHRG
CHRG Pin Output Low Voltage
ICHRG = 5mA
65
100
mV
ICHRG
CHRG Pin Leakage Current
VCHRG = 5V
1
μA
RON_CHG
Battery Charger Power FET
On-Resistance (Between VOUT and BAT)
0.18
Ω
TLIM
Junction Temperature in Constant
Temperature Mode
110
°C
3556f
3
LTC3556
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCOLD
Cold Temperature Fault Threshold
Voltage
Rising Threshold
Hysteresis
75.0
76.5
1.5
78.0
%VBUS
%VBUS
VHOT
Hot Temperature Fault Threshold
Voltage
Falling Threshold
Hysteresis
33.4
34.9
1.5
36.4
%VBUS
%VBUS
VDIS
NTC Disable Threshold Voltage
Falling Threshold
Hysteresis
0.7
1.7
50
2.7
%VBUS
mV
INTC
NTC Leakage Current
VNTC = VBUS = 5V
–50
50
nA
VFWD
Forward Voltage
VBUS = 0V, IOUT = 10mA
IOUT = 10mA
RDROPOUT
Internal Diode On-Resistance, Dropout VBUS = 0V
IMAX_DIODE
Internal Diode Current Limit
NTC
Ideal Diode
2
15
mV
mV
0.18
Ω
1.6
A
Always On 3.3V Supply
VLDO3V3
Regulated Output Voltage
0mA < ILDO3V3 < 25mA
3.1
3.3
3.5
V
RCL_LDO3V3
Closed-Loop Output Resistance
4
Ω
ROL_LDO3V3
Dropout Output Resistance
23
Ω
Logic (ENALL, PGOODALL)
VIL
Logic Low Input Voltage
ENALL Pin
0.4
VIH
Logic High Input Voltage
ENALL Pin
RPD
Pull-Down Resistance
ENALL Pin
4.5
VOL
Logic Low Output Voltage
PGOODALL Pin, IPULL-UP = 5mA
0.07
IOH
Logic High Leakage Current
PGOODALL Pin, VPGOODALL = 5V
tPGOODALL
PGOODALL Assertion Delay
1.2
V
V
MΩ
0.2
1
230
V
μA
ms
I2C Port (Note 9)
DVCC
Input Supply Voltage
IDVCC
DVCC Current
1.6
SCL/SDA = 0kHz
0.3
5.5
V
1
μA
VDVCC_UVLO
DVCC UVLO
ADDRESS
I2C Address
1.0
V
VIH SDA, SCL
VIL SDA, SCL
Input High Voltage
Input Low Voltage
70
IIH, IIL SDA, SCL
Input High/Low Current
–1
VOL SDA
SDA Output Low Voltage
fSCL
Clock Operating Frequency
tBUF
Bus Free Time Between Stop and Start
Condition
1.3
μs
tHD_STA
Hold Time After (Repeated) Start
Condition
0.6
μs
tSU_STA
Repeated Start Condition Setup Time
0.6
μs
tSU_STO
Stop Condition Setup Time
0.6
μs
tHD_DAT(O)
Data Hold Time Output
0001 001[0]
ISDA = 3mA
0
0
30
%DVCC
%DVCC
1
μA
0.4
V
400
kHz
900
ns
3556f
4
LTC3556
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
tHD_DAT(I)
Data Hold Time Input
tSU_DAT
CONDITIONS
MIN
TYP
MAX
UNITS
0
ns
Data Setup Time
100
ns
tLOW
SCL Clock Low Period
1.3
μs
tHIGH
SCL Clock High Period
tf
Clock/Data Fall Time
CB = Capacitance of One BUS Line (pF)
20 + 0.1CB
300
ns
tr
Clock/Data Rise Time
CB = Capacitance of One BUS Line (pF)
20 + 0.1CB
300
ns
tSP
Input Spike Suppression Pulse Width
50
ns
0.6
μs
Switching Regulators 1, 2 and 3
VIN1,2,3
Input Supply Voltage
VOUTUVLO
VOUT UVLO—VOUT Falling
VOUT UVLO—VOUT Rising
fOSC
2.7
VIN1,2,3 Connected to VOUT Through Low
Impedance. Switching Regulators are
Disabled in UVLO
2.5
l
Oscillator Frequency
1.8
5.5
V
2.6
2.8
2.9
V
V
2.25
2.7
MHz
225
35
20
20
400
60
35
35
1
μA
μA
μA
μA
μA
800
1100
mA
Switching Regulator 1 (Buck)
IVIN1
Pulse Skip Mode Input Current
Burst Mode® Input Current
Forced Burst Mode Input Current
LDO Mode Input Current
Shutdown Input Current
IOUT1 = 0μA (Note 6)
IOUT1 = 0μA (Note 6)
IOUT1 = 0μA (Note 6)
IOUT1 = 0μA (Note 6)
IOUT1 = 0μA, FB1 = 0V
ILIM1
PMOS Switch Current Limit
Pulse Skip/Burst Mode Operation
600
IOUT1
Available Output Current
Pulse Skip/Burst Mode Operation (Note 9)
Forced Burst Mode Operation (Note 9)
LDO Mode (Note 9)
400
60
50
mA
mA
mA
VFBHIGH1
Maximum Servo Voltage
Full Scale (1, 1, 1, 1) (Note 7)
l
0.780
0.800
0.820
V
VFBLOW1
Minimum Servo Voltage
Zero Scale (0, 0, 0, 0) (Note 7)
l
0.405
0.425
0.445
V
VLSB1
VFB1 Servo Voltage Step Size
25
mV
RP1
PMOS RDS(ON)
0.6
Ω
RN1
NMOS RDS(ON)
0.7
Ω
RLDO_CL1
LDO Mode Closed-Loop ROUT
0.25
Ω
RLDO_OL1
LDO Mode Open-Loop ROUT
(Note 8)
2.5
Ω
IFB1
FB1 Input Current
VFB1 = 0.85V
D1
Maximum Duty Cycle
RSW1
SW1 Pull-Down in Shutdown
–50
l
50
100
nA
%
10
kΩ
Switching Regulator 2 (Buck)
IVIN2
Pulse Skip Mode Input Current
Burst Mode Input Current
Forced Burst Mode Input Current
LDO Mode Input Current
Shutdown Input Current
IOUT2 = 0μA (Note 6)
IOUT2 = 0μA (Note 6)
IOUT2 = 0μA (Note 6)
IOUT2 = 0μA (Note 6)
IOUT2 = 0μA, FB2 = 0V
ILIM2
PMOS Switch Current Limit
Pulse Skip/Burst Mode Operation
600
IOUT2
Available Output Current
Pulse Skip/Burst Mode Operation (Note 9)
Forced Burst Mode Operation (Note 9)
LDO Mode (Note 9)
400
60
50
225
35
20
20
400
60
35
35
1
μA
μA
μA
μA
μA
800
1100
mA
mA
mA
mA
Burst Mode is a registered trademark of Linear Technology Corporation.
3556f
5
LTC3556
ELECTRICAL CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V,
RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VFB2
VFB2 Servo Voltage
(Note 7)
RP2
PMOS RDS(ON)
0.6
Ω
RN2
NMOS RDS(ON)
0.7
Ω
RLDO_CL2
LDO Mode Closed-Loop ROUT
0.25
Ω
RLDO_OL2
LDO Mode Open-Loop ROUT
(Note 8)
IFB2
FB2 Input Current
VFB2 = 0.85V
D2
Maximum Duty Cycle
RSW2
SW2 Pull-Down in Shutdown
l
MIN
TYP
MAX
UNITS
0.780
0.800
0.820
V
2.5
–50
l
Ω
50
100
nA
%
10
kΩ
Switching Regulator 3 (Buck-Boost)
IVIN3
Input Current
PWM Mode, IOUT3 = 0μA
Burst Mode Operation, IOUT3 = 0μA
Shutdown
220
13
0
400
20
1
μA
μA
μA
VOUT3(LOW)
Minimum Regulated Output Voltage
For Burst Mode Operation or Synchronous
PWM Operation
2.65
2.75
V
A
VOUT3(HIGH)
Maximum Regulated Output Voltage
ILIMF3
Forward Current Limit (Switch A)
5.50
5.60
l
2
2.5
3
IPEAK3(BURST)
Forward Burst Current Limit (Switch A) Burst Mode Operation
l
200
275
350
IZERO3(BURST)
Reverse Burst Current Limit (Switch D) Burst Mode Operation
l
–30
0
30
IMAX3(BURST)
Maximum Deliverable Output Current
in Burst Mode Operation
2.7V ≤ VIN3 ≤ 5.5V, 2.75V ≤ VOUT3 ≤ 5.5V
(Note 9)
VFBHIGH3
Maximum Servo Voltage
Full Scale (1, 1, 1, 1)
l
0.780
0.800
0.820
V
VFBLOW3
Minimum Servo Voltage
Zero Scale (0, 0, 0, 0)
l
0.405
0.425
0.445
V
VLSB3
VFB3 Servo Voltage Step Size
PWM Mode
V
50
mA
mA
mA
25
mV
IFB3
FB3 Input Current
VFB3 = 0.8V
RDS(ON)P
PMOS RDS(ON)
Switches A, D
0.22
Ω
RDS(ON)N
NMOS RDS(ON)
Switches B, C
0.17
Ω
ILEAK(P)
PMOS Switch Leakage
Switches A, D
–1
1
μA
ILEAK(N)
NMOS Switch Leakage
Switches B, C
–1
1
μA
RVOUT3
VOUT3 Pull-Down in Shutdown
50
10
DBUCK(MAX)
Maximum Buck Duty Cycle
PWM Mode
DBOOST(MAX)
Maximum Boost Duty Cycle
PWM Mode
tSS3
Soft-Start Time
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3556E is guaranteed to meet performance speciﬁcations
from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3556E includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the speciﬁed maximum operating
junction temperature may impair device reliability.
6
–50
l
100
nA
kΩ
%
75
%
0.5
ms
Note 4: Total input current is the sum of quiescent current, IVBUSQ, and
measured current given by:
VCLPROG/RCLPROG • (hCLPROG +1)
Note 5: hC/10 is expressed as a fraction of measured full charge current
with indicated PROG resistor.
Note 6: FBx above regulation such that regulator is in sleep. Speciﬁcation
does not include resistive divider current reﬂected back to VINx.
Note 7: Applies to Pulse Skip, Burst Mode operation and Forced Burst
Mode operation only.
Note 8: Inductor series resistance adds to open-loop ROUT.
Note 9: Guaranteed by design.
3556f
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Ideal Diode Resistance
vs Battery Voltage
Ideal Diode V-I Characteristics
1.0
0.25
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
4.50
0.20
INTERNAL IDEAL
DIODE ONLY
0.4
0.2
4.25
INTERNAL IDEAL
DIODE
0.15
0.10
INTERNAL IDEAL DIODE
WITH SUPPLEMENTAL
EXTERNAL VISHAY
Si2333 PMOS
0.05
VBUS = 0V
VBUS = 5V
0.12
0.16
0.08
FORWARD VOLTAGE (V)
0
2.7
0.20
3.0
3.6
3.9
3.3
BATTERY VOLTAGE (V)
3556 G01
600
125
VBUS = 5V
RPROG = 1k
RCLPROG = 3.01k
CHARGE CURRENT (mA)
400
300
200
25
VBUS = 5V
RPROG = 1k
RCLPROG = 3.01k
75
50
90
1x USB SETTING,
BATTERY CHARGER SET FOR 1A
0
2.7
3.0
100
EFFICIENCY (%)
70
60
80
1x CHARGING
EFFICIENCY
RCLPROG = 3.01k
RPROG = 1k
IVOUT = 0mA
5x CHARGING
EFFICIENCY
70
3556 G07
3.6
3.9
3.3
BATTERY VOLTAGE (V)
60
2.7
3.0
3.6
3.9
3.3
BATTERY VOLTAGE (V)
4.2
VBUS Current vs VBUS Voltage
(Suspend)
50
1
3.0
3556 G06
Battery Charging Efﬁciency vs
Battery Voltage with No External
Load (PBAT/PBUS)
80
VBUS = 5V
(SUSPEND MODE)
0
2.7
4.2
3.3
3.6
3.9
BATTERY VOLTAGE (V)
5x, 10x MODE
0.1
LOAD CURRENT (A)
10
3556 G05
90
40
0.01
15
5
PowerPath Switching Regulator
Efﬁciency vs Load Current
1x MODE
IVOUT = 0μA
VBUS = 0V
100
4.2
1000
20
3556 G04
BAT = 3.8V
600
800
400
LOAD CURRENT (mA)
Battery Drain Current
vs Battery Voltage
25
5x USB SETTING,
BATTERY CHARGER SET FOR 1A
0
3.0
3.3
3.6
2.7
3.9
BATTERY VOLTAGE (V)
200
0
3556 G03
4.2
3556 G08
50
BAT = 3.8V
IVOUT = 0mA
QUIESCENT CURRENT (μA)
CHARGE CURRENT (mA)
150
100
EFFICIENCY (%)
3.25
4.2
USB Limited Battery Charge
Current vs Battery Voltage
700
100
BAT = 3.4V
3.75
3556 G02
USB Limited Battery Charge
Current vs Battery Voltage
500
4.00
3.50
BATTERY CURRENT (μA)
0.04
OUTPUT VOLTAGE (V)
0.6
0
VBUS = 5V
5x MODE
BAT = 4V
RESISTANCE (Ω)
CURRENT (A)
0.8
0
Output Voltage vs Load Current
(Battery Charger Disabled)
40
30
20
10
0
0
1
3
2
BUS VOLTAGE (V)
4
5
3556 G09
3556f
7
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage vs Load Current
in Suspend
VBUS Current vs Load Current
in Suspend
5.0
3.5
3.0
0.1
0.3
0.2
0.3
0.4
0.2
LOAD CURRENT (mA)
0
0.5
0.3
0.4
0.2
LOAD CURRENT (mA)
3556 G10
600
0.5
200
15
20
10
LOAD CURRENT (mA)
25
Low-Battery (Instant On) Output
Voltage vs Temperature
4.21
3.68
4.20
3.66
BAT = 2.7V
IVOUT = 100mA
5x MODE
OUTPUT VOLTAGE (V)
FLOAT VOLTAGE (V)
THERMAL REGULATION
5
0
3556 G12
500
CHARGE CURRENT (mA)
BAT = 3V
BAT = 3.1V
BAT = 3.2V
BAT = 3.3V
2.8
Battery Charger Float Voltage
vs Temperature
300
BAT = 3.6V
3556 G11
Battery Charge Current
vs Temperature
400
BAT = 3.5V
3.0
2.6
0.1
0
BAT = 3.4V
3.2
0.1
VBUS = 5V
BAT = 3.3V
RCLPROG = 3k
0
BAT = 3.9V, 4.2V
OUTPUT VOLTAGE (V)
VBUS CURRENT (mA)
OUTPUT VOLTAGE (V)
VBUS = 5V
BAT = 3.3V
RCLPROG = 3.01k
0.4
4.0
2.5
3.4
0.5
4.5
3.3V LDO Output Voltage
vs Load Current, VBUS = 0V
4.19
4.18
3.64
3.62
100
RPROG = 2k
10x MODE
0
–40 –20 0
20 40 60 80
TEMPERATURE (°C)
4.17
–40
100 120
–15
35
10
TEMPERATURE (°C)
60
3556 G13
FREQUENCY (MHz)
2.2
BAT = 3V
VBUS = 0V
2.0
60
70
VBUS = 5V
IVOUT = 0μA
5x MODE
12
85
VBUS Quiescent Current in
Suspend vs Temperature
QUIESCENT CURRENT (μA)
15
QUIESCENT CURRENT (mA)
2.6
VBUS = 5V
35
10
TEMPERATURE (°C)
3556 G15
VBUS Quiescent Current
vs Temperature
BAT = 3.6V
VBUS = 0V
–15
3556 G14
Oscillator Frequency
vs Temperature
2.4
3.60
–40
85
9
1x MODE
6
IVOUT = 0μA
60
50
40
BAT = 2.7V
VBUS = 0V
1.8
–40
–15
35
10
TEMPERATURE (°C)
60
85
3556 G16
3
–40
–15
35
10
TEMPERATURE (°C)
60
85
3556 G17
30
–40
–15
35
10
TEMPERATURE (°C)
60
85
3556 G18
3556f
8
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
PGOODALL, CHRG Pin Current
vs Voltage (Pull-Down State)
50
VBUS = 5V
BAT = 3.8V
80
ILDO3V3
5mA/DIV
60
0mA
40
VLDO3V3
20mV/DIV
AC COUPLED
20
0
Battery Drain Current
vs Temperature
40
BATTERY CURRENT (μA)
PGOODALL, CHRG PIN CURRENT (mA)
100
3.3V LDO Step Response
(5mA to 15mA)
BAT = 3.8V
1
3
4
2
PGOODALL, CHRG PIN VOLTAGE (V)
0
30
20
10
3556 G20
20μs/DIV
BAT = 3.8V
VBUS = 0V
ALL REGULATORS OFF
0
–40
5
–15
35
10
TEMPERATURE (°C)
60
3556 G19
3556 G21
Switching Regulators 1, 2 Pulse
Skip Mode Quiescent Currents
1.95
VIN1,2 = 3.8V
100
100
90
1.90
1.85
250
1.80
1.75
225
VOUT1,2 = 1.25V
(PULSE SKIPPING)
200
–40
–15
35
10
TEMPERATURE (°C)
60
80
VOUT1,2 = 1.2V
70
VOUT1,2 = 1.8V
60
50
40
85
10
VIN1,2 = 3.8V
1
10
100
LOAD CURRENT (mA)
50
40
30
0
0.1
VIN1,2 = 3.8V
1
10
100
LOAD CURRENT (mA)
1000
3556 G25
1.845
Burst Mode
OPERATION
1.215
PULSE SKIP
MODE
10
100
LOAD CURRENT (mA)
1.823
PULSE SKIP MODE
1.800
FORCED
Burst Mode
OPERATION
1.778
FORCED
Burst Mode
OPERATION
1
VBUS = 3.8V
Burst Mode OPERATION
1.200
1.170
0.1
1000
Switching Regulators 1, 2 Load
Regulation at VOUT1,2 = 1.8V
VBUS = 3.8V
1.185
20
10
100
LOAD CURRENT (mA)
3556 G24
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
VOUT1,2 = 1.8V
VIN1,2 = 3.8V
1
3556 G23
1.230
60
10
0
0.1
1000
Switching Regulators 1, 2 Load
Regulation at VOUT1,2 = 1.2V
VOUT1,2 = 1.2V
70
40
20
0
VOUT1,2 = 2.5V
80
50
20
Switching Regulators 1, 2
Forced Burst Mode Efﬁciency
90
VOUT1,2 = 1.8V
60
30
3556 G22
100
VOUT1,2 = 1.2V
70
30
10
1.70
VOUT1,2 = 2.5V
90
VOUT1,2 = 2.5V
80
EFFICIENCY (%)
VOUT1,2 = 2.5V
(CONSTANT FREQUENCY)
INPUT CURRENT (mA)
INPUT CURRENT (μA)
300
275
Switching Regulators 1, 2
Burst Mode Efﬁciency
Switching Regulators 1, 2
Pulse Skip Mode Efﬁciency
EFFICIENCY (%)
325
85
1000
3556 G26
1.755
0.1
1
10
100
LOAD CURRENT (mA)
1000
3556 G27
3556f
9
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Regulator 3 Burst Mode
Operation Input Quiescent Current
Switching Regulators 1, 2 Load
Regulation at VOUT1,2 = 2.5V
14.0
VBUS = 3.8V
2600
VOUT3 = 3.3V
TA = 27°C
VIN3 = 3V
VIN3 = 3.6V
PULSE SKIP MODE
2.50
2550
VIN3 = 4.5V
2.53 Burst Mode OPERATION
VIN3 = 3.6V
13.0
IVIN3 (μA)
OUTPUT VOLTAGE (V)
13.5
FORCED
Burst Mode
OPERATION
2500
VIN3 = 3V
ILIMF3 (mA)
2.56
Switching Regulator 3 Forward
Current Limit vs Temperature
12.5
VIN3 = 4.5V
2450
12.0
2400
11.5
2350
2.47
2.44
0.1
1
10
100
LOAD CURRENT (mA)
11.0
–55 –35 –15
1000
5
25
45
65
2300
–55 –35 –15
85 105 125
5
25
45
65
85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3556 G28
3556 G30
3556 G29
RDS(ON)’s for Switching Regulator 3
vs Temperature
Switching Regulator 3 Efﬁciency
vs Load Current
0.30
0.40
0.25
0.35
100
0.20
VIN3 = VOUT3 = 3V
VIN3 = VOUT3 = 3.6V
VIN3 = VOUT3 = 4.5V
0.15
0.30
0.25
0.10
0.20
NMOS
VIN3 = 3V
0.05
VIN3 = 4.5V
0
–55 –35 –15
5
45
Burst Mode
OPERATION
CURVES
70
PWM MODE
CURVES
60
50
40
VOUT3 = 3.3V
TA = 27°C
30
20
0.15
VIN3 = 3.6V
25
80
EFFICIENCY (%)
PMOS
NMOS RDS(ON) (Ω)
PMOS RDS(ON) (Ω)
90
VIN3 = 3V
VIN3 = 3.6V
VIN3 = 4.5V
10
65
0.10
85 105 125
0
0.1
1
TEMPERATURE (°C)
10
100
LOAD CURRENT (mA)
3556 G32
3556 G31
Switching Regulator 3 PWM Mode
Efﬁciency vs Input Voltage
100
Switching Regulator 3 Reduction in
Current Deliverability at Low VIN3
300
IOUT3 = 50mA
VOUT3 = 3.3V
TA = 27°C
EFFICIENCY (%)
IOUT3 = 200mA
70
REDUCTION BELOW 1A (mA)
90
80
IOUT3 = 1000mA
60
50
40
30
20
10
0
2.7
3.1
3.5
250
200
150
STEADY STATE LOAD
100
START-UP WITH A
RESISTIVE LOAD
START-UP WITH A
CURRENT SOURCE LOAD
50
VOUT3 = 3.3V
TA = 27°C
3.9
4.3
VIN3 (V)
0
4.7
3556 G33
1000
2.7
3.1
3.5
3.9
4.3
VIN3 (V)
4.7
3556 G34
3556f
10
LTC3556
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Sequencing with SEQ = 0V
VIN1 = VIN2 = VIN3 = 4.2V
All Outputs Loaded with 5mA
Switching Regulator 3 Step
Response (0mA to 300mA)
VOUT3 V = 3.8V
100mV/DIV VIN3 = 3.3V
OUT3
AC
COUPLED
ENALL
VOUT3 = 3.3V
1V/DIV
VOUT2 = 1.8V
VOUT1 = 1.6V
300mA
IOUT3
200mA/
0
DIV
100μs/DIV
3556 G35
200μs/DIV
3556 G36
PIN FUNCTIONS
LDO3V3 (Pin 1): 3.3V LDO Output Pin. This pin provides
a regulated, always-on, 3.3V supply voltage. LDO3V3
gets its power from VOUT. It may be used for light loads
such as a watchdog microprocessor or real time clock.
A 1μF capacitor is required from LDO3V3 to ground. If
the LDO3V3 output is not used it should be disabled by
connecting it to VOUT.
CLPROG (Pin 2): USB Current Limit Program and Monitor Pin. A resistor from CLPROG to ground determines
the upper limit of the current drawn from the VBUS pin.
A fraction of the VBUS current is sent to the CLPROG pin
when the synchronous switch of the PowerPath switching
regulator is on. The switching regulator delivers power until
the CLPROG pin reaches 1.188V. Several VBUS current limit
settings are available via user input which will typically
correspond to the 500mA and 100mA USB speciﬁcations.
A multilayer ceramic averaging capacitor or R-C network
is required at CLPROG for ﬁltering.
NTC (Pin 3): Input to the Thermistor Monitoring Circuits.
The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the
battery’s temperature is out of range, charging is paused
until it re-enters the valid range. A low drift bias resistor
is required from VBUS to NTC and a thermistor is required
from NTC to ground. If the NTC function is not desired,
the NTC pin should be grounded.
SW1 (Pin 4): Power Transmission Pin for (Buck) Switching Regulator 1.
VIN1 (Pin 5): Power Input for (Buck) Switching Regulator 1. This pin will generally be connected to VOUT. A 1μF
MLCC capacitor is recommended on this pin.
FB1 (Pin 6): Feedback Input for (Buck) Switching Regulator 1. When regulator 1’s control loop is complete, this
pin servos to 1 of 16 possible set-points based on the
commanded value from the I2C serial port. See Table 4.
FB3 (Pin 7): Feedback Input for (Buck-Boost) Switching
Regulator 3. When regulator 3’s control loop is complete,
this pin servos to 1 of 16 possible set-points based on the
commanded value from the I2C serial port. See Table 4.
VC3 (Pin 8): Output of the Error Ampliﬁer and Voltage
Compensation Node for (Buck-Boost) Switching Regulator 3. External Type I or Type III compensation (to FB3)
connects to this pin. See Applications Information section
for selecting buck-boost compensation components.
SWAB3 (Pin 9): Switch Node for (Buck-Boost) Switching
Regulator 3. Connected to internal power switches A and B.
External inductor connects between this node and SWCD3.
DVCC (Pin 10): Logic Supply for the I2C Serial Port.
VIN3 (Pin 11): Power Input for (Buck-Boost) Switching
Regulator 3. This pin will generally be connected to VOUT. A
1μF (min) MLCC capacitor is recommended on this pin.
VOUT3 (Pin 12): Regulated Output Voltage for (Buck-Boost)
Switching Regulator 3.
3556f
11
LTC3556
PIN FUNCTIONS
SCL (Pin 13): Clock Input Pin for the I2C Serial Port. The
I2C logic levels are scaled with respect to DVCC.
to BAT. If the external ideal diode FET is not used, GATE
should be left ﬂoating.
SWCD3 (Pin 14): Switch Node for (Buck-Boost) Switching Regulator 3. Connected to internal power switches
C and D. External inductor connects between this node
and SWAB3.
BAT (Pin 23): Single Cell Li-Ion Battery Pin. Depending on
available VBUS power, a Li-Ion battery on BAT will either
deliver power to VOUT through the ideal diode or be charged
from VOUT via the battery charger.
PGOODALL (Pin 15): Logic Output. This in an open-drain
output which indicates that all enabled switching regulators have settled to their ﬁnal value. It can be used as a
power-on reset for the primary microprocessor.
VOUT (Pin 24): Output Voltage of the Switching PowerPath Controller and Input Voltage of the Battery Charger.
The majority of the portable product should be powered
from VOUT. The LTC3556 will partition the available power
between the external load on VOUT and the internal battery
charger. Priority is given to the external load and any extra
power is used to charge the battery. An ideal diode from
BAT to VOUT ensures that VOUT is powered even if the load
exceeds the allotted power from VBUS or if the VBUS power
source is removed. VOUT should be bypassed with a low
impedance ceramic capacitor.
SDA (Pin 16): Data Input Pin for the I2C Serial Port. The
I2C logic levels are scaled with respect to DVCC.
FB2 (Pin 17): Feedback Input for (Buck) Switching Regulator 2. When regulator 2’s control loop is complete, this
pin servos to a ﬁxed voltage of 0.8V.
VIN2 (Pin 18): Power Input for (Buck) Switching Regulator 2. This pin will generally be connected to VOUT. A 1μF
MLCC capacitor is recommended on this pin.
SW2 (Pin 19): Power Transmission Pin for (Buck) Switching Regulator 2.
PROG (Pin 20): Charge Current Program and Charge
Current Monitor Pin. Connecting a resistor from PROG
to ground programs the charge current. If sufﬁcient input power is available in constant-current mode, this pin
servos to 1V. The voltage on this pin always represents
the actual charge current.
CHRG (Pin 21): Open-Drain Charge Status Output. The
CHRG pin indicates the status of the battery charger. Four
possible states are represented by CHRG: charging, not
charging, unresponsive battery and battery temperature
out of range. CHRG is modulated at 35kHz and switches
between a low and a high duty cycle for easy recognition by either humans or microprocessors. See Table 1.
CHRG requires a pull-up resistor and/or LED to provide
indication.
GATE (Pin 22): Analog Output. This pin controls the gate
of an optional external P-channel MOSFET transistor used
to supplement the ideal diode between VOUT and BAT. The
external ideal diode operates in parallel with the internal
ideal diode. The source of the P-channel MOSFET should
be connected to VOUT and the drain should be connected
12
VBUS (Pin 25): Primary Input Power Pin. This pin delivers
power to VOUT via the SW pin by drawing controlled current
from a DC source such as a USB port or wall adapter.
SW (Pin 26): Power Transmission Pin for the USB Power
Path. The SW pin delivers power from VBUS to VOUT via the
step-down switching regulator. A 3.3μH inductor should
be connected from SW to VOUT.
SEQ (Pin 27): Sequence Select Logic Input. Three-state
input which determines start-up sequence after ENALL
is asserted.
If tied to GND, start-up sequence is:
Buck 1 → Buck 2 → Buck-Boost
If tied to VOUT , start-up sequence is:
Buck 1 → Buck-Boost → Buck 2
If left ﬂoating, start-up sequence is:
Buck-Boost → Buck 1 → Buck 2
ENALL (Pin 28): Enable All Logic Input. Enables all three
switching regulators in sequence according to the state of
the SEQ pin. Active high. Has a 5.5M internal pull-down
resistor. Alternately, all switching regulators can be individually enabled via the I2C serial port.
Exposed Pad (Pin 29): Ground. The Exposed Pad should
be connected to a continuous ground plane on the second
layer of the printed circuit board by several vias directly
under the LTC3556.
3556f
LTC3556
BLOCK DIAGRAM
VBUS 25
2.25MHz
PowerPath
SWITCHING
REGULATOR
26 SW
1 LDO3V3
3.3V LDO
SUSPEND
LDO
500μA
+
–
+
BATTERY
TEMPERATURE
MONITOR
IDEAL
CC/CV
CHARGER
+
+
–
CLPROG 2
NTC 3
24 VOUT
–
+
0.3V
+–
22 GATE
–
15mV
23 BAT
3.6V
1.188V
20 PROG
5 VIN1
EN1
CHRG 21
CHARGE
STATUS
4 SW1
400mA
2.25MHz
(BUCK)
SWITCHING
REGULATOR 1
D/A
4
6 FB1
18 VIN2
EN2
400mA
2.25MHz
(BUCK)
SWITCHING
REGULATOR 2
PGOODALL 15
POWER
GOOD
19 SW2
17 FB2
11 VIN3
EN3
A
9 SWAB3
SEQ 27
MASTER LOGIC
AND
SEQUENCER
D/A
4
1A
2.25MHz
(BUCK-BOOST)
SWITCHING
REGULATOR 3
B
12 VOUT3
D
14 SWCD3
C
ENALL 28
7 FB3
DVCC 10
SDA 16
8 VC3
I2C PORT
SCL 13
29
3556 BD
GND
3556f
13
LTC3556
TIMING DIAGRAM
I2C Timing Diagram
DATA BYTE A
ADDRESS
DATA BYTE B
WR
A7
0
0
0
1
0
0
1
0
SDA
0
0
0
1
0
0
1
0
ACK
SCL
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
START
STOP
ACK
1
2
3
4
5
6
7
8
9
ACK
1
2
3
4
5
6
7
8
9
SDA
tSU, STA
tSU, DAT
tLOW
tHD, STA
tHD, DAT
tBUF
tSU, STO
3556 TD
SCL
tHIGH
tHD, STA
START
CONDITION
tr
tSP
tf
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
OPERATION
Introduction
The LTC3556 is a highly integrated power management IC
which includes a high efﬁciency switch mode PowerPath
controller, a battery charger, an ideal diode, an always-on
LDO, two 400mA buck switching regulators and a 1A buckboost switching regulator. The entire chip is controllable
via an I2C serial port.
Designed speciﬁcally for USB applications, the PowerPath
controller incorporates a precision average input current
step-down switching regulator to make maximum use of
the allowable USB power. Because power is conserved,
the LTC3556 allows the load current on VOUT to exceed
the current drawn by the USB port without exceeding the
USB load speciﬁcations.
The PowerPath switching regulator and battery charger
communicate to ensure that the input current never violates
the USB speciﬁcations.
The ideal diode from BAT to VOUT guarantees that ample
power is always available to VOUT even if there is insufﬁcient or absent power at VBUS.
An “always-on” LDO provides a regulated 3.3V from available power at VOUT. Drawing very little quiescent current,
this LDO will be on at all times and can be used to supply
up to 25mA.
The three switching regulators can be enabled together
in any desired sequence via the ENALL and SEQ pins
or can be independently enabled via the I2C serial port.
Under I2C control, one of the 400mA bucks and the 1A
buck-boost have adjustable set-points so that voltages
can be reduced when high processor performance is not
needed. Along with constant frequency PWM mode, all
three switching regulators have a low power burst-only
mode setting for signiﬁcantly reduced quiescent current
under light load conditions. Additionally, the 400mA bucks
can be conﬁgured for automatic Burst Mode operation or
LDO mode.
High Efﬁciency Switching PowerPath Controller
Whenever VBUS is available and the PowerPath switching regulator is enabled, power is delivered from VBUS to
VOUT via SW. VOUT drives the combination of the external
load (including switching regulators 1, 2 and 3) and the
battery charger.
If the combined load does not exceed the PowerPath switching
regulator’s programmed input current limit, VOUT will track
0.3V above the battery (Bat-Track). By keeping the voltage
across the battery charger low, efﬁciency is optimized because
power lost to the linear battery charger is minimized. Power
available to the external load is therefore optimized.
3556f
14
LTC3556
OPERATION
If the voltage at BAT is below 3.3V, or the battery is not
present and the load requirement does not cause the
switching regulator to exceed the USB speciﬁcation, VOUT
will regulate at 3.6V, thereby providing instant-on operation.
If the load exceeds the available power, VOUT will drop to
a voltage between 3.6V and the battery voltage. If there
is no battery present when the load exceeds the available
USB power, VOUT can drop toward ground.
The power delivered from VBUS to VOUT is controlled
by a 2.25MHz constant-frequency step-down switching
regulator. To meet the USB maximum load speciﬁcation,
the switching regulator includes a control loop which
ensures that the average input current is below the level
programmed at CLPROG.
The current at CLPROG is a fraction (hCLPROG–1) of the VBUS
current. When a programming resistor and an averaging
capacitor are connected from CLPROG to GND, the voltage
on CLPROG represents the average input current of the
switching regulator. When the input current approaches
the programmed limit, CLPROG reaches VCLPROG, 1.188V
and power out is held constant. The input current limit is
programmed by the B1 and B0 bits of the I2C serial port.
It can be conﬁgured to limit average input current to one
of several possible settings as well as be deactivated (USB
Suspend). The input current limit will be set by the VCLPROG
servo voltage and the resistor on CLPROG according to
the following expression:
IVBUS = IVBUSQ +
VCLPROG
• (hCLPROG + 1)
RCLPROG
Figure 1 shows the range of possible voltages at VOUT as
a function of battery voltage.
4.5
4.2
VOUT (V)
3.9
NO LOAD
3.6
300mV
3.3
3.0
2.7
2.4
2.4
2.7
3.0
3.6
3.3
BAT (V)
4.2
3.9
3556 F01
Figure 1. VOUT vs BAT
Ideal Diode from BAT to VOUT
The LTC3556 has an internal ideal diode as well as a controller for an optional external ideal diode. The ideal diode
controller is always on and will respond quickly whenever
VOUT drops below BAT.
If the load current increases beyond the power allowed
from the switching regulator, additional power will be
pulled from the battery via the ideal diode. Furthermore,
if power to VBUS (USB or wall power) is removed, then all
of the application power will be provided by the battery via
the ideal diode. The transition from input power to battery
power at VOUT will be quick enough to allow only the 10μF
capacitor to keep VOUT from drooping. The ideal diode
consists of a precision ampliﬁer that enables a large onchip P-channel MOSFET transistor whenever the voltage at
2200
VISHAY Si2333
OPTIONAL EXTERNAL
IDEAL DIODE
2000
1800
1600
CURRENT (mA)
If the combined load at VOUT is large enough to cause the
switching power supply to reach the programmed input
current limit, the battery charger will reduce its charge current by that amount necessary to enable the external load
to be satisﬁed. Even if the battery charge current is set to
exceed the allowable USB current, the USB speciﬁcation
will not be violated. The switching regulator will limit the
average input current so that the USB speciﬁcation is never
violated. Furthermore, load current at VOUT will always be
prioritized and only remaining available power will be used
to charge the battery.
1400
LTC3556
IDEAL DIODE
1200
1000
800
600
ON
SEMICONDUCTOR
MBRM120LT3
400
200
0
0
60 120 180 240 300 360 420 480
FORWARD VOLTAGE (mV) (BAT – VOUT)
3556 F02
Figure 2. Ideal Diode Operation
3556f
15
LTC3556
OPERATION
VOUT is approximately 15mV (VFWD) below the voltage at
BAT. The resistance of the internal ideal diode is approximately 180mΩ. If this is sufﬁcient for the application, then
no external components are necessary. However, if more
conductance is needed, an external P-channel MOSFET
transistor can be added from BAT to VOUT.
When an external P-channel MOSFET transistor is present,
the GATE pin of the LTC3556 drives its gate for automatic
ideal diode control. The source of the external P-channel MOSFET should be connected to VOUT and the drain
should be connected to BAT. Capable of driving a 1nF load,
the GATE pin can control an external P-channel MOSFET
transistor having an on-resistance of 40mΩ or lower.
Suspend LDO
If the LTC3556 is conﬁgured for USB suspend mode, the
switching regulator is disabled and the suspend LDO
provides power to the VOUT pin (presuming there is power
available to VBUS). This LDO will prevent the battery from
running down when the portable product has access to
a suspended USB port. Regulating at 4.6V, this LDO only
becomes active when the switching converter is disabled
(suspended). To remain compliant with the USB speciﬁcation, the input to the LDO is current limited so that it will
not exceed the 500μA low power suspend speciﬁcation.
TO USB
OR WALL
ADAPTER
25
If the load on VOUT exceeds the suspend current limit,
the additional current will come from the battery via the
ideal diode.
3.3V Always-On Supply
The LTC3556 includes a low quiescent current low dropout
regulator that is always powered. This LDO can be used to
provide power to a system pushbutton controller, standby
microcontroller or real time clock. Designed to deliver up
to 25mA, the always-on LDO requires at least a 1μF low
impedance ceramic bypass capacitor for compensation.
The LDO is powered from VOUT , and therefore will enter
dropout at loads less than 25mA as VOUT falls near 3.3V.
If the LDO3V3 output is not used, it should be disabled
by connecting it to VOUT.
VBUS Undervoltage Lockout (UVLO)
An internal undervoltage lockout circuit monitors VBUS and
keeps the PowerPath switching regulator off until VBUS
rises above 4.30V and is about 200mV above the battery
voltage. Hysteresis on the UVLO turns off the regulator if
VBUS drops below 4.00V or to within 50mV of BAT. When
this happens, system power at VOUT will be drawn from
the battery via the ideal diode.
VBUS
SW
VOUT
PWM AND
GATE DRIVE
IDEAL
DIODE
ISWITCH/
hCLPROG
CONSTANT CURRENT
CONSTANT VOLTAGE
BATTERY CHARGER
15mV
CLPROG
1.188V
–
+
AVERAGE INPUT
CURRENT LIMIT
CONTROLLER
+
+
–
2
–
+
+
–
GATE
3.5V TO
(BAT + 0.3V)
TO SYSTEM
LOAD
26
24
OPTIONAL
EXTERNAL
IDEAL DIODE
PMOS
22
0.3V
3.6V
+–
BAT
23
AVERAGE OUTPUT
VOLTAGE LIMIT
CONTROLLER
+
SINGLE CELL
Li-Ion
3556 F03
Figure 3. PowerPath Block Diagram
3556f
16
LTC3556
OPERATION
Battery Charger
The LTC3556 includes a constant-current/constant-voltage battery charger with automatic recharge, automatic
termination by safety timer, low voltage trickle charging,
bad cell detection and thermistor sensor input for out-oftemperature charge pausing.
Battery Preconditioning
When a battery charge cycle begins, the battery charger
ﬁrst determines if the battery is deeply discharged. If the
battery voltage is below VTRKL, typically 2.85V, an automatic
trickle charge feature sets the battery charge current to
10% of the programmed value. If the low voltage persists
for more than 1/2 hour, the battery charger automatically
terminates and indicates via the CHRG pin that the battery
was unresponsive.
Once the battery voltage is above 2.85V, the battery charger
begins charging in full power constant-current mode. The
current delivered to the battery will try to reach 1022V/
RPROG. Depending on available input power and external
load conditions, the battery charger may or may not be
able to charge at the full programmed rate. The external
load will always be prioritized over the battery charge
current. The USB current limit programming will always
be observed and only additional power will be available to
charge the battery. When system loads are light, battery
charge current will be maximized.
Charge Termination
The battery charger has a built-in safety timer. When
the voltage on the battery reaches the pre-programmed
ﬂoat voltage of 4.200V, the battery charger will regulate
the battery voltage and the charge current will decrease
naturally. Once the battery charger detects that the battery
has reached 4.200V, the four hour safety timer is started.
After the safety timer expires, charging of the battery will
discontinue and no more current will be delivered.
Automatic Recharge
After the battery charger terminates, it will remain off
drawing only microamperes of current from the battery.
If the portable product remains in this state long enough,
the battery will eventually self discharge. To ensure that
the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below 4.1V.
In the event that the safety timer is running when the
battery voltage falls below 4.1V, it will reset back to zero.
To prevent brief excursions below 4.1V from resetting the
safety timer, the battery voltage must be below 4.1V for
more than 1.3ms. The charge cycle and safety timer will
also restart if the VBUS UVLO cycles low and then high
(e.g., VBUS is removed and then replaced), or if the battery
charger is cycled on and off by the I2C port.
Charge Current
The charge current is programmed using a single resistor from PROG to ground. 1/1022th of the battery charge
current is sent to PROG which will attempt to servo to
1.000V. Thus, the battery charge current will try to reach
1022 times the current in the PROG pin. The program
resistor and the charge current are calculated using the
following equations:
RPROG =
1022V
1022V
, ICHRG =
ICHRG
RPROG
In either the constant-current or constant-voltage charging
modes, the voltage at the PROG pin will be proportional to
the actual charge current delivered to the battery. Therefore, the actual charge current can be determined at any
time by monitoring the PROG pin voltage and using the
following equation:
IBAT =
VPROG
• 1022
RPROG
In many cases, the actual battery charge current, IBAT , will
be lower than ICHRG due to limited input power available and
prioritization with the system load drawn from VOUT.
Charge Status Indication
The CHRG pin indicates the status of the battery charger.
Four possible states are represented by CHRG which include charging, not charging, unresponsive battery, and
battery temperature out of range.
The signal at the CHRG pin can be easily recognized as
one of the above four states by either a human or a microprocessor. An open-drain output, the CHRG pin can
3556f
17
LTC3556
OPERATION
drive an indicator LED through a current limiting resistor
for human interfacing or simply a pull-up resistor for
microprocessor interfacing.
To make the CHRG pin easily recognized by both humans
and microprocessors, the pin is either Low for charging,
High for not charging, or it is switched at high frequency
(35kHz) to indicate the two possible faults, unresponsive
battery and battery temperature out of range.
When charging begins, CHRG is pulled low and remains
low for the duration of a normal charge cycle. When charging is complete, i.e., the BAT pin reaches 4.200V and the
charge current has dropped to one tenth of the programmed
value, the CHRG pin is released (Hi-Z). If a fault occurs,
the pin is switched at 35kHz. While switching, its duty
cycle is modulated between a high and low value at a very
low frequency. The low and high duty cycles are disparate
enough to make an LED appear to be on or off thus giving
the appearance of “blinking”. Each of the two faults has
its own unique “blink” rate for human recognition as well
as two unique duty cycles for machine recognition.
The CHRG pin does not respond to the C/10 threshold if
the LTC3556 is in VBUS current limit. This prevents false
end of charge indications due to insufﬁcient power available to the battery charger.
Table 1 illustrates the four possible states of the CHRG
pin when the battery charger is active.
Table 1. CHRG Signal
STATUS
Charging
Not Charging
NTC Fault
Bad Battery
FREQUENCY
0Hz
0Hz
35kHz
35kHz
MODULATION
(BLINK) FREQUENCY
0Hz (Lo-Z)
0Hz (Hi-Z)
1.5Hz at 50%
6.1Hz at 50%
DUTY CYCLES
100%
0%
6.25%, 93.75%
12.5%, 87.5%
An NTC fault is represented by a 35kHz pulse train whose
duty cycle alternates between 6.25% and 93.75% at a
1.5Hz rate. A human will easily recognize the 1.5Hz rate
as a “slow” blinking which indicates the out-of-range
battery temperature while a microprocessor will be able
to decode either the 6.25% or 93.75% duty cycles as an
NTC fault.
If a battery is found to be unresponsive to charging (i.e.,
its voltage remains below 2.85V for 1/2 hour), the CHRG
pin gives the battery fault indication. For this fault, a human
would easily recognize the frantic 6.1Hz “fast” blink of the
LED while a microprocessor would be able to decode either
the 12.5% or 87.5% duty cycles as a bad battery fault.
Note that the LTC3556 is a 3-terminal PowerPath product where system load is always prioritized over battery
charging. Due to excessive system load, there may not be
sufﬁcient power to charge the battery beyond the trickle
charge threshold voltage within the bad battery timeout
period. In this case, the battery charger will falsely indicate
a bad battery. System software may then reduce the load
and reset the battery charger to try again.
Although very improbable, it is possible that a duty cycle
reading could be taken at the bright-dim transition (low
duty cycle to high duty cycle). When this happens the
duty cycle reading will be precisely 50%. If the duty cycle
reading is 50%, system software should disqualify it and
take a new duty cycle reading.
NTC Thermistor
The battery temperature is measured by placing a negative temperature coefﬁcient (NTC) thermistor close to the
battery pack.
To use this feature, connect the NTC thermistor, RNTC, between the NTC pin and ground and a resistor, RNOM, from
VBUS to the NTC pin. RNOM should be a 1% resistor with
a value equal to the value of the chosen NTC thermistor
at 25°C (R25). A 100k thermistor is recommended since
thermistor current is not measured by the LTC3556 and
will have to be budgeted for USB compliance.
The LTC3556 will pause charging when the resistance of
the NTC thermistor drops to 0.54 times the value of R25
or approximately 54k. For Vishay “Curve 1” thermistor,
this corresponds to approximately 40°C. If the battery
charger is in constant-voltage (ﬂoat) mode, the safety
timer also pauses until the thermistor indicates a return
to a valid temperature. As the temperature drops, the
resistance of the NTC thermistor rises. The LTC3556 is
also designed to pause charging when the value of the
NTC thermistor increases to 3.25 times the value of R25.
For Vishay “Curve 1” this resistance, 325k, corresponds
to approximately 0°C. The hot and cold comparators each
3556f
18
LTC3556
OPERATION
have approximately 3°C of hysteresis to prevent oscillation
about the trip point. Grounding the NTC pin disables the
NTC charge pausing function.
Thermal Regulation
To optimize charging time, an internal thermal feedback
loop may automatically decrease the programmed charge
current. This will occur if the die temperature rises to
approximately 110°C. Thermal regulation protects the
LTC3556 from excessive temperature due to high power
operation or high ambient thermal conditions and allows
the user to push the limits of the power handling capability
with a given circuit board design without risk of damaging the LTC3556 or external components. The beneﬁt
of the LTC3556 thermal regulation loop is that charge
current can be set according to actual conditions rather
than worst-case conditions with the assurance that the
battery charger will automatically reduce the current in
worst-case conditions.
I2C Interface
The LTC3556 may receive commands from a host (master) using the standard I2C 2-wire interface. The Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 I2C accelerator, are
required on these lines. The LTC3556 is a receive-only
(slave) device. The I2C control signals, SDA and SCL are
scaled internally to the DVCC supply. DVCC should be connected to the same power supply as the microcontroller
generating the I2C signals.
The I2C port has an undervoltage lockout on the DVCC
pin. When DVCC is below approximately 1V, the I2C serial
port is cleared and switching regulators 1 and 3 are set
to full scale.
Bus Speed
The I2C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I2C compliant master
device. It also contains input ﬁlters designed to suppress
glitches should the bus become corrupted.
Start and Stop Condition
A bus master signals the beginning of a communication
to a slave device by transmitting a Start condition. A Start
condition is generated by transitioning SDA from high
to low while SCL is high. When the master has ﬁnished
communicating with the slave, it issues a Stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for communication with another I2C
device.
Byte Format
Each byte sent to the LTC3556 must be eight bits long
followed by an extra clock cycle for the Acknowledge bit
to be returned by the LTC3556. The data should be sent
to the LTC3556 most signiﬁcant bit (MSb) ﬁrst.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active low)
generated by the slave (LTC3556) lets the master know
that the latest byte of information was received. The
Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (high) during
the Acknowledge clock cycle. The slave receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable Low during the High period of
this clock pulse.
Slave Address
The LTC3556 responds to only one 7-bit address which
has been factory programmed to 0001001. The LSb of the
address byte is 1 for Read and 0 for Write. This device is
write only corresponding to an address byte of 00010010
(0×12). If the correct seven bit address is given but the
R/W bit is 1, the LTC3556 will not respond.
3556f
19
LTC3556
OPERATION
Table 2. I2C Serial Port Mapping (Defaults to 0xFF00 in Reset State or if DVCC = 0V)
A7
A6
A5
A4
A3
Switching Regulator 1
Voltage (See Table 4)
A2
A1
A0
Switching Regulator 3
Voltage (See Table 4)
B7
Disable
Battery
Charger
B6
B5
B4
B3
B2
B1
B0
Switching Regulator
Enable
Enable
Enable Input Current Limit
Modes (See Table 5) Regulator Regulator Regulator
(See Table 3)
1
2
3
Bus Write Operation
Table 3. USB Current Limit Settings
B1
B0
USB SETTING
0
1
10x Mode (Wall 1A Limit)
1
1
5x Mode (USB 500mA Limit)
0
0
1x Mode (USB 100mA Limit)
1
0
Suspend
Table 4. Switching Regulator Servo Voltage
A7
A6
A5
A4
SWITCHING REGULATOR 1 SERVO VOLTAGE
A3
A2
A1
A0
SWITCHING REGULATOR 3 SERVO VOLTAGE
0
0
0
0
0.425V
0
0
0
1
0.450V
0
0
1
0
0.475V
0
0
1
1
0.500V
0
1
0
0
0.525V
0
1
0
1
0.550V
0
1
1
0
0.575V
0
1
1
1
0.600V
1
0
0
0
0.625V
1
0
0
1
0.650V
1
0
1
0
0.675V
1
0
1
1
0.700V
1
1
0
0
0.725V
1
1
0
1
0.750V
1
1
1
0
0.775V
1
1
1
1
0.800V
Table 5. Switching Regulator Modes
B6
MODE OF (BUCK) SWITCHING MODE OF (BUCK-BOOST)
B5 REGULATORS 1 AND 2
SWITCHING REGULATOR 3
0
0
Pulse Skip Mode
1
1
Burst Mode Operation
0
1
Forced Burst Mode Operation
1
0
LDO Mode
PWM Mode
Burst Mode Operation
The master initiates communication with the LTC3556
with a Start condition and a 7-bit address followed by
the Write Bit R/W = 0. If the address matches that of the
LTC3556, the LTC3556 returns an Acknowledge. The master
should then deliver the most signiﬁcant data byte. Again
the LTC3556 acknowledges and the cycle is repeated for
a total of one address byte and two data bytes. Each data
byte is transferred to an internal holding latch upon the
return of an Acknowledge. After both data bytes have been
transferred to the LTC3556, the master may terminate the
communication with a Stop condition. Alternatively, a
Repeat-Start condition can be initiated by the master and
another chip on the I2C bus can be addressed. This cycle
can continue indeﬁnitely and the LTC3556 will remember
the last input of valid data that it received. Once all chips on
the bus have been addressed and sent valid data, a global
Stop condition can be sent and the LTC3556 will update its
command latch with the data that it had received.
In certain circumstances the data on the I2C bus may
become corrupted. In these cases the LTC3556 responds
appropriately by preserving only the last set of complete
data that it has received. For example, assume the LTC3556
has been successfully addressed and is receiving data
when a Stop condition mistakenly occurs. The LTC3556
will ignore this stop condition and will not respond until
a new Start condition, correct address, new set of data
and Stop condition are transmitted.
Likewise, with only one exception, if the LTC3556 was
previously addressed and sent valid data but not updated
with a Stop, it will respond to any Stop that appears on
the bus, independent of the number of Repeat-Starts that
have occurred. If a Repeat-Start is given and the LTC3556
successfully acknowledges its address and ﬁrst byte, it
will not respond to a Stop until both bytes of the new data
have been received and acknowledged.
3556f
20
LTC3556
OPERATION
Disabling the I2C Port
The I2C serial port can be disabled by grounding the
DVCC pin. In this mode, control automatically passes to
the individual logic input pins ENALL and SEQ. However,
considerable functionality is not available in this mode such
as the ability to independently enable the three switching
regulators and disable the battery charger. In addition,
with the I2C port disabled, both programmable switching
regulators default to a ﬁxed servo voltage of 0.8V, both
400mA bucks default to pulse skip mode, the 1A buckboost defaults to PWM mode, and the USB input current
limit defaults to 1x mode (100mA Limit).
PGOODALL Pin
The PGOODALL pin is an open-drain output used to indicate that all enabled switching regulators have reached
their ﬁnal voltage. PGOODALL remains low impedance
until the last enabled regulator in the sequence reaches
92% of its regulation value. A 230ms delay is included
to allow a system microcontroller ample time to reset
itself. PGOODALL may be used as a power-on reset to the
microprocessor powered by one (or more) of the three
regulated outputs. PGOODALL is an open-drain output
and requires a pull-up resistor to the input voltage of
the monitoring microprocessor or another appropriate
power source.
400mA Step-Down Switching Regulators
The LTC3556 contains two 2.25MHz step-down (buck)
constant-frequency current mode switching regulators.
Each buck regulator can provide up to 400mA of output
current. Both buck regulators can be programmed for a
minimum output voltage of 0.8V and can be used to power
a microcontroller core, microcontroller I/O, memory, disk
drive or other logic circuitry. One of the buck regulators
has I2C programmable set-points for on-the-ﬂy power
savings. Both buck converters support 100% duty cycle
operation (low dropout mode) when their input voltage
drops very close to their output voltage. To suit a variety
of applications, selectable mode functions can be used to
trade off noise for efﬁciency. Four modes are available to
control the operation of the LTC3556’s buck regulators.
At moderate to heavy loads, the pulse skip mode provides
the least noise switching solution. At lighter loads, either
Burst Mode operation, forced Burst Mode operation or
LDO mode may be selected. The buck regulators include
soft-start to limit inrush current when powering on, shortcircuit current protection and switch node slew limiting
circuitry to reduce radiated EMI. No external compensation
components are required. The operating mode of the buck
regulators can be set by I2C control and defaults to pulse
skip mode if the I2C port is not used. Both buck converters
are enabled (along with the buck-boost) when the ENALL
pin is asserted or each may be individually enabled by the
I2C port. Buck regulator 1 has a programmable feedback
servo voltage via I2C control (which defaults to 800mV if
the I2C port is not used) whereas buck regulator 2 has a
ﬁxed feedback servo voltage of 800mV. The buck regulator
input supplies VIN1 and VIN2 will generally be connected
to the system load pin VOUT.
Buck Regulator Output Voltage Programming
Both buck regulators can be programmed for output
voltages greater than 0.8V. The full-scale output voltage
for each buck regulator is programmed using a resistor
divider from the buck regulator output connected to the
feedback pins (FB1 and FB2) such that:
⎛ R1 ⎞
VOUTX = VFBX ⎜ + 1⎟
⎝ R2 ⎠
where VFBX ranges from 0.425V to 0.8V for buck regulator 1 and VFBX is ﬁxed at 0.8V for buck regulator 2. See
Figure 4.
Typical values for R1 are in the range of 40k to 1M. The
capacitor, CFB , cancels the pole created by feedback resistors and the input capacitance of the FBx pin and also helps
to improve transient response for output voltages much
VINx
L
VOUTx
SWx
LTC3556
CFB
R1
COUT
FBx
R2
GND
3556 F04
Figure 4. Buck Converter Application Circuit
3556f
21
LTC3556
OPERATION
greater than 0.8V. A variety of capacitor sizes can be used
for CFB but a value of 10pF is recommended for most applications. Experimentation with capacitor sizes between
2pF and 22pF may yield improved transient response.
Buck Regulator Operating Modes
The LTC3556’s buck regulators include four possible operating modes to meet the noise/power needs of a variety
of applications.
In pulse skip mode, an internal latch is set at the start of
every cycle which turns on the main P-channel MOSFET
switch. During each cycle, a current comparator compares
the peak inductor current to the output of an error ampliﬁer.
The output of the current comparator resets the internal
latch which causes the main P-channel MOSFET switch to
turn off and the N-channel MOSFET synchronous rectiﬁer
to turn on. The N-channel MOSFET synchronous rectiﬁer
turns off at the end of the 2.25MHz cycle or if the current
through the N-channel MOSFET synchronous rectiﬁer
drops to zero. Using this method of operation, the error
ampliﬁer adjusts the peak inductor current to deliver the
required output power. All necessary compensation is
internal to the switching regulator requiring only a single
ceramic output capacitor for stability. At light loads in PWM
mode, the inductor current may reach zero on each pulse
which will turn off the N-channel MOSFET synchronous
rectiﬁer. In this case, the switch node (SW) goes high
impedance and the switch node voltage will “ring.” This
is discontinuous mode operation and is normal behavior
for a switching regulator. At very light loads in pulse skip
mode, the buck regulators will automatically skip pulses
as needed to maintain output regulation.
At high duty cycles (VOUTx > VINx/2) it is possible for the
inductor current to reverse, causing the buck regulator
to operate continuously at light loads. This is normal and
regulation is maintained, but the supply current will increase
to several milliamperes due to continuous switching.
In forced Burst Mode operation, the buck regulators use a
constant-current algorithm to control the inductor current.
By controlling the inductor current directly and using a
hysteretic control loop, both noise and switching losses
are minimized. In this mode output power is limited. While
in forced Burst Mode operation, the output capacitor is
charged to a voltage slightly higher than the regulation
point. The step-down converter then goes into sleep mode,
during which the output capacitor provides the load cur
rent. In sleep mode, most of the regulator’s circuitry is
powered down, helping conserve battery power. When
the output voltage drops below a predetermined value, the
buck regulator circuitry is powered on and another burst
cycle begins. The duration for which the buck regulator
operates in sleep mode depends on the load current. The
sleep time decreases as the load current increases. The
maximum output current in forced Burst Mode operation
is about 100mA for buck regulators 1 and 2. The buck
regulators will not enter sleep mode if the maximum output
current is exceeded in forced Burst Mode operation and
the output will drop out of regulation. Forced Burst Mode
operation provides a signiﬁcant improvement in efﬁciency
at light loads at the expense of higher output ripple when
compared to pulse skip mode. For many noise-sensitive
systems, forced Burst Mode operation might be undesirable
at certain times (i.e., during a transmit or receive cycle
of a wireless device), but highly desirable at others (i.e.,
when the device is in low power standby mode). The I2C
port can be used to enable or disable forced Burst Mode
operation at any time, offering both low noise and low
power operation when they are needed.
In Burst Mode operation, the buck regulator automatically switches between ﬁxed frequency PWM operation
and hysteretic control as a function of the load current.
At light loads, the buck regulators operate in hysteretic
mode in much the same way as described for the forced
Burst Mode operation. Burst Mode operation provides
slightly less output ripple at the expense of slightly lower
efﬁciency than forced Burst Mode operation. At heavy
loads, the buck regulator operates in the same manner
as pulse skip operation does at high loads. For applications that can tolerate some output ripple at low output
currents, Burst Mode operation provides better efﬁciency
than pulse skip at light loads while still providing the full
speciﬁed output current of the buck regulator.
Finally, the buck regulators have an LDO mode that gives
a DC option for regulating their output voltages. In LDO
mode, the buck regulators are converted to linear regula3556f
22
LTC3556
OPERATION
tors and deliver continuous power from their SWx pins
through their respective inductors. This mode gives the
lowest possible output noise as well as low quiescent
current at light loads.
The buck regulators allow mode transition on the ﬂy,
providing seamless transition between modes even under
load. This allows the user to switch back and forth between
modes to reduce output ripple or increase low current
efﬁciency as needed.
Buck Regulator in Shutdown
The buck regulators are in shutdown when not enabled for
operation. In shutdown, all circuitry in the buck regulator
is disconnected from the buck regulator input supply
leaving only a few nanoamperes of leakage current. The
buck regulator outputs are individually pulled to ground
through a 10k resistor on the switch pins (SW1 and SW2)
when in shutdown.
Buck Regulator Dropout Operation
It is possible for a buck regulator’s input voltage, VINX, to
approach its programmed output voltage (e.g., a battery
voltage of 3.4V with a programmed output voltage of 3.3V).
When this happens, the PMOS switch duty cycle increases
until it is turned on continuously at 100%. In this dropout
condition, the respective output voltage equals the buck
regulator’s input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.
Buck Regulator Soft-Start Operation
Soft-start is accomplished by gradually increasing the
peak inductor current for each buck regulator over a
500μs period. This allows each output to rise slowly,
helping minimize the battery surge current. A soft-start
cycle occurs whenever a given buck regulator is enabled,
or after a fault condition has occurred (thermal shutdown
or UVLO). A soft-start cycle is not triggered by changing
operating modes. This allows seamless output operation
when transitioning between forced Burst Mode, Burst
Mode, pulse skip mode or LDO operation.
Buck Regulator Switching Slew Rate Control
The buck regulators contain new patent pending circuitry
to limit the slew rate of the switch node (SW1 and SW2).
This new circuitry is designed to transition the switch node
over a period of a couple of nanoseconds, signiﬁcantly
reducing radiated EMI and conducted supply noise.
Low Supply Operation
The LTC3556 incorporates an undervoltage lockout circuit
on VOUT which shuts down both buck regulators (as well
as the buck-boost) when VOUT drops below VOUTUVLO.
This UVLO prevents unstable operation.
Buck-Boost DC/DC Switching Regulator
The LTC3556 contains a 2.25MHz constant-frequency voltage mode buck-boost switching regulator. The regulator
provides up to 1A of output load current. The buck-boost
can be programmed to a minimum output voltage of 2.5V
and can be used to power a microcontroller core, microcontroller I/O, memory, disk drive or other logic circuitry.
When controlled by I2C, the buck-boost has programmable
set-points for on-the-ﬂy power savings. To suit a variety of
applications, a selectable mode function allows the user to
trade off noise for efﬁciency. Two modes are available to
control the operation of the LTC3556’s buck-boost regulator. At moderate to heavy loads, the constant frequency
PWM mode provides the least noise switching solution. At
lighter loads Burst Mode operation may be selected. The
full-scale output voltage is programmed by a user-supplied
resistive divider returned to the FB3 pin. An error ampliﬁer
compares the divided output voltage with a reference and
adjusts the compensation voltage accordingly until the FB3
has stabilized to the selected reference voltage (0.425V to
0.8V). The buck-boost regulator also includes a soft-start to
limit inrush current and voltage overshoot when powering
on, short circuit current protection, and switch node slew
limiting circuitry for reduced radiated EMI.
3556f
23
LTC3556
OPERATION
Input Current Limit
Buck-Boost Regulator Burst Mode Operation
The input current limit comparator will shut the input
PMOS switch off once current exceeds 2.5A (typical).
The 2.5A input current limit also protects against a
grounded VOUT3 node.
In Burst Mode operation, the buck-boost regulator uses
a hysteretic FB3 voltage algorithm to control the output
voltage. By limiting FET switching and using a hysteretic
control loop, switching losses are greatly reduced. In this
mode output current is limited to 50mA typical. While
operating in Burst Mode operation, the output capacitor
is charged to a voltage slightly higher than the regulation
point. The buck-boost converter then goes into a sleep
state, during which the output capacitor provides the load
current. The output capacitor is charged by charging the
inductor until the input current reaches 250mA typical
and then discharging the inductor until the reverse current
reaches 0mA typical. This process is repeated until the
feedback voltage has charged to 6mV above the regulation
point. In the sleep state, most of the regulator’s circuitry is
powered down, helping to conserve battery power. When
the feedback voltage drops 6mV below the regulation
point, the switching regulator circuitry is powered on and
another burst cycle begins. The duration for which the
regulator sleeps depends on the load current and output
capacitor value. The sleep time decreases as the load current increases. The maximum load current in Burst Mode
operation is 50mA typical. The buck-boost regulator will
not go to sleep if the current is greater than 50mA, and
if the load current increases beyond this point while in
Burst Mode operation the output will lose regulation. Burst
Mode operation provides a signiﬁcant improvement in efﬁciency at light loads at the expense of higher output ripple
when compared to PWM mode. For many noise-sensitive
systems, Burst Mode operation might be undesirable at
certain times (i.e., during a transmit or receive cycle of a
wireless device), but highly desirable at others (i.e., when
the device is in low power standby mode). The B6 and
B5 bits of the I2C port are used to enable or disable Burst
Mode operation at any time, offering both low noise and
low power operation when they are needed.
Output Overvoltage Protection
If the FB3 node were inadvertently shorted to ground, then
the output would increase indeﬁnitely with the maximum
current that could be sourced from VIN3. The LTC3556
protects against this by shutting off the input PMOS if
the output voltage exceeds 5.6V (typical).
Low Output Voltage Operation
When the output voltage is below 2.65V (typical) during
startup, Burst Mode operation is disabled and switch D
is turned off (allowing forward current through the well
diode and limiting reverse current to 0mA).
Buck-Boost Regulator PWM Operating Mode
In PWM mode the voltage seen at FB3 is compared to the
selected reference voltage (0.425V to 0.8V). From the FB3
voltage an error ampliﬁer generates an error signal seen
at VC3. This error signal commands PWM waveforms
that modulate switches A, B, C and D. Switches A and B
operate synchronously as do switches C and D. If VIN3 is
signiﬁcantly greater than the programmed VOUT3, then the
converter will operate in buck mode. In this case switches
A and B will be modulated, with switch D always on (and
switch C always off), to step down the input voltage to
the programmed output. If VIN3 is signiﬁcantly less than
the programmed VOUT3, then the converter will operate in
boost mode. In this case switches C and D are modulated,
with switch A always on (and switch B always off), to step
up the input voltage to the programmed output. If VIN3 is
close to the programmed VOUT3, then the converter will
operate in 4-switch mode. In this mode the switches sequence through the pattern of AD, AC, BD to either step the
input voltage up or down to the programmed output.
3556f
24
LTC3556
OPERATION
Buck-Boost Regulator Soft-Start Operation
Soft-start is accomplished by gradually increasing the
reference voltage input to the error ampliﬁer over a 0.5ms
(typical) period. This limits transient inrush currents during
start-up because the output voltage is always “in regulation.” Ramping the reference voltage input also limits the
rate of increase in the VC3 voltage which helps minimize
output overshoot during start-up. A soft-start cycle occurs whenever the buck-boost is enabled, or after a fault
condition has occurred (thermal shutdown or UVLO). A
soft-start cycle is not triggered by changing operating
modes. This allows seamless operation when transitioning
between Burst Mode operation and PWM mode.
Low Supply Operation
The LTC3556 incorporates an undervoltage lockout circuit
on VOUT (connected to VIN3) which shuts down the buckboost regulator when VOUT drops below 2.6V. This UVLO
prevents unstable operation.
APPLICATIONS INFORMATION
CLPROG Resistor and Capacitor
As described in the High Efﬁciency Switching PowerPath
Controller section, the resistor on the CLPROG pin determines the average input current limit when the switching
regulator is set to either the 1x mode (USB 100mA), the
5x mode (USB 500mA) or the 10x mode. The input current will be comprised of two components, the current
that is used to drive VOUT and the quiescent current of the
switching regulator. To ensure that the USB speciﬁcation
is strictly met, both components of input current should
be considered. The Electrical Characteristics table gives
values for quiescent currents in either setting as well as
current limit programming accuracy. To get as close to
the 500mA or 100mA speciﬁcations as possible, a 1%
resistor should be used. Recall that IVBUS = IVBUSQ +
VCLPROG/RCLPPROG • (hCLPROG +1).
An averaging capacitor or an R-C combination is required
in parallel with the CLPROG resistor so that the switching
regulator can determine the average input current. This
network also provides the dominant pole for the feedback
loop when current limit is reached. To ensure stability,
the capacitor on CLPROG should be 0.47μF or larger.
Alternatively, faster transient response may be achieved
with 0.1μF in series with 8.2Ω.
Choosing the PowerPath Inductor
Because the input voltage range and output voltage range
of the power path switching regulator are both fairly nar-
row, the LTC3556 was designed for a speciﬁc inductance
value of 3.3μH. Some inductors which may be suitable
for this application are listed in Table 6.
Table 6. Recommended Inductors for PowerPath Controller
INDUCTOR L
TYPE
(μH)
MAX
IDC
(A)
MAX
DCR
(Ω)
0.08
SIZE IN mm
(L × W × H)
MANUFACTURER
3.9 × 3.9 × 1.7 Coilcraft
www.coilcraft.com
LPS4018
3.3
2.2
D53LC
DB318C
3.3
3.3
2.26 0.034 5.0 × 5.0 × 3.0 Toko
1.55 0.070 3.8 × 3.8 × 1.8 www.toko.com
WE-TPC
Type M1
3.3
1.95 0.065 4.8 × 4.8 × 1.8 Würth Elektronik
www.we-online.com
CDRH6D12
CDRH6D38
3.3
3.3
2.2 0.0625 6.7 × 6.7 × 1.5 Sumida
3.5 0.020 7.0 × 7.0 × 4.0 www.sumida.com
VBUS and VOUT Bypass Capacitors
The style and value of capacitors used with the LTC3556
determine several important parameters such as regulator
control-loop stability and input voltage ripple. Because
the LTC3556 uses a step-down switching power supply
from VBUS to VOUT , its input current waveform contains
high frequency components. It is strongly recommended
that a low equivalent series resistance (ESR) multilayer
ceramic capacitor be used to bypass VBUS. Tantalum and
aluminum capacitors are not recommended because of
their high ESR. The value of the capacitor on VBUS directly
controls the amount of input ripple for a given load current. Increasing the size of this capacitor will reduce the
input ripple.
3556f
25
LTC3556
APPLICATIONS INFORMATION
To prevent large VOUT voltage steps during transient load
conditions, it is also recommended that a ceramic capacitor be used to bypass VOUT. The output capacitor is used
in the compensation of the switching regulator. At least
4μF of actual capacitance with low ESR are required on
VOUT. Additional capacitance will improve load transient
performance and stability.
Multilayer ceramic chip capacitors typically have exceptional ESR performance. MLCCs combined with a tight
board layout and an unbroken ground plane will yield very
good performance and low EMI emissions.
There are several types of ceramic capacitors available,
each having considerably different characteristics. For
example, X7R ceramic capacitors have the best voltage
and temperature stability. X5R ceramic capacitors have
apparently higher packing density but poorer performance
over their rated voltage and temperature ranges. Y5V
ceramic capacitors have the highest packing density,
but must be used with caution, because of their extreme
nonlinear characteristic of capacitance vs voltage. The
actual in-circuit capacitance of a ceramic capacitor should
be measured with a small AC signal (ideally less than
200mV) as is expected in-circuit. Many vendors specify
the capacitance vs voltage with a 1VRMS AC test signal and
as a result overstate the capacitance that the capacitor will
present in the application. Using similar operating conditions as the application, the user must measure or request
from the vendor the actual capacitance to determine if the
selected capacitor meets the minimum capacitance that
the application requires.
400mA Step-Down Switching Regulator Inductor
Selection
Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right
inductor from such a large selection of devices can be
overwhelming, but following a few basic guidelines will
make the selection process much simpler.
The buck converters are designed to work with inductors in
the range of 2.2μH to 10μH. For most applications a 4.7μH
inductor is suggested for both buck regulators. Larger
value inductors reduce ripple current which improves
output ripple voltage. Lower value inductors result in higher
ripple current and improved transient response time. To
maximize efﬁciency, choose an inductor with a low DC
resistance. For a 1.2V output, efﬁciency is reduced about
2% for 100mΩ series resistance at 400mA load current,
and about 2% for 300mΩ series resistance at 100mA load
current. Choose an inductor with a DC current rating at
least 1.5 times larger than the maximum load current to
ensure that the inductor does not saturate during normal
operation. If output short-circuit is a possible condition,
the inductor should be rated to handle the maximum peak
current speciﬁed for the buck converters.
Different core materials and shapes will change the
size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or Permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. Inductors that are
very thin or have a very small volume typically have much
higher core and DCR losses, and will not give the best efﬁciency. The choice of which style inductor to use often
depends more on the price vs size, performance and any
radiated EMI requirements than on what the LTC3556
requires to operate.
The inductor value also has an effect on forced burst
and Burst Mode operations. Lower inductor values will
cause the Burst Mode and forced Burst Mode switching
frequencies to increase.
Table 7 shows several inductors that work well with the
LTC3556’s buck regulators. These inductors offer a good
compromise in current rating, DCR and physical size.
Consult each manufacturer for detailed information on
their entire selection of inductors.
Table 7. Recommended Inductors for 400mA Step-Down
Switching Regulators
NDUCTOR
TYPE
L
MAX
MAX
(μH) IDC (A) DCR (Ω)
DE2818C
4.7
1.25
0.072*
DE2812C
4.7
1.15
0.13*
CDRH3D16 4.7
0.9
0.11
4.0 × 4.0 × 1.8 Sumida
www.sumida.com
SD3118
4.7
1.3
0.162
SD3112
4.7
0.8
0.246
3.1 × 3.1 × 1.8 Cooper
www.cooperet.
3.1 × 3.1 × 1.2
com
LPS3015
4.7
1.1
0.2
SIZE IN mm
(L × W × H)
MANUFACTURER
3.0 × 2.8 × 1.8 Toko
www.toko.com
3.0 × 2.8 × 1.2
3.0 × 3.0 × 1.5 Coilcraft
www.coilcraft.com
*Typical DCR
3556f
26
LTC3556
APPLICATIONS INFORMATION
400mA Step-Down Switching Regulator Input/Output
Capacitor Selection
Low ESR (equivalent series resistance) MLCC capacitors
should be used at both buck regulator outputs as well as at
each buck regulator input supply (VIN1 and VIN2). Only X5R
or X7R ceramic capacitors should be used because they
retain their capacitance over wider voltage and temperature
ranges than other ceramic types. A 10μF output capacitor is sufﬁcient for most applications. For good transient
response and stability the output capacitor should retain
at least 4μF of capacitance over operating temperature
and bias voltage. Each buck regulator input supply should
be bypassed with a 1μF capacitor. Consult with capacitor
manufacturers for detailed information on their selection
and speciﬁcations of ceramic capacitors. Many manufacturers now offer very thin (<1mm tall) ceramic capacitors
ideal for use in height-restricted designs. Table 8 shows a
list of several ceramic capacitor manufacturers.
Table 8. Recommended Ceramic Capacitor Manufacturers
AVX
www.avxcorp.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay Siliconix
www.vishay.com
TDK
www.tdk.com
Buck-Boost Regulator Inductor Selection
Inductor selection criteria for the buck-boost are similar to
those given for the 400mA step-down switching regulators.
The buck-boost converter is designed to work with inductors in the range of 1μH to 5μH. For most applications a
2.2μH inductor will sufﬁce. Choose an inductor with a DC
current rating at least 2 times larger than the maximum
load current to ensure that the inductor does not saturate
during normal operation. If output short circuit is a possible condition, the inductor should be rated to handle
the maximum peak current speciﬁed for the buck-boost
converter.
Table 9. Recommended Inductors for Buck-Boost Regulator
INDUCTOR L
TYPE
(μH)
MAX
IDC
(A)
MAX
DCR
(Ω)
SIZE IN mm
(L × W × H)
MANUFACTURER
LPS4018
3.3
2.2
2.2
2.5
0.08
0.07
3.9 × 3.9 × 1.7 Coilcraft
3.9 × 3.9 × 1.7 www.coilcraft.com
D53LC
2.0
3.25
0.02
5.0 × 5.0 × 3.0 Toko
www.toko.com
7440430022
2.2
2.5
0.028 4.8 × 4.8 × 2.8 Würth-Elektronik
www.we-online.com
CDRH4D22/
HP
2.2
2.4
0.044 4.7 × 4.7 × 2.4 Sumida
www.sumida.com
SD14
2.0
2.56 0.045
5.2 × 5.2 ×
1.45
Cooper
www.cooperet.com
Buck-Boost Regulator Input/Output Capacitor
Selection
Low ESR MLCC capacitors should also be used at both the
buck-boost regulator output (VOUT3) and the buck-boost
regulator input supply (VIN3). Again, only X5R or X7R ceramic capacitors should be used because they retain their
capacitance over wider voltage and temperature ranges
than other ceramic types. A 22μF output capacitor is sufﬁcient for most applications. The buck-boost regulator
input supply should be bypassed with a 2.2μF capacitor.
Refer to Table 8 for recommended ceramic capacitor
manufacturers.
Buck-Boost Regulator Output Voltage Programming
The buck-boost regulator can be programmed for output
voltages greater than 2.75V and less than 5.5V. The fullscale output voltage is programmed using a resistor divider
from the VOUT3 pin connected to the FB3 pin such that:
⎛ R1 ⎞
+1
VOUT 3 = VFB3 ⎜
⎝ R2 ⎟⎠
where VFB3 ranges from 0.425V to 0.8V.
Table 9 shows several inductors that work well with the
LTC3556’s buck-boost regulator. These inductors offer a
good compromise in current rating, DCR and physical
size. Consult each manufacturer for detailed information
on their entire selection of inductors.
3556f
27
LTC3556
APPLICATIONS INFORMATION
Closing the Feedback Loop
The LTC3556 incorporates voltage mode PWM control. The
control to output gain varies with operation region (buck,
boost, buck-boost), but is usually no greater than 20. The
output ﬁlter exhibits a double-pole response given by:
where COUT is the output ﬁlter capacitor.
The output ﬁlter zero is given by:
1
2 • π • RESR • COUT
Hz
where RESR is the capacitor equivalent series resistance.
A troublesome feature in boost mode is the right-half plane
zero (RHP), and is given by:
fRHPZ =
fUG =
1
Hz
2 • π • R1 • CP1
Most applications demand an improved transient response
to allow a smaller output ﬁlter capacitor. To achieve a higher
bandwidth, Type III compensation is required. Two zeros
are required to compensate for the double-pole response.
Type III compensation also reduces any VOUT3 overshoot
at start-up.
1
fFILTER _ POLE =
Hz
2 • π • L • COUT
fFILTER _ ZERO =
The unity-gain frequency of the error ampliﬁer with the
Type I compensation is given by:
The compensation network depicted in Figure 6 yields the
transfer function:
VC3
1
=
VOUT 3 R1 (C1 + C2)
•
VIN2
Hz
2 • π • IOUT • L • VOUT
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network (as shown in
Figure 5) can be incorporated to stabilize the loop but
at the cost of reduced bandwidth and slower transient
response. To ensure proper phase margin, the loop must
cross unity-gain a decade before the LC double pole.
(1 + sR2C2) [1 + s (R1 + R3)C3 ]
s ⎡⎣1 + sR2(C1|| C2)⎤⎦ (1 + sR3C3)
A Type III compensation network attempts to introduce
a phase bump at a higher frequency than the LC double
pole. This allows the system to cross unity gain after the
LC double pole, and achieve a higher bandwidth. While
attempting to cross over after the LC double pole, the
system must still cross over before the boost right-half
plane zero. If unity gain is not reached sufﬁciently before
the right-half plane zero, then the –180° of phase lag from
VOUT3
+
+
ERROR
AMP
–
VOUT3
0.8V
R1
FB3
8
–
0.8V
CP1
R2
R1
FB3
R3
C3
7
VC3
7
VC3
ERROR
AMP
C2
R2
8
RFB
3556 F06
C1
3556 F05
Figure 5. Error Ampliﬁer with Type I Compensation
Figure 6. Error Ampliﬁer with Type III Compensation
3556f
28
LTC3556
APPLICATIONS INFORMATION
the LC double pole combined with the –90° of phase lag
from the right-half plane zero will result in negating the
phase bump of the compensator.
The compensator zeros should be placed either before
or only slightly after the LC double pole such that their
positive phase contributions offset the –180° that occurs
at the ﬁlter double pole. If they are placed at too low of a
frequency, they will introduce too much gain to the system
and the crossover frequency will be too high. The two high
frequency poles should be placed such that the system
crosses unity gain during the phase bump introduced
by the zeros and before the boost right-half plane zero
and such that the compensator bandwidth is less than
the bandwidth of the error amp (typically 900kHz). If the
gain of the compensation network is ever greater than
the gain of the error ampliﬁer, then the error ampliﬁer no
longer acts as an ideal op amp, and another pole will be
introduced at the same point.
Recommended Type III compensation components for a
3.3V output:
R1: 324kΩ
RFB: 105kΩ
C1: 10pF
R2: 15kΩ
C2: 330pF
R3: 121kΩ
C3: 33pF
COUT: 22μF
LOUT: 2.2μH
Over-Programming the Battery Charger
The USB high power speciﬁcation allows for up to 2.5W to
be drawn from the USB port (5V × 500mA). The PowerPath
switching regulator transforms the voltage at VBUS to just
above the voltage at BAT with high efﬁciency, while limiting
power to less than the amount programmed at CLPROG.
In some cases the battery charger may be programmed
(with the PROG pin) to deliver the maximum safe charging
current without regard to the USB speciﬁcations. If there
is insufﬁcient current available to charge the battery at the
programmed rate, the PowerPath regulator will reduce
charge current until the system load on VOUT is satisﬁed
and the VBUS current limit is satisﬁed. Programming the
battery charger for more current than is available will
not cause the average input current limit to be violated.
It will merely allow the battery charger to make use of
all available power to charge the battery as quickly as
possible, and with minimal power dissipation within the
battery charger.
Alternate NTC Thermistors and Biasing
The LTC3556 provides temperature qualiﬁed charging if
a grounded thermistor and a bias resistor are connected
to NTC. By using a bias resistor whose value is equal to
the room temperature resistance of the thermistor (R25)
the upper and lower temperatures are pre-programmed
to approximately 40°C and 0°C, respectively (assuming
a Vishay “Curve 1” thermistor).
The upper and lower temperature thresholds can be adjusted by either a modiﬁcation of the bias resistor value
or by adding a second adjustment resistor to the circuit.
If only the bias resistor is adjusted, then either the upper
or the lower threshold can be modiﬁed but not both. The
other trip point will be determined by the characteristics
of the thermistor. Using the bias resistor in addition to an
adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with
the constraint that the difference between the upper and
lower temperature thresholds cannot decrease. Examples
of each technique follow.
NTC thermistors have temperature characteristics which
are indicated on resistance-temperature conversion tables.
The Vishay-Dale thermistor NTHS0603N011-N1003F, used
3556f
29
LTC3556
APPLICATIONS INFORMATION
in the following examples, has a nominal value of 100k
and follows the Vishay “Curve 1” resistance-temperature
characteristic.
In the explanation below, the following notation is used.
R25 = Value of the thermistor at 25°C
RNTC|COLD = Value of thermistor at the cold trip point
to the nonlinear behavior of the thermistor. The following
equations can be used to easily calculate a new value for
the bias resistor:
RNOM =
rHOT
• R25
0.536
RNOM =
rCOLD
• R25
3.25
RNTC|HOT = Value of thermistor at the hot trip point
rCOLD = Ratio of RNTC|COLD to R25
rHOT = Ratio of RNTC|COLD to R25
RNOM = Primary thermistor bias resistor (see Figure 7a)
R1 = Optional temperature range adjustment resistor
(see Figure 7b)
The trip points for the LTC3556’s temperature qualiﬁcation
are internally programmed at 0.349 • VBUS for the hot
threshold and 0.765 • VBUS for the cold threshold.
Therefore, the hot trip point is set when:
RNTCHOT
|
RNOM + RNTCHOT
|
• VBUS = 0.349 • VBUS
and the cold trip point is set when:
RNTC|COLD
RNOM + RNTC|COLD
• VBUS = 0.765 • VBUS
Solving these equations for RNTC|COLD and RNTC|HOT results
in the following:
RNTC|HOT = 0.536 • RNOM
and
RNTC|COLD = 3.25 • RNOM
By setting RNOM equal to R25, the above equations result
in rHOT = 0.536 and rCOLD = 3.25. Referencing these ratios
to the Vishay Resistance-Temperature Curve 1 chart gives
a hot trip point of about 40°C and a cold trip point of about
0°C. The difference between the hot and cold trip points
is approximately 40°C.
By using a bias resistor, RNOM, different in value from
R25, the hot and cold trip points can be moved in either
direction. The temperature span will change somewhat due
where rHOT and rCOLD are the resistance ratios at the desired hot and cold trip points. Note that these equations
are linked. Therefore, only one of the two trip points can
be chosen, the other is determined by the default ratios
designed in the IC. Consider an example where a 60°C
hot trip point is desired.
From the Vishay Curve 1 R-T characteristics, rHOT is 0.2488
at 60°C. Using the above equation, RNOM should be set
to 46.4k. With this value of RNOM, the cold trip point is
about 16°C. Notice that the span is now 44°C rather than
the previous 40°C. This is due to the decrease in “temperature gain” of the thermistor as absolute temperature
increases.
The upper and lower temperature trip points can be independently programmed by using an additional bias resistor
as shown in Figure 7b. The following formulas can be used
to compute the values of RNOM and R1:
RNOM =
rCOLD – rHOT
• R25
2.714
R1 = 0.536 • RNOM – rHOT • R25
For example, to set the trip points to 0°C and 45°C with
a Vishay Curve 1 thermistor choose:
RNOM =
3.266 – 0.4368
• 100k = 104.2k
2.714
The nearest 1% value is 105k.
R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k
The nearest 1% value is 12.7k. The ﬁnal solution is shown
in Figure 7b and results in an upper trip point of 45°C and
a lower trip point of 0°C.
3556f
30
LTC3556
APPLICATIONS INFORMATION
VBUS
LTC3556
NTC BLOCK
VBUS
RNOM
100k
NTC
0.765 • VBUS
TOO_COLD
+
3
T
–
RNTC
100k
–
TOO_HOT
0.349 • VBUS
+
+
NTC_ENABLE
0.017V • VBUS
–
3556 F07a
(7a)
VBUS
VBUS
RNOM
105k
NTC
LTC3556
NTC BLOCK
0.765 • VBUS
–
TOO_COLD
3
+
R1
12.7k
–
TOO_HOT
0.349 • VBUS
T
RNTC
100k
+
+
NTC_ENABLE
0.017 • VBUS
–
3556 F07b
(7b)
Figure 7. NTC Circuits
3556f
31
LTC3556
APPLICATIONS INFORMATION
USB Inrush Limiting
Printed Circuit Board Layout Considerations
When a USB cable is plugged into a portable product,
the inductance of the cable and the high-Q ceramic input
capacitor form an L-C resonant circuit. If the cable does
not have adequate mutual coupling or if there is not much
impedance in the cable, it is possible for the voltage at
the input of the product to reach as high as twice the USB
voltage (~10V) before it settles out. To prevent excessive
voltage from damaging the LTC3556 during a hot insertion,
it is best to have a low voltage coefﬁcient capacitor at the
VBUS pin to the LTC3556. This is achievable by selecting an
MLCC capacitor that has a higher voltage rating than that
required for the application. For example, a 16V, X5R, 10μF
capacitor in a 1206 case would be a more conservative
choice than a 6.3V, X5R, 10μF capacitor in a smaller 0805
case. The size of the input overshoot will be determined
by the “Q” of the resonant tank circuit formed by CIN and
the input lead inductance. It is recommended to measure
the input ringing with the selected components to verify
compliance with the Absolute Maximum speciﬁcations.
In order to be able to deliver maximum current under
all conditions, it is critical that the Exposed Pad on the
backside of the LTC3556 package be soldered to the PC
board ground. Failure to make thermal contact between
the Exposed Pad on the backside of the package and the
copper board will result in higher thermal resistances.
Alternatively, the following soft connect circuit (Figure 8)
can be employed. In this circuit, capacitor C1 holds MP1
off when the cable is ﬁrst connected. Eventually C1 begins
to charge up to the USB input voltage applying increasing
gate support to MP1. The long time constant of R1 and
C1 prevent the current from building up in the cable too
fast thus dampening out any resonant overshoot.
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitors, inductors and
output capacitors be as close to the LTC3556 as possible
and that there be an unbroken ground plane under the
LTC3556 and all of its external high frequency components. High frequency currents such as the VBUS, VIN1,
VIN2 and VIN3 currents on the LTC3556, tend to ﬁnd their
way along the ground plane in a myriad of paths ranging
from directly back to a mirror path beneath the incident
path on the top of the board. If there are slits or cuts
in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to ﬂow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the package leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the second layer of the PC board.
MP1
Si2333
5V USB
INPUT
VBUS
C1
100nF
USB CABLE
R1
40k
C2
10μF
LTC3556
GND
3556 F08
Figure 8. USB Soft Connect Circuit
3556f
32
LTC3556
APPLICATIONS INFORMATION
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an offset to the 15mV
ideal diode of approximately 10mV. To minimize leakage,
the trace can be guarded on the PC board by surrounding
it with VOUT connected metal, which should generally be
less that one volt higher than GATE.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3556.
1. Are the capacitors at VBUS, VIN1, VIN2 and VIN3 as close
as possible to the LTC3556? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers. Minimizing inductance from these capacitors
to the LTC3556 is a top priority.
2. Are COUT and L1 closely connected? The (–) plate of COUT
returns current to the GND plane, and then back to CIN.
3. Keep sensitive components away from the SW pins.
Battery Charger Stability Considerations
The LTC3556’s battery charger contains both a constantvoltage and a constant-current control loop. The constantvoltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
lead length, however, may add enough series inductance
to require a bypass capacitor of at least 1μF from BAT to
GND. Furthermore, when the battery is disconnected, a
100μF OSCON B6 capacitor in series with a 0Ω jumper
from BAT to GND is required to keep ripple voltage low.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22μF may
be used in parallel with a battery, but larger ceramics should
be decoupled with 0.2Ω to 1Ω of series resistance.
In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
CPROG, the following equation should be used to calculate
the maximum resistance value for RPROG:
RPROG ≤
1
2π • 100kHz • CPROG
3556 F09
Figure 9. Higher Frequency Ground Currents Follow Their Incident Path.
Slices in the Ground Plane Cause High Voltage and Increased Emissions
3556f
33
LTC3556
TYPICAL APPLICATION
Watchdog Microcontroller Operation
USB/WALL
4.5V TO 5.5V
25
C1
10μF
SW
VBUS
VOUT
100k
3
20
T
2k
8.25Ω
0.1μF
2
GATE
NTC
BAT
PROG
CLPROG
GND
3.01k
CHRG
VOUT3
26
L1
3.3μH
TO OTHER
LOADS
24
22
MP1
23
+
Li-Ion
29
510Ω
C2
22μF
RED
2.5V TO
3.3V
1A
21
12
HDD
10pF
121k
1
1μF
10
LDO3V3
DVCC
VC3
15k
VIN3
9
324k
22μF
2.2μF
105k
L2
2.2μH
11
LTC3555
SW2
33pF
330pF
7
FB3
14
SWCD3
SWAB3
PUSHBUTTON
MICROCONTROLLER
8
19
L3
4.7μH
1.8V
400mA
I/O
1.02M
2
13,16
FB2
I
C1: MURATA GRM21BR61A106KE19
C2: TDK C2012X5R0J226M
L1: COILCRAFT LPS4018-332LM
L2: COILCRAFT LPS4018-222MLC
L3, L4: TOKO 1098AS-4R7M
MP1: SILICONIX Si2333
SW1
27
10μF
806k
VIN2
28
10pF
17
2C (SCL, SDA)
1μF
MICROPROCESSOR
18
4
0.8V TO
1.6V
400mA
L4
4.7μH
CORE
POR
806k
ENALL
FB1
10pF
6
SEQ
806k
VIN1
PGOODALL
10μF
1μF
10k
5
15
3556 TA02
3556f
34
LTC3556
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
s 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.25 ± 0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3556f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3556
TYPICAL APPLICATION
Pushbutton Start with Automatic Sequencing, Reverse Input Voltage Protection and 10 Second Push and Hold Hard Shutdown
MP1
USB
CONNECTOR
25
VOUT3
VBUS
10μF
VC3
10
4.7k
DVCC
9
SWAB3
15
PGOODALL
CORE
LDO3V3
1μF
1k
MEMORY
8
7
FB3
14
SWCD3
0.1μF
1
12
SW1
LTC3556
4
6
FB1
1M
28
MN1
27
ENALL
SEQ
I2C (SCL, SDA)
SW2
10k
29
SDA
2
SCL
I/O
10μF
10μF
13,16
GND
FB2
19
17
SEND I2C CODE: “0x12FF1C”
ONCE POWER IS DETECTED
MN1: 2N7002
MP1: SILICONIX Si2333DS
3556 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3455
Dual DC/DC Converter with USB Power
Manager and Li-Ion Battery Charger
Seamless Transition Between Input Power Sources: Li-Ion Battery, USB and 5V Wall
Adapter. Two High Efﬁciency DC/DC Converters: Up to 96%. Full Featured Li-Ion Battery
Charger with Accurate USB Current Limiting (500mA/100mA). Pin Selectable Burst Mode
Operation. Hot SwapTM Output for SDIO and Memory Cards. 24-Lead 4mm × 4mm QFN
Package
LTC3456
2-Cell, Multi-Output DC/DC Converter
with USB Power Manager
Seamless Transition Between 2-Cell Battery, USB and AC Wall Adapter Input Power
Sources. Main Output: Fixed 3.3V Output, Core Output: Adjustable from 0.8V to VBATT(MIN).
Hot Swap Output for Memory Cards. Power Supply Sequencing: Main and Hot Swap
Accurate USB Current Limiting. High Frequency Operation: 1MHz. High Efﬁciency: Up to
92%. 24-Lead 4mm × 4mm QFN Package
LTC3552
Standalone Linear Li-Ion Battery
Charger with Adjustable Output Dual
Synchronous Buck Converter
Synchronous Buck Converter, Efﬁciency: >90%, Adjustable Outputs at 800mA and 400mA,
Charge Current Programmable up to 950mA, USB Compatible, 16-Lead 5mm × 3mm DFN
Package
LTC3555/
LTC3555-1
High Efﬁciency USB Power Manager Plus Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
Triple Step-Down DC/DC
Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO,
Three Synchronous Buck Regulators (400mA/400mA/1A), 4mm × 5mm QFN28 Package
LTC3557/
LTC3557-1
Linear USB Power Manager with Li-Ion/
Polymer Charger and Triple Synchronous
Buck Converter
Complete Multifunction ASSP: Linear Power Manager and Three Buck Regulators
Charge Current Programmable up to 1.5A from Wall Adapter Input, Thermal Regulation,
Synchronous Buck Efﬁciency: >95%, ADJ Outputs: 0.8V to 3.6V at 400mA/400mA/600mA
Bat-Track Adaptive Output Control, 200mΩ Ideal Diode, 4mm × 4mm QFN28 Package
LTC4085
Linear USB Power Manager with Ideal
Diode Controller and Li-Ion Charger
Charges Single Cell Li-Ion Batteries Directly from a USB Port, Thermal Regulation, 200mΩ
Ideal Diode with <50mΩ option, 4mm × 3mm DFN14 Package
LTC4088/
LTC4088-1
High Efﬁciency USB Power Manager and
Battery Charger
Maximizes Available Power from USB Port, Bat-Track, “Instant On” Operation, 1.5A Max
Charge Current, 180mΩ Ideal Diode with <50mΩ Option, 3.3V/25mA Always-On LDO,
4mm × 3mm DFN14 Package
Hot Swap is a trademark of Linear Technology Corporation.
3556f
36 Linear Technology Corporation
LT 0208 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008

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