LTC692/LTC693 Microprocessor Supervisory Circuits U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ UL Recognized ® Guaranteed Reset Assertion at VCC = 1V 1.5mA Maximum Supply Current Fast (35ns Max.) On-Board Gating of RAM Chip Enable Signals SO8 and SO16 Packaging 4.40V Precision Voltage Monitor Power OK/Reset Time Delay: 200ms or Adjustable Minimum External Component Count 1µA Maximum Standby Current Voltage Monitor for Power Fail or Low Battery Warning Thermal Limiting Performance Specified Over Temperature Superior Upgrade for MAX690 Family ® ■ ■ ■ S Critical µP Power Monitoring Intelligent Instruments Battery-Powered Computers and Controllers Automotive Systems UO ■ The LTC692/LTC693 power the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an early warning of impending power failure, the LTC692/LTC963 provide an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset time-out period. UO APPLICATI The LTC692/LTC693 provide complete power supply monitoring and battery control functions for microprocessor reset, battery backup, CMOS RAM write protection, power failure warning and watchdog timing. A precise internal voltage reference and comparator circuit monitor the power supply line. When an out-of-tolerance condition occurs, the reset outputs are forced to active states and the Chip Enable output unconditionally write-protects external memory. In addition, the RESET output is guaranteed to remain logic low even with VCC as low as 1V. TYPICAL APPLICATI RESET Output Voltage vs Supply Voltage + 10µF LT1086-5 VIN VOUT ADJ 5V VCC + 100µF 0.1µF VOUT 0.1µF LTC692 LTC693 POWER TO µP CMOS RAM POWER µP SYSTEM VBATT 3V RESET 51k PFI 10k MICROPROCESSOR RESET, BATTERY BACKUP, POWER FAILURE WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEMS. GND µP RESET PFO µP NMI WDI I/O LINE 0.1µF LTC692/3 • TA01 100Ω RESET OUTPUT VOLTAGE (V) 5 VIN ≥ 7.5V TA = 25°C EXTERNAL PULL-UP = 10µA VBATT = 0V 4 3 2 1 0 0 1 3 4 2 SUPPLY VOLTAGE (V) 5 LTC692/3 • TA02 1 LTC692/LTC693 W W W AXI U U ABSOLUTE RATI GS (Notes 1 and 2) Terminal Voltage VCC .................................................... – 0.3V to 6.0V VBATT ................................................. – 0.3V to 6.0V All Other Inputs .................. – 0.3V to (VOUT + 0.3V) Input Current VCC .............................................................. 200mA VBATT ............................................................. 50mA GND............................................................... 20mA W U U PACKAGE/ORDER I FOR ATIO VOUT 1 8 VBATT VCC 2 7 RESET GND 3 6 WDI PFI 4 5 PFO N8 PACKAGE 8-LEAD PLASTIC DIP (Note 3) ORDER PART NUMBER TOP VIEW S8 PART MARKING TJMAX = 110°C, θJA = 130°C/W (N) VBATT 1 16 RESET VOUT 2 15 RESET VCC 3 14 WDO GND 4 13 CE IN BATT ON 5 12 CE OUT LOW LINE 6 11 WDI OSC IN 7 10 PFO OSC SEL 8 9 LTC693CN LTC693IN LTC693CS LTC693IS PFI N PACKAGE S PACKAGE 16-LEAD PLASTIC DIP 16-LEAD PLASTIC SOL 692 692I TJMAX = 110°C, θJA = 180°C/W (S) S8 Package Conditions: PCB Mount on FR4 Material, Still Air at 25°C, Copper Trace ORDER PART NUMBER TOP VIEW LTC692CN8 LTC692IN8 LTC692CS8 LTC692IS8 S8 PACKAGE 8-LEAD PLASTIC SOIC VOUT Output Current .................. Short Circuit Protected Power Dissipation............................................. 500mW Operating Temperature Range LTC692C/LTC693C ............................... 0°C to 70°C LTC692I/LTC693I ............................ – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C TJMAX = 110°C, θJA = 130°C/W (N, S) S16 Package Conditions: PCB Mount on FR4 Material, Still Air at 25°C, Copper Trace U PRODUCT SELECTIO GUIDE PINS RESET THRESHOLD (V) WATCHDOG TIMER BATTERY BACKUP POWER FAIL WARNING LTC692 8 4.40 X X X LTC693 16 4.40 X X X LTC690 8 4.65 X X X LTC691 16 4.65 X X X LTC694 8 4.65 X X X LTC695 16 4.65 X X X LTC699 8 4.65 X LTC1232 8 4.37/4.62 X LTC1235 16 4.65 X X X LTC694-3.3 8 2.90 X X X LTC695-3.3 16 2.90 X X X 2 RAM WRITE PROTECT PUSHBUTTON RESET CONDITIONAL BATTERY BACKUP X X X X X X X X LTC692/LTC693 ELECTRICAL CHARACTERISTICS VCC = Full Operating Range, VBATT = 2.8V, TA = 25°C, unless otherwise noted. PARAMETER CONDITONS MIN TYP MAX UNITS 5.50 4.00 V V Battery Backup Switching Operating Voltage Range VCC VBATT VOUT Output Voltage 4.50 2.00 IOUT = 1mA VCC – 0.05 VCC – 0.10 VCC – 0.005 VCC – 0.005 V V IOUT = 50mA VCC – 0.50 VCC – 0.250 V VOUT in Battery Backup Mode IOUT = 250µA, VCC < VBATT VBATT – 0.1 VBATT – 0.02 Supply Current (Exclude IOUT) IOUT ≤ 50mA ● Supply Current in Battery Backup Mode ● 1.5 2.5 mA mA ● 0.04 0.04 1 5 µA µA 0.02 0.10 µA µA VCC = 0V, VBATT = 2.8V Battery Standby Current (+ = Discharge, – = Charge) 5.5 > VCC > VBATT + 0.2V Battery Switchover Threshold VCC – VBATT Power Up Power Down ● – 0.1 – 1.0 Battery Switchover Hysteresis BATT ON Output Voltage (Note 4) ISINK = 3.2mA BATT ON Output Short-Circuit Current (Note 4) BATT ON = VOUT Sink Current BATT ON = 0V Source Current V 0.6 0.6 70 50 mV mV 20 mV 0.4 V 0.5 35 1 25 mA µA 4.25 4.40 4.50 Reset and Watchdog Timer Reset Voltage Threshold ● Reset Threshold Hysteresis 40 Reset Active Time (Note 5) OSC SEL HIGH, VCC = 5V Watchdog Time-Out Period, Internal Oscillator Long Period, VCC = 5V mV ● 160 140 200 200 240 280 ms ms ● 1.2 1.0 1.6 1.6 2.00 2.25 sec sec ● 80 70 100 100 120 140 ms ms 4097 1025 Clock Cycles Short Period, VCC = 5V Watchdog Time-Out Period, External Clock (Note 6) V Long Period Short Period 4032 960 Reset Active Time PSRR 1 ms/V Watchdog Time-Out Period PSRR, Internal OSC 1 ms/V Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3.5V RESET Output Voltage At VCC = 1V ISINK = 10µA, VCC = 1V RESET and LOW LINE Output Voltage (Note 4) ISINK = 1.6mA, VCC = 4.25V ISOURCE = 1µA, VCC = 5V 3.5 RESET and WDO Output Voltage (Note 4) ISINK = 1.6mA, VCC = 5V ISOURCE = 1µA, VCC = 4.25V 3.5 ● 200 ns 4 200 mV 0.4 V V 0.4 V V 3 LTC692/LTC693 ELECTRICAL CHARACTERISTICS VCC = Full Operating Range, VBATT = 2.8V, TA = 25°C, unless otherwise noted. PARAMETER CONDITONS RESET, RESET, WDO, LOW LINE Output Short-Circuit Current (Note 4) Output Source Current Output Sink Current WDI Input Threshold Logic Low Logic High WDI Input Current MIN TYP MAX 1 3 25 25 µA mA 0.8 V V 4 –8 50 µA µA 1.3 1.35 3.5 WDI = VOUT WDI = 0V ● ● – 50 VCC = 5V ● 1.25 UNITS Power Fail Detector PFI Input Threshold PFI Input Threshold PSRR 0.3 ±0.01 PFI Input Current PFO Output Voltage (Note 4) ISINK = 3.2mA ISOURCE = 1µA ±25 nA 0.4 V V 25 µA mA 3.5 1 3 25 V mV/V PFO Short Circuit Source Current (Note 4) PFI = HIGH, PFO = 0V PFI = LOW, PFO = VOUT PFI Comparator Response Time (falling) ∆VIN = –20mV, VOD = 15mV 2 µs PFI Comparator Response Time (rising) (Note 4) ∆VIN = 20mV, VOD = 15mV with 10kΩ Pull-Up 40 8 µs µs Chip Enable Gating CE IN Threshold VIL VIH 0.8 2.0 CE IN Pullup Current (Note 7) CE OUT Output Voltage CE Propagation Delay 0.4 V V V 35 45 ns ns VOUT – 1.50 VOUT – 0.05 VCC = 5V, CL = 20pF 20 20 ● CE OUT Output Short Circuit Current µA 3 ISINK = 3.2mA ISOURCE = 3.0mA ISOURCE = 1µA, VCC = 0V Output Source Current Output Sink Current V V 30 35 mA mA ±2 µA Oscillator OSC IN Input Current (Note 7) OSC SEL Input Pull-Up Current (Note 7) OSC SEL = 0V OSC IN Frequency with External Capacitor OSC SEL = 0V, COSC = 47pF The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range, consult the factory. Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pull-ups of typically 3µA. However, external pull-up resistors may be used when higher speed is required. 4 µA 5 OSC IN Frequency Range ● 0 250 4 kHz kHz Note 5: The LTC692/LTC693 have minimum reset active times of 140ms (200ms typically). The reset active time of the LTC693 can be adjusted (see Table 2 in Applications Information Section). Note 6: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer (See BLOCK DIAGRAM). Variation in the time-out period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the time-out period is 64 clocks plus one clock of jitter. Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal pull-ups which pull to the supply when the input pins are floating. LTC692/LTC693 U W TYPICAL PERFOR A CE CHARACTERISTICS VOUT vs IOUT 5.00 2.80 OUTPUT VOLTAGE (V) 4.90 SLOPE = 5Ω 4.85 1.308 VCC = 0V VBATT = 2.8V TA = 25°C 2.78 VCC = 5V 1.306 PFI INPUT THRESHOLD (V) VCC = 5V VBATT = 2.8V TA = 25°C 4.95 OUTPUT VOLTAGE (V) Power Failure Input Threshold vs Temperature VOUT vs IOUT SLOPE = 125Ω 2.76 2.74 4.80 1.304 1.302 1.300 1.298 1.296 4.75 10 0 30 40 20 LOAD CURRENT (mA) 2.72 50 0 100 300 400 200 LOAD CURRENT (µA) LTC692/3 • TPC01 1.294 –50 –25 500 LTC692/3 • TPC02 Reset Active Time vs Temperature PFO OUTPUT VOLTAGE (V) 4.41 RESET VOLTAGE THRESHOLD (V) 216 208 200 192 4.40 4.39 4.38 6 VCC = 5V TA = 25°C 5 4 3 VPFI + 2 1.3V – 50 25 75 0 TEMPERATURE (°C) 100 0 1.305V 4.36 50 25 75 0 TEMPERATURE (°C) LTC692/3 • TPC04 100 VPFI = 20mV STEP 4 3 2 VPFI + 1 1.3V – PFO 30pF 0 20 40 1 2 3 4 5 TIME (µs) 6 7 8 LTC692/3 • TPC06 6 5 VCC = 5V TA = 25°C 4 3 2 5V 1 0 1.315V VPFI = 20mV STEP 0 PFO OUTPUT VOLTAGE (V) PFO OUTPUT VOLTAGE (V) VCC = 5V TA = 25°C 1.295V 0 Power Fail Comparator Response Time with Pull-Up Resistor 6 1.315V 125 LTC692/3 • TPC05 Power Fail Comparator Response Time 5 30pF 4.37 4.35 –50 –25 125 PFO 1 1.285V 184 –50 –25 125 Power Fail Comparator Response Time VCC = 5V 224 100 LTC692/3 • TPC03 Reset Voltage Threshold vs Temperature 232 RESET ACTIVE TIME 50 25 75 0 TEMPERATURE (°C) LTC692/3 • TPC07 + 1.3V – 10k PFO 30pF VPFI = 20mV STEP 1.295V 60 80 100 120 140 160 180 TIME (µs) VPFI 0 2 4 8 10 12 14 16 18 TIME (µs) 6 LTC692/3 • TPC08 5 LTC692/LTC693 U U U PI FU CTIO S VCC: 5V Supply Input. The VCC pin should be bypassed with a 0.1µF capacitor. VOUT: Voltage Output for Backed Up Memory. Bypass with a capacitor of 0.1µF or greater. During normal operation, VOUT obtains power from VCC through an NMOS power switch, M1, which can deliver up to 50mA and has a typical ON resistance of 5Ω. When VCC is lower than VBATT, VOUT is internally switched to VBATT. If VOUT and VBATT are not used, connect VOUT to VCC. VBATT: Backup Battery Input. When VCC falls below VBATT, auxiliary power connected to VBATT, is delivered to VOUT through PMOS switch, M2. If backup battery or auxiliary power is not used, VBATT should be connected to GND. GND: Ground Pin. BATT ON: Battery On Logic Output from Comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VOUT is internally switched to VBATT. PFI: Power Failure Input. PFI is the noninverting input to the Power Fail Comparator, C3. The inverting input is internally connected to a 1.3V reference. The Power Failure Output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or VOUT when C3 is not used. PFO: Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. When VCC is lower than VBATT, C3 is shut down and PFO is forced low. RESET: Logic Output for µP Reset Control. Whenever VCC falls below either the reset voltage threshold (4.40V typically) or VBATT, RESET goes active low. After VCC returns to 5V, reset pulse generator forces RESET to remain active low for a minimum of 140ms. When the watchdog timer is enabled but not serviced prior to a preset time-out period, reset pulse generator also forces RESET to active low for a minimum of 140ms for every preset 6 time-out period (see Figure 11). The reset active time is adjustable on the LTC693. An external pushbutton reset can be used in connection with the RESET output. See Pushbutton Reset in the Applications Information section. RESET: RESET is an Active High Logic Ouput. It is the inverse of RESET. LOW LINE: Logic Output from Comparator C1. LOW LINE indicates a low line condition at the VCC input. When VCC falls below the reset voltage threshold (4.40V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when VCC drops below VBATT (see Table 1). WDI: Watchdog Input. WDI is a three level input. Driving WDI either high or low for longer than the watchdog timeout period, forces both RESET and WDO low. Floating WDI disables the Watchdog Timer. The timer resets itself with each transition of the Watchdog Input (see Figure 11). WDO: Watchdog Logic Output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set high whenever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11). CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN can be derived from microprocessor's address line and/or decoder output. See Applications Information Section and Figure 5 for additional information. CE OUT: Logic Output on the Chip Enable Gating Circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 5). OSC SEL: Oscillator Selection Input. When OSC SEL is high or floating, the internal oscillator sets the reset active time and watchdog time-out period. Forcing OSC SEL low allows OSC IN to be driven from an external clock signal or an external capacitor to be connected between OSC IN and GND. LTC692/LTC693 U U U PI FU CTIO S OSC IN: Oscillator Input. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND when OSC SEL is forced low. In this configuration the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula (see Applications Information section). When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 200ms typical. OSC IN selects between the 1.6 seconds and 100ms typical watchdog time-out periods. In both cases the time-out period immediately after a reset is 1.6 seconds typical. W BLOCK DIAGRA M2 VBATT VOUT M1 VCC CHARGE PUMP – BATT ON C2 + LOW LINE + C1 – CE OUT 1.3V GND CE IN – C3 RESET OSC IN OSC OSC SEL WDI PFO + PFI RESET PULSE GENERATOR RESET TRANSITION DETECTOR WATCHDOG TIMER WDO LTC692/3 • BD 7 LTC692/LTC693 U W U UO APPLICATI S I FOR ATIO Microprocessor Reset Battery Switchover The LTC692/LTC693 use a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see BLOCK DIAGRAM). When VCC falls below the reset voltage threshold, the RESET output is forced to active low state. The reset voltage threshold accounts for a 10% variation on VCC, so the RESET output becomes active low when VCC falls below 4.50V (4.40V typical). On power-up, the RESET signal is held active low for a minimum of 140ms after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. The reset active time is adjustable on the LTC693. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The battery switchover circuit compares VCC to the VBATT input, and connects VOUT to whichever is higher. When VCC rises to 70mV above VBATT, the battery switchover comparator, C2, connects VOUT to VCC through a charge pumped NMOS power switch, M1. When VCC falls to 50mV above VBATT, C2 connects VOUT to VBATT through a PMOS switch, M2. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT. The response time of C2 is approximately 20µs. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at the VCC pin do not activate the RESET output. Response time is typically 10µs. To help prevent mistriggering due to transient loads, VCC pin should be bypassed with a 0.1µF capacitor with the leads trimmed as short as possible. The LTC693 has two additional outputs: RESET and LOW LINE. RESET is an active high output and is the inverse of RESET. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold. V2 V1 VCC RESET t1 During normal operation, the LTC692/LTC693 use a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical “on” resistance of 5Ω. The VOUT pin should be bypassed with a capacitor of 0.1µF or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC – VOUT voltage differential) is desired, the LTC693 should be used. This product provides BATT ON output to drive the base of the external PNP transistor (Figure 2). If higher currents are needed with the LTC692, a high current Schottky diode can be connected from the VCC pin to the VOUT pin to supply the extra current. V2 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS V1 t1 t1 = RESET ACTIVE TIME LOW LINE LTC692/3 • F01 Figure 1. Reset Active Time 8 LTC692/LTC693 W U U UO APPLICATI S I FOR ATIO ANY PNP POWER TRANSISTOR I= VOUT – VBATT R 5 3 5V 0.1µF LTC693 1 3V R BATT ON 2 VOUT VCC 5V 0.1µF VOUT VCC LTC692 LTC693 0.1µF 0.1µF VBATT VBATT GND 4 3V GND LTC692/3 • F02 LTC692/3 • F03 Figure 2. Using BATT ON to Drive External PNP Transistor Figure 3. Charging External Battery Through VOUT The LTC692/LTC693 are protected for safe area operation with a short circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long periods of time, thermal shutdown turns the power switch off until the device cools down. The threshhold temperature for thermal shutdown is approximately 155°C with about 10°C of hysteresis which prevents the device from oscillating in and out of shutdown. memory backup instead of a battery. The charging resistor for the rechargeable batteries should be connected to VOUT since this eliminates the discharge path that exists when the resistor is connected to VCC (Figure 3). The PNP switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the VBATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. The LTC692/LTC693 use a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by the VBATT pin is strictly junction leakage. A 125Ω PMOS switch connects the VBATT input to VOUT in battery backup mode. The switch is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. The supply current in battery backup mode is 1µA maximum. The operating voltage at the VBATT pin ranges from 2.0V to 4.0V. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short term Replacing the Backup Battery When changing the backup battery with system power on, spurious resets can occur while the battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the VBATT pin. The oscillation cycle is as follows: When VBATT reaches within 50mV of VCC, the LTC692/LTC693 switch to battery backup. VOUT pulls VBATT low and the devices go back to normal operation. The leakage current then charges up the VBATT pin again and the cycle repeats. If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, a resistor from VBATT to GND will hold the pin low while changing the battery. For example, the battery standby current is 1µA maximum over temperature and the external resistor required to hold VBATT below VCC is: V – 50mV R ≤ CC 1µA With VCC = 4.25V, a 3.9M resistor will work. With a 3V battery, this resistor will draw only 0.77µA from the battery, which is negligible in most cases. 9 LTC692/LTC693 W U U UO APPLICATI S I FOR ATIO If battery connections are made through long wires, a 10Ω to 100Ω series resistor and a 0.1µF capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4). alternative signal to drive the CE, CS, or Write input of battery backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. 10Ω VBATT 3.9M CE IN can be derived from the microprocessor's address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application. 0.1µF LTC692 LTC693 Memory protection can also be achieved with the LTC692 by using RESET as shown in Figure 7. GND LTC692/3 • F04 Figure 4. 10Ω/0.1µF combination eliminates inductive overshoot and prevents spurious resets during battery replacement. Table 1. Input and Output Status in Battery Backup Mode Table 1 shows the state of each pin during battery backup. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC. Memory Protection The LTC693 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at an invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is 5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an V2 VCC V1 SIGNAL VCC STATUS C2 monitors VCC for active switchover. VOUT VOUT is connected to VBATT through an internal PMOS switch. VBATT BATT ON The supply current is 1µA maximum. Logic high. The open-circuit output voltage is equal to VOUT. PFI Power Failure Input is ignored. PFO RESET Logic low Logic low RESET Logic high. The open-circuit output voltage is equal to VOUT. LOW LINE Logic low WDI Watchdog Input is ignored. WDO Logic high. The open-circuit output voltage is equal to VOUT. CE IN CE OUT Chip Enable Input is ignored. Logic high. The open-circuit output voltage is equal to VOUT. OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS CE IN CE OUT VOUT = VBATT VOUT = VBATT LTC692/3 • F05 Figure 5. Timing Diagram for CE IN and CE OUT 10 LTC692/LTC693 U UO 0.1µF W S I FOR ATIO VOUT VCC 5V U APPLICATI + LTC693 VCC 10µF 0.1µF 62512 RAM CE OUT VBATT CS 20ns PROPAGATION DELAY FROM DECODER CE IN RESET 3V GND GND LTC692/3 • F06 RESET TO µP Figure 6. A Typical Nonvolatile CMOS RAM Application VOUT VCC 5V + 0.1µF VCC 0.1µF 10µF 62128 RAM CS1 LTC692 CS VBATT RESET GND 3V CS2 GND LTC692/3 • F07 Figure 7. Write Protect for RAM with the LTC692 VIN ≥ 7.5V + LT1086-5 VOUT VIN 10µF 5V + ADJ R3 300k R1 51k LTC692 LTC693 PFO GND PFI R2 10k TO µP LTC692/3 • F08 Figure 8. Monitoring Unregulated DC Supply with the LTC692/LTC693 Power Fail Comparator VIN ≥ 6.5V + LT1086-5 VIN VOUT 10µF ADJ 5V + 10µF R1 R4 27k 10k R3 2.7M R2 8.2k R1 R1 VH = 1.3V 1+ + R2 R3 When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction. R1 (5V – 1.3V)R1 VL = 1.3V 1 + – R2 1.3V(R3 + R4) Assuming R4 << R3,VHYSTERESIS = 5V VCC 0.1µF The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R3 sinks current from the summing junction at the PFI pin. VCC 0.1µF R4 10k 100µF Power Fail Warning The LTC692/LTC693 generate a Power Failure Output (PFO) for early warning of failure in the microprocessor's power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at the PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at the PFI pin falls below 1.3V, several milliseconds before the 5V supply falls below the maximum reset voltage threshold of 4.50V. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and RESET or RESET. LTC692 LTC693 PFO PFI GND TO µP R5 3.3k LTC692/3 • F09 Figure 9. Monitoring Regulated DC Supply with the LTC692/LTC693 Power Fail Comparator R1 R3 Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shutdown procedure is 8ms. Also, the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 7.25V which is 1.25V greater than the sum of maximum reset voltage threshold and the dropout voltage of LT1086-5 (4.5V + 1.5V) and VHYSTERESIS = 850mV. 11 LTC692/LTC693 U W U UO APPLICATI S I FOR ATIO 5V R1 VHYSTERESIS = 5V = 850mV R3 VBATT R3 ≈ 5.88 R1 Choose R3 = 300k and R1 = 51k. Also select R4 = 10k which is much smaller than R3. VCC PFO R1 1M PFI 3V LTC693 R2 1M CE IN CE OUT 51k (5V – 1.3V)51k 7.25V = 1.3V 1+ – 1.3 V(310 k ) R2 51k (5V – 1.3V)51k VL = 1.3V 1 + – = 7.32 V 1.3V(310k ) 10k 51k 51k VH = 1.3V 1 + + = 8.151V 10k 300k (7.32V – 6.25V) = 10.7ms 100mV/ms VHYSTERESIS = 8.151V – 7.32V = 831mV The 10.7ms allows enough time to execute shutdown procedure for microprocessor and 831mV of hysteresis would prevent PFO from going low due to the noise of VIN. Example 2: The circuit in Figure 9 can be used to measure the regulated 5V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 4.6V). Monitoring the Status of the Battery C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered. 12 I/O PIN GND RL 20K OPTIONAL TEST LOAD R2 = 10.1k, Choose nearest 5% resistor 10k and recalculate VL, LOW BATTERY SIGNAL TO µP I/O PIN LTC692/3 • F10 Figure 10. Backup Battery Monitor with Optional Test Load Watchdog Timer The LTC692/LTC693 provide a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within a seleced time-out period, RESET is forced to active low for a minimum of 140ms. The reset active time is adjustable on the LTC693. Since many systems cannot service the watchdog timer immediately after a reset, the LTC693 has longer time-out period (1.0 second minimum) right after a reset is issued. The normal time-out period (70ms minimum) becomes effective following the first transition of WDI after RESET is inactive. The watchdog time-out period is fixed at a 1.0 second minimum on the LTC692. Figure 11 shows the timing diagram of watchdog time-out period and reset active time. The watchdog time-out period is restarted as soon as RESET is inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to time-out, the watchdog timer is reset and begins to time-out again. To ensure the watchdog timer does not time-out, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog timer can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or VBATT. LTC692/LTC693 W U U UO APPLICATI S I FOR ATIO The LTC693 provides an additional output (Watchdog Output, WDO) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or VBATT. The LTC693 has two additonal pins OSC SEL and OSC IN, which allow reset active time and watchdog time-out period to be adjusted per Table 2. Several configurations are shown in Figure 12. GND when OSC SEL is forced low. In these configurations, the nominal reset active time and watchdog time-out period are determined by the number of clocks or set by the formula in Table 2. When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is fixed at 140ms minimum. OSC IN selects between the 1 second and 70ms minimum normal watchdog time-out periods. In both cases, the time-out period immediately after a reset is at least 1 second. OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and VCC = 5V WDI t1 = RESET ACTIVE TIME t2 = NORMAL WATCHDOG TIME-OUT PERIOD t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY AFTER A RESET WDO t2 t3 RESET t1 t1 LTC692/3 • F11 Figure 11. Watchdog Time-out Period and Reset Active Time EXTERNAL OSCILLATOR EXTERNAL CLOCK 3 5V VCC OSC SEL 8 5V 3 VCC GND OSC IN 4 7 INTERNAL OSCILLATOR 1.6 SECOND WATCHDOG 3 5V VCC OSC SEL 8 GND GND OSC IN OSC IN 7 INTERNAL OSCILLATOR 100ms WATCHDOG FLOATING OR HIGH 5V 3 VCC LTC693 4 8 LTC693 LTC693 4 OSC SEL OSC SEL 8 FLOATING OR HIGH LTC693 7 FLOATING OR HIGH 4 GND Figure 12. Oscillator Configurations OSC IN 7 LTC692/3 • F12 13 LTC692/LTC693 W U U UO APPLICATI S I FOR ATIO Table 2. LTC693 Reset Active Time and Watchdog Time-Out Selections WATCHDOG TIME-OUT PERIOD OSC SEL OSC IN IMMEDIATELY AFTER RESET (Long Period) NORMAL (Short Period) Low RESET ACTIVE TIME LTC693 External Clock Input 1024 clks 4096 clks 2048 clks Low External Capacitor* 400ms ×C 47pF 1.6 sec ×C 47pF 800ms ×C 47pF Floating or High Floating or High Low Floating or High 100ms 1.6 sec 1.6 sec 1.6 sec 200ms 200ms *The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is FOSC (Hz) = 184,000 C(pF) Pushbutton Reset The LTC692/LTC693 do not provide a logic input for direct connection to a pushbutton. However, a pushbutton in series with a 100Ω resistor connected to the RESET output pin (Figure 13) provides an alternative for manual reset. Connecting a 0.1µF capacitor to the RESET pin debounces the pushbutton input. 5V VCC RESET RESET 0.1µF LTC692 LTC693 GND The 100Ω resistor in series with the pushbutton is required to prevent the ringing, due to the capacitance and lead inductance, from pulling the RESET pins of the MPU and LTC692/LT693 below ground. Figure 13. The External Pushbutton Reset S Capacitor Backup with 74HC4016 Switch 5V VCC VOUT 0.1µF R1 10k R2 30k 0.1µF LTC693 10 11 12 14 1 2 74HC4016 7 13 VBATT + 100µF LOW LINE GND LTC692/3 • TA3 14 MPU (e.g. 6805) LTC692/3 • F13 UO TYPICAL APPLICATI 100Ω LTC692/LTC693 UO TYPICAL APPLICATI S Write Protect for Additional RAMs 0.1µF 5V VOUT VCC 0.1µF 62512 RAMA 10µF LTC693 CE OUT VBATT CE IN 3V VCC + CS 20ns PROPAGATION DELAY CSA LOW LINE GND 0.1µF VCC 62128 RAMB CS1 CSB CS2 0.1µF VCC 62128 RAMC CSC CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs LTC692/3 • TA04 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. 0.300 – 0.320 (7.620 – 8.128) N8 Package 8-Lead Plastic DIP 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 +0.635 8.255 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.400 (10.160) MAX 0.130 ± 0.005 (3.302 ± 0.127) 8 7 6 5 0.065 (1.651) TYP 0.250 ± 0.010 (6.350 ± 0.254) 0.125 (3.175) MIN 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 0.020 (0.508) MIN 1 2 4 3 N8 0393 0.018 ± 0.003 (0.457 ± 0.076) 0.189 – 0.197 (4.801 – 5.004) 0.010 – 0.020 × 45° (0.254 – 0.508) S8 Package 8-Lead Plastic SOIC 0.008 – 0.010 (0.203 – 0.254) 7 6 5 0.004 – 0.010 (0.101 – 0.254) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 8 0.053 – 0.069 (1.346 – 1.752) 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) BSC 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157 (3.810 – 3.988) SO8 0393 1 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights. 2 3 4 15 LTC692/LTC693 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead Plastic DIP 0.300 – 0.325 (7.620 – 8.255) 0.130 ± 0.005 (3.302 ± 0.127) ( 0.045 – 0.065 (1.143 – 1.651) 0.015 (0.381) MIN 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 +0.635 8.255 –0.381 0.770 (19.558) MAX ) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.045 ± 0.015 (1.143 ± 0.381) 16 15 14 13 12 11 10 1 2 3 4 5 6 7 9 0.260 ± 0.010 (6.604 ± 0.254) 0.018 ± 0.003 (0.457 ± 0.076) 8 N16 0393 0.100 ± 0.010 (2.540 ± 0.254) S Package 16-Lead SOL 0.005 (0.127) RAD MIN 0.398 – 0.413 (10.109 – 10.490) (NOTE 2) 0.291 – 0.299 (7.391 – 7.595) (NOTE 2) 0.010 – 0.029 × 45° (0.254 – 0.737) 0.093 – 0.104 (2.362 – 2.642) 0.037 – 0.045 (0.940 – 1.143) 16 15 14 13 12 11 10 9 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.050 (1.270) TYP 0.016 – 0.050 (0.406 – 1.270) 16 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.014 – 0.019 (0.356 – 0.482) TYP NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS. 2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). Linear Technology Corporation 0.004 – 0.012 (0.102 – 0.305) 1 2 3 4 5 6 7 8 S16 0393 LT/GP 0493 10K REV 0 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1993