Ordering number : ENA0913 Bi-CMOS IC LV7107M For Video/Audio Signal Input/ Output Interface of DVD Recorder Overview The LV7107M is an IC which integrates on a single chip the analog video/audio signal input switch and video drivers. The IC, which conforms to the Scart connector standard in Europe, is an interface optimal for use in DVD recorders in Europe and DVD complex machines. Functions • Video audio canal SW • S signal 3 input switch • 6dB amplifier • 6MHz/12MHz low pass filter • 11-channel video driver (AV1, AV2, Line output, S output, R·G·B output, component output) • Video signal detection • Composite sync output • Audio ALC Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage 1 VCC max Maximum supply voltage 2 VCC max Allowable power dissipation Pd max Conditions Ratings Unit 6.0 Ta≤75°C Mounted on a specified board * V 13.0 V 1200 mW Operating temperature Topr -20 to +75 °C Storage temperature Tstg -40 to +150 °C Note *: Mounted on a specified board: 114.3mm×76.1mm×1.6mm glass epoxy Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 91207 TI IM 20051012-S00007 No.A0913-1/35 LV7107M Recommended Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Recommended supply voltage 1 VCC 5.0 V Recommended supply voltage 2 VCC 11.6 V Operating supply voltage range 1 VCC opg 4.5 to 5.3 V Operating supply voltage range 2 VCC opg 11.1 to 12.1 V Electrical Characteristics at Ta = 25°C, VCCV = 5.0V, VCCA = 11.6V Parameter Input signal Symbol Point Current dissipation 1 (5V) Signal Out Freq ICC1 Pin6, 8, 25, 40 flow in current when non-signal Current dissipation 2 ICC2 Pin42, 84, 94 flow in current (ALL5V) Current dissipation 3 when non-signal ICC3 Pin46 flow in current when (11.6V) Ratings Test condition Point non-signal Unit min typ max 97.7 115 132.2 mA 16.6 19.5 22.4 mA 18.7 22 25.3 mA 0.3 0.5 0.7 V 5.5 6.0 6.5 dB -1.0 0.0 +1.0 dB -1 0 +1 % -1.5 0 +1.5 deg -60 -50 dB -70 -65 dB Video CANAL SW part Output voltage 1 VDCC 26 AV1, AV2-OUT (Sync tip) 28 Voltage gain VGC 100k 26 VIN=1Vp-p, AV1, AV2-OUT 28 Frequency characteristics DG differential gain VFC 26 DGC 28 VIN=1Vp-p, f=10MHz/100kHz 26 VIN=Video: 1Vp-p 28 DP differential phase DPC 26 VIN=Video: 1Vp-p 28 Cross-talk CTC 4.43M 26 Selected input=GND 28 Non-selected input=1Vp-p, f=4.43MHz Picture S/N VSNC 26 VIN=Video (50%White) 28 Maximum output level VOMAXC 26 Output level at which the 28 linearity of AVI-OUT (pin 26) and AV2-OUT (pin 28) exceeds 1%. 2.8 3.0 Vp-p VIN=Linearity (lamp) signal Output level at linearity 1% Video INPUT SW part Output voltage 1 VDCI1 83 Composite (Sync-Tip) 0.8 1.0 1.2 Output voltage 2 VDCI2 83 Y (Sync-Tip) 0.8 1.0 1.2 V Output voltage 3 VDCI3 81 Chroma (Center) 1.8 2.1 2.4 V 81 VIN=1Vp-p, /load =10kΩ -0.5 0.0 +0.5 dB 5.5 6.0 6.5 dB -1.0 0.0 +1.0 dB Voltage gain 1 VGI1 100k 83 Voltage gain 2 Frequency characteristics VGI2 100k VFI 85 VIN=1Vp-p, /load =10kΩ (SLICER output only) 81 83 VIN=1Vp-p, f=10MHz/100kHz V DG Differential Gain DGSW 83 VIN=Video:1Vp-p -1 0 +1 DP Differential Phase DPSW 83 VIN=Video:1Vp-p -1.5 0 +1.5 deg 81 Selected input =GND 83 Non-selected input =1Vp-p, -60 -50 dB -66 -60 dB Cross-talk CTC 4.43M % f=4.43MHz Picture S/N Maximum output level VSNC 83 VIN=Video (50%White) VOMAXSW 83 Output level when the linearity of pin 83 exceeds 1%. 1.8 2.0 Vp-p Linearity (lamp) signal Output level at linearity 1% Continued on next page. No.A0913-2/35 LV7107M Continued from preceding page. Parameter Input signal Symbol Point Signal Out Freq Ratings Test condition Point min typ Unit max Video Driver part Output voltage 1 Output voltage 2 VDCD1 VDCD2 95 9 97 12 99 17 93 14 RGB (Pedestal) 0.3 0.5 0.7 V 0.5 0.7 0.9 V 1.4 1.7 2 V 5.5 6.0 6.5 dB -1.5 0.0 +1.5 dB -35 -25 dB 0.0 +1.5 dB -40 -30 dB -60 -50 dB -1 0 +1 % -1.5 0 +1.5 deg VIN=1Vp-p, f=4.43MHz, Driver output terminated with 75Ω -60 -50 dB VIN=Video (50%White) -70 -65 dB Y (Sync tip) 19 23 Output voltage 3 Voltage gain 1 VDCD3 95 7 99 11 91 22 VGD 100k C, R-Y, B-Y (Center) VIN=1Vp-p, Line output: 2 drives, Scart output: DC directly-coupled single drive Note 1) Frequency characteristics 1 VFD1 VIN=1Vp-p, f=6MHz/100kHz when 6MHzLPF is selected Frequency characteristics 2 VFD2 f=27MHz/100kHz when 6MHzLPF is selected Frequency characteristics 3 VFD3 f=12MHz/100kHz when 12MHzLPF is selected Frequency characteristics 4 VFD4 -1.5 f=54MHz/100kHz when 12MHzLPF is selected Mute attenuation DG Differential Gain VMUD DG1 VIN=1Vp-p, f=4.43MHz 91 23 VIN=Video: 1Vp-p 23 VIN=Video: 1Vp-p 93 DP Differential Phase DP1 91 93 Cross-talk CTD Picture S/N VSND Maximum output level 1 VOMAXD1 4.43M 9 Output level when the 12 linearity of pins 9, 12, and 17 17 exceeds 1%. 2.8 3.0 Vp-p 2.8 3.0 Vp-p 2.0 2.5 Vp-p 4.3 4.7 5.0 V 0 0.3 0.6 V 0.7 1.0 1.3 µs 3.2 4.2 5.2 µs 4.3 4.7 5.0 V 0 0.3 0.6 V VIN=Linearity (lamp) signal Output level at linearity 1% Maximum output level 2 VOMAXD2 14 Output level when the 19 linearity of pins 14, 19, and 23 23 exceeds 1% VIN=Linearity (lamp) signal Output level at linearity 1% Maximum output level 3 VOMAXD3 7 Output level at which the 11 linearity of pins 7, 11, and 22 22 exceeds 1% VIN=sin 10kHz Output level at linearity 1% Sync-SEP part C.SYNC output VCSH 86 VCSL 86 TDCS 86 Note 2) TWCS 86 Note 2) VVSH 82 VVSL 82 High voltage C.SYNC output Low voltage C.SYNC output delay time C.SYNC output pulse width V.SYNC output High voltage V.SYNC output Low voltage Note 1) The Line output can drive two systems through capacitive coupling while the Scart output drives only one system through DC direct coupling. Note 2) When pin 10 is open Continued on next page. No.A0913-3/35 LV7107M Continued from preceding page. Parameter Input signal Symbol Point Signal Out Freq Ratings Test condition Point min typ Unit max Audio canal switches part V.SYNC output TDVS 82 Note 2) TWVS 82 VIN=PAL Video: 1Vp-p Note 2) VDETH 90 VDETL 90 VOMAXC 71 AV1, AV2-OUT (L, R) to BW=400 to 30kHz 74 Output level at f=1kHz, delay time V.SYNC output pulse width V.DET output High voltage V.DET output Low voltage Maximum output level 7 15 25 µs 125 155 185 µs 4.3 4.7 5.0 V 0 0.3 0.6 V 2.2 2.5 -1.5 0.0 +1.5 dB 0.003 0.01 % -100 -80 dBV -90 -75 dB 100 120 kΩ -110 -80 dB 10.0 12.0 14.0 dB Vrms THD=1% Channel balance CVSW 71 to VIN=2Vrms, f=1kHz Lch Gain-Rch Gain 74 Total harmonic distortion THDAC 71 to VIN=2Vrms, f=1kHz, BW=400 to 30kHz 74 Output noise voltage VNAC 71 Rg=0Ω, BW=JIS-A to 74 Mute attenuation Input impedance Cross talk between channel VMUAC 71 to VIN=2Vrms, f=1kHz, BW=JIS-A 74 20log (VOUT/VIN) ZIN CTSW and selctors 80 71 to VIN=2Vrms, f=1kHz Rg=0Ω, BW=JIS-A 74 Tuner gain GTU 71 VIN=0.5Vrms to 74 Output off set voltage VOFSET 71 Off set voltage at the time of to changeover SW. -20 0 20 mV VIN=1Vrms, f=1kHz, EVR=0dB 4.5 6.0 7.5 dB 4.0 5.5 7.0 dB 3.5 5.0 6.5 dB -1.5 0.0 +1.5 dB -1.5 0.0 +1.5 dB 2.2 2.5 74 Audio ADC block Voltage gain 1 VGA1 78 79 Serial control select 6dB. Voltage gain 2 VGA2 78 79 VIN=1Vrms, f=1kHz, EVR=0dB Serial control select 5.5dB. Voltage gain 3 VGA3 78 79 VIN=1Vrms, f=1kHz, EVR=0dB Serial control select 5dB. Voltage gain 4 VGA4 78 79 VIN=1Vrms, f=1kHz, EVR=0dB Serial control select 0dB. Channel balance CVVR 78 79 VIN=2Vrms, f=1kHz, AMP=5.5dB, AEVR=-12dB Lch Gain-Rch Gain Maximum output level VOMAXI 78 ADC-OUT (L, R), 79 AMP=0dB, EVR=0dB BW=400 to 30kHz Vrms Output level at f=1kHz, THD=1% Total harmonic distortion THDAI 78 79 VIN=2Vrms, f=1kHz, AMP=5.5dB, EVR=-12dB 0.002 0.005 % BW=400 to 30kHz Note 2) When pin 10 is open Continued on next page. No.A0913-4/35 LV7107M Continued from preceding page. Parameter Input signal Symbol Point Output noise voltage Cross talk between channel VNAI CTVR and selctors Signal Out Freq min 78 AMP=5.5dB, EVR=-12dB 79 Rg=0Ω, BW=JIS-A 78 VIN=2Vrms, f=1kHz, AMP=5.5dB, EVR=-12dB 79 Ratings Test condition Point typ Unit max -100 -80 dBV -110 -80 dB -106 -85 dB -106 -80 dBV Rg=0Ω, BW=JIS-A Max attenuation amount VMUAI 78 79 VIN=2Vrms, f=1kHz, AMP=5.5dB, BW=JIS-A EVR=mute/EVR=0dB Residual noise voltage VNAR 78 AMP=5.5dB, EVR=mute 79 Rg=0Ω, BW=JIS-A Audio ALC block Note 3) ALC I/O level 1 ALC1 76 VIN=2Vrms, f=1kHz -3.0 -1.0 dBV ALC I/O level 2 ALC2 76 VIN=2Vrms, f=1kHz -5.0 -3.0 dBV ALC I/O level 3 ALC3 76 VIN=2Vrms, f=1kHz -7.0 -5.0 dBV VMUALC 76 VIN=2Vrms, f=1kHz, BW=JIS-A -73 -65 dB 10.6 11.1 11.6 V 5.5 6.0 6.5 V 0.0 0.1 0.5 V 1.0 ms Mute attenuation 20log (VOUT/VIN) External control part FSS output H voltage VHFSS 27 Serial control FSS OUT H selection, load =10kΩ external output resistor 470 recommended Serial control select FSS OUT H. FSS output M voltage VMFSS 27 Serial control FSS OUT M selection, load =10kΩ external output resistor 470 recommended. Serial control select FSS OUT M. FSS output L voltage VLFSS 27 Serial control FSS OUT L selection, load=10kΩ Serial control select FSS OUT L. FSS risinge time FB output H voltage TFSSLH 27 VHFB 34 Serial control FB OUT H selection. load=150Ω 3.0 4.0 5.0 V 0.0 0.2 0.4 V 0.0 0.5 V 1.0 3.0 V Serial control select FB OUT H. FB output L voltage VLFB 34 Serial control FB OUT L selection. load=150Ω Serial control select FB OUT L. FB external control VLFBIN 32 Pin 32 input voltage range at L range which the pin 34 output becomes L FB external control VHFBIN 32 Pin 32 input voltage range H range when the pin 34 output becomes H External control output H VEXTH voltage 10 2kΩ load for data 1 36 4.0 4.5 5.0 V 0.0 0.3 1.0 V 2.3 2.5 2.7 V 8.7 9.0 9.3 V 4.3 4.5 4.7 V 38 External control output L VEXTL voltage 10 2kΩ load for data 0 36 38 Internal reference regulator REG2.5V VREG25 2 Pins 2 and 100 voltage 100 REG9.0V VREG90 57 Pins 57 and 65 voltage 65 VRE4.5 VREG45 49 Pin 49 voltage Note 3) Audio ALC AMP block When pin 76 (RF MOD OUT) is not used, it is recommended that pin 77 is pulled up to VCC (11.6 V). No.A0913-5/35 LV7107M Package Dimensions unit : mm (typ) 3349 23.2 0.8 20.0 80 51 50 100 31 14.0 17.2 81 1 30 0.65 0.22 0.15 3.0MAX 0.1 (2.7) (0.58) SANYO : QIP100EK(14X20) Audio ALC Characteristics Diagram 10 VIN=1kHz 5 Output Level (dBV) 0 -5 -10 -15 -20 -3dBV -25 -5dBV -7dBV -30 OFF -35 -40 -40 -30 -20 -10 0 10 Input Level (dBV) No.A0913-6/35 LV7107M AV3_R_IN VCR_R_IN DAC_R_IN Graphical View of Audio Block Power Supply No.A0913-7/35 LV7107M Graphical View of The Video Block Power Supply GND * The thick line indicates the circuit operative in the power save mode. In the power save mode, 5V is applied to Pin 42 (VCC5_All), pin 84 (VCC5V_VSW), and pin 94 (VCC_LOGIC) only. No.A0913-8/35 No.A0913-9/35 AV2(15pin) R/C_IN GND_AL REG 2.5 A_ADC_R AV2(11pin) G_IN + 0dB/ -12dB A_ADC_L 0dB/ -12dB + GND_VD AV2(7pin) B_IN RF_MOD VCA Mute GND_AR VCC 5V_VD AV2(1pin) R_OUT R-Y_OUT 6dB Mute Buf Mute AV2(3pin) L_OUT + Buf VCC 5V_RGB AV1(15pin) R/C_OUT AV1(1pin) R_OUT Mute 6dB Buf AV1(3pin) L_OUT SYNC_SEP_LPF Buf Mute B-Y_OUT N.C. 6dB 6dB N.C. Mute AV1(7pin) B_OUT EXT_CTL1 + N.C. N.C. 6dB Mute Y_OUT (Component) GND_REG Audio_Mute_Filter REG 9V AL Mute AV1(11pin) G_OUT A_DAC_L_IN 6dB Mute VCR_L_IN GND-RGB 6dB TUNER_AL_IN Mute Y_OUT (Line_OUT) 12dB Mute AV2(6pin) L_IN Mute AV1(6pin) L_IN C_OUT (Line_OUT) GND_VL AV4(Rear) L_IN TUNER2 AL IN Mute 6dB 6dB AV3(Front) L_IN Mute V_OUT (Line_OUT) REG 9V AR Mute A_DAC_R_IN VCC 5V_VL AV1(19pin) V_OUT VCR_R_IN 6dB AV1(8pin) FSS_OUT TUNER_AR_IN Mute 12dB AV2(19pin) V_OUT AV2(2pin) R_IN Mute 6dB AV1(2pin) R_IN GND_VC + AV4(Rear) R_IN TUNER2 AR IN Tuner V_IN + Block Diagram LV7107M No.A0913-10/35 + AV2(15pin) R/C_IN GND_AL REG 2.5VA A_ADC R_OUT AV2(11pin) G_IN A_ADC L_OUT GND_VD AV2(7pin) B_IN RF_OUT Vcc 5V_VD GND_AR AV2(3pin) R_OUT R-Y_OUT AV2(1pin) L_OUT VCC 5V_RGB AV1(15pin) R/C_OUT AV1(3pin) R_OUT AV1(1pin) L_OUT SYNC_SEP_LPF NC B-Y_OUT AV1(7pin) B_OUT NC NC EXT_CTL1 Y_OUT (Component) NC GND_REG Audio_Mute_Filter REG 9V AL AV1(11pin) G_OUT A_DAC L_IN VCR L_IN GND-RGB Y_OUT (Line_OUT) TUNER_AL_IN AV2(6pin) L_IN AV1(6pin) L_IN GND_VL AV4(Rear) L_IN Tuner2 L IN C_OUT (Line_OUT) AV3(Front) L_IN V_OUT (Line_OUT) REG 9V AR A_DAC R_IN VCC 5V_VL + AV1(19pin) V_OUT VCR R_IN AV1(8pin) FSS_OUT Tuner1 R_IN AV1(2pin) R_IN GND_VC AV2(2pin) R_IN AV2(19pin) V_OUT Tuner1 V_IN AV4(Rear) R_IN Tuner2 L IN + + Test Circuit LV7107M LV7107M Cautions for Use 1. Drive capacity of video driver Line and component outputs can drive two systems through capacitive coupling. Scart output can drive one system only through DC coupling. 2. Application not using the SAG correction function in the video driver with SAG correction When the SAG correction function is not to be used in the video driver with SAG correction, short-circuit output and correction pins for output through capacitive coupling. Application using SAG correction function Video output pin + Application without using SAG correction function 75Ω Video output pin 100µF SAG correction pin + + 75Ω 1000µF 75Ω 75Ω SAG correction pin 22µF 3. Treatment of the pin when Audio RF_MOD output is not used When RF MOD OUT (Pin76) is not used, it is recommended to pull up the ALC filter pin (pin77) to VCC (11.6V). 4. Audio Mute This IC incorporates a mute transistor to reduce the POP noise of audio output when power is turned ON/OFF. Mute control can be made by serial control. 5. Resistor to limit the Audio input When the large signal is input in the input pin with power OFF, cross-talke between input and output occurs through the protective diode and parasitic elements. Because of the structure of LSI, such cross-talke is difficult to avoid. If cross-talk at a time of power OFF presents a problem, the cross-talk amount can be reduced by inserting the limiting resistor in the input. In this case, the input signal level changes depending on the resistance value. Determine the constant while taking both the cross-talk amount and input level into account. 6. Pin treatment when external control is not to be used When external control pins (Pins 13, 36, and 38) are not used, pull-down to GND is recommended. 7. Pin treatment of N.C pin It is recommended to connect N.C. pins (Pins 67, 68, 69, and 70) directly to the GND. 8. Audio 9V_REG pin external capacitance Use the Audio 9V_REG pins (pins 57 and 66) external capacitance of 10µF or more and with the equivalent series resistance component of 7Ω or less. 9. Power application and disconnection sequences The recommended power application sequence to this IC is VCC_ALL5V (Pin42) → VCC5V (Pins 6, 8, 25, 40, 84 and 94), VCC11.6V (Pin46). (No particular order is established between VCC5V and VCC11.6V.) It is recommended to reverse the above sequence when power supply is turned OFF. No.A0913-11/35 LV7107M Serial Control Table ADDRESS 8 * indicates initial. 7 6 5 4 3 2 Group 1 SV1 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 * Y+C PB MIX(ENC) PB(SCART Y/C) 1 Y(VCR) PB(VCR SCART Y/C) 0 CV(VCR) PB(VCR) 0 1 MUTE 1 * PROHIBIT SV2 00000001 0 VIDEO CANAL-SW VIDEO 0 0 V(AV1) V(TU) 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 * Y+C PB MIX(ENC) CV(VCR) PB(VCR) MUTE PROHIBIT and after SV3 SV3 0 0 V(AV1) 0 1 V(AV2) 1 0 V(TU) 1 1 Y(VCR) 8 7 6 5 4 3 2 * PB Remarks 1 SV4 SV4 0 0 1 V(AV4) 1 0 SV3-OUT 1 SV5/6 MIX 1 0 Group 2 00000010 VIDEO INPUT-SW SV7 0 V(AV3) 0 SV5/6 * SV5 SV6 0 Y(AV3) C(AV3) FRONT Y(AV4) C(AV4) REAR SCART-YC 0 0 1 0 1 0 Y(AV2) C(AV2) 0 1 1 Y(VCR) C(VCR) 1 0 0 MUTE MUTE 1 0 1 PROHIBIT PROHIBIT and after * SV7 Y 0 0 0 1 CV 1 0 MUTE 1 1 MUTE SV16 Note 1) V(AV2) Y(ENC) SV2 ADDRESS Remarks 1 SV1 * SV16 0 1 THROUGH * CLAMP input fixed Note 1) G2D8/G3D8="11" is prohibited. Follow the AV2 (16) FB_IN (Pin32) control in case of THROUGH. AV2_16pin SV16 H L a: Clamp input (RGB) b: Bias input (COMPONENT) No.A0913-12/35 LV7107M ADDRESS 8 7 6 5 4 3 2 Remarks 1 RESERVE 0 1 RGB SV11b output 0 1 SV11a SV12a 0 0 0 0 0 1 SV13a 0 0 1 1 0 1 0 1 AV2_G AV2_B SV11a SV12a SV13a f: AV2_RGB(EXTERNAL) * MUTE ENC_Y MUTE a: ENC_Y * ENC_Y ENC_B-Y b: component ENC_B-Y c: component ENC_B-Y d: component (12MLPF) (component) ENC_R-Y ENC_Y (12MLPF) (component) ENC_R-Y 1 0 SV13b AV2_R ENC_R-Y 0 1 SV12b According to G3D3/D4/D5 control ENC_Y (12MLPF) (component) MUTE ENC_R-Y MUTE MUTE e: mute ENC_Y ENC_B-Y f: component (12MLPF) (component) PROHIBIT PROHIBIT 1 1 0 SV11b SV12b SV13b 0 0 0 ENC_R ENC_G ENC_B a: ENC_RGB(6MLPF) 0 0 1 MUTE MUTE MUTE b: mute * effective 0 1 0 ENC_C MUTE MUTE c: ENC_C at 0 1 1 VCR_C MUTE MUTE d: VCR_C G3D2="0" 1 0 0 MUTE MUTE MUTE e: mute AV2_R AV2_G AV2_B f: AV2_RGB(EXTERNAL) PROHIBIT PROHIBIT PROHIBIT Group 3 00000011 SV11b VIDEO SV12b OTHER-1 SV13b SV14 0 1 1 1 0 and after * SV14 0 1 SV15 0 1 CV(PB) PB MUTE * SV15a(Y) SV15b(C) SV17Y-OUT SV17C-OUT PB(according to DVD/VCR of GR4) MUTE MUTE * SV16 SV16 Note 1) 1 and after PROHIBIT 0 1 THROUGH BIAS input fixed * Note 1) G2D8/G3D8="11" is prohibited. Follow the AV2 (16) FB_IN (Pin32) control in case of THROUGH. AV2_16pin SV16 H L a: Clamp input (RGB) b: Bias input (COMPONENT) No.A0913-13/35 LV7107M ADDRESS 8 7 6 5 4 3 2 Remarks 1 SV17 SV17 DVD/VCR (V/C/Y) Note 2) Y+C MIX 0 1 SV18 TUNER1/2 Note 2) Y+C AUDIO(VCR) PB(VCR) SA18(L/R) 0 Tuner1 Tuner1 1 Tuner2 Tuner2 * * SWF 0 0 0 0 1 5V 00000100 1 0 THROUGH 1 THROUGH VIDEO OTHER-1 PB(DVD) MIX(VCR) Group 4 AUDIO AUDIO(DAC) (ENC) SV18 FB AV1(16) & SA17(L/R) 1 FSS * FSS-OUT AV1(8) 0 LOW(0.5V) 0 1 MID(6.0V) 1 0 HIGH(11.0V) 1 1 HIGH(11.0V) 0 Note 3) SLICE * SLICE AMP AMP gain 0 0dB 1 6dB A-MUTE * All MUTE Note 4) (Audio) 0 THROUGH 1 MUTE Pins 71 to 74 output MUTE * Note 2) Operates in VIDEO/AUDIO interlock. Note 3) Same polarity as the AV2 (16) FB_IN (Pin32) control in case of THROUGH. Note 4) AUDIO MUTE control RF_MOD output: Serial control MUTE, Power-ON_MUTE CANAL output: Serial control MUTE, Power-ON_MUTE 8 ADDRESS 7 6 5 4 2 1 SA1L SA1R 0 0 0 L(AV2) R(AV2) R(DAC) PB(DAC) SA1L/R and after 00000101 AUDIO CANAL-SW SA4L/R 0 0 1 0 1 0 L(DAC) R(DAC) PB(DAC) 0 1 1 L(VCR) R(VCR) PB(VCR) MUTE PROHIBIT 1 0 0 MUTE 1 0 1 PROHIBIT SA2L SA2R L(AV1) R(AV1) 0 0 0 0 0 1 L(TU) R(TU) 0 1 0 L(DAC) R(DAC) PB 0 1 1 L(VCR) R(VCR) PB 1 0 0 1 0 1 and after MUTE MUTE PROHIBIT PROHIBIT SA4L SA4R L(AV3) R(AV3) 0 0 0 1 L(AV4) R(AV4) 1 0 SL3 out SR3 out 1 MUTE MUTE 1 * L(DAC) SA2L/R Group 5 Remarks 3 * * No.A0913-14/35 LV7107M ADDRESS 8 7 6 5 4 3 2 and after 00000110 ALC-LEVE INPUT-SW L SA3R 0 0 L(AV1) R(AV1) 0 0 1 L(AV2) R(AV2) R(TU) 0 1 0 L(TU) 0 1 1 L(DAC) R(DAC) 1 0 0 L(VCR) R(VCR) 1 0 1 PROHIBIT PROHIBIT * PB RF_MOD output Note 4) AUDIO SA3L 0 SA5 Group 6 Remarks 1 SA3L/R 0 THROUGH 1 MUTE Pin 77 output MUTE * Audio ALC 0 0 -3dBV 0 1 -5dBV 1 0 -7dBV 1 1 MUTE * PROHIBIT ADC-AMP ADC-AMP-g ain 0 0 6.0dB 0 1 5.5dB 1 0 5.0dB 1 1 PROHIBIT * Note 4) AUDIO MUTE control RF_MOD output: Serial control MUTE, Power-ON_MUTE CANAL output: Serial control MUTE, Power-ON_MUTE ADDRESS 8 7 6 5 4 3 2 Audio EVR(L) EVR-L 0 0 0 0 0 0 0dB 0 0 1 1 0 0 -12dB 1 1 1 1 1 1 Mute 00000111 General (Pin13) 0 L 1 H Changeover R/R-Y_IN of VIDEO BIAS/CLAMP ADDRESS Input changeover (Pin97) (Pin99) CLAMP input BIAS input Component 1 CLAMP input CLAMP input CLAMP input RGB 7 6 5 4 3 2 Audio 0 0 0 0 0 0 0dB 0 0 1 1 0 0 -12dB 1 1 1 1 1 1 Other than above * Remarks 1 EVR(R) purpose 3 B/B-Y_IN (Pin95) EVR-R 00001000 * G/Y_IN BIAS input AUDIO General General purpose OUT1 0 8 Group 8 * EXT_CTL1 purpose 1 input Pin 78 output MUTE PROHIBIT Other than above Group 7 Remarks 1 AUDIO Mute Pin 79 output MUTE * General purpose OUT3 * General purpose OUT4 * PROHIBIT EXT_CTL3 (Pin36) 0 1 General L H EXT_CTL4 purpose 4 (Pin38) 0 L 1 H No.A0913-15/35 LV7107M Serial Control Specification 1. Slave address MSB 1 LSB 0 0 1 0 1 0 0 Ï Slave receiver One-way communication (this IC is dedicated to receive) 2. DATA TRANSFER MANUAL: [1] is High level. [0] is Low level. I2C-BUS control system is adopted in SW LSI. SW LSI is controlled by SCL (Serial Clock) and SDA (Serial Data) At first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data, which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data transfer order (MSB→LSB). The 9th bit is called as ACK (Acknowledge), SW LSI sends [0] to the SDA terminal during SCL [1] period. So, please open the port of microprocessor during this period. LV7107M adopt auto-increment, so you input only first group-address and you can transfer data in order. As thus the Data transfer Stop condition*2 is finished. *1 SDA rise up during SCI is [1] *2 SDA fall down during SCL is [1] 3. TRANSFER DATA FORMAT The transfer data is composed by START condition, Slave address, Group address*1, data, and STOP condition. After setting up the START condition, please transfer the Slave Address (regulated as “1001000” in SW LSI). Group and next control data*2 (Please see the Fig.1) Slave Address is composed by 7bits, and this bit 8th bit*3 should be set as [0]. The both of Group address and control data are composed by 8bits, and the one control action is defined with combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by sending some control data together. The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over. But LV7107M adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data. If you want to stop transfer action, please transfer the STOP condition without fail. *1/2 There are 8 control groups. *3 This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept mode with SW LSI) and [1] means accept mode (send mode with SW LSI) fundamentally. But SW LSI is not equipped with such a data out function, please keep this bit as [0]. Fig.1 DATA STRUCTURE START condition Ï Start condition Slave address R/W ACK Group address Ï Acknowledge ACK Control data ACK … STOP condition Ï Stop condition No.A0913-16/35 LV7107M 4. INITIALIZE AND OTHERS SW LSI is initialized as the following mode for circuit protection. Please see “SERIAL CONTROL TABLE”. Characteristics of the SDA and SCL 1/0 stages for SW LSI Parameter Symbol Min Max Unit LOW level input voltage VIL 0 0.8 HIGH level input voltage VIH 3.0 5.0 V LOW level output current IOL 3.0 mA SCL clock frequency fSCL 400 kHz Set-up time for a repeated START condition tSU:STA Hold time START condition. After this period, the first clock pulse is generated. tHD:STA 0.6 µs LOW period of the SCL clock tLOW 1.3 µs Rise time of both SDA and SDL signals tR HIGH period of the SCL clock tHIGH Fall time of both SDA and SDL signals tF 0 0.3 µs Data hold time: tHD:DAT 0 0.9 µs Data set-up time tSU:DAT 100 ns Set-up time for STOP condition tSU:STO 0.6 µs BUS fredd time between a STOP and START condition tBUF 1.3 µs µs 0.6 0 V 0.3 µs µs 0.6 Fig.2 Definition of timing. tHIGH tR tF SCL (86pin) tSU:STA tHD:STA tLOW tHD:DAT tSU:DAT tSU:STO tBUF SDA (87pin) No.A0913-17/35 LV7107M Pin Function Pin No. Pin name P1 AV2 R/C_IN DC voltage Signal wave form In put/Out put form 1.6V R 4kΩ 1kΩ 0.7Vpp 1.6V 4kΩ 300Ω 20kΩ 2.1V Chroma 300Ω 0.7Vpp 2.1V 1 P2 REG 2.5VA 2.5V DC 10pF 50Ω 1kΩ 100Ω 2 6.8kΩ 13kΩ 18.5kΩ 30kΩ P3 AV2 G_IN 18.5kΩ 22.8kΩ 23kΩ 910Ω 1.6V G 1kΩ 4kΩ 4kΩ 0.7Vpp 300Ω 1.6V 300Ω 3 P4 GND_VD P5 AV2 B_IN 1.6V B 1kΩ 4kΩ 4kΩ 0.7Vpp 300Ω 300Ω 1.6V 5 Continued on next page. No.A0913-18/35 LV7107M Continued from preceding page. Pin No. Pin name P6 VCC 5V_VD P7 R-Y_OUT DC voltage Signal wave form In put/Out put form 1.7V R-Y 100Ω 2kΩ 1.7V 1.4Vpp 10.7 kΩ 10kΩ 3.3pF P8 VCC 5V_RGB P9 AV1 R/C_OUT 1pF 100Ω 7 1pF 100 kΩ 0.5V R 1.4Vpp 100Ω 1.25pF 2kΩ 10.7 kΩ 0.5V 3.3pF 1.7V Chroma 200Ω 10 kΩ 9 1.25pF 1.4Vpp 1.7V P10 SYNC_SEP_LPF 2.2V Y 10 500Ω 500Ω 1.0Vpp 40kΩ 2.2V 8pF P11 B-Y_OUT 1.7V B-Y 100Ω 1.7V 2kΩ 1.4Vpp 10.7 kΩ 10kΩ 3.3pF 1pF 100Ω 11 1pF 100 kΩ Continued on next page. No.A0913-19/35 LV7107M Continued from preceding page. Pin No. Pin name P12 AV1 B_OUT DC voltage Signal wave form In put/Out put form 0.5V B 100Ω 1.25pF 2kΩ 10.7 kΩ 1.4Vpp 200Ω 12 0.5V 3.3pF P13 10 kΩ 1.25pF EXT_CTL1 5V 13 0V P14 Y_OUT 0.7V Y 15 (Component) 2.0Vpp 100Ω 0.7V P15 Y_SAG_IN 1kΩ 2kΩ 10.4 kΩ 3pF 100Ω 0.7V Y (Component) 2.0Vpp 3pF 14 10 kΩ 100 kΩ 3pF 0.7V P16 Audio_Mute _Filter 140kΩ 500Ω 16 60kΩ P17 AV1 G_OUT 0.5V G 100Ω 1.4Vpp 2kΩ 10.7 kΩ 1.25pF 200Ω 17 0.5V 3.3pF 10 kΩ 1.25pF Continued on next page. No.A0913-20/35 LV7107M Continued from preceding page. Pin No. Pin name P18 GND_RGB P19 Y_OUT DC voltage Signal wave form In put/Out put form 0.7V Y 20 (Line_OUT) 2.0Vpp 100Ω 2kΩ 10.4 kΩ 0.7V P20 Y_SAG_IN 0.7V Y 10 kΩ (Line_OUT) 3pF 2.0Vpp 1kΩ 3pF 100Ω 19 3pF 100 kΩ 0.7V P21 P22 GND_VL C_OUT 1.7V Chroma (Line_OUT) 100Ω 1.4Vpp P23 V_OUT 1.7V 2kΩ 1pF 100Ω 10.7 kΩ 22 10kΩ 0.7V Video 100 kΩ 1pF 3.3pF 24 (Line_OUT) 2.0Vpp 100Ω 2kΩ 10.4 kΩ 0.7V P24 V_SAG_IN 0.7V Video (Line_OUT) 10 kΩ 3pF 1kΩ 3pF 100Ω 3pF 2.0Vpp 23 100 kΩ 0.7V P25 VCC 5V_VL P26 AV1 V_OUT 0.5V Video 2.0Vpp 100Ω 2kΩ 0.5V 10.7 kΩ 1.25pF 200Ω 26 0.5V Y 3.3pF 10 kΩ 1.25pF 2.0Vpp 0.5V Continued on next page. No.A0913-21/35 LV7107M Continued from preceding page. Pin No. Pin name P27 AV1 FSS_OUT DC voltage Low:0.5V Signal wave form In put/Out put form DC Midol:6.0V High:11.1V 27 100kΩ P28 AV2 V_OUT 0.5V Video 100Ω 2kΩ 10.7 kΩ 2.0Vpp 1.25pF 200Ω 28 0.5V P29 GND_VC P30 Tuner1 V_IN 10 kΩ 3.3pF 1.25pF 1.6V Video 1kΩ 4kΩ 1.0Vpp 4kΩ 300Ω 300Ω 1.6V 30 P31 AV2 V/Y_IN 1.6V Video 1.0Vpp 4kΩ 1kΩ 1.6V 4kΩ 1.6V Y 300Ω 300Ω 1.0Vpp 31 1.6V P32 AV2 FB_IN 2V 1kΩ 32 0V Continued on next page. No.A0913-22/35 LV7107M Continued from preceding page. Pin No. Pin name P33 AV1 V_IN DC voltage Signal wave form In put/Out put form 1.6V Videoo 4kΩ 1kΩ 1.0Vpp 4kΩ 300Ω 1.6V 300Ω 33 P34 AV1 FB_OUT L:0V H:3.8V 10kΩ Through: 0/3.8V 3.8V 1kΩ 34 1kΩ 100 kΩ 0V 1kΩ P35 AV4 V_IN 1kΩ 1.6V Video 1kΩ 4kΩ 1.0Vpp 4kΩ 300Ω 300Ω 1.6V 35 P36 EXT_CTL3 5V 36 0V P37 AV3 V_IN 1.6V Video 1kΩ 4kΩ 1.0Vpp 4kΩ 300Ω 300Ω 1.6V 37 Continued on next page. No.A0913-23/35 LV7107M Continued from preceding page. Pin No. Pin name P38 EXT_CTL4 DC voltage Signal wave form In put/Out put form 5V 38 0V P39 AV4 Y_IN/ 1.6V Y Tuner2 V_IN 1.0Vpp 1kΩ 4kΩ 1.6V 4kΩ 1.6V Video 300Ω 300Ω 1.0Vpp 39 1.6V P40 VCC 5V_VC P41 AV3 Y_IN 1.6V Y 1kΩ 4kΩ 4kΩ 1.0Vpp 300Ω 300Ω 1.6V 41 P42 VCC 5V_ALL P43 AV4 C_IN 5V DC 2.1V Chroma 1kΩ 4kΩ 0.7Vpp 2.1V 20.3kΩ 300Ω 43 P44 GND_REF 0V DC Continued on next page. No.A0913-24/35 LV7107M Continued from preceding page. Pin No. Pin name P45 AV3 C_IN DC voltage Signal wave form In put/Out put form 2.1V Chroma 1kΩ 4kΩ 0.7Vpp 2.1V 300Ω 20.3kΩ 45 P46 VCC 11.6V_A 11.6V P47 VCR Y_IN 1.6V Y DC 1kΩ 4kΩ 1.0Vpp 4kΩ 300Ω 300Ω 1.6V 47 P48 VCR C_IN 2.1V Chroma 1kΩ 0.7Vpp 2.1V 4kΩ 20.3kΩ 300Ω 48 P49 REF 4.5V 4.5V 57 60kΩ 1kΩ 49 60kΩ Continued on next page. No.A0913-25/35 LV7107M Continued from preceding page. Pin No. Pin name P50 AV3 R_IN DC voltage Signal wave form In put/Out put form 4.5V 4.5V 50 500Ω 100kΩ Max 5.6Vpp P51 AV4 R_IN/ 4.5V 4.5V Tuner2 R_IN 4.5V 51 500Ω 100kΩ Max 5.6Vpp P52 AV1 R_IN 4.5V 4.5V 4.5V 52 500Ω 100kΩ Max 5.6Vpp P53 AV2 R_IN 4.5V 4.5V 4.5V 53 500Ω 100kΩ Max 5.6Vpp P54 Tuner1 R_IN 4.5V 4.5V 4.5V 54 500Ω 100kΩ Max 5.6Vpp 4.5V Continued on next page. No.A0913-26/35 LV7107M Continued from preceding page. Pin No. Pin name P55 VCR R_IN DC voltage Signal wave form In put/Out put form 4.5V 4.5V 55 500Ω 100kΩ Max 5.6Vpp P56 A_DAC R_IN 4.5V 4.5V 4.5V 56 500Ω 100kΩ Max 5.6Vpp P57 REG 9V AR 9V 4.5V DC 50Ω 100Ω 57 141kΩ 23kΩ P58 AV3 L_IN 4.5V 4.5V 58 500Ω 100kΩ Max 5.6Vpp P59 AV4 L_IN/ 4.5V 4.5V Tuner2 L_IN 4.5V 59 500Ω 100kΩ Max 5.6Vpp 4.5V Continued on next page. No.A0913-27/35 LV7107M Continued from preceding page. Pin No. Pin name P60 AV1 L_IN DC voltage Signal wave form In put/Out put form 4.5V 4.5V 60 500Ω 100kΩ Max 5.6Vpp 4.5V P61 AV2 L_IN 4.5V 4.5V 61 500Ω 100kΩ Max 5.6Vpp P62 Tuner1 L_IN 4.5V 4.5V 4.5V 62 500Ω 100kΩ Max 5.6Vpp P63 VCR L_IN 4.5V 4.5V 4.5V 63 500Ω 100kΩ Max 5.6Vpp P64 A_DAC L_IN 4.5V 4.5V 4.5V 64 500Ω Max 5.6Vpp 100kΩ 4.5V Continued on next page. No.A0913-28/35 LV7107M Continued from preceding page. Pin No. Pin name P65 REG 9V AL DC voltage 9V Signal wave form In put/Out put form DC 50Ω 100Ω 65 141kΩ 23kΩ P66 GND_REG P67 N.C. P68 N.C. P69 N.C. P70 N.C. P71 AV1 L_OUT 0V DC 4.5V 4.5V 700Ω 100Ω 71 Max 5.6Vpp 20kΩ 4.5V P72 AV1 R_OUT 4.5V 4.5V 700Ω 100Ω 72 Max 5.6Vpp 20kΩ 4.5V Continued on next page. No.A0913-29/35 LV7107M Continued from preceding page. Pin No. Pin name P73 AV2 L_OUT DC voltage Signal wave form In put/Out put form 4.5V 4.5V 700Ω 100Ω 73 Max 5.6Vpp 20kΩ 4.5V P74 AV2 R_OUT 4.5V 4.5V 700Ω 100Ω 74 Max 5.6Vpp 20kΩ 4.5V P75 GND_AR 0V P76 RF_OUT 4.5V DC 15.3kΩ 50Ω 76 5kΩ 4.5V 100kΩ Max 5.6Vpp P77 PALCFIL 0V 500Ω 10kΩ DC 250Ω 250Ω 2kΩ 77 Continued on next page. No.A0913-30/35 LV7107M Continued from preceding page. Pin No. Pin name P78 A_DAC L_OUT DC voltage Signal wave form In put/Out put form 4.5V 100Ω 4.5V 78 Max 5.6Vpp P79 A_DAC R_OUT 4.5V 100Ω 4.5V 79 Max 5.6Vpp P80 GND_AL P81 DAC C_OUT 2.1V 500Ω 0.7Vpp 2.1V 81 500µA P82 V_SYNC_OUT 4.7V 300Ω 82 300Ω 0.3V Continued on next page. No.A0913-31/35 LV7107M Continued from preceding page. Pin No. Pin name P83 DAC V/Y_OUT DC voltage Signal wave form In put/Out put form 1.0V Y 1.0Vpp 500Ω 1.0V 1.0V Video 83 500µA 1.0Vpp 1.0V P84 VCC 5V_VSW P85 Slicer_OUT 1.0V Y Max 2.0Vpp or 1.0Vpp 500Ω 1.0V 1.0V Video 85 Max 2.0Vpp or 1.0Vpp 500µA 1.0V P86 C_CYNC_OUT 4.7V 300Ω 86 300Ω 0.3V P87 V_DET_IN 87 4.7V 10kΩ 0.3V 25kΩ 50µA Continued on next page. No.A0913-32/35 LV7107M Continued from preceding page. Pin No. Pin name P88 SCL_IN DC voltage Signal wave form In put/Out put form 50kΩ 5V 2.3V 88 1.0V 30kΩ P89 SDL_IN 50kΩ 5V 2.3V 89 1.0V 30kΩ P90 V_DET_OUT 4.7V with signal DC 0V without signal 300Ω 90 300Ω P91 ENC. C_IN 2.1V Chroma 1kΩ 4kΩ 20.3kΩ 0.7Vpp 2.1V 300Ω 91 P92 V_DET_FIL DC 92 200Ω 1kΩ 1kΩ 1kΩ 60µA Continued on next page. No.A0913-33/35 LV7107M Continued from preceding page. Pin No. Pin name P93 ENC. Y_IN DC voltage Signal wave form In put/Out put form 1.6V Y 1kΩ 4kΩ 1.0Vpp 4kΩ 300Ω 300Ω 1.6V 93 P94 VCC_LOGIC P95 ENC. R/ 1.6V R R-Y_IN 1kΩ 4kΩ 0.7Vpp 1.6V 4kΩ 2.1V R-Y 20kΩ 2.1V 300Ω 300Ω 0.7Vpp 95 P96 GND_LOGIC P97 ENC. G/Y_IN 1.6V G 1kΩ 4kΩ 0.7Vpp 1.6V 4kΩ 1.6V Y 300Ω 300Ω 1.0Vpp 97 1.6V P98 GND_VSW P99 ENC. B/B-Y_IN 1.6V B 1kΩ 0.7Vpp 4kΩ 1.6V 4kΩ 2.1V B-Y 20kΩ 2.1V 300Ω 300Ω 0.7Vpp 99 Continued on next page. No.A0913-34/35 LV7107M Continued from preceding page. Pin No. Pin name P100 REG 2.5V DC voltage 2.5V Signal wave form In put/Out put form DC 10pF 50Ω 1kΩ 100Ω 100 6.8kΩ 13kΩ 18.5kΩ 30kΩ 910Ω 18.5kΩ 23kΩ SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2007. Specifications and information herein are subject to change without notice. PS No.A0913-35/35