SANYO LV71081E

Ordering number : ENA1610A
Bi-CMOS IC
LV71081E
For Video/Audio Signal Input/
Output Interface of DVD Recorder
Overview
The LV71081E is for video/audio signal input/output interface of DVD recorder.
Functions
• Video audio canal SW
• S signal 3 input switch
• 6dB amplifier
• 6MHz/12MHz/27MHz-LPF / 6MHz/12MHz/27MHz low pass filter
• 6ch video driver (AV1, AV2, Line output, R•G•B output)
• Video signal detection
• Composite sync output
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage 1
Symbol
Conditions
Ratings
VCC max
Unit
6.0
V
Maximum supply voltage 2
VCC max
Allowable power dissipation
Pd max
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-40 to +150
°C
Ta ≤ 75°C Mounted on a specified board *
13.0
V
1200
mW
* Mounted on a specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
92910 SY/D0909 SY PC 20091028-S00001 No.A1610-1/31
LV71081E
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Recommended supply voltage 1
Conditions
Ratings
Unit
VCC
5.0
V
12.0
V
Recommended supply voltage 2
VCC
Operating supply voltage range 1
VCC opg
4.5 to 5.3
V
Operating supply voltage range 2
VCC opg
11.1 to 12.5
V
Electrical Characteristics at Ta = 25°C, VCC = 2.8V
Parameter
Input signal
Symbol
Point
Current dissipation 1 (5V)
Signal
Out
Freq
ICC1
Ratings
Test condition
Point
min
Unit
typ
max
97.7
115.0
132.2
mA
20.0
23.0
26.0
mA
18.7
22.0
25.3
mA
AV1, AV2-OUT (Sync tip)
0.3
0.5
0.7
V
VIN = 1Vp-p, AV1, AV2-OUT
5.5
6.0
6.5
dB
-1.0
0.0
+1.0
dB
Pin6, 8, 25, 40 flow in current
when non-signal
Current dissipation 2
ICC2
Pin42, 84, 94 flow in current
(ALL5V)
Current dissipation 3
when non-signal
ICC3
Pin46 flow in current when
(11.6V)
non-signal
Video CANAL SW part
Output voltage 1
VDCC
26
28
Voltage gain
VGC
100k
26
28
Frequency characteristics
Differential gain
VFC
26
DGC
28
VIN = 1Vp-p,
f = 10MHz/100kHz
26
VIN = Video : 1Vp-p
-1
0
+1
%
VIN = Video : 1Vp-p
-1.5
0
+1.5
°C
-60
-50
dB
-70
-65
dB
28
Differential phase
DPC
26
28
Cross-talk
CTC
4.43M
26
Selected input = GND
28
Non-selected input = 1Vp-p,
f = 4.43MHz
Picture S/N
VSNC
26
VIN = Video (50%White)
28
Maximum output level
VOMAXC
26
Output level ar which the
28
linearity of AVI-OUT (pin 26)
2.8
3.0
Vp-p
Composite (Sync-Tip)
0.8
1.0
1.2
V
V
and AV2-OUT (pin 28)
exceeds 1%.
VIN = Linearity (lamp) signal
Output level at linearity 1%
Video INPUT SW part
Output voltage 1
VDCI1
83
Output voltage 2
VDCI2
83
Y (Sync-Tip)
0.8
1.0
1.2
Output voltage 3
VDCI3
81
Chroma (Center)
1.8
2.1
2.4
V
Voltage gain 1
VGI1
100k
81
VIN = 1Vp-p, load = 10kΩ
-0.5
0.0
+0.5
dB
Voltage gain 2
VGI2
100k
85
VIN = 1Vp-p, load = 10kΩ
5.5
6.0
6.5
dB
-1.0
0.0
+1.0
dB
83
(SLICER output only)
Frequency characteristics
VFI
81
83
VIN = 1Vp-p,
f = 10MHz/100kHz
Differential Gain
DGSW
83
VIN = Video :1Vp-p
-1
0
+1
%
Differential Phase
DPSW
83
VIN = Video :1Vp-p
-1.5
0
+1.5
°C
Cross-talk
CTC
81
Selected input = GND
-60
-50
dB
83
Non-selected input = 1Vp-p,
-66
-60
4.43M
f = 4.43MHz
Picture S/N
VSNC
83
VIN = Video (50%White)
Maximum output level
VOMAXSW
83
Output level when the linearity
1.8
2.0
dB
Vp-p
of pin 83 exceeds 1%.
VIN = Linearity (lamp) signal
Output level at linearity 1%
Continued on next page.
No.A1610-2/31
LV71081E
Continued from preceding page.
Parameter
Input signal
Symbol
Point
Signal
Out
Freq
Ratings
Test condition
Point
min
typ
Unit
max
Video Driver part
Output voltage 1
Output voltage 2
VDCD1
VDCD2
95
9
97
12
99
17
93
14
RGB (Pedestal)
0.3
0.5
0.7
V
Y (Sync tip)
0.5
0.7
0.9
V
VIN = 1Vp-p, Line output : 2
5.5
6.0
6.5
dB
-1.5
0.0
+1.5
dB
-35
-25
dB
0.0
+1.5
dB
-40
-30
dB
20
35
ns
23
Voltage gain 1
VGD
100k
drives, Scart output: DC
directly-coupled single drive
Note 1)
Frequency characteristics 1
VFD1
VIN = 1Vp-p,
f = 6MHz/100kHz when
6MHzLPF is selected
Frequency characteristics 2
VFD2
f = 27MHz/100kHz when
6MHzLPF is selected
Frequency characteristics 3
VFD3
f = 12MHz/100kHz when
-1.5
12MHzLPF is selected
Frequency characteristics 4
VFD4
f = 54MHz/100kHz when
12MHzLPF is selected
Group delay
VGDD1
f = 6MHz/100kHz when
6MHzLPF is selected
Mute attenuation
VMUD
Differential Gain
DG1
VIN = 1Vp-p, f=4.43MHz
91
-60
-50
dB
23
VIN = Video : 1Vp-p
-1
0
+1
%
23
VIN = Video : 1Vp-p
-1.5
0
+1.5
°C
-60
-50
dB
-70
-65
93
Differential Phase
DP1
91
93
Cross-talk
CTD
4.43M
VIN = 1Vp-p, f = 4.43MHz,
Driver output terminated with
75Ω
Picture S/N
VSND
Maximum output level 1
VOMAXD1
VIN = Video (50%White)
9
Output level when the linearity
12
of pins 9, 12, and 17 exceeds
17
1%.
dB
2.8
3.0
Vp-p
2.6
2.8
Vp-p
2.0
2.5
Vp-p
VIN = Linearity (lamp) signal
Output level at linearity 1%
Maximum output level 2
VOMAXD2
14
Output level when the linearity
19
of pins 14, 19, and 23 exceeds
23
1%
VIN = Linearity (lamp) signal
Output level at linearity 1%
Maximum output level 3
VOMAXD3
7
Output level at which the
11
linearity of pins 7, 11, and 22
22
exceeds 1%
VIN = sin 10kHz
Output level at linearity 1%
Sync-SEP part
C.SYNC output
VCSH
86
4.3
4.7
5.0
V
VCSL
86
0
0.3
0.6
V
TDCS
86
Note 2)
1.0
1.7
2.4
μs
TWCS
86
Note 2)
3.2
4.2
5.2
μs
VVSH
82
4.3
4.7
5.0
V
VVSL
82
0
0.3
0.6
V
High voltage
C.SYNC output
Low voltage
C.SYNC output
delay time
C.SYNC output
pulse width
V.SYNC output
High voltage
V.SYNC output
Low voltage
Note 1) The Line output can drive two systems through capacitive coupling while the Scart output drives only one system through DC direct coupling.
Note 2) When pin 10 is open
Continued on next page.
No.A1610-3/31
LV71081E
Continued from preceding page.
Parameter
Input signal
Symbol
Point
V.SYNC output
Signal
Out
Freq
Ratings
Test condition
Point
min
typ
Unit
max
7
15
25
μs
125
155
185
μs
90
4.3
4.7
5.0
V
VDETL
90
0
0.3
0.6
V
VOMAXC
71
AV1, AV2-OUT (L, R)
2.2
2.5
to
BW = 400 to 30kHz
74
Output level at f = 1kHz,
71
VIN = 2Vrms, f = 1kHz
Lch Gain-Rch Gain
-1.5
0.0
+1.5
dB
0.003
0.01
%
-100
-80
dBV
-90
-75
dB
100
120
kΩ
-110
-80
dB
10.0
12.0
14.0
dB
-20
0
+20
mV
4.5
6.0
7.5
dB
4.0
5.5
7.0
dB
3.5
5.0
6.5
dB
-1.5
0.0
+1.5
dB
-1.5
0.0
1.5
dB
2.2
2.5
TDVS
82
Note 2)
TWVS
82
VIN = PAL Video : 1Vp-p
Note 2)
VDETH
delay time
V.SYNC output
pulse width
V.DET output
High voltage
V.DET output
Low voltage
Audio canal switches part
Maximum output level
Vrms
THD = 1%
Channel balance
CVSW
to
74
Total harmonic distortion
THDAC
71
to
VIN = 2Vrms, f = 1kHz,
BW = 400 to 30kHz
74
Output noise voltage
VNAC
71
Rg = 0Ω, BW = JIS-A
to
74
Mute attenuation
VMUAC
Input impedance
ZIN
Cross talk between channel
CTSW
and selctors
71
to
VIN = 2Vrms, f = 1kHz,
BW = JIS-A
74
20log (VOUT/VIN)
80
71
to
VIN = 2Vrms, f = 1kHz
Rg = 0Ω, BW = JIS-A
74
Tuner gain
GTU
71
VIN = 0.5Vrms
to
74
Output off set voltage
VOFSET
71
Off set voltage at the time of
to
changeover SW.
74
Audio ADC block
Voltage gain 1
VGA1
78
79
VIN = 1Vrms, f = 1kHz,
EVR = 0dB
Serial control select 6dB.
Voltage gain 2
VGA2
78
79
VIN = 1Vrms, f = 1kHz,
EVR = 0dB
Serial control select 5.5dB.
Voltage gain 3
VGA3
78
79
VIN = 1Vrms, f = 1kHz,
EVR = 0dB
Serial control select 5dB.
Voltage gain 4
VGA4
78
79
VIN = 1Vrms, f = 1kHz,
EVR = 0dB
Serial control select 0dB.
Channel balance
CVVR
78
79
VIN = 2Vrms, f = 1kHz,
AMP = 5.5dB, AEVR = -12dB
Lch Gain-Rch Gain
Maximum output level
VOMAXI
78
ADC-OUT (L, R),
79
AMP = 0dB, EVR = 0dB
Vrms
BW = 400 to 30kHz
Output level at f = 1kHz,
THD = 1%
Total harmonic distortion
THDAI
78
79
VIN = 2Vrms, f = 1kHz,
AMP = 5.5dB, EVR = -12dB
0.002
0.005
%
BW = 400 to 30kHz
Note 2) When pin 10 is open
Continued on next page.
No.A1610-4/31
LV71081E
Continued from preceding page.
Parameter
Input signal
Symbol
Point
Output noise voltage
Cross talk between channel
VNAI
CTVR
and selctors
Signal
Out
Freq
min
78
AMP = 5.5dB, EVR = -12dB
79
Rg = 0Ω, BW = JIS-A
78
VIN = 2Vrms, f = 1kHz,
AMP = 5.5dB, EVR = -12dB
79
Ratings
Test condition
Point
typ
Unit
max
-100
-80
dBV
-110
-80
dB
-106
-85
dB
-106
-80
dBV
Rg = 0Ω, BW = JIS-A
Max attenuation amount
VMUAI
78
79
VIN = 2Vrms, f = 1kHz,
AMP = 5.5dB, BW = JIS-A
EVR = mute/EVR = 0dB
Residual noise voltage
VNAR
78
AMP = 5.5dB, EVR = mute
79
Rg = 0Ω, BW = JIS-A
External control part
I2C-BUS High level input
VIH
voltage
I2C-BUS Low level input
VIL
voltage
FSS output H voltage
88
2.5
VCC
V
GND
0.8
V
89
88
89
VHFSS
27
Serial control select FSS OUT
10.6
11.1
11.6
V
5.5
6.3
7.0
V
0.0
0.1
0.5
V
1.0
ms
3.0
4.0
5.0
V
0.0
0.2
0.4
V
0.0
0.5
V
1.0
3.0
V
H, load = 10kΩ
external output resistor 470
recommended
FSS output M voltage
VMFSS
27
Serial control select FSS OUT
M, load = 10kΩ
external output resistor 470
recommended
FSS output L voltage
VLFSS
27
Serial control select FSS OUT,
load = 10kΩ
FSS risinge time
TFSSLH
27
FB output H voltage
VHFB
34
Serial control select FB OUT
H. load = 150Ω
FB output L voltage
VLFB
34
Serial control select FB OUT L.
load = 150Ω
FB external control L range
VLFBIN
32
Pin 32 input voltage range at
which the pin 34 output
becomes L
FB external control H range
VHFBIN
32
Pin 32 input voltage range
when the pin 34 output
becomes H
External control output H
VEXTH
voltage
10
2kΩ load for data 1
4.0
4.5
5.0
V
2kΩ load for data 0
0.0
0.3
1.0
V
Pins 2 and 100 voltage
2.3
2.5
2.7
V
Pins 57 and 65 voltage
8.7
9.0
9.3
V
Pin 49 voltage
4.3
4.5
4.7
V
36
38
External control output L
VEXTL
voltage
10
36
38
Internal reference regulator
REG2.5V
VREG25
2
100
REG9.0V
VREG90
57
65
VRE4.5
VREG45
49
No.A1610-5/31
LV71081E
Package Dimensions
unit : mm (typ)
3349
23.2
0.8
20.0
80
51
50
100
31
14.0
17.2
81
1
30
0.65
0.15
0.22
3.0MAX
0.1 (2.7)
(0.58)
SANYO : QIP100EK(14X20)
VCC = 11.6V
46
Buffer
9VREG
AV3_R_IN
56 55
50
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
Rch input bias
57
VCR_R_IN
DAC_R_IN
Graphical View of Audio Block Power Supply
Input Buffer
R-ch
Buffer
Power supply standard
of each block
49
4.5VREF
Buffer
Mute
Canal output
12dB
AMP
Buffer
SW
R-ch
All 5V 42
SW
EVA standard
P.Mute
EVA
ADC
AMP
EVR output
ADC AMP standard
Buffer
12dBAMP standard
L-ch 12dB AMP
standard
65
9VREG
Buffer
R Mute Bias
L Mute Bias
REG_GND 66
L-ch
Buffer
L-ch Power supply of each block
No.A1610-6/31
LV71081E
Graphical View of The Video Block Power Supply
* The thick line indicates the circuit operative in the power save mode.
In the power save mode, 5V is applied to Pin 42 (VCC5_All), pin 84 (VCC5V_VSW), and pin 94 (VCC_LOGIC) only.
VCC5V_VD
6
INPUT
VCC5V_RGB
8
LPF
SW
AMP
DR
RGB system
GND_VD
4
GND_RGB
18
40
25
VCC5V_VC
VCC5V_VL
INPUT
LPF
SW
AMP
DR
Line-out
system
INPUT
LPF
SW
AMP
DR
Canal AV1/2
system
GND_VC
GND_VL
21
29
42
VCC5V_ALL
INPUT
SW
AMP
Recording system
VCC5V_VSW
84
Synchronous detection
GND_VSW
Synchronous detection
98
VCC11.6V
46
FB
Control
system
Output
stage
FSS
Control
system
Output
stage
VCC_LOGIC
94
Serial
96
Circuit operative in the P.S mode
GND_LOGIC
No.A1610-7/31
GND_AL
0.1μF
1μF
0.1μF
0.1μF
95 Clamp
/Bias
REG 2.5 0.01μF
Clamp
1
2
3
Clamp
0.1μF
Mute
8
Mute
VCC 5V_RGB
7
9
6dB
N.C.
6
75Ω
11
N.C.
10
bd f
ce
75Ω
12
6dB
5
a
SV13b
15
N.C.
14
N.C.
N.C.
13
EXT_CTL1
EXT
CTL1
16
a
SV12b
bd f
ce
75Ω
17
6dB
4
Clamp
a b c b f
e
SV11b
a b
SV17V
22
21
GND_VL
20
N.C.
19
SA1R
e d c b a
75Ω
SA3R
75Ω
27
FSS OUT
Serial
SV1
f
e
d
c
b
a
SV2
e
d
c
b
a
1.0μF
75Ω
29
SV1
REF
Dr
0.1μF
30
Clamp
Clamp
0.1μF AV3(Front)Y_IN
40 VCC5V_VC
41
34
31
32
AV1(16pin)FB_OUT
AV2(16pin)FB_IN
0.1μF AV2(20pin) V/Y_IN
75Ω
0.1μF AV1(20pin)V_IN
75Ω
0.1μF AV4(Rear)V_IN
36 EXT_CTL3
0.1μF AV3(Front)V_IN
0.1μF AV4(Rear)Y_IN
TUNER2 V IN
38 EXT_CTL4
Clamp 33
5V a
0V b
c
0.1μF AV4(Rear)C_IN
42 VCC ALL 5V
43
Clamp 35
EXT
CTL3
0.1μF AV3(Front)C_IN
44 GND_REF
45
Clamp 37
EXT
CTL4
0.1μF VCR Y_IN
0.1μF VCR C_IN
+
22μF REF 4.5V
1.0μF AV3(Front)R_IN
46 VCC 12V_A
47
48
49
50
Clamp 39
Clamp
Bias
Bias
Clamp
Bias
SA2R
e d c b a
28
SA4R
d c b a
75Ω
6dB
75Ω
SA18R
e d c b a
26
VCC 5V_VL
6dB
23
24
25
+
+
100μF 22μF
b a
SV14
N.C.
N.C.
18
SA2L
1.0μF
1.0μF
1.0μF
6dB
0.1μF 0.01μF 0.1μF
Bias
REG
Mute
SV16
SA4L
d c b a
SA3L
e d c b a
1.0μF
56
55
54
53
52
51
100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ
1.0μF
REG
57
Mute
100 REG1
Mute
0.1μF
6MHz
e d c b a
SA1L
Mute
a b
Clamp
/Bias
6MHz
6MHz
SV6
e d c b a
SV5
1.0μF
Mute
99
GND_VSW 98
0.1μF
6MHz
d c b a
SV3
d c b a
SV6
1.0μF
Mute
ENC. B/B-Y_IN
ENC. G/Y_IN
97 Clamp
/Bias
GND_LOGIC 96
ENC. R/R-Y_IN
Bias
Video signal
detection
93 Clamp 6MHz
92
VCC_LOGIC 94
ENC. Y_IN
ENC. C_IN
91
V_DET_OUT 90
SDA_IN 89
SCL_IN 88
A_ADC_R
Mute
V_DET_IN
0dB/
-12dB
Mute
87
A_ADC_L
SV4
Buf
86
N.C.
Mute
C_SYNC_OUT
Buf
a SV7
b
c d Mute
Buf
e d c b a
Mute
e d c b a
SA18L
12dB
6dB
/0dB
1.0μF
1.0μF
1.0μF
Mute
Slicer 85
LPF
1.0μF
Mute
0dB
GND_AR
12dB
VCC 5V_VSW 84
+
Buf
LPF
+
SYNC
SEP
+
64
63
62
61
60
59
58
100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ
100kΩ
Y/V_ADC 83
N.C.
LPF
N.C.
LPF
A_DAC_L_IN
1.0μF
VCR_L_IN
LPF
66
TUNER_AL_IN
REG
65
GND_REG
67
AV2(6pin)
L_IN
Mute Mute Mute Mute
REG 9V AL
68
AV1(6pin)
L_IN
69
AV4(Rear)L_IN
TUNER2 AL
70
RV3(Front)
L_IN
71
REG 9V AR
72
A_DAC_R_IN
73
VCR_R_IN
V_SYNC_OUT 82
ADC
AMP
0dB/
-12dB
ADC
AMP
+
74
AV2(1pin)
R_OUT
75
TUNER1 AR_IN
V-SYNC
SEP
77
AV2(2pin)
R_IN
0dB
76
N.C.
78
1kΩ
10μF
AV1(2pin)
R_IN
C_ADC 81
N.C.
79
AV2(3pin)
L_OUT
1kΩ
10μF
AV4(Rear)R_IN
Tuner2 AR IN
80
AV1(1pin)
R_OUT
1kΩ
10μF
AV1(3pin)
L_OUT
1kΩ
10μF
LV71081E
Block Diagram
GND_VC
Tuner V_IN
AV2(19pin)
V_OUT
AV1(8pin)
FSS_OUT
AV1(19pin)
V_OUT
GND-RGB
VCC 5V_VD
GND_VD
V_OUT
(Line_OUT)
AV1(11pin)
G_OUT
Audio_Mute_Filter
AV1(7pin)
B_OUT
SYNC_SEP_LPF
AV1(15pin)
R/C_OUT
AV2(7pin)
B_IN
AV2(11pin)
G_IN
REG 2.5
AV2(15pin)
R/C_IN
No.A1610-8/31
+
T89
T88
+
0.1μF
1μF
T99
T98
T97
T96
T95
T93
T92
T90
T86
T85
0.1μF
T100
0.1μF
0.1μF
0.1μF
0.01μF
75Ω
T99A
75Ω
T97A
75Ω
T95A
75Ω
T93A
75Ω
T91A
10kΩ
10kΩ
10kΩ
+
100μH
100μH
GND_AL
T83
A_ADC R_OUT
REG 2.5VA
AV2(15pin)
R/C_IN
75Ω
AV2(7pin)
B_OUT
T5A
75Ω
100μH
T7A
open
75Ω
100μH
T9A
open
75Ω
open
75Ω
open
75Ω
2kΩ
open
75Ω
11
12
13
14
15
T11 T12 T13 T14
+
+
330μF
100μF
75Ω
75Ω
75Ω
T11A T12A
T14A
B-Y_OUT
T3A
RF_OUT
AV1(7pin)
B_OUT
75Ω
VCC 5V_VD
EXT_CTL1
0.01μF
75Ω
+
GND_AR
75Ω
R-Y_OUT
Y_OUT
(Component)
T1A
+
AV2(3pin)
R_OUT
T17A
open
75Ω
75Ω
17
T17
1μF
16
NC
0.1μF
VCC 5V_RGB
Audio_Mute_Filter
0.1μF
AV2(1pin)
L_OUT
18
AV1(11pin)
G_OUT
0.1μF
AV1(15pin)
R/C_OUT
GND-RGB
10
AV1(3pin)
R_OUT
75Ω
open
75Ω
open
open open
75Ω
open
75Ω
open
100μH
5V +
open
50
REF 4.5V 49
51
T47
T40
T41
0.1μF 75Ω
T41A
open
T32
T33
T34
T35
T36
T37
AV1(20pin)
T31
V/Y_IN 31
AV2(16pin)FB_IN 32
AV1(20pin)V_IN 33
AV1(16pin)FB_OUT 34
AV4(Rear)V_IN 35
EXT_CTL3 36
AV3(Front)V_IN 37
0.1μF 75Ω
75Ω
T31A
0.1μF 75Ω
75Ω 75Ω
T33A
0.1μF 75Ω
T35A
0.1μF 75Ω
T35A
T39
T39A
AV4(Rear)Y_IN
39
Tuner2 V IN
0.1μF 75Ω
T38
EXT_CTL4 38
VCC5V_VC 40
AV3(Front)Y_IN 41
0.1μF 75Ω
T43A
0.1μF 75Ω
T45A
0.1μF 75Ω
0.1μF 75Ω
T47A
1kΩ
1μF
+
22μF
T48A
AV3(Front)R_IN
T50
+
T49
VCC5V_ALL 42
AV(Rear)C_IN 43
GND_REF 44
AV3(Front)C_IN 45
VCC11.6V_A 46
VCR Y_IN 47
19
20
21
22
23
24
25
26
27
28
29
30
T26 T27 T28 T29 T30
T19 T20
T22
T23 T24
+ 330μF +
+
+
+
0.1μF
75Ω 470Ω 75Ω
+
100μF 22μF
100μF 22μF
75Ω 75Ω
T26A
T28A
T30A
T22A
75Ω 75Ω
75Ω 75Ω
T20A
75Ω 10kΩ 75Ω
75Ω
75Ω 75Ω T24A
Y_OUT
(Line_OUT)
9
T9
SYNC_SEP_LPF
GND_YL
8
AV1(1pin)
L_OUT
C_OUT
(Line_OUT)
7
T7
NC
V_OUT
(Line_OUT)
6
NC
VCC 5V_VL
5
T5
NC
AV1(19pin)
V_OUT
2
T2
NC
AV1(8pin)
FSS_OUT
1
T1
100 REG 2.5V
99 ENC. B/B-Y_IN
98 GND_VSW
97 ENC. G/Y_IN
96 GND_LOGIC
95 ENC. R/R-Y_IN
94 VCC_LOGIC
93 ENC. Y_IN
92 V_DET_FIL
91 ENC. C_IN
90 V_DET_OUT
89 SDA_IN
88 SCL_IN
87 V_DET_IN
86 C_SYNC_OUT
85 Slicer_OUT
84 VCC 5V_VSW
GND_REG
VCR C_IN 48
REG 9V AL
AV2(19pin)
V_OUT
4
T4
+
83 DAC V/Y_OUT
A_DAG L_IN
GND_VC
3
T3
A_ADC L_OUT
82 V_SYNC_OUT
52
53
54
55
56
57
58
59
60
61
62
63
64
+
VCR L_IN
65
+
TUNER_AL_IN
66
+
AV2(6pin)
L_IN
67
+
AV1(6pin)
L_IN
68
+
RV4(Rear)L_IN
Tuner2 L IN
69
+
RV3(Front)
L_IN
70
+
REG 9V AR
71
+
A_DAC R_IN
72
+
VCR R_IN
73
+
Tuner1 R_IN
74
+
AV2(2pin)
R_IN
75
+
AV1(2pin)
R_IN
76
+
10kΩ
+
78
10μF 10μF 10μF 10μF
T73
T72
T71
1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ
1kΩ 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ
10μF
10μF
T64
T63
T62
T61
T60
T59
T58
T56
T55
T54
T53
T52
T51
T65
1μF
1μF
1μF
1μF
1μF
1μF 1μF
1μFT57
1μF
1μF
1μF
1μF 1μF
+
T82
77
GND_VD
AV2(11pin)
G_IN
79
T74
10kΩ 10kΩ 10kΩ 10kΩ
T73A T72A T71A
+
10kΩ
80
4.7μF
T74A
+
81
T76
10kΩ
+
T81
+
10μF 10μF
T78
T77
+
T79
T76A
1.5Meg
+
+
DAC C_OUT
10kΩ 10kΩ
T78A
22μF
AV4(Rear)R_IN
Tuner2 L IN
10kΩ
T79A
+
2kΩ
2kΩ
+ 100μH
47μF
+ 100μH
47μF
5V
+
+ 100μH 11.6V
47μF
LV71081E
Test Circuit
Ttuner1 V_IN
No.A1610-9/31
LV71081E
Cautions for Use
1. Drive capacity of video driver
Line and component outputs can drive two system through capacitive coupling.
Scart output can drive one system only through DC coupling.
2. Application not using the SAG correction function in the video driver with SAG correction
When the SAG correction function is not to be used in the video driver with SAG correction, short-circuit output and
correction pins for output through capacitive coupling.
Application using SAG correction function
Video output pin
+
75Ω
Application without using SAG correction function
Video output pin
100μF
SAG correction pin
+
+
75Ω
1000μF
75Ω
SAG correction pin
75Ω
22μF
3. Treatment of the pin when Audio RF_MOD output is not used
When RF MOD OUT (Pin76) is not used, it is recommended to pull up the ALC filter pin (pin77) to VCC (11.6V).
4. Audio Mute
This IC incorporates a mute transistor to reduce the POP noise of audio output when power is turned ON/OFF.
Mute control can be made by serial control.
5. Resistor to limit the Audio input
When the large signal is input in the input pin with power OFF, cross-talk between input and output occurs through the
protective diode and parasitic elements. Because of the structure of LSI, such cross-talk is difficult to avoid. If
cross-talk at a time of power OFF presents a problem, the cross-talk amount can be reduced by inserting the limiting
resistor in the input. In this case, the input signal level changes depending on the resistance value. Determine the
constant while taking both the cross-talk amount and input level into account.
6. Pin treatment when external control is not to be used
When external control pins (Pins 13, 36, and 38) are not used, pull-down to GND is recommended.
7. Pin treatment of N.C pin
It is recommended to connect N.C. pins (Pins 67, 68, 69, and 70) directly to the GND.
8. Audio 9V_REG pin external capacitance
Use the Audio 9V_REG pins (pins 57 and 66) external capacitance of 10μF or more and with the equivalent series
resistance component of 7Ω or less.
9. Power application and disconnection sequences
The recommended power application sequence to this IC is VCC_ALL5V (Pin42) → VCC5V (Pins 6, 8, 25, 40, 84 and
94), VCC11.6V (Pin46).
(No particular order is established between VCC5V and VCC11.6V.) It is recommended to reverse the above sequence
when power supply is turned OFF.
No.A1610-10/31
LV71081E
Serial Control Table
ADDRESS
8
* indicates initial.
7
6
5
4
3
2
1
SV1
Group 1
0
0
0
V (AV2)
0
0
1
Y+C MIX (ENC)
*
PB
0
1
0
Y (ENC)
PB (SCART Y/C)
0
1
1
Y (VCR)
PB (VCR SCART Y/C)
1
0
0
CV (VCR)
PB (VCR)
1
0
1
MUTE
1
1
*
PROHIBIT
SV2
SV2
00000001
VIDEO
CANAL-SW
VIDEO
0
0
0
V (AV1)
0
0
1
V (TU)
0
1
0
Y+C MIX (ENC)
PB
0
1
1
CV (VCR)
PB (VCR)
1
0
0
1
0
1
*
MUTE
and after
PROHIBIT
SV3
SV3
ADDRESS
Remarks
SV1
0
0
V (AV1)
0
1
V (AV2)
1
0
V (TU)
1
1
Y (VCR)
8
7
6
5
4
3
2
1
0
0
0
1
V (AV4)
1
0
SV3-OUT
1
1
SV5/6 MIX
SV4
*
PB
Remarks
SV4
SV5/6
V (AV3)
*
SV5
SV6
0
0
0
Y (AV3)
C (AV3)
0
0
1
Y (AV4)
C (AV4)
REAR
0
1
0
Y (AV2)
C (AV2)
SCART-YC
00000010
0
1
1
Y (VCR)
C (VCR)
VIDEO
1
0
0
INPUT-SW
1
0
1 and after
Group 2
SV7
MUTE
PROHIBIT
*
SV7
0
0
Y
0
1
CV
1
0
MUTE
1
1
MUTE
SV16
Note 1)
MUTE
PROHIBIT
FRONT
*
SV16
0
THROUGH
1
CLAMP input fixed
*
Note 1) G2D8/G3D8 = “11” is prohibited. Follow the AV2 (16) FB_IN (Pin32) control in case of THROUGH.
AV2_16pin SV16
H a : Clamp input (RGB)
L b : Bias input (COMPONENT)
No.A1610-11/31
LV71081E
ADDRESS
8
7
6
5
4
3
2
1
Remarks
0
x = 12MHz
1
x = 27MHz
12/27MHz
LPF SW
RGB output
SV11b
0
1
SV12b
*
SV13b
According to G3D3/D4/D5 control
AV2_R
AV2_G
AV2_B
f : AV2_RGB (EXTERNAL)
*
N/A
Group 3
SV11b
00000011
SV12b
VIDEO
SV13b
OTHER-1
* effective at
G3D2 = “0”
SV14
0
0
0
N/A
N/A
N/A
0
0
1
N/A
N/A
N/A
0
1
0
N/A
N/A
N/A
0
1
1
N/A
N/A
N/A
1
0
0
N/A
N/A
N/A
1
0
1
N/A
N/A
N/A
1
1
0 and after
PROHIBIT
PROHIBIT
PROHIBIT
SV11b
SV12b
SV13b
ENC_R
ENC_G
ENC_B
*
0
0
0
a : ENC_RGB (6MLPF)
0
0
1
MUTE
MUTE
MUTE
b : mute
0
1
0
ENC_C
MUTE
MUTE
c : ENC_C
0
1
1
VCR_C
MUTE
MUTE
d : VCR_C
1
0
0
MUTE
MUTE
MUTE
e : mute
1
0
1
AV2_R
AV2_G
AV2_B
f : AV2_RGB (EXTERNAL)
1
1
0 and after
PROHIBIT
PROHIBIT
PROHIBIT
*
SV14
0
CV (PB)
1
MUTE
PB
*
N/A
0
N/A
N/A
1
MUTE
MUTE
SV16
Note 1)
*
SV16
0
THROUGH
1
BIAS input fixed
*
Note 1) G2D8/G3D8 = “11” is prohibited. Follow the AV2 (16) FB_IN (Pin32) control in case of THROUGH.
AV2_16pin SV16
H a : Clamp input (RGB)
L b : Bias input (COMPONENT)
No.A1610-12/31
LV71081E
ADDRESS
8
7
6
5
4
3
2
1
SV17
Remarks
SV17 (V/C/Y)
SA17 (L/R)
DVD/VCR
0
Y+C MIX (ENC)
AUDIO (DAC)
PB (DVD)
Note 2)
1
Y+C MIX (VCR)
AUDIO (VCR)
PB (VCR)
SV18
SA18 (L/R)
SV18
TUNER1/2
0
Tuner1
Tuner1
Note 2)
1
Tuner2
Tuner2
FB
*
SWF
AV1 (16)
0
0
0
Group 4
0
1
5V
00000100
1
0
THROUGH
VIDEO
1
1
THROUGH
&
FSS
AUDIO
AV1 (8)
0
0
LOW (0.5V)
OTHER-1
Note 3)
0
1
MID (6.0V)
1
0
HIGH (11.0V)
1
1
*
FSS-OUT
*
HIGH (11.0V)
SLICE AMP
SLICE AMP gain
0
0dB
1
*
6dB
A-MUTE
Note 4)
*
All MUTE (Audio)
0
THROUGH
1
MUTE
Pins 71 to 74 output MUTE
*
Note 2) Operates in VIDEO/AUDIO interlock.
Note 3) Same polarity as the AV2 (16) FB_IN (Pin32) control in case of THROUGH.
Note 4) AUDIO MUTE control
RF_MOD output : Serial control MUTE, Power-ON_MUTE
CANAL output : Serial control MUTE, Power-ON_MUTE
ADDRESS
8
7
6
5
4
3
2
1
SA1L/R
Remarks
SA1L
and after
0
0
0
L (AV2)
R (AV2)
0
0
1
L (DAC)
R (DAC)
00000101
AUDIO
CANAL-SW
SA4L/R
*
PB (DAC)
0
1
0
L (DAC)
R (DAC)
PB (DAC)
0
1
1
L (VCR)
R (VCR)
PB (VCR)
1
0
0
MUTE
MUTE
1
0
1
PROHIBIT
PROHIBIT
SA2L/R
Group 5
SA1R
SA2L
SA2R
L (AV1)
R (AV1)
0
0
0
0
0
1
L (TU)
R (TU)
0
1
0
L (DAC)
R (DAC)
PB
0
1
1
L (VCR)
R (VCR)
PB
1
0
0
1
0
1
and after
MUTE
MUTE
PROHIBIT
PROHIBIT
SA4L
SA4R
L (AV3)
R (AV3)
0
0
0
1
L (AV4)
R (AV4)
1
0
SL3 out
SR3 out
1
1
MUTE
MUTE
*
*
No.A1610-13/31
LV71081E
ADDRESS
8
7
6
5
4
3
2
1
SA3L/R
and after
Remarks
SA3L
SA3R
0
0
0
L (AV1)
R (AV1)
0
0
1
L (AV2)
R (AV2)
0
1
0
L (TU)
R (TU)
0
1
1
L (DAC)
R (DAC)
1
0
0
L (VCR)
R (VCR)
1
0
1
PROHIBIT
PROHIBIT
*
PB
N/A
Group 6
00000110
AUDIO
INPUT-SW
0
N/A
1
N/A
MUTE
0
0
N/A
0
1
N/A
1
0
N/A
1
1
PROHIBIT
ADDRESS
0
0
6.0dB
0
1
5.5dB
1
0
5.0dB
1
1
PROHIBIT
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0dB
0
0
1
1
0
0
-12dB
1
1
1
1
1
1
Mute
AUDIO
Other than above
General
00000111
purpose 1
0
General purpose OUT1
H
*
G/Y_IN
B/B-Y_IN
Input changeover
(Pin95)
(Pin97)
(Pin99)
0
BIAS input
CLAMP input
BIAS input
Component
1
CLAMP input
CLAMP input
CLAMP input
RGB
8
7
6
5
4
3
2
1
AUDIO
*
Remarks
Audio EVR (R)
EVR-R
0
0
0
0
0
0
0dB
0
0
1
1
0
0
-12dB
1
1
1
1
1
1
Other than above
General
Mute
Pin 79 output MUTE
*
General purpose OUT3
*
General purpose OUT4
*
PROHIBIT
EXT_CTL3 (Pin36)
purpose 3
0
L
1
H
EXT_CTL4 (Pin38)
General
purpose 4
*
PROHIBIT
R/R-Y_IN
VIDEO input
Group 8
Pin 78 output MUTE
L
1
ADDRESS
Remarks
EXT_CTL1 (Pin13)
Changeover of
BIAS/CLAMP
*
Audio EVR (L)
EVR-L
Group 7
*
ADC-AMP-gain
ADC-AMP
00001000
*
N/A
0
L
1
H
No.A1610-14/31
LV71081E
Serial Control Specification
1. Slave address
LSB
MSB
1
0
0
1
0
1
0
0
Slave receiver
One-way communication (this IC is dedicated to receive)
2. DATA TRANSFER MANUAL : [1] is High level. [0] is Low level.
I2C-BUS control system is adopted in SW LSI. SW LSI is controlled by SCL (Serial Clock) and SDA (Serial Data) At
first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data,
which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data
transfer order (MSB→LSB). The 9th bit is called as ACK (Acknowledge), SW LSI sends [0] to the SDA terminal
during SCL [1] period. So, please open the port of microprocessor during this period. LV71081E adopt auto-increment,
so you input only first group-address and you can transfer data in order. As thus the Data transfer Stop condition*2 is
finished.
*1
SDA rise up during SCI is [1]
*2
SDA fall down during SCL is [1]
3. TRANSFER DATA FORMAT
The transfer data is composed by START condition, Slave address, Group address*1, data, and STOP condition.
After setting up the START condition, please transfer the Slave Address (regulated as “1001000” in SW LSI). Group
and next control data*2 (Please see the Fig.1)
Slave Address is composed by 7bits, and this bit 8th bit*3 should be set as [0].
The both of Group address and control data are composed by 8bits, and the one control action is defined with
combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by
sending some control data together.
The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over.
But LV71081E adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data.
If you want to stop transfer action, please transfer the STOP condition without fail.
*1/2
There are 8 control groups.
*3
This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept
mode with SW LSI) and [1] means accept mode (send mode with SW LSI) fundamentally. But SW LSI is not
equipped with such a data out function, please keep this bit as [0].
Fig. 1 DATA STRUCTURE
START condition
Start condition
Slave address
R/W ACK Group address
Acknowledge
ACK
Control data
ACK .....
STOP condition
Stop condition
No.A1610-15/31
LV71081E
4. INITIALIZE AND OTHERS
SW LSI is initialized as the following mode for circuit protection. Please see “SERIAL CONTROL TABLE”.
Characteristics of the SDA and SCL 1/0 stages for SW LSI
Parameter
Symbol
Min
Max
Unit
LOW level input voltage
VIL
0
0.8
V
HIGH level input voltage
VIH
3.0
5.0
V
LOW level output current
IOL
3.0
mA
SCL clock frequency
fSCL
400
kHz
Set-up time for a repeated START condition
tSU : STA
Hold time START condition. After this period, the first clock pulse is generated.
LOW period of the SCL clock
Rise time of both SDA and SDL signals
tR
0.6
μs
tHD : STA
0.6
μs
tLOW
1.3
0
μs
0.3
μs
μs
HIGH period of the SCL clock
tHIGH
Fall time of both SDA and SDL signals
tF
0.6
0
0.3
μs
Data hold time:
tHD : DAT
0
0.9
μs
Data set-up time
tSU : DAT
100
ns
Set-up time for STOP condition
tSU : STO
0.6
μs
BUS fredd time between a STOP and START condition
tBUF
1.3
μs
Fig.2 Definition of timing.
tHIGH
tR
tF
SCL (86pin)
tSU:STA
tHD:STA
tLOW
tHD:DAT
tSU:DAT
tSU:STO
tBUF
SDA (87pin)
No.A1610-16/31
LV71081E
Pin Function
Pin No.
Pin name
P1
AV2R/C_IN
DC voltage
Signal wave form
In put/Out put form
1.6V R
1kΩ
0.7Vp-p
4kΩ
1.6V
4kΩ
2.1V Chroma
20kΩ
300Ω
300Ω
0.7Vp-p 2.1V
1
P2
REG 2.5VA
2.5V
DC
10pF
50Ω
1kΩ
100Ω
2
6.8kΩ
22.8kΩ
13kΩ
30kΩ
P3
AV2 G_IN
18.5kΩ 18.5kΩ
910Ω
23kΩ
1.6V G
1kΩ
4kΩ
0.7Vp-p
4kΩ
300Ω
1.6V
300Ω
3
P4
GND_VD
P5
AV2 B_IN
1.6V B
1kΩ
4kΩ
0.7Vp-p
1.6V
4kΩ
300Ω
300Ω
5
P6
VCC 5V_VD
P7
N.C.
P8
VCC 5V_RGB
Continued on next page.
No.A1610-17/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P9
AV1 R/C_OUT
DC voltage
Signal wave form
In put/Out put form
0.5V R
1.4Vp-p
100Ω
0.5V
1.25pF
2kΩ 10.7kΩ
200Ω
9
3.3pF
1.7V Chroma
10kΩ
1.25pF
1.4Vp-p 1.7V
P10
SYNC_SEP_LPF
1.0V Y
10
500Ω
1.0Vp-p
500Ω
2.2V
40kΩ
8pF
P11
N.C.
P12
AV1 B_OUT
0.5V B
100Ω
1.4Vp-p
200Ω
12
3.3pF
0.5V
P13
1.25pF
2kΩ 10.7kΩ
10kΩ
1.25pF
EXT_CTL1
5V
13
0V
P14
N.C.
P15
N.C.
P16
Audio_Mute_
Filter
140kΩ
16
500Ω
60kΩ
Continued on next page.
No.A1610-18/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P17
AV1 G_OUT
DC voltage
Signal wave form
In put/Out put form
0.5V G
100Ω
1.4Vp-p
1.25pF
2kΩ 10.7kΩ
0.5V
P18
GND_RGB
P19
N.C.
P20
N.C.
P21
GND_VL
P22
N.C.
P23
V_OUT
V_SAG_IN
17
1.25pF
24
2.0Vp-p
0.7V
P24
10kΩ
0.7V Video
(Line_OUT)
200Ω
3.3pF
100Ω 2kΩ
0.7V Video
10kΩ
3pF
(Line_OUT)
3pF
10.4kΩ
2.0Vp-p
1kΩ
100Ω
23
3pF
100kΩ
0.7V
P25
VCC 5V_VL
P26
AV1 V_OUT
0.5V Video
2.0Vp-p
100Ω
1.25pF
2kΩ 10.7kΩ
0.5V
200Ω
26
3.3pF
0.5V Y
10kΩ
2.0Vp-p
1.25pF
0.5V
P27
AV1 FSS_OUT
Low : 0.5V
DC
Midol : 6.0V
High : 11.1V
27
100kΩ
P28
AV2 V_OUT
0.5V Video
100Ω
1.25pF
2kΩ 10.7kΩ
2.0Vp-p
200Ω
3.3pF
0.5V
P29
10kΩ
28
1.25pF
GND_VC
Continued on next page.
No.A1610-19/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P30
Tuner1 V_IN
DC voltage
Signal wave form
In put/Out put form
1.6V Video
1kΩ
4kΩ
1.0Vp-p
4kΩ
300Ω
300Ω
1.6V
30
P31
AV2 V/Y_IN
1.6V Video
1.0Vp-p
1kΩ
4kΩ
1.6V
4kΩ
300Ω
1.6V Y
300Ω
1.0Vp-p
1.6V
P32
31
AV2 FB_IN
2V
32
1kΩ
0V
P33
AV1 V_IN
1.6V Video
1kΩ
4kΩ
1.0Vp-p
4kΩ
300Ω
300Ω
1.6V
33
P34
AV1 FB_OUT
L : 0V
H : 3.8V
10Ω
Through :0/3.8V
3.8V
1kΩ
1kΩ
34
100kΩ
0V
1kΩ 1kΩ
Continued on next page.
No.A1610-20/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P35
AV4 V_IN
DC voltage
Signal wave form
In put/Out put form
1.6V Video
1kΩ
4kΩ
1.0Vp-p
4kΩ
300Ω
300Ω
1.6V
35
P36
EXT_CTL3
5V
36
0V
P37
AV3 V_IN
1.6V Video
1kΩ
4kΩ
1.0Vp-p
4kΩ
300Ω
300Ω
1.6V
37
P38
EXT_CTL4
5V
38
0V
P39
AV4 Y_IN/
1.6V Y
Tuner2 V_IN
1.0Vp-p
1kΩ
4kΩ
1.6V
4kΩ
300Ω
1.6V Video
300Ω
1.0Vp-p
1.6V
P40
39
VCC 5V_VC
Continued on next page.
No.A1610-21/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P41
AV3 Y_IN
DC voltage
Signal wave form
In put/Out put form
1.6V Y
1kΩ
4kΩ
4kΩ
1.0Vp-p
300Ω
300Ω
1.6V
41
P42
VCC 5V_ALL
P43
AV4 C_IN
5V
DC
2.1V Chroma
1kΩ
4kΩ
0.7Vp-p 2.1V
20.3kΩ
300Ω
43
P44
GND_REF
0V
P45
AV3 C_IN
2.1V Chroma
DC
1kΩ
4kΩ
0.7Vp-p 2.1V
20.3kΩ
300Ω
45
P46
VCC 11.6V_A
11.6V
P47
VCR Y_IN
1.6 Y
DC
1kΩ
4kΩ
4kΩ
1.0Vp-p
300Ω
300Ω
1.6V
47
P48
VCR C_IN
2.1V Chroma
1kΩ
0.7Vp-p 2.1V
4kΩ
20.3kΩ
300Ω
48
Continued on next page.
No.A1610-22/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P49
REF 4.5V
DC voltage
Signal wave form
In put/Out put form
4.5V
57
60kΩ
1kΩ
49
60kΩ
P50
AV3 R_IN
4.5V
4.5V
Max
5.6Vp-p
50
500Ω
100kΩ
4.5V
P51
AV4 R_IN/
4.5V
Tuner2 R_IN
4.5V
Max
5.6Vp-p
51
500Ω
100kΩ
4.5V
P52
AV1 R_IN
4.5V
4.5V
Max
5.6Vp-p
52
500Ω
100kΩ
4.5V
P53
AV2 R_IN
4.5V
4.5V
Max
5.6Vp-p
53
500Ω
100kΩ
4.5V
Continued on next page.
No.A1610-23/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P54
Tuner1 R_IN
DC voltage
Signal wave form
In put/Out put form
4.5V
4.5V
Max
5.6Vp-p
54
500Ω
100kΩ
4.5V
P55
VCR R_IN
4.5V
4.5V
Max
5.6Vp-p
55
500Ω
100kΩ
4.5V
P56
A_DAC R_IN
4.5V
4.5V
Max
5.6Vp-p
56
500Ω
100kΩ
4.5V
P57
REG 9V AR
9V
DC
50Ω
57
100Ω
141kΩ
23kΩ
P58
AV3 L_IN
4.5V
4.5V
Max
5.6Vp-p
58
500Ω
100kΩ
4.5V
Continued on next page.
No.A1610-24/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P59
AV4 L_IN/
DC voltage
Signal wave form
In put/Out put form
4.5V
Tuner2 L_IN
4.5V
Max
5.6Vp-p
59
500Ω
100kΩ
4.5V
P60
AV1 L_IN
4.5V
4.5V
Max
5.6Vp-p
60
500Ω
100kΩ
4.5V
P61
AV2 L_IN
4.5V
4.5V
Max
5.6Vp-p
61
500Ω
100kΩ
4.5V
P62
Tuner1 L_IN
4.5V
4.5V
Max
5.6Vp-p
62
500Ω
100kΩ
4.5V
P63
VCR L_IN
4.5V
4.5V
Max
5.6Vp-p
63
500Ω
100kΩ
4.5V
P64
A_DAC L_IN
4.5V
4.5V
Max
5.6Vp-p
64
500Ω
100kΩ
4.5V
Continued on next page.
No.A1610-25/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P65
REG 9V AL
DC voltage
9V
Signal wave form
In put/Out put form
DC
50Ω
65
100Ω
141kΩ
23kΩ
P66
GND_REG
P67
N.C.
P68
N.C.
P69
N.C.
P70
N.C.
P71
AV1 L_OUT
0V
DC
4.5V
4.5V
Max
5.6Vp-p
700Ω
100Ω
700Ω
100Ω
700Ω
100Ω
71
20kΩ
4.5V
P72
AV1 R_OUT
4.5V
4.5V
Max
5.6Vp-p
72
20kΩ
4.5V
P73
AV2 L_OUT
4.5V
4.5V
Max
5.6Vp-p
73
20kΩ
4.5V
Continued on next page.
No.A1610-26/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P74
AV2 R_OUT
DC voltage
Signal wave form
In put/Out put form
4.5V
4.5V
Max
5.6Vp-p
700Ω
100Ω
74
20kΩ
4.5V
P75
GND_AR
P76
N.C.
P77
N.C.
P78
A_DAC L_OUT
P79
A_DAC R_OUT
P80
GND_AL
P81
DAC C_OUT
0V
DC
4.5V
4.5V
Max
5.6Vp-p
100Ω
4.5V
Max
5.6Vp-p
100Ω
78
4.5V
79
2.1V
500Ω
0.7Vp-p 2.1V
81
500μA
P82
V_SYNC_OUT
4.7V
300Ω
82
0.3V
300Ω
Continued on next page.
No.A1610-27/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P83
DAC V/Y_OUT
DC voltage
Signal wave form
In put/Out put form
1.0V Y
500Ω
1.0Vp-p
1.0V
1.0V Video
83
1.0Vp-p
500μA
1.0V
P84
VCC 5V_VSW
P85
Slicer_OUT
1.0V Y
Max
2.0Vp-p
or
1.0Vp-p
1.0V
500Ω
1.0V Video
85
Max
2.0Vp-p
or
1.0Vp-p
500μA
1.0V
P86
C_CYNC_OUT
4.7V
300Ω
86
300Ω
0.3V
P87
V_DET_IN
87
4.7V
10kΩ
0.3V
25kΩ
P88
50μA
SCL_IN
50kΩ
5V
2.3V
88
1.0V
30kΩ
Continued on next page.
No.A1610-28/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P89
SDL_IN
DC voltage
Signal wave form
In put/Out put form
50kΩ
5V
2.3V
89
1.0V
30kΩ
P90
V_DET_OUT
4.7V with signal
DC
0V without signal
300Ω
90
300Ω
P91
ENC. C_IN
2.1V Chroma
1kΩ
4kΩ
0.7Vp-p 2.1V
20.3kΩ
300Ω
91
P92
V_DET_FIL
DC
92
200Ω
1kΩ
1kΩ
1kΩ
60μA
P93
ENC. Y_IN
1.6V Y
1kΩ
4kΩ
1.0Vp-p
1.6V
4kΩ
300Ω
300Ω
93
P94
VCC_LOGIC
Continued on next page.
No.A1610-29/31
LV71081E
Continued from preceding page.
Pin No.
Pin name
P95
ENC. R/
DC voltage
Signal wave form
In put/Out put form
1.6V R
R-Y_IN
1kΩ
0.7Vp-p
4kΩ
1.6V
4kΩ
2.1V R-Y
20kΩ
0.7Vp-p
2.1V
60μA
P96
GND_LOGIC
P97
ENC. G/Y_IN
300Ω
300Ω
95
1.6V G
1kΩ
0.7Vp-p
4kΩ
1.6V
4kΩ
1.6V Y
300Ω
300Ω
1.0Vp-p
1.6V
P98
GND_VSW
P99
ENC. B/
97
1.6V B
B-Y_IN
1kΩ
0.7Vp-p
4kΩ
1.6V
4kΩ
2.1V B-Y
20kΩ
2.1V
300Ω
300Ω
0.7Vp-p
99
P100
REG 2.5V
2.5V
DC
10pF
50Ω
1kΩ
100Ω
100
6.8kΩ
13kΩ
30kΩ
18.5kΩ
910Ω
18.5kΩ
22.8kΩ
23kΩ
No.A1610-30/31
LV71081E
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of September, 2010. Specifications and information herein are subject
to change without notice.
PS No.A1610-31/31