STMICROELECTRONICS M27V256

M27V256
256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM
■
LOW VOLTAGE READ OPERATION:
3V to 3.6V
■
FAST ACCESS TIME: 90ns
■
LOW POWER CONSUMPTION:
– Active Current 10mA at 5MHz
28
28
– Standby Current 10µA
■
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
1
1
■
PROGRAMMING TIME: 100µs/byte (typical)
FDIP28W (F)
PDIP28 (B)
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 8Dh
DESCRIPTION
The M27V256 is a low voltage 256 Kbit EPROM
offered in the two ranges UV (ultra violet erase)
and OTP (one time programmable). It is ideally
suited for microprocessor systems and is organized as 32,768 by 8 bits.
The M27V256 operates in the read mode with a
supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
Table 1. Signal Names
A0-A14
Address Inputs
Q0-Q7
Data Outputs
E
Chip Enable
G
Output Enable
VPP
Program Supply
VCC
Supply Voltage
VSS
Ground
PLCC32 (K)
TSOP28 (N)
8 x 13.4mm
Figure 1. Logic Diagram
VCC
VPP
15
8
A0-A14
E
Q0-Q7
M27V256
G
May 1998
VSS
AI01908
1/15
M27V256
AI01909
1 32
A6
A5
A4
A3
A2
A1
A0
NC
Q0
9
M27V256
25
A8
A9
A11
NC
G
A10
E
Q7
Q6
17
VSS
DU
Q3
Q4
Q5
VCC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3
1
28
2
27
3
26
4
25
5
24
6
23
7
22
M27V256
8
21
9
20
10
19
11
18
12
17
13
16
14
15
A7
A12
VPP
DU
VCC
A14
A13
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
Figure 2B. LCC Pin Connections
Q1
Q2
Figure 2A. DIP Pin Connections
AI01910
Warning: NC = Not Connected, DU = Dont’t Use.
Figure 2C. TSOP Pin Connections
G
A11
A9
A8
A13
A14
VCC
VPP
A12
A7
A6
A5
A4
A3
22
28
1
7
21
M27V256
15
14
8
AI01911
2/15
For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
DEVICE OPERATION
The modes of operation of the M27V256 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic
Signature.
Read Mode
The M27V256 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after delay
of t GLQV from the falling edge of G, assuming that
E has been low and the addresses have been stable for at least tAVQV-tGLQV.
M27V256
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature (3)
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage (except A9)
–2 to 7
V
Supply Voltage
–2 to 7
V
–2 to 13.5
V
–2 to 14
V
TA
VCC
VA9 (2)
A9 Voltage
Program Supply Voltage
VPP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
E
G
A9
VPP
Q0-Q7
Read
V IL
VIL
X
VCC
Data Out
Output Disable
V IL
VIH
X
VCC
Hi-Z
VIL Pulse
VIH
X
VPP
Data In
Verify
VIH
VIL
X
VPP
Data Out
Program Inhibit
VIH
VIH
X
VPP
Hi-Z
Standby
VIH
X
X
VCC
Hi-Z
Electronic Signature
V IL
VIL
VID
VCC
Codes
Mode
Program
Note: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
VIL
0
0
1
0
0
0
0
0
20h
Device Code
VIH
1
0
0
0
1
1
0
1
8Dh
Standby Mode
The M27V256 has a standby mode which reduces
the supply current from 10mA to 10µA with low
voltage operation VCC ≤ 3.6V, see Read Mode DC
Characteristics table for details. The M27V256 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
3/15
M27V256
Table 5. AC Measurement Conditions
High Speed
Standard
Input Rise and Fall Times
≤ 10ns
≤ 20ns
Input Pulse Voltages
0 to 3V
0.4V to 2.4V
1.5V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
Standard
2.4V
OUT
CL
2.0V
0.8V
0.4V
AI01822
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol
C IN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condit ion
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: Sampled only, not 100% tested.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
4/15
system control bus. This ensures that all deselected memory devices are in their low power standby
mode and hat the output pins are only active when
data is desired from a particular memory device.
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, I CC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output.
M27V256
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ V CC
±10
µA
0V ≤ VOUT ≤ VCC
±10
µA
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, V CC ≤ 3.6V
10
mA
E = VIH
1
mA
E > VCC – 0.2V, VCC ≤ 3.6V
10
µA
VPP = VCC
10
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
IPP
Program Current
VIL
Input Low Voltage
–0.3
0.8
V
VIH (2)
Input High Voltage
2
VCC + 1
V
VOL
Output Low Voltage
0.4
V
VOH
IOL = 2.1mA
Output High Voltage TTL
IOH = –400µA
2.4
V
Output High Voltage CMOS
IOH = –100µA
Vcc – 0.7V
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85°; VCC = 3.3V ± 10%; VPP = VCC)
M27V256
Symbol
Alt
Parameter
-90 (3)
Test Condition
Min
tAVQV
tACC
Address Valid to Output Valid
tELQV
tCE
tGLQV
Max
Unit
-100
Min
Max
E = VIL, G = VIL
90
100
ns
Chip Enable Low to Output Valid
G = VIL
90
100
ns
tOE
Output Enable Low to Output Valid
E = VIL
40
45
ns
tEHQZ (2)
tDF
Chip Enable High to Output Hi-Z
G = VIL
0
25
0
30
ns
tGHQZ (2)
tDF
Output Enable High to Output Hi-Z
E = VIL
0
25
0
30
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
0
0
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
M27V256
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70°C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = Vcc)
M27V256
Symbol
Alt
Parameter
Test Condition
-120
Min
tAVQV
tACC Address Valid to Output Valid
tELQV
tCE
tGLQV
-150
Max
Min
Unit
-200
Max
Min
Max
E = VIL , G = VIL
120
150
200
ns
Chip Enable Low to Output
Valid
G = VIL
120
150
200
ns
tOE
Output Enable Low to Output
Valid
E = VIL
45
50
60
ns
tEHQZ (2)
tDF
Chip Enable High to Output
Hi-Z
G = VIL
0
35
0
40
0
50
ns
tGHQZ (2)
tDF
Output Enable High to Output
Hi-Z
E = VIL
0
35
0
40
0
50
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
0
0
0
ns
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
A0-A14
VALID
tAVQV
VALID
tAXQX
E
tGLQV
tEHQZ
G
tELQV
Q0-Q7
tGHQZ
Hi-Z
AI00758B
Programming
The M27V256 has been designed to be fully compatible with the M27C256B and has the same
electronic signature. As a result the M27V256 can
be programmed as the M27C256B on the same
programming equipments applying 12.75V on VPP
and 6.25V on VCC by the use of the same PRESTO II algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V256
are in the ’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations.
6/15
Although only ’0’s will be programmed, both ’1’s
and ’0’s can be present in the data word. The only
way to change a ’0’ to a ’1’ is by die exposition to
ultraviolet light (UV EPROM). The M27V256 is in
the programming mode when VPP input is at
12.75V, G is at VIH and E is pulsed to VIL. The data
to be programmed is applied to 8 bits in parallel to
the data output pins. The levels required for the
address and data inputs are TTL. VCC is specified
to be 6.25 V ± 0.25 V.
M27V256
Table 9. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol
Parameter
Test Condition
ILI
Input Leakage Current
VIL ≤ VIN ≤ VIH
ICC
Supply Current
IPP
Program Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1mA
VOH
Output High Voltage TTL
IOH = –1mA
VID
A9 Voltage
Min
Max
Unit
±10
µA
50
mA
50
mA
–0.3
0.8
V
2
VCC + 0.5
V
0.4
V
E = VIL
3.6
V
11.5
12.5
V
Note: VCC must be applied simultaneously with or before V PP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V
Symbol
Alt
Parameter
Test Condition
Min
Max
tAVEL
tAS
Address Valid to Chip Enable Low
2
µs
tQVEL
tDS
Input Valid to Chip Enable Low
2
µs
tVPHEL
tVPS
VPP High to Chip Enable Low
2
µs
t VCHEL
tVCS
VCC High to Chip Enable Low
2
µs
tELEH
tPW
Chip Enable Program Pulse Width
95
tEHQX
tDH
Chip Enable High to Input Transition
2
µs
tQXGL
tOES
Input Transition to Output Enable Low
2
µs
tGLQV
tOE
Output Enable Low to Output Valid
tGHQZ
tDFP
Output Enable High to Output Hi-Z
0
tGHAX
tAH
Output Enable High to Address
Transition
0
105
Unit
µs
100
ns
130
ns
ns
Note: VCC must be applied simultaneously with or before V PP and removed simultaneously or after VPP.
7/15
M27V256
Figure 6. rogramming and Verify Modes AC Waveforms
VALID
A0-A14
tAVEL
Q0-Q7
DATA IN
tQVEL
DATA OUT
tEHQX
VPP
tGLQV
tVPHEL
tGHQZ
VCC
tVCHEL
tGHAX
E
tELEH
tQXGL
G
PROGRAM
VERIFY
AI00759
Figure 7. Programming Flowchart
VCC = 6.25V, VPP = 12.75V
n=0
E = 100µs Pulse
NO
++n
= 25
YES
FAIL
NO
VERIFY
++ Addr
YES
Last
Addr
NO
YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
AI00760B
8/15
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows to program the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE at VCC much higher than
3.6V provides necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27V256s in parallel
with different data is also easily accomplished. Except for E, all like inputs including G of the parallel
M27V256 may be common. A TTL low level pulse
applied to a M27V256’s E input, with VPP at 12.75
V, will program that M27V256. A high level E input
inhibits the other M27V256s from being programmed.
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with G
at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
M27V256
On-Board Programming
The M27V256 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27V256. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V256, with
VCC = VPP = 5V. Two identifier bytes may then be
sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address
lines must be held at VIL during Electronic Signature mode. Byte 0 (A0=VIL) represents the manufacturer code and byte 1 (A0=VIH) the device
identifier code. For the STMicroelectronics
M27V256, these two identifier bytes are given in
Table 4 and can be read-out on outputs Q0 to Q7.
Note that the M27V256 and M27C256B have the
same identifier bytes.
ERASURE OPERATION (applies for UV EPROM)
The erasure characteristics of the M27V256 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27V256 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V256 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27V256 window to prevent unintentional erasure. The recommended erasure procedure for
the M27V256 is exposure to short wave ultraviolet
light which has wavelength 2537Å. The integrated
dose (i.e. UV intensity x exposure time) for erasure
should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with 12000
µW/cm2 power rating. The M27V256 should be
placed within 2.5 cm (1 inch) of the lamp tubes
during the erasure. Some lamps have a filter on
their tubes which should be removed before erasure.
9/15
M27V256
Table 11. Ordering Information Scheme
Example:
M27V256
-90 K
1
TR
Device Type
Speed
-90 (1) = 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
-200 = 200 ns
Package
F = FDIP28W
B = PDIP28
K = PLCC32
N = TSOP28: 8 x 13.4mm
Temperature Range
1 = –0 to 70 °C
6 = –40 to 85 °C
Optio n
TR =Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
10/15
M27V256
Table 12. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
5.72
Max
0.225
A1
0.51
1.40
0.020
0.055
A2
3.91
4.57
0.154
0.180
A3
3.89
4.50
0.153
0.177
B
0.41
0.56
0.016
0.022
B1
–
–
–
–
C
1.45
0.23
0.30
0.009
0.012
D
36.50
37.34
1.437
1.470
–
–
1.300
–
–
0.600
D2
33.02
E
15.24
E1
0.057
–
–
13.06
13.36
–
–
0.514
0.526
e
2.54
–
–
0.100
–
–
eA
14.99
–
–
0.590
–
–
eB
16.18
18.03
0.637
0.710
L
3.18
S
1.52
2.49
–
–
α
4°
11°
N
28
∅
7.11
0.125
0.280
0.060
0.098
–
–
4°
11°
28
Figure 8. FDIP28W - 28 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A1
B1
B
A
L
e
α
eA
D2
C
eB
D
S
N
∅
E1
E
1
FDIPW-a
Drawing is not to scale.
11/15
M27V256
Table 13. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
–
A1
Min
Max
5.08
–
0.200
0.38
–
0.015
–
A2
3.56
4.06
0.140
0.160
B
0.38
0.51
0.015
0.020
–
–
–
–
C
0.20
0.30
0.008
0.012
D
36.83
37.34
1.450
1.470
B1
1.52
Typ
0.060
D2
33.02
–
–
1.300
–
–
E
15.24
–
–
0.600
–
–
13.59
13.84
0.535
0.545
E1
e1
2.54
–
–
0.100
–
–
eA
14.99
–
–
0.590
–
–
eB
15.24
17.78
0.600
0.700
L
3.18
3.43
0.125
0.135
S
1.78
2.08
0.070
0.082
α
0°
10°
0°
10°
N
28
28
Figure 9. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2
A1
B1
B
A
L
e1
α
eA
D2
C
eB
D
S
N
E1
E
1
PDIP
Drawing is not to scale.
12/15
M27V256
Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data
mm
Symb
Typ
inches
Min
Max
A
2.54
A1
Min
Max
3.56
0.100
0.140
1.52
2.41
0.060
0.095
A2
–
0.38
–
0.015
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
D
12.32
12.57
0.485
0.495
D1
11.35
11.56
0.447
0.455
D2
9.91
10.92
0.390
0.430
E
14.86
15.11
0.585
0.595
E1
13.89
14.10
0.547
0.555
E2
12.45
13.46
0.490
0.530
–
–
–
–
0.00
0.25
0.000
0.010
–
–
–
–
e
1.27
F
R
0.89
Typ
0.050
0.035
N
32
32
Nd
7
7
Ne
9
9
CP
0.10
0.004
Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline
D
D1
A1
A2
1 N
B1
E1 E
Ne
e
D2/E2
F
B
0.51 (.020)
1.14 (.045)
A
Nd
R
CP
PLCC
Drawing is not to scale.
13/15
M27V256
Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Mechanical Data
mm
inches
Symb
Typ
A
Min
Max
1.00
1.25
A1
Typ
Min
Max
0.039
0.049
0.20
A2
0.95
0.008
1.05
B
0.037
0.30
0.012
C
0.10
0.21
0.004
0.008
D
13.10
13.70
0.516
0.539
D1
11.70
11.90
0.461
0.469
E
7.90
8.25
0.311
0.325
-
-
-
-
L
0.30
0.70
0.012
0.028
α
0°
5°
0°
5°
N
28
e
0.55
0.022
28
CP
0.10
0.004
Figure 11. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm, Package Outline
A2
22
21
e
28
1
E
B
7
8
D1
A
CP
D
DIE
C
TSOP-c
Drawing is not to scale
14/15
0.041
A1
α
L
M27V256
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