M36L0R7060T1 M36L0R7060B1 128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package Features ■ ■ ■ ■ Multichip package – 1 die of 128 Mbit (8 Mb x16, Multiple Bank, Multilevel, Burst) Flash memory – 1 die of 64 Mbit (4 Mb x16) Pseudo SRAM FBGA Supply voltage – VDDF = VCCP = VDDQF = 1.7 to 1.95 V – VPPF = 9 V for fast program Electronic signature – Manufacturer Code: 20h – Top Device Code M36L0R7060T1: 88C4h – Bottom Device Code M36L0R7060B1: 88C5h Package – ECOPACK® TFBGA88 (ZAQ) 8 x 10 mm ■ Security – 64 bit unique device number – 2112 bit user programmable OTP Cells ■ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WPF for Block Lock-Down – Absolute Write Protection with VPPF = VSS Flash memory ■ Synchronous / Asynchronous Read – Synchronous Burst Read mode: 54 MHz, 66 MHz – Random Access: 70 ns, 85 ns ■ Synchronous Burst Read Suspend ■ Programming time – 2.5 µs typical word program time using Buffer Enhanced Factory Program command ■ Memory organization – Multiple Bank memory array: 8 Mbit banks – Parameter Blocks (top or bottom location) ■ Common Flash Interface (CFI) ■ 100 000 program/erase cycles per block ■ Dual operations – program/erase in one Bank while read in others – No delay between read and write operations May 2007 PSRAM ■ Access time: 70 ns ■ Asynchronous Page Read – Page Size: 4, 8 or 16 words – Subsequent read within page: 20 ns ■ Low power features – Automatic Temperature-compensated SelfRefresh (TCR) – Partial Array Self-Refresh (PASR) – Deep Power-Down (DPD) mode ■ Synchronous Burst Read/Write Rev 1 1/22 www.st.com 1 Contents M36L0R7060T1, M36L0R7060B1 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.16 PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 11 2.17 VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.18 VCCP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.19 VDDQF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.20 VPPF Program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.21 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/22 M36L0R7060T1, M36L0R7060B1 Contents 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3/22 List of tables M36L0R7060T1, M36L0R7060B1 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. 4/22 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 M36L0R7060T1, M36L0R7060B1 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline . . . . . . . . . . . . . . 18 5/22 Description 1 M36L0R7060T1, M36L0R7060B1 Description The M36L0R7060T1 and M36L0R7060B1 combine two memory devices in a multichip package: ● a 128-Mbit, Multiple Bank Flash memory, the M58LR128HT or M58LR128HB ● a 64-Mbit PseudoSRAM, the M69KB096AM The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58LR128HTB and M69KB096AM datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from your local STMicroelectronics distributor. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 × 10 mm, 8 × 10 ball array, 0.8 mm pitch) package. The memory is supplied with all the bits erased (set to ‘1’). Figure 1. Logic diagram VDDQF VPPF VDDF VCCP 23 16 A0-A22 DQ0-DQ15 EF GF WAIT WF RPF WPF L M36L0R7060T1 M36L0R7060B1 K EP GP WP CRP UBP LBP VSS 6/22 AI13200 M36L0R7060T1, M36L0R7060B1 Table 1. Description Signal names Signal name Function Direction A0-A22 Address inputs Inputs DQ0-DQ15 Common Data input/output I/O L Latch Enable input for Flash memory and PSRAM Input K Burst Clock for Flash memory and PSRAM Input WAIT Wait Data in Burst Mode for Flash memory and PSRAM Output VDDF Flash memory power supply VDDQF Flash power supply for I/O buffers VPPF Flash optional supply voltage for Fast Program & Erase VSS Ground VCCP PSRAM power supply NC Not connected internally DU Do not use as internally connected Flash memory EF Chip Enable input Input GF Output Enable Input Input WF Write Enable input Input RPF Reset input Input WPF Write Protect input Input EP Chip Enable input Input GP Output Enable input Input WP Write Enable input Input CRP Configuration Register Enable input Input UBP Upper Byte Enable input Input LBP Lower Byte Enable input Input PSRAM 7/22 Description M36L0R7060T1, M36L0R7060B1 Figure 2. TFBGA connections (top view through package) 1 2 3 4 5 A DU DU B A4 A18 A19 VSS VDDF C A5 LBP NC VSS D A3 A17 NC E A2 A7 F A1 G 6 7 8 DU DU NC A21 A11 NC K A22 A12 VPPF WP EP A9 A13 NC WPF L A20 A10 A15 A6 UBP RPF WF A8 A14 A16 A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT NC H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQF K EF DU DU NC VCCP NC VDDQF CRP L VSS VSS VDDQF VDDF VSS VSS VSS VSS M DU DU DU DU AI12023 8/22 M36L0R7060T1, M36L0R7060B1 2 Signal descriptions Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connect-ed to this device. 2.1 Address inputs (A0-A22) Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The other lines (A22) is an input for the Flash memory component only. The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP). 2.2 Data input/output (DQ0-DQ15) The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. For the PSRAM component, the upper Byte Data inputs/outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data inputs/outputs (DQ0-DQ7) carry the data to or from the lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data inputs/outputs are high impedance. 2.3 Latch Enable (L) The Latch Enable pin is common to the Flash memory and PSRAM components. For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory. 2.4 Clock (K) The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AM for the PSRAM and M58LR128HTB for the Flash memory. 9/22 Signal descriptions 2.5 M36L0R7060T1, M36L0R7060B1 Wait (WAIT) WAIT is an output pin common to the Flash memory and PSRAM components. However the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KB096AM datasheet for the PSRAM and to the M58LR128HTB datasheet for the Flash memory. 2.6 Flash Chip Enable (EF) The Flash Chip Enable input activates the control logic, input buffers, decoders and sense amplifiers of the Flash memory component. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.7 Flash Output Enable (GF) The Output Enable pin controls the data outputs during Flash memory Bus Read operations. 2.8 Flash Write Enable (WF) The Write Enable controls the Bus Write operation of the Flash memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 2.9 Flash Write Protect (WPF) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R7000T1/B1 datasheet). 2.10 Flash Reset (RPF) The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58LR128HTB datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied to VRPH (refer to the M58LR128HTB datasheet). 10/22 M36L0R7060T1, M36L0R7060B1 2.11 Signal descriptions PSRAM Chip Enable input (EP) The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode, according to the RCR settings. 2.12 PSRAM Write Enable (WP) Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. 2.13 PSRAM Output Enable (GP) When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the memory. 2.14 PSRAM Upper Byte Enable (UBP) The Upper Byte En-able, UBP, gates the data on the Upper Byte Data inputs/outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation. 2.15 PSRAM Lower Byte Enable (LBP) The Lower Byte Enable, LBP, gates the data on the Lower Byte Data inputs/outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation. If both LBP and UBP are disabled (High) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as EP remains Low. 2.16 PSRAM Configuration Register Enable (CRP) When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19. 2.17 VDDF supply voltage VDDF provides the power supply to the internal core of the Flash memory. It is the main power supply for all Flash memory operations (Read, Program and Erase). 2.18 VCCP supply voltage VCCP provides the power supply to the internal core of the PSRAM device. It is the main power supply for all PSRAM operations. 11/22 Signal descriptions 2.19 M36L0R7060T1, M36L0R7060B1 VDDQF supply voltage VDDQF provides the power supply for the Flash I/O pins. This allows all outputs to be powered independently of the Flash core power supplies, VDDF and VCCP. 2.20 VPPF Program supply voltage VPPF is both a Flash control input and a Flash power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against Program or Erase, while VPP in the VPP1 range enables these functions (see the M58LR128HTB datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. 2.21 VSS ground VSS is the common ground reference for all voltage measurements in the Flash (core and I/O buffers) and PSRAM chips. It must be connected to the system ground. Note: 12/22 Each Flash memory device in a system should have their supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1 µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. M36L0R7060T1, M36L0R7060B1 3 Functional description Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for the Flash memory and EP for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations on one of the Flash memory and the PSRAM components which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram A22 EF WF RPF WPF 128 Mbit Flash Memory GF WAIT VDDF VDDQF VPPF K L VCCP A0-A21 VSS DQ0-DQ15 EP GP WP 64 Mbit PSRAM CRP UBP LBP AI12024 13/22 Functional description Main operating modes(1) Table 2. Operation M36L0R7060T1, M36L0R7060B1 (2)(3) EF GF WF LF RPF WAITF(4) Flash Read VIL VIL VIH VIL(5) VIH Flash Write VIL VIH VIL VIL(5) VIH Flash Address Latch VIL Flash Output Disable Flash Standby Flash Reset X VIH EP CRP GP A0A17 WP LBP,UBP A19 A18 A20A21 DQ15-DQ0 Flash Data Out PSRAM must be disabled. Flash Data In Flash Data Out or Hi-Z(6) VIL VIH VIL VIH VIH X VIH Hi-Z VIH X X X VIH Hi-Z X X X X VIL Hi-Z Hi-Z Any PSRAM mode is allowed. Hi-Z Hi-Z PSRAM Read VIL VIL VIL VIH VIL Valid PSRAM data out PSRAM Write VIL VIL X VIL VIL Valid PSRAM data in VIL VIH X VIL X 00(RCR) BCR/ 10(BCR) RCR (8) Data Hi-Z VIH VIL X X X X X X Hi-Z VIH X X X X X X X Hi-Z PSRAM Program Configuration Register (CR Controlled)(7) The Flash memory must be disabled. PSRAM Standby Any Flash mode is allowed. PSRAM Deep Power-Down(9) 1. X = Don't care. 2. In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in Standby and Deep Power-Down modes. 3. The PSRAM must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value). 4. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LR128HTB datasheet for details. 5. LF can be tied to VIH if the valid address has been previously latched. 6. Depends on GF. 7. BCR and RCR only. 8. A18 and A19 are used to select the BCR, RCR or DIDR registers. 9. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, VIH, during Deep PowerDown mode. 14/22 M36L0R7060T1, M36L0R7060B1 4 Maximum rating Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute maximum ratings Value Symbol Parameter Unit Min Max Ambient operating temperature –25 85 °C TBIAS Temperature under bias –25 85 °C TSTG Storage temperature –55 125 °C Input or output voltage –0.2 2.45 V –0.2 2.45 V –0.2 10 V Output short circuit current 100 mA Time for VPPF at VPPFH 100 hours TA VIO VDDF, VDDQF, Core and input/output supply VCCP voltages VPPF IO tVPPFH Flash program voltage 15/22 DC and AC parameters 5 M36L0R7060T1, M36L0R7060B1 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC measurement conditions Flash memory PSRAM Parameter Unit Min Max Min Max VDDF supply voltage 1.7 1.95 – – V VCCP supply voltage – – 1.7 1.95 V VDDQF supply voltage 1.7 1.95 – – V VPPF supply voltage (Factory environment) 8.5 9.5 – – V –0.4 VDDQF +0.4 – – V –25 85 –25 85 °C VPPF supply voltage (Application environment) Ambient operating temperature Load capacitance (CL) Output circuit resistors (R1, R2) 30 30 pF 16.7 16.7 kΩ Input rise and fall times 5 Input pulse voltages Input and output timing ref. voltages Figure 4. 2 ns 0 to VDDQF 0 to VCCP/2 V VDDQF/2 VCCP/2 V AC measurement I/O waveform VDDQF VDDQF/2 0V AI06161b 16/22 M36L0R7060T1, M36L0R7060B1 Figure 5. DC and AC parameters AC measurement load circuit VDDQF VDDF VDDQF R1 DEVICE UNDER TEST CL 0.1µF R2 0.1µF CL includes JIG capacitance AI08364c Table 5. Symbol CIN COUT Device capacitance Parameter Input capacitance Output capacitance Max(1) Unit VIN = 0 V 14 pF VOUT = 0 V 18 pF Test Condition Min 1. Sampled only, not 100% tested. Please refer to the M58LR128HTB and M69KB096AM datasheets for further DC and AC characteristics values and illustrations. 17/22 Package mechanical 6 M36L0R7060T1, M36L0R7060B1 Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 FD SD A2 A A1 BGA-Z42 1. Drawing is not to scale. 18/22 M36L0R7060T1, M36L0R7060B1 Table 6. Package mechanical Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 0.0472 0.200 A2 0.850 Max 0.0079 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 5.600 0.2205 ddd 0.100 9.900 E 10.000 E1 7.200 0.2835 E2 8.800 0.3465 – 10.100 0.0039 – 0.3937 e 0.800 FD 1.200 0.0472 0.0315 FE 1.400 0.0551 FE1 0.600 0.0236 SD 0.400 0.0157 SE 0.400 0.0157 0.3898 0.3976 – – 19/22 Part numbering 7 M36L0R7060T1, M36L0R7060B1 Part numbering Table 7. Ordering information scheme Example: M36 L 0 R 7 0 6 0 T 1 ZAQ E Device Type M36 = Multichip package (Multiple Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VCCP = VDDQF = 1.7 to 1.95V Flash 1 Density 7 = 128 Mbits Flash 2 Density 0 = No Die RAM 1 Density 6 = 64 Mbits RAM 0 Density 0 = No Die Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 1 = 90 nm Flash technology Multilevel Design, 70 and 85 ns speed 0.11 µm PSRAM, 70 ns speed, burst mode Package ZAQ = Stacked TFBGA88 8 x 10 mm - 8 x 10 active ball array, 0.8 mm pitch Option E = ECOPACK® Standard packing F = ECOPACK® Tape & Reel packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 20/22 M36L0R7060T1, M36L0R7060B1 8 Revision history Revision history Table 8. Document revision history Date Revision Changes 23-May-2006 0.1 First release. 31-Aug-2006 0.2 PSRAM changed to M69KM096AM. Blank and T removed below Option in Table 7: Ordering information scheme. 07-May-2007 1 Document status promoted from Target Specification to full Datasheet. 70 ns speed class and 66 MHz frequency added. 21/22 M36L0R7060T1, M36L0R7060B1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 22/22