MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
These are single-chip microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash
memory. These microcomputers support the 7900 Series instruction
set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set.
The CPU of these microcomputers is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. Also, the
bus interface unit of these microcomputers enhances the memory
access efficiency to execute instructions fast. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require high-speed processing of large data.
For the internal flash memory, single-power-supply programming
and erasure, using a PROM programmer or the control by the central processing unit (CPU), is supported. Also, each of these microcomputers has the memory area dedicated for storing a certain
software which controls programming and erasure (reprogramming
control software). Therefore, on these microcomputers, the program
can easily be changed even after they are mounted on the board.
DISTINCTIVE FEATURES
<Microcomputer mode>
Number of basic machine instructions .................................... 203
Memory
[M37902FCCHP]
Flash memory (User ROM area) ................................. 120 Kbytes
RAM ............................................................................. 4096 bytes
[M37902FGCHP]
Flash memory (User ROM area) ................................. 248 Kbytes
RAM ............................................................................. 6144 bytes
[M37902FJCHP]
Flash memory (User ROM area) ................................. 498 Kbytes
RAM ........................................................................... 12288 bytes
[All of the above computers]
Flash memory (Boot ROM area) ................................... 16 Kbytes
Instruction execution time
The fastest instruction at 26 MHz frequency ........................ 38 ns
Single power supply .................................................... 5 V ± 0.5 V
Interrupts ........... 6 external sources, 16 internal sources, 7 levels
Multi-functional 16-bit timer ................................................... 5 + 3
Serial I/O (UART or Clock synchronous) ..................................... 2
10-bit A-D converter ............................................ 8-channel inputs
8-bit D-A converter ............................................ 3-channel outputs
Real-time output
.... 4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel
12-bit watchdog timer
Programmable input/output (ports P0–P8, P10, P11) ............... 84
•
•
•
•
•
•
•
•
•
•
•
•
<Flash memory mode>
Power supply voltage .................................................. 5 V ± 0.5 V
Programming/Erase voltage ........................................ 5 V ± 0.5 V
Programming method ............ Programming in a unit of 256 bytes
Erase method ............................................ Block erase or Total erase
(Data protection per block is enabled.)
•
•
•
•
• Programming/Erase control by software command
• Maximum number of reprograms ............................................ 100
APPLICATION
Control devices for personal computer peripheral equipment such as
CD-ROM drives, DVD-ROM drives, hard disk drives, high density
FDD, printers
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
↔ P104/A4
↔ P105/A5
↔ P106/A6
↔ P107/A7
↔ P110/A8
↔ P111/A9
↔ P112/A10
↔ P113/A11
↔ P114/A12
↔ P115/A13
↔ P116/A14
↔ P117/A15
↔ P00/A16
↔ P01/A17
↔ P02/A18
↔ P03/A19
↔ P04/A20
↔ P05/A21
↔ P06/A22
↔ P07/A23
VSS
← MD1
↔ P10/D0/LA0
↔ P11/D1/LA1
↔ P12/D2/LA2
M37902FxCHP PIN CONFIGURATION (TOP VIEW)
M37902FCCHP
M37902FGCHP
M37902FJCHP
P70/AN0 ↔
P67/TB2IN ↔
P66/TB1IN ↔
P65/TB0IN ↔
P64/INT2 ↔
P63/INT1 ↔
P62/INT0 ↔
P61/TA4IN ↔
P60/TA4OUT ↔
P57/TA3IN/RTP13/KI3 ↔
P56/TA3OUT/RTP12/KI2 ↔
P55/TA2IN/RTP11/KI1 ↔
P54/TA2OUT/RTP10/KI0 ↔
P53/TA1IN/RTP03 ↔
P52/TA1OUT/RTP02 ↔
P51/TA0IN/RTP01 ↔
P50/TA0OUT/RTP00 ↔
P47/CS3 ↔
P46/CS2 ↔
P45/CS1 ↔
P44/CS0 ↔
P43/HOLD ↔
P42/HLDA ↔
P41/φ1 ↔
P40/ALE ↔
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P103/A3 ↔ 76
P102/A2 ↔ 77
P101/A1 ↔ 78
P100/A0 ↔ 79
P87/TXD1 ↔ 80
P86/RXD1 ↔ 81
P85/CTS1/CLK1 ↔ 82
P84/CTS1/RTS1/INT4 ↔ 83
P83/TXD0 ↔ 84
P82/RXD0 ↔ 85
P81/CTS0/CLK0 ↔ 86
VCC
87
AVCC
88
VREF → 89
90
AVSS
VSS
91
NMI → 92
P80/CTS0/RTS0/DA2/INT3 ↔ 93
P77/AN7/ADTRG/DA1/(INT2) ↔ 94
P76/AN6/DA0 ↔ 95
P75/AN5/(INT4) ↔ 96
P74/AN4/(INT3) ↔ 97
P73/AN3 ↔ 98
P72/AN2 ↔ 99
P71/AN1 ↔ 100
Outline 100P6Q-A
2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
↔ P13/D3/LA3
↔ P14/D4/LA4
↔ P15/D5/LA5
↔ P16/D6/LA6
↔ P17/D7/LA7
↔ P20/D8
↔ P21/D9
↔ P22/D10
↔ P23/D11
↔ P24/D12
↔ P25/D13
↔ P26/D14
↔ P27/D15
VCC
→ XOUT
← XIN
VSS
← MD0
← RESET
VCONT
← BYTE
↔ P30/RDY
↔ P31/RD
↔ P32/BLW
↔ P33/BHW
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data Bus (Even)
Data Bus (Odd)
Instruction Queue Buffer Q1 (8)
Input/Output
port P1
P1(8)
NMI
Instruction Queue Buffer Q0 (8)
Instruction Queue Buffer Q4 (8)
RAM
4096 bytes
6144 bytes
12288 bytes
Input/Output
port P2
P2(8)
Instruction Queue Buffer Q3 (8)
VREF
Reference
voltage input
Instruction Queue Buffer Q2 (8)
Flash memory
120 Kbytes
248 Kbytes
498 Kbytes
Address Bus
Data Buffer DQ3 (8)
M37902FCCHP
M37902FGCHP
M37902FJCHP
Data Buffer DQ2 (8)
Input/Output
port P0
P0(8)
Data Buffer DQ1 (8)
BYTE
External data bus width
select input
Data Buffer DQ0 (8)
Note:
Input/Output
port P4
Input/Output
port P5
P3(4)
P4(8)
P5(8)
P6(8)
D-A0 converter (8)
Program Counter PC (16)
Input/Output
port P6
MD0
Incrementer/Decrementer (24)
UART0 (9)
UART1 (9)
MD1
Data Address Register DA (24)
Bus
Interface
Unit
(BIU)
Incrementer (24)
Program Address Register PA (24)
A-D converter (10)
D-A2 converter (8)
Instruction Queue Buffer Q9 (8)
D-A1 converter (8)
Instruction Queue Buffer Q8 (8)
(0V)
AVSS
AVcc
Instruction register (8)
Instruction Queue Buffer Q6 (8)
Instruction Queue Buffer Q7 (8)
Input/Output
port P3
Instruction Queue Buffer Q5 (8)
Input/Output
port P7
Input/Output
port P8
P7(8)
P8(8)
Timer TB0 (16)
Timer TA0 (16)
Timer TB2 (16)
Timer TB1 (16)
Timer TA1 (16)
Vcc
Direct Page Register DPR0 (16)
Watchdog timer
Processor Status Register PS (11)
Timer TA4 (16)
Input Buffer Register IB (16)
Timer TA2 (16)
(0V)
Vss
Data bank Register DT (8)
Timer TA3 (16)
Program Bank Register PG (8)
RAM
(Note)
P10(8)
Input/Output
port P10
Flash memory
(Note)
P11(8)
Input/Output
port P11
Direct Page Register DPR1 (16)
RESET
Direct Page Register DPR3 (16)
Stack Pointer S (16)
Clock Generating Circuit
XOUT
Clock output
Clock input
XIN
VCONT
BLOCK DIAGRAM
Index Register Y (16)
Index Register X (16)
Accumulator B (16)
Accumulator A (16)
Arithmetic Logic
Unit (16)
Central Processing Unit (CPU)
Reset input
Direct Page Register DPR2 (16)
3
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS (Microcomputer mode)
Parameter
Number of basic machine instructions
203
Instruction execution time
38 ns (the fastest instruction at f(fsys) = 26 MHz)
External clock input frequency f(XIN)
26 MHz (Max.)
System clock frequency f(fsys)
26 MHz (Max.)
Memory size
Functions
Flash memory (User ROM area)
(Note)
RAM
(Note)
Flash memory (Boot ROM area)
16 Kbytes
Programmable input/output
P0–P2, P4–P8, P10, P11
8-bit ✕ 10
ports
P3
4-bit ✕ 1
Multi-functional timers
TA0–TA4
16-bit ✕ 5
TB0–TB2
16-bit ✕ 3
UART0 and UART1
(UART or Clock synchronous serial I/O) ✕ 2
Serial I/O
A-D converter
10-bit successive approximation method ✕ 1 (8 channels)
D-A converter
8-bit ✕ 3
Watchdog timer
12-bit ✕ 1
Chip-select wait control
Chip select area ✕ 4 (CS0–CS3). A bus cycle type and bus width
can be set for each chip select area.
Real-time output
4 bits ✕ 2 channels; or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel
Interrupts
Maskable interrups
5 external types, 13 internal types. Each interrupt can be set to a
priority level within the range of 0–7 by software.
Non-maskable interrups
1 external type, 3 internal types.
Clock generating circuit
Built-in (externally connected to a ceramic resonator or quartz
crystal resonator).
PLL frequency multiplier
The following multiplication methods are available: double, triple,
and quadruple.
Power supply voltage
5 V±0.5 V
Power dissipation
150 mW (at f(fsys ) = 26 MHz, Typ., PLL frequency multiplier
stopped)
5V
5 mA
Up to 16 Mbytes. Note that bank FF16 is a reserved area.
–20 to 85 °C
CMOS high-performance silicon gate process
100-pin plastic molded QFP
Ports’ input/output
characteristics
Input/Output withstand voltage
Output current
Memory expansion
Operating ambient temperature range
Device structure
Package
Note:
Flash memory
(User ROM area)
RAM
4
M37902FCCHP
M37902FGCHP
M37902FJCHP
M37902FCCHP
M37902FGCHP
M37902FJCHP
120 Kbytes
248 Kbytes
498 Kbytes
4096 bytes
6144 bytes
12288 bytes
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS (Flash memory mode)
Power supply voltage
Parameter
Functions
5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V)
Programming/Erase voltage
5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V)
Flash memory mode
Block division for erasure
3 modes: parallel I/O, serial I/O, and CPU reprogramming modes
User ROM area
(Note 1)
Boot ROM area
1 block (16 Kbytes ✕ 1) (Note 2)
Programming method
Programmed per page (in a unit of 256 Kbytes)
Flash memory parallel I/O mode
User ROM area + Boot ROM area
Flash memory serial I/O mode
User ROM area
Flash memory CPU reprogramming mode User ROM area
Erase method
Total erase/Block erase
Flash memory parallel I/O mode
User ROM area + Boot ROM area
Flash memory serial I/O mode
User ROM area
Flash memory CPU reprogramming mode User ROM area
Programming/Erase control
Programming/Erase control by software commands
Data protection method
Protected per block, by using a lock bit.
Number of commands
8 commands
Maximum number of reprograms
100
Notes 1:
User ROM area M37902FCCHP
M37902FGCHP
M37902FJCHP
5 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 1), total 120 Kbytes
7 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 3), total 248 Kbytes
11 blocks (2 Kbytes ✕ 1, 8 Kbytes ✕ 2, 32 Kbytes ✕ 1, 64 Kbytes ✕ 7), total 498 Kbytes
2: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.
Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode.
5
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (MICROCOMPUTER MODE)
Pin
Name
Input/
Output
Vcc, Vss
Power supply input
MD0
MD0
Input
This pin controls the processor mode. Connect this pin to VSS for the single-chip
mode or memory expansion mode, and VCC for the microprocessor mode.
MD1
MD1
Input
Connect this pin to Vss.
RESET
Reset input
Input
The microcomputer is reset when “L” level is applied to this pin.
XIN
Clock input
Input
XOUT
Clock output
These are input and output pins of the internal clock generating circuit. Connect a
ceramic or quartz- crystal resonator between the XIN and XOUT pins. When an
external clock is used, the clock source should be connected to the XIN pin, and the
XOUT pin should be left open.
BYTE
External data bus width
select input
Input
This pin determines whether the external data bus has an 8-bit width or 16-bit width
for the memory expansion mode or microprocessor mode. The width is 16 bits when
“L” signal is input, and 8 bits when “H” signal is input. When BYTE = Vss level, by
the register setting, the external data bus for each of areas CS1 to CS3 can have a
width of 8 bits.
VCONT
Filter circuit connection
—
When using the PLL frequency multiplier, connect this pin to the filter circuit. When
not using, this pin should be left open.
AVcc,
AVss
Analog power supply input
—
Power supply input pins for the A-D converter and the D-A converter. Connect AVcc
to Vcc, and AVss to Vss externally.
VREF
Reference voltage input
Input
This is the reference voltage input pin for the A-D converter and the D-A converter.
P00–P07
I/O port P0
I/O
■ In single-chip mode
Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin
can be programmed for input or output. These pins enter the input mode at
reset.
■ In memory expansion and microprocessor modes
Address (A16–A23) is output. These pins also function as I/O port pins according
to the register setting.
P10–P17
I/O port P1
I/O
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
The low-order 8 bits of data (D0–D7) are input/output. When the external data bus
has an 8-bit width, address (LA0–LA7) output and data (D0–D7) input/output can
be performed with the time-sharing method, according to the register setting.
P20–P27
I/O port P2
I/O
■ In single-chip mode or When 8-bit external data bus is used in memory expansion
mode and microprocessor mode
These pins have the same functions as port P0.
■ When the 16-bit external data bus is used in memory expansion or microprocessor mode
The high-order 8 bits of data (D8–D15) are input or output.
P30–P33
I/O port P3
I/O
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion mode
P30 functions as an I/O port pin; and P31, P32, and P33 function as the output
pins of RD, BLW, BHW, respectively. P30 also functions as an output pin of RDY
according to the register setting. When the external data bus has a width of 8 bits,
the BHW pin functions as an I/O port pin (P33).
■ In microprocessor mode
P30 functions as an input pin of RDY; and P31,P32, P33 function as the output
pins of RD, BLW, BHW, respectively. P30 also functions as an I/O port pin according to the register setting. When the external data bus has a width of 8 bits,
the BHW pin functions as an I/O port pin (P33).
P40–P47
I/O port P4
I/O
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion mode
P40–P47 function as I/O port pins. According to the register setting, these pins
function as output pins or input pins of ALE, φ1, HLDA, HOLD, CS0–CS3, respectively.
■ In microprocessor mode
P40–P44 function as output or input pins of ALE, φ1, HLDA, HOLD, CS0, and
P45–P47 as I/O port pins, respectively. According to the register setting, P40–P43
also function as I/O port pins, and P45–P47 as output pins of CS1–CS3.
6
—
Functions
Output
Apply 5 V±0.5 V to Vcc, and 0 V to Vss.
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin
Name
Input/
Output
P50–P57
I/O port P5
I/O
P60–P67
I/O port P6
I/O
Functions
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timers A0–A3, output pins for the real-time output,
and input pins for the key-input interrupt.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timer A4, input pins for external interrupt inputs
INT0–INT2, and input pins for timers B0–B2.
____ ____
P70–P77
I/O port P7
I/O
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as input pins for the A-D converter, output pins for the D-A
converter, and input pins for INT2, INT3, and INT4.
P80–P87
I/O port P8
I/O
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for UART0, UART1, output pins for D-A converter,
and input pins for INT3 and INT4.
P100–P107
I/O port P10
I/O
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
Address (A0–A7) is output.
P110–P117
I/O port P11
I/O
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
Address (A8–A15) is output. Also, these pins function as I/O port pins according to
the register setting.
NMI
Non-maskable interrupt
Input
This pin is for a non-maskable interrupt.
7
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE)
Pin
Name
VCC, VSS
MD0
MD1
_____
RESET
XIN
XOUT
BYTE
VCONT
AVcc, AVss
VREF
P00–P07
P10–P17
P20–P27
P30–P33
P40,
P44– P47
P41
P42
P43
P50–P57
P60–P67
P70–P77
P80–P87
P100–P107
P110–P117
NMI
Power supply input
MD0
MD1
Reset input
Clock input
Clock output
BYTE
Filter circuit connection
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Input port P3
8
Input port P4
SCLK input
SDA I/O
BUSY output
Input port P5
Input port P6
Input port P7
Input port P8
Input port P10
Input port P11
Non-maskable interrupt
Input
/Output
—
Input
Input
Input
Input
Output
Input
—
—
Input
Input
Input
Input
Input
Input
Input
I/O
Output
Input
Input
Input
Input
Input
Input
Input
Functions
Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss.
Connect this pin to Vss.
Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ.
The reset input pin.
Connect a ceramic resonator between the XIN and XOUT pins, or input an external
clock from the XIN pin with the XOUT pin left open.
Connect this pin to Vcc or Vss. (This is not used in the flash memory serial I/O mode.)
Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.)
Connect AVcc to Vcc, and AVss to Vss.
Input an arbitrary level within the range of VSS–VCC. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
This is an input pin for a serial clock.
This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ).
This is an output pin for the BUSY signal.
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H”, or leave this pin open.
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
These microcomputers contain the following devices on the single
chip: the flash memory, RAM, CPU, bus interface unit, and peripheral devices such as the interrupt control circuit, timers, serial I/O,
A-D converter, D-A converter, I/O ports, clock generating circuit, etc.
MEMORY
Figures 1 to 3 show the memory maps. The address space is 16
Mbytes from addresses 016 to FFFFFF16. The address space is divided into 64-Kbyte units called banks. The banks are numbered
from 016 to FF16. Bank FF16 is a reserved area for the development
support tool. Therefore, do not use bank FF16.
00000016
00000016
0000FF16
Bank 016
00FFFF16
01000016
Internal flash memory and internal RAM are assigned as shown in
Figures 1 to 3.
Addresses FFC016 to FFFF16 contain the RESET and the interrupt
vector addresses, and the interrupt vectors are stored there.
For details, refer to the section on interrupts.
Assigned to addresses 016 to FF16 are peripheral devices such as
I/O ports, A-D converter, D-A converter, UART, timers, interrupt control registers, etc. Figures 7 and 8 show the location of SFRs.
For the flash memory in the boot ROM area, refer to the section on
the flash memory mode.
Peripheral devices
control registers
Interrupt vector table
00FFC016
00080016
Bank 116
01FFFF16
Internal RAM
4096 bytes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0017FF16
00180016
Address matching detect
001FFF16
00200016
INT4
INT3
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
Reserved area
Reserved area
00FFC016
00FFFF16
Internal flash memory
120 Kbytes
(User ROM area)
INT2
INT1
INT0
NMI
Watchdog timer
FE000016
;;
;;
;;
Bank FE16
FEFFFF16
FF000016
Bank FF16
FFFFFF16
Reserved area
for development
support tool
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
00FFFE16
DBC
BRK instruction
Zero divide
RESET
Fig. 1 Memory map of M37902FCCHP (Single-chip mode)
9
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
00000016
00000016
0000FF16
Bank 016
00FFFF16
01000016
Peripheral devices
control registers
Interrupt vector table
00FFC016
00080016
Bank 116
01FFFF16
02000016
Internal RAM
6144 bytes
Bank 216
02FFFF16
03000016
Address matching detect
Reserved area
Reserved area
Bank 316
INT4
INT3
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
001FFF16
00200016
03FFFF16
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
00FFC016
00FFFF16
Internal flash memory
248 Kbytes
(User ROM area)
INT2
INT1
INT0
NMI
Watchdog timer
FE000016
;;
;;
;;
Bank FE16
FEFFFF16
FF000016
Bank FF16
FFFFFF16
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
for development
support tool
00FFFE16
DBC
BRK instruction
Zero divide
RESET
Fig. 2 Memory map of M37902FGCHP (Single-chip mode)
00000016
00000016
0000FF16
Bank 016
00FFFF16
01000016
Peripheral devices
control registers
Interrupt vector table
00FFC016
00080016
Bank 116
01FFFF16
02000016
Internal RAM
12288 bytes
Bank 216
02FFFF16
03000016
Address matching detect
0037FF16
00380016
Reserved area
Reserved area
Bank 316
INT4
INT3
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
03FFFF16
04000016
Bank 416
04FFFF16
05000016
Bank 516
00FFC016
00FFFF16
05FFFF16
06000016
Bank 616
06FFFF16
07000016
Bank 716
07FFFF16
•
•
•
•
•
•
•
Internal flash memory
498 Kbytes
(User ROM area)
INT2
INT1
INT0
NMI
Watchdog timer
;;
;;
;;
FE000016
Bank FE16
FEFFFF16
FF000016
Bank FF16
FFFFFF16
Reserved area
for development
support tool
Fig. 3 Memory map of M37902FJCHP (Single-chip mode)
10
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
00FFFE16
DBC
BRK instruction
Zero divide
RESET
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
Address (Hexadecimal notation)
00000016
00000116
00000216
00000316
00000416
00000516
00000616
00000716
00000816
00000916
00000A16
00000B16
00000C16
00000D16
00000E16
00000F16
00001016
00001116
00001216
00001316
00001416
00001516
00001616
00001716
00001816
00001916
00001A16
00001B16
00001C16
00001D16
00001E16
00001F16
00002016
00002116
00002216
00002316
00002416
00002516
00002616
00002716
00002816
00002916
00002A16
00002B16
00002C16
00002D16
00002E16
00002F16
00003016
00003116
00003216
00003316
00003416
00003516
00003616
00003716
00003816
00003916
00003A16
00003B16
00003C16
00003D16
00003E16
00003F16
00004016
00004116
00004216
00004316
00004416
00004516
00004616
00004716
00004816
00004916
00004A16
00004B16
00004C16
00004D16
00004E16
00004F16
00005016
00005116
00005216
00005316
00005416
00005516
00005616
00005716
00005816
00005916
00005A16
00005B16
00005C16
00005D16
00005E16
00005F16
00006016
00006116
00006216
00006316
00006416
00006516
00006616
00006716
00006816
00006916
00006A16
00006B16
00006C16
00006D16
00006E16
00006F16
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
Reserved area (Note)
Reserved area (Note)
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P8 direction register
Port P10 register
Port P11 register
Port P10 direction register
Port P11 direction register
A-D control register 0
A-D control register 1
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
UART0 transmit/receive mode register
UART0 baud rate register (BRG0)
UART0 transmit buffer register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 baud rate register (BRG1)
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
Count start register
One-shot start register
Up-down register
Timer A clock division select register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency select register
Particular function select register 0
Particular function select register 1
Particular function select register 2
Reserved area (Note)
Debug control register 0
Debug control register 1
Address comparison register 0
Address comparison register 1
INT3 interrupt control register
INT4 interrupt control register
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
Note: Do not write to this address.
Fig. 7 Location of SFRs (1)
11
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
00008016 CS0 control register L
00008116 CS0 control register H
00008216 CS1 control register L
00008316 CS1 control register H
00008416 CS2 control register L
00008516 CS2 control register H
00008616 CS3 control register L
00008716 CS3 control register H
00008816
00008916
00008A16 Area CS0 start address register
00008B16
00008C16 Area CS1 start address register
00008D16
00008E16 Area CS2 start address register
00008F16
00009016 Area CS3 start address register
00009116
00009216 Port function control register
00009316
00009416 External interrupt input control register
00009516 External interrupt input read-out register
00009616 D-A control register
00009716
00009816 D-A register 0
00009916 D-A register 1
00009A16 D-A register 2
00009B16
00009C16 Reserved area (Note)
00009D16 Reserved area (Note)
00009E16 Flash memory control register
00009F16
0000A016 Real-time output control register
0000A116
0000A216 Pulse output data register 0
0000A316
0000A416 Pulse output data register 1
0000A516
0000A616
0000A716
0000A816
0000A916
0000AA16
0000AB16
0000AC16 Serial I/O pin control register
0000AD16
0000AE16
0000AF16
0000B016
0000B116
0000B216
0000B316
0000B416
0000B516
0000B616
0000B716
0000B816
0000B916
0000BA16 Reserved area (Note)
0000BB16 Reserved area (Note)
0000BC16 Clock control register
0000BD16 Reserved area (Note)
0000BE16 Reserved area (Note)
0000BF16 Reserved area (Note)
Note: Do not write to this address.
Fig. 8 Location of SFRs (2)
12
Address (Hexadecimal notation)
0000C016
0000C116
0000C216
0000C316
0000C416
0000C516
0000C616
0000C716
0000C816
0000C916
0000CA16
0000CB16
0000CC16
0000CD16
0000CE16
0000CF16
0000D016
0000D116
0000D216
0000D316
0000D416
0000D516
0000D616
0000D716
0000D816
0000D916
0000DA16
0000DB16
0000DC16
0000DD16
0000DE16
0000DF16
0000E016
0000E116
0000E216
0000E316
0000E416
0000E516
0000E616
0000E716
0000E816
0000E916
0000EA16
0000EB16
0000EC16
0000ED16
0000EE16
0000EF16
0000F016
0000F116
0000F216
0000F316
0000F416
0000F516
0000F616
0000F716
0000F816
0000F916
0000FA16
0000FB16
0000FC16
0000FD16
0000FE16
0000FF16
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
INDEX REGISTER X (X)
The CPU has 13 registers and is shown in Figure 9. Each of these
registers is described below.
Index register X consists of 16 bits and the low-order 8 bits can be
used separately. Index register length flag x determines whether the
register is used as 16-bit register or as 8-bit register. It is used as a
16-bit register when flag x is “0” and as an 8-bit register when flag x
is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register X is used as the index
register, the contents of this address are added to obtain the real address.
Index register X functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists
of 16 bits and the low-order 8 bits can be used separately. Data
length flag m determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is
“0” and as an 8-bit register when flag m is “1”. Flag m is a part of the
processor status register (PS) which is described later.
Data operations such as calculations, data transfer, input/output,
etc., are executed mainly through accumulator A.
INDEX REGISTER Y (Y)
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the use
of accumulator B requires more instruction bytes and execution
cycles than accumulator A.
ACCUMULATOR E
Accumulator E is a 32-bit register and consists of accumulator A
(low-order 16 bits) and accumulator B (high-order 16 bits). It is used
for 32-bit data processing.
Accumulator B
15
Accumulator A
7
BH
Index register Y consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag x determines whether
the register is used as 16-bit register or as 8-bit register. It is used as
a 16-bit register when flag x is “0” and as an 8-bit register when flag
x is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register Y is used as the index
register, the contents of this address are added to obtain the real address.
Index register Y functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
0 15
BL
7
AH
0
AL
31
0
Accumulator E
15
7
AH
15
0
AL
7
BH
15
0
BL
0
7
XH
15
Index register X
XL
7
0
Index register Y
YL
YH
15
7
0
PG
7
Stack pointer S
S
Program bank register PG
15
0
Program counter PC
PC
0
DT
0
Data bank register DT
15
15
0 0 0 0 0
0
DPR0 to DPR3
7
IPL2 IPL1 IPL0 N V m x D
I
Direct page registers DPR0 to DPR3
0
Z C Processor status register PS
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level IPL
Fig. 9 Register structure
13
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
PROCESSOR STATUS REGISTER (PS)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative,
or stack pointer relative indirect indexed Y addressing mode.
Processor status register (PS) is an 11-bit register. It consists of
flags to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V, and
N.
The details of each bit of the processor status register are described
below.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through bus interface unit.
This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is increased
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
using the branch instruction, the contents of the program bank register (PG) is increased or decreased by 1, so that programs can be
written without worrying about bank boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, the data bank register (DT) is used to specify a part of the
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer
relative indirect indexed Y.
DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3)
The direct page register is a 16-bit register. An addressing mode of
which name includes ‘direct’ generates an address of data to be accessed, regarding the contents of this register as the base address.
The 7900 Series has been expanded direct page registers up to 4
(DPR0 to DPR3), in comparison to the 7700 Series which has the
single direct page register. Accordingly, the 7900 Series’s direct addressing method which uses direct page registers differs from that of
the 7700 Series. However, the conventional direct addressing
method, using only DPR0, is still be selectable, in order to make use
of the 7700 Series software property. For more details, refer to the
section on the direct page.
14
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC
and CLC instructions or with the SEP and CLP instructions.
2. Zero flag (Z)
The zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset
directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to “1”, all interrupts except
___
watchdog timer, NMI, and software interrupt are disabled. This flag
is set to “1” automatically when an interrupt is accepted. It can be set
and reset directly with the SEI and CLI instructions or SEP and CLP
instructions.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed as binary or decimal. Binary arithmetic is performed
when this flag is “0”. If it is “1”, decimal arithmetic is performed with
each word treated as 2- or 4- digit decimal. Arithmetic operation is
performed using four digits when data length flag m is “0” and with
two digits when it is “1”. Decimal adjust is automatically performed.
(Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions.
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8bit registers when it is “1”.
This flag can be set and reset with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit or
8-bit. The data length is 16 bits when flag m is “0” and 8 bits when it
is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag is valid when addition or subtraction is performed
with a word treated as a signed binary number. If data length flag m
is “0”, the overflow flag is set when the result of addition or subtraction is outside the range between –32768 and +32767. If data length
flag m is “1”, the overflow flag is set when the result of addition or
subtraction is outside the range between –128 and +127. It is reset
in all other cases. The overflow flag can also be set and reset directly
with the SEP, and CLV or CLP instructions.
Additionally, the overflow flag is set when a result of unsigned/signed
division exceeds the length of the register where the result is to be
stored; the flag is also set when the addition result is outside range
of –2147483648 to +2147483647 in the RMPA operation.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, data’s bit 15 is
“1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other
cases. It can also be set and reset with the SEP and CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7.
Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher than
the processor interrupt priority. When an interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level
of the device requesting the interrupt. Refer to the section on interrupts for more details.
Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.
15
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BANK
In order to effectively use the integrated hardware on the chip, this
CPU core uses an address generating method with a 24-bit address
split into high-order 8 bits and low-order 16 bits. In other words, the
64 Kbytes specified by the low-order 16 bits are one unit (referred to
as “bank”), and the address space is divided into 256 banks (016 to
FF16) specified by the high-order 8 bits.
In the program area on the address space, the bank is specified by
the program bank register (PG), and the address in the bank is
specified by the program counter (PC).
As for each bank boundary, when an overflow has occurred in PC,
the contents of PG are incremented by 1. When a borrow has occurred in PC, the contents of PG are decremented by 1. Under the
normal conditions, therefore, programming without concern for the
bank boundaries is possible. Furthermore, as for the data area on
the address space, the bank is specified by the data bank register
(DT), and the address in the bank is specified by the operation result
by using the various addressing modes (Note).
Note: Some addressing modes directly specify a bank.
DIRECT PAGE
The internal memory and control registers for internal peripheral devices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The
direct page and direct addressing modes have been provided for the
effective access to bank 016. In the 7900 Series, two types of direct
addressing modes are available: the conventional direct addressing
mode which uses only DPR0, as in the 7700 Series, and the expanded direct addressing mode, which uses up to 4 direct page registers as selected by the user. The addressing mode is selected
according to the contents of bit 1 of the processor mode register 1.
This bit 1 is cleared to “0” at reset. (In other words, the conventional
direct addressing mode is selected.) However, once this bit 1 has
been set to “1” by software, this bit cannot be cleared to “0” again,
except by reset. That is to say, when one of these two direct addressing modes has been selected just after reset, the selected addressing mode cannot be switched to another one while the program is
running.
■ Conventional direct addressing mode
The direct page area consists of 256-byte space. Its bank address is
“0016”, and the base address of its low-order 16-bit address is specified by the contents of the direct page register 0 (DPR0). In this conventional direct addressing modes, a value (1 byte) just after an
instruction code is regarded as an offset value for the DPR0 contents, and the CPU accesses each address in the direct page area.
■ Expanded direct addressing mode
The direct page area consists of four 64-byte spaces. Their bank
address is “0016”, and the four base addresses of their low-order 16bit addresses are respectively specified by the contents of four direct
page registers. In this expanded direct addressing mode, a value (1
byte) just after an instruction code is regarded as follows:
• High-order 2 bits: regarded as a selection field for DPR0 to DPR3.
• Low-order 6 bits: regarded as an offset value for the selected direct
page register.
Then, the CPU accesses each address in each direct page area:
16
Refer to “7900 Series Software Manual” for details concerning the
various addressing modes which use the direct page area.
Instruction Set
The CPU core of the 7900 Series has an expanded instruction set
based on the existing 7700/7751 Series’ CPU core. In addition, its
source code (mnemonic) has the complete upper compatibility with
the 7700 Series instruction set.
For details concerning addressing modes and instruction set, refer to
“7900 Series Software Manual”.
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BUS INTERFACE UNIT
Data transfer between the central processing unit (CPU) and internal memory, internal peripheral devices, or external areas is always
performed via the bus interface unit (BIU), which is located between
the CPU and the internal buses.
Figure 10 shows the BIU and the bus structure. The CPU and BIU
are connected by a dedicated bus, and any transfer between the
CPU and BIU is controlled by this dedicated bus.
On the other hand, data transfer between the BIU and internal peripheral devices uses the following internal common buses: 32-bit
code bus, 16-bit data bus, 24-bit address bus, and control signals.
The bus control method where the code bus and the data bus separate out (hereafter, this method is referred to as the separate code/
data bus method) is employed in order to improve data transfer capabilities. As a result, the internal memory is connected to both the
code bus and the data bus, and registers of all other internal peripheral devices are connected only to the data bus.
Each width of external buses are as follows: a 24-bit address bus,
16-bit data bus.
The external data bus transfers instruction codes and data. When
the code or data access occurs for the external, the external access
is performed via the bus conversion circuit.
For details of the connection with the external devices, refer to the
section on the processor modes and chip select wait controller described later.
M37902
Internal buses
CPU bus
Internal code bus (CB0 to CB31)
Central
Processing
Unit
Bus
Interface
Unit
(CPU)
(BIU)
Internal data bus (DB0 to DB15)
Internal address bus (AD0 to AD23)
Internal
memory
Internal control signal
Internal
peripheral
devices
(SFR)
External bus
A0 to A23
Bus
conversion
circuit
D0 to D7 (LA0 to LA7)
D8 to D15
External
devices
Control signal
Hold request
HOLD
HLDA
SFR : Special Function Register
❈ The CPU bus, internal bus, and external bus separate out independently.
Fig. 10 BIU and bus structure
17
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BIU structure
The BIU consists of four registers shown in Figure 11. Table 1 lists
the functions of each register.
Table 1. Functions of each register
Name
Program address register
Functions
Indicates a storage address for an instruction to be next taken into an instruction queue buffer.
Instruction queue buffer
Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes.
Data address register
Indicates an address where data will be next read from or written to.
Data buffer
Temporarily stores data which has been read from internal memory, internal peripheral devices, and
external areas by the BIU; or temporarily stores data which is to be written to internal memory, internal
peripheral devices, and external areas by the CPU. Consists of 32 bits.
b23
b0
Program address register
PA
b7
b0
Q0
Instruction queue buffer
Q9
b23
b0
Data address register
DA
b31
b0
DQ
Fig.11 Register structure of BIU
18
Data buffer
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BIU Functions
(1) Instruction prefetch
The BIU has ten instruction queue buffers; each buffer consists of 1
byte. When there is an opening in the bus and the instruction queue
buffer, an instruction code is read from the program memory (in other
words, the memory where a program is stored) and prefetched into
an instruction queue buffer. The prefetched instruction code is transferred from the BIU to the CPU, in response to a request from the
CPU, via a dedicated bus.
When a branch occurs as a result of a branch instruction (JMP, BRA,
etc.), subroutine call, or interrupt, the contents of the instruction
queue buffer are initialized and the BIU reads a new instruction from
the branch destination address.
Note that the operations of the BIU instruction prefetch also differ depending on the store addresses for instructions. The store addresses
for instructions to be prefetched are categorized as listed in Table 2.
(2) Data read operation
When executing an instruction for reading data from the internal
memory, internal peripheral devices, or external areas, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU reads the above data from the specified address,
passes it to the data buffer, and then, transfers it to the CPU.
(3) Data write operation
When executing an instruction for writing data into the internal
memory, internal peripheral devices, or external area, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU passes the above data to the data buffer register, and
then, writes it into the specified address.
(4) Bus cycle
In order for the BIU to execute the above operations (1) through (3),
the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal
control signals must be appropriately controlled during data transfer
between the BIU and internal memory, internal peripheral devices,
external areas. This operation is called “bus cycle”. The bus cycle is
affected by the following conditions at instruction prefetch and data
access.
[Instruction prefetch]
• Whether the address area locates in the internal area or the external area.
• When the address area locates in the external area
➀ Whether the external bus width = 16 bits or 8 bits:
(a) When the external bus width = 16 bits:
whether the start address for access locates at a 4byte boundary or at an 8-byte boundary.
(b) When the external bus width = 8 bits:
whether the start address for access locates at an
even address, a 4-byte boundary or at the 8-byte bound
ary.
➁ Whether the prefetch operation is generated by a branch, or
not.
➂ Number of waits
➃ Whether the burst ROM access is specified or not.
Table 2. Store addresses for instructions to be prefetched
Low-order 3 bits of store address for instruction
AD2 (A2)
AD1 (A1)
AD0 (A0)
X
0
X
Even address
4-byte boundary
X
0
0
8-byte boundary
0
0
0
X: 0 or 1
[Data Access]
• Whether the address area locates in the internal area or the external area.
• Length of data to be transferred: byte, word, double word
• When the address area locates in the external area:
➀ Whether the external bus width = 16 bits or 8 bits:
➁ Number of waits
The BIU controls the bus cycle depending on the above conditions.
Figures 12 to 16 show the bus cycle waveform examples for instruction prefetch and data access.
19
20
Internal code bus
CB0 to CB31
Internal address bus Address
φBIU
Code
When branched or at instruction
prefetch
Access to internal area
φ1
D0 to D7
Fig. 12 Bus cycle waveform example for instruction prefetch
BHW
φ1
D8 to D15
D8 to D15
D0 to D7
Address + 6
φ1
D0 to D7
A0 to A23
RD
BLW
BHW
RD
BLW
BHW
ALE
D8 to D15
D8 to D15
D8 to D15
D0 to D7
Address + 4
ALE
D0 to D7
Address + 2
D0 to D7
Address
D0 to D7
A0 to A23
D0 to D7
Address
D0 to D7
Address + 1
D0 to D7
Address
D0 to D7
Address + 1
D0 to D7
Address + 2
D0 to D7
Address + 3
When address of instruction to be prefetched locates at 4-byte boundary or
8-byte boundary: quadruple consecutive access
BHW
BLW
When address of instruction to be prefetched locates at 8-byte boundary:
quadruple consecutive access
RD
BLW
RD
ALE
D8 to D15
D8 to D15
D8 to D15
φ1
A0 to A23
ALE
D0 to D7
Address + 2
D0 to D7
Address
D0 to D7
A0 to A23
When external data bus width = 8 bits
When address is even address or when branched:
double consecutive access
Access to external area
When address locates at 4-byte boundary or when branched:
double consecutive access
When external data bus width = 16 bits
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even address
Access starting from odd address
φBIU
8-bit
data
read
Internal address bus
φBIU
Address
Internal data bus
Internal address bus
D0 to D7
DB0 to DB7
φBIU
8-bit
data
written
Internal address bus
Internal address bus
D0 to D7
DB0 to DB7
DB0 to DB7
DB8 to DB15
DB8 to DB15
Access to internal area
Internal address bus
D0 to D7
Internal data bus
DB0 to DB7
DB8 to DB15
D8 to D15
DB0 to DB7
DB8 to DB15
φ1
16-bit
data
written
A0 to A23
D0 to D7
D0 to D7
D8 to D15
D8 to D15
D8 to D15
φBIU
32-bit
data
read
Internal data bus
DB0 to DB7
DB8 to DB15
32-bit
data
written
DB0 to DB7
DB8 to DB15
Address + 1
Invalid
D0 to D7
D8 to D15
Invalid
Address
Address + 1
D0 to D7
D8 to D15
φBIU
Address
Internal address
bus
Address + 2
D0 to D7
D0 to D7
Internal data bus
D8 to D15
D8 to D15
DB0 to DB7
DB8 to DB15
D0 to D7
D0 to D7
Internal address
bus
Internal data bus
D8 to D15
D8 to D15
φBIU
Internal address
bus
Internal data bus
Address
φ1
Address
D0 to D7
Internal address
bus
D8 to D15
φBIU
Address
Internal data bus
A0 to A23
Address
Internal data bus
φBIU
16-bit
data
read
D8 to D15
φBIU
Address
Internal data bus
Internal address bus
Invalid
DB0 to DB7
DB8 to DB15
Invalid
DB8 to DB15
Address
Internal data bus
Address
Address + 1
Address + 3
Invalid
D0 to D7
D0 to D7
D8 to D15
D8 to D15
Invalid
φBIU
Address
Address + 2
Address
D0 to D7
DB0 to DB7
DB8 to DB15
Address + 1
D8 to D15
Address + 3
D0 to D7
D8 to D15
Fig. 13 Bus cycle waveform example for data access (access to internal area)
21
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even address
φ1
A0 to A23
8-bit
data
read
φ1
Address
D0 to D7
Invalid
D8 to D15
Invalid
D8 to D15
D8 to D15
ALE
ALE
RD
RD
BLW
BLW
BHW
BHW
External data bus width = 16 bits
D0 to D7
φ1
Address
D0 to D7
ALE
ALE
RD
RD
BLW
BLW
BHW
BHW
φ1
Address
D0 to D7
D8 to D15
D8 to D15
φ1
Address
A0 to A23
Address
Address + 1
D0 to D7
D7 to D0
D0 to D7
Invalid
D0 to D7
D8 to D15
D8 to D15
D8 to D15
D8 to D15
Invalid
ALE
ALE
RD
RD
BLW
BLW
BHW
BHW
φ1
A0 to A23
φ1
Address
A0 to A23
D0 to D7
D0 to D7
D0 to D7
D8 to D15
D8 to D15
D8 to D15
ALE
ALE
RD
RD
BLW
BLW
BHW
BHW
Fig. 14 Bus cycle waveform example for data access (access to external area) (1)
22
A0 to A23
D8 to D15
A0 to A23
16-bit
data
written
Address
D0 to D7
φ1
16-bit
data
read
A0 to A23
D0 to D7
A0 to A23
8-bit
data
written
Access starting from odd address
Address
Address + 1
D0 to D7
D8 to D15
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even address
φ1
External data bus width = 16 bits
A0 to A23
32-bit
data
read
φ1
Address
Address + 2
A0 to A23
Address
Address + 1
Address + 3
D0 to D7
D0 to D7
D0 to D7
D0 to D7
Invalid
D0 to D7
D0 to D7
D8 to D15
D8 to D15
D8 to D15
D8 to D15
D8 to D15
D8 to D15
Invalid
ALE
ALE
RD
RD
BLW
BLW
BHW
BHW
φ1
A0 to A23
32-bit
data
written
Access starting from odd address
φ1
Address
Address + 2
A0 to A23
D0 to D7
D0 to D7
D0 to D7
D0 to D7
D8 to D15
D8 to D15
D8 to D15
D8 to D15
ALE
Address
Address + 1
D0 to D7
D8 to D15
Address + 3
D0 to D7
D8 to D15
ALE
RD
RD
BLW
BLW
BHW
BHW
Fig. 15 Bus cycle waveform example for data access (access to external area) (2)
23
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even or odd address
φ1
A0 to A23
External data bus width = 8 bits
D0 to D7
32/16/
8-bit
data
read
Address
Address + 1
D0 to D7
Address + 2
D0 to D7
D0 to D7
Address + 3
D0 to D7
D8 to D15
(Note)
ALE
RD
BLW
BHW
(Note)
8-bit data access
16-bit data access
32-bit data access
φ1
A0 to A23
D0 to D7
32/16/
8-bit
data
written
Address
Address + 1
D0 to D7
Address + 2
D0 to D7
D0 to D7
Address + 3
D0 to D7
D8 to D15
(Note)
ALE
RD
BLW
BHW
(Note)
8-bit data access
16-bit data access
32-bit data access
Note: When the voltage level at pin BYTE = “L”, functions as pins D8 to D15 are valid. However, when 8-bit width is selected
as the external bus width by the chip select wait controller, the functions as pins D8 to D15 and BHW become invalid.
(D8 to D15 = floating, BHW = “H” output.) When the voltage level at pin BYTE = “H”, these pins function as programmable
I/O port (P2, P33) pins.
Fig. 16 Bus cycle waveform example for data access (access to external area) (3)
24
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Number of bus cycles
Figure 17 shows the bus cycle waveform at access to the internal
area. Bit 7 of the processor mode register 1 (address 5F16) selects
the number of bus cycles for the internal ROM: 3φ or 2φ. (This bit 7 is
the internal ROM bus cycle select bit.) The internal RAM, SFRs (in-
ternal peripheral devices’ control registers) are always accessed with
1 bus cycle = 2φ. Figure 18 shows the bus cycle waveform at access
to the external area. The bus cycle select bits 0, 1 (See the note in
___
Figure 18.) select the number of the bus cycles for each CSi area
from 8 types of numbers.
1 bus cycle = 3φ (Note)
1 bus cycle = 2φ
(Internal ROM bus cycle select bit = 0)
(Internal ROM bus cycle select bit = 1)
1 bus cycle = 2φ
1 bus cycle = 3φ
φBIU
ROM
Internal address bus
φBIU
Internal address bus
Address
Internal data bus
Internal code bus
Internal data bus
Internal code bus
Data
Address
Data
1 bus cycle = 2φ
RAM
φBIU
Internal address bus
SFR
Internal data bus
Internal code bus
Address
Data
Note: When reprogramming the internal flash memory in the CPU reprogramming mode, select the bus cycle = 3φ.
Fig. 17 Bus cycle waveform at access to internal area
25
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus cycle
select bit 0
Bus cycle select bit 1 = 0
Bus cycle select bit 1 = 1
❈
Bus cycle 1φ + 1φ
Bus cycle 2φ + 3φ
1 bus cycle = 2φ
00
External address
bus
External data bus
φ1
External address
bus
Address
CSi
CSi
RD
BLW,BHW
RD
BLW,BHW
ALE
ALE
❈
φ1
φ1
External address
bus
Address
CSi
CSi
RD
BLW,BHW
RD
BLW,BHW
ALE
ALE
❈
Data
1 bus cycle = 6φ
3φ
φ1
External address
bus
Address
External data bus
Data
Address
External data bus
CSi
CSi
RD
BLW,BHW
RD
BLW,BHW
ALE
ALE
Data
Bus cycle 3φ + 4φ
1 bus cycle = 4φ
1 bus cycle = 7φ
4φ
3φ
φ1
φ1
External address
bus
Address
External data bus
Data
External data bus
CSi
CSi
RD
BLW,BHW
RD
BLW,BHW
ALE
ALE
Notes 1: The bus cycle type is determined by the following bits:
• Areas out of area CSi : external bus cycle select bit 0 (bits 2 and 3 at address 5E16)
external bus cycle select bit 1 (bit 0 at address 5F16)
: area CSi bus cycle select bit 0 (bits 0 and 1 at addresses 8016, 8216, 8416, 8616)
• Area CSi
area CSi bus cycle select bit 1 (bit 3 at addresses 8116, 8316, 8516, 8716)
2: ❈ indicates the bus cycle, where the burst ROM access specification is enabled.
Fig. 18 Bus cycle types at access to external area
26
3φ
φ1
Bus cycle 2φ + 2φ
11
Address
Bus cycle 3φ + 3φ
1 bus cycle = 4φ
External address
bus
4φ
External data bus
Data
Bus cycle 1φ + 3φ
10
❈
1 bus cycle = 6φ
2φ
External address
bus
External address
bus
Data
Bus cycle 2φ + 4φ
1 bus cycle = 3φ
External data bus
Address
External data bus
Data
Bus cycle 1φ + 2φ
01
3φ
2φ
φ1
❈
1 bus cycle = 5φ
Address
Data
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Recovery cycle
A recovery cycle which is equivalent to 1 or 2 cycles of φ1 can be in___
serted after each area CSi’s access cycle. Whether the recovery
cycle is inserted or not is determined by the recovery cycle insert
___
select bit of each CSi control register L (bit 6 at addresses 8016, 8216,
8416, 8616). Also, the number of the recovery cycles is selected by
the recovery-cycle-insert-number select bit of the processor mode
register 1 (bit 6 at address 5F16). Figure 19 shows a waveform example when a recovery cycle is inserted.
At double consecutive
access
Recovery cycle = 1 cycle of φ1
At instruction prefetch
At quadruple consecutive
access ❈❈
❈
Instruction prefetch
A0 to A23
Recovery cycle
Instruction prefetch
Next access
cycle
φ1
φ1
Address
A0 to A23
Address + 2
ALE
ALE
RD
RD
Address
Address + 2
❈ When address locates at 4-byte boundary, or when branched.
Instruction prefetch
Recovery
cycle
φ1
A0 to A23
Next access
cycle
Instruction prefetch
Recovery cycle
Next access
cycle
φ1
Address
Address + 2
Address + 4
Address + 6
A0 to A23
ALE
ALE
RD
RD
Address
Address + 2
Address + 4
Address + 6
❈❈ When address locates at 8-byte boundary.
Access cycle
At data access
Recovery cycle = 2 cycles of φ1
Recovery
Next access
cycle
cycle
Recovery
cycle
Next access
cycle
A0 to A23
Access cycle
Recovery cycle
Next access
cycle
φ1
φ1
Address
A0 to A23
ALE
ALE
RD,
BLW, BHW
RD,
BLW, BHW
Address
Notes 1: The recovery cycle insert is specified by the recovery cycle insert select bit and the recovery-cycle-insert-number select bit (bits 4 and 6 at address 5F16).
Recovery cycle insertion is valid only at access to area CSi.
2: The above is applied when 1 bus cycle = 2φ.
Fig. 19 Waveform example when recovery cycle is inserted
27
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Burst ROM access
When ROM supporting the burst ROM access has been allocated to
___
area CSi, the burst ROM access can be specified. The burst ROM
___
access is specified by each burst ROM access select bit of the CSi
control register L (bit 5 at addresses 8016, 8216, 8416, 8616). The
burst ROM access is valid only when the external data bus width =
16 bits with an instruction prefetched. In the other cases, the normal
access is performed regardless of the contents of the burst ROM access select bit. The burst ROM access can be specified only in the
case of ❈ in Figure 18.
At quadruple consecutive access
(a)
Figure 20 shows a waveform example at burst ROM access.
When an instruction is prefetched from the burst ROM, 8 bytes are
fetched starting from an 8-byte boundary (the low-order 3 bits of address, A2, A1, A0 = “000”) in waveform (a). When branched, regardless of the 8-byte boundary of the branch destination address,
access starting from the 4-byte boundary (the low-order 2 bits of address, A1, A0 = “00”) is performed in waveform (b). Once the 8-byte
boundary has been selected, instructions will be prefetched in waveform (a) until a branch.
φ1
RD
External address bus
(A0 to A23)
Address
Address
Address
Address
External data bus
(D0 to D7)
(Instruction)
External data bus
(D8 to D15)
Data
Data
Data
Data
(Instruction)
(Instruction)
(Instruction)
(Instruction)
Data
Data
Data
Data
(Instruction)
(Instruction)
(Instruction)
Note: The above is applied when 1 bus cycle = 2φ.
At double consecutive access
(b)
φ1
RD
External address bus
(A0 to A23)
Address
Address
External data bus
(D0 to D7)
Data
Data
(Instruction)
(Instruction)
External data bus
(D8 to D15)
Data
Data
(Instruction)
(Instruction)
Note: The above is applied when 1 bus cycle = 2φ.
Notes 1: The burst ROM access is selected by the burst ROM access select bit (bit 5 at addresses 8016, 8216, 8416, 8616).
2: The burst ROM access can be selected only in the case of ❈ in Figure 18.
Fig. 20 Waveform example at burst ROM access
28
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Address output selection
As shown in Figure 21, the unnecessary state change of address
output pins (A0 to A23) can be avoided, without outputting an address
at access to the internal area.
When the address output select bit of the particular function select
register 1 (bit 4 at address 6316) is set to “1”, an address is output
only at access to the external area. Also, at access to the internal
area, the address at the preceding access to the external area is retained. The address output start timing in this case is the half cycle
of φ1 later than that at the normal access (when the address output
select bit = “0”). For the bit structure of the particular function select
register 1, refer to the section on the standby function.
Also, at the normal access, an address is output at both of the access to the internal and external areas.
Access to
external area
Access to
internal area
Access to
external area
φ1
Address output select bit = 0
A0 to A23
Address
Undefined
Undefined
Address
RD,
BLW,BHW
Address output select bit = 1
(Address waveform changes only
when external access is generated.)
A0 to A23
Address
Address
RD,
BLW,BHW
Fig. 21 Waveform example depending on address output function selection
29
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Area multiplication
of an address (LA0 to LA7) are output, and the low-order 8 bits of
data (D0 to D7) are input/output with the time-sharing method, respectively.
Figure 22 shows a waveform example of area multiplication for each
bus cycle. Do not select the area multiplication function for a bus
cycle not shown in Figure 22.
___
When area CS2’s external data bus width = 8 bits with the multi___
plexed bus select bit of the CS2 control register H (bit 5 at address
8516) = “1”, the external bus type can be changed to the multiplexed
___
bus type only at access to area CS2. In this case, the low-order 8 bits
Area CS2 bus
Bus cycle
cycle select
select bit 0
bit 0
Multiplexed bus select bit = 1
1 bus cycle = 4φ
Bus cycle 2φ + 2φ
2φ
2φ
φ1
External address bus
0
11
Address
At write, LA0/D0 to LA7/D7
LA0 to LA7
At read, LA0/D0 to LA7/D7
LA0 to LA7
D0 to D7
D0 to D7
CSi
RD,
BLW
ALE
Bus cycle 3φ + 3φ
1 bus cycle = 6φ
3φ
3φ
φ1
External address bus
1
10
Address
At write, LA0/D0 to LA7/D7
LA0 to LA7
At read, LA0/D0 to LA7/D7
LA0 to LA7
D0 to D7
D0 to D7
CSi
RD,
BLW
ALE
Bus cycle 3φ + 4φ
1 bus cycle = 7φ
3φ
4φ
φ1
External address bus
1
11
Address
At write, LA0/D0 to LA7/D7
LA0 to LA7
At read, LA0/D0 to LA7/D7
LA0 to LA7
CSi
RD,
BLW
ALE
Notes 1: The number of bus cycles is determined by the following bits:
• Area CS2 bus cycle select bit 0 (bits 0 and 1 at address 8416)
• Area CS2 bus cycle select bit 1 (bit 3 at address 8516)
Area multiplication is specified by the multiplexed bus select bit (bit 5 at address 8516).
2: Do not select the area multiplication function for a bus cycle not shown in Figure 22.
Fig. 22 Waveform example of area multiplication for each bus cycle
30
D0 to D7
D0 to D7
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PROCESSOR MODES
function as these devices’ I/O pins.) In this mode, only the internal
area (SFRs, internal RAM, internal ROM) is accessible.
In the memory expansion and microprocessor modes, external devices assigned in the external memory area can be connected via
buses. Therefore, ports P0 to P4, P10, P11 function as I/O pins for
the address bus, data bus, bus control signals. (Some port functions
are selectable.) Table 4 lists each bus control signal’s function.
In the memory expansion mode, all of the internal area (SFRs, internal RAM, internal ROM) and external area are accessible. In the microprocessor mode, the internal area except for the internal ROM (in
other words, SFRs and internal RAM) and the external area are accessible.
Note that, when the external devices are located to an area where
the internal area and external area overlap, only the internal area
can be read/written; the external area cannot be read/written.
Any of the three processor modes (single-chip mode, memory expansion mode, microprocessor mode) can be selected with the following:
• Processor mode bits of the processor mode register 0 (bits 1 and 0
at address 5E16; Figure 24)
• Voltage level applied to pin MD0
Table 3 lists the selection method of a processor mode.
The memory map which the CPU can access depends on the selected processor mode. Figure 23 shows the memory maps in three
processor modes.
Also, the functions of ports P0 to P4, P10, P11 depend on the selected processor mode. For details, see Tables 5 and 6.
Figures 24 to 26 show the bit configurations of the processor mode
registers 0, 1, and port function control register.
In the single-chip mode, ports P0 to P4, P10, P11 function as I/O
ports. (While the internal peripheral devices are used, these ports
Single-chip mode
Memory expansion mode
Microprocessor mode
SFR area
SFR area
SFR area
Internal RAM
area
Internal RAM
area
016
FF16
Unused area
Internal RAM
area
Unused area
Internal ROM
area
Internal ROM
area
FEFFFF16
FF000016
FFFFFF16
Reserved area
Reserved area
(Note)
(Note)
SFR area : Internal peripheral devices’ control registers are allocated here.
External area : Access to this area enables the access to the devices which
are connected with the external.
Note: Do not access this area (bank FF16).
Fig. 23 Memory maps in three processor modes
31
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 3. Selection method of processor mode
MD0
VSS
VCC
Processor mode bits
00
01
10
10
(Note 1)
(Note 2)
Processor mode
Description
Single-chip mode
Memory expansion mode
Microprocessor mode
Microprocessor mode
After reset is removed, the single-chip mode is selected. By changing the processor mode bits’ contents by software, the memory expansion mode or microprocessor mode can be selected.
After reset is removed, the microprocessor mode is selected.
Notes 1: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E16)
2: While the Vcc level voltage is applied to pin MD0, the processor mode bits are fixed to “10”.
Table 4. Each bus control signal’s function
Signal
RD
I/O
Function
Output Read signal. Outputs “L” at read from the external area.
Remarks
BLW
BHW
ALE
Output Write signal. Outputs “L” at write to the external area.
For operation differences between BLW and BHW depending on the external data bus width, see Table 5.
In order to latch an address with signal ALE, do as follows:
• While ALE = “H”, be sure to open a latch, so the address
will pass it.
• While ALE = “L”, be sure to hold the address.
φ1
Output Internal standard clock’s output. Outputs system clock
(fsys).
Input Ready signal. The “L” level period of the last φ1 in the access cycle for the external area (in other words, “L” level
period of RD, BLW, BHW) will be extended while “L” level
voltage is applied to this pin.
Input Hold request signal. Appliance of “L” level voltage will generate a hold request; appliance of “H” level voltage will request to terminate the hold state.
Output Hold acknowledge signal. Outputs “L” in the hold state.
RDY
HOLD
HDLA
CS0–CS3
BYTE
32
Output Address latch enable signal. Outputs “H” level pulse in the
period just before signals RD, BLW, BHW become “L”.
This is used to latch an address in an external circuit.
Output Chip select signal. Outputs “L” in access to the specified
chip select area.
Input Input signal to select the external data bus width. When
this pin’s level = Vss, 16-bit width will be selected; and
when Vcc, 8-bit width will be selected.
Acceptance and termination of a hold request is performed
at completion of the bus cycle while the BIU operates.
In the hold state, A0–A23, D0–D15, RD, BLW, BHW, ALE,
CS0–CS3 enter the floating state. At termination of the hold
state, simultaneously with the timing when HLDA becomes
“H” level, the above floating state is terminated. Then, bus
access will be restarted 1 cycle of φ1 after.
In the hold state, also, the CPU operates with access to
the internal area. If the CPU accesses the external area, in
the hold state, the CPU stops its operation.
For details, refer to the section on the chip select wait controller.
When BYTE = Vss level, by the register setting, each chip
select area (CS1 to CS3) can have the 8-bit data bus, independently.
For details, refer to the section on the chip select wait controller.
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory area
Table 5. Relationship between processor modes, memory area, and port function (1)
Single-chip mode
Memory expansion mode
VSS level voltage is applied
VSS level voltage is applied
Pin
MD0
Mode
(Note 1) Processor mode
00
01
bits (Note 2)
SFR area
SFR area
SFR area
Internal RAM area
Internal RAM area
Internal RAM area
Internal ROM area
Internal ROM area
Internal ROM area
(Do not access.)
External memory area
Other area
I/O port pins P100 to P107
Low-order address (A0 to A7) is output.
Port pins P100 to P107
I/O port pins P110 to P117
Middle-order address (A 8 to A15 ) is
Port pins P110 to P117
output.
I/O port pins P110 to P117 (Note 3)
I/O
port
pins
P0
0
to
P0
7
High-order address (A16 to A23) is outPort pins P00 to P07
put.
I/O port pins P00 to P07 (Note 3)
External data bus I/O port pins P10 to P17
Low-order data (D 0 to D 7 , data at
width = 16 bits
even address) is input/output.
Low-order data (D 0 to D 7 , data at
External data bus
even/odd address) is input/output.
Port pins width = 8 bits
Low-order address (LA0 to LA7) is outP10 to P17
put. Low-order data (D0 to D7, data at
even/odd address) is input/output
(Note 4).
External data bus I/O port pins P20 to P27
High-order data (D8 to D 15, data at
width = 16 bits
odd address) is input/output.
Port pins
I/O port pins P20 to P27 (Note 5)
P20 to P27 External data bus
width = 8 bits
I/O port pin P30
I/O port pin P30
Port pin P30
Ready signal RDY is input (Note 6).
I/O port pin P31
Port pin P31
Read signal RD is output.
Write signal BLW (write to even adExternal data bus I/O port pin P32
dress) is output.
Port pin width = 16 bits
P32
External data bus
Write signal BLW (write to even/odd
width = 8 bits
address) is output.
Write signal BHW (write to odd adExternal data bus I/O port pin P33
dress) is output.
Port pin width = 16 bits
P33
External data bus
I/O port pin P33 (Note 5)
width = 8 bits
Microprocessor mode
VCC level voltage is applied
10
SFR area
Internal RAM area
External memory area
External memory area
Low-order address (A0 to A7) is output.
Middle-order address (A 8 to A15) is
output.
I/O port pins P110 to P117 (Note 3)
High-order address (A16 to A23) is output.
I/O port pins P00 to P07 (Note 3)
Low-order data (D 0 to D 7 , data at
even address) is input/output.
Low-order data (D 0 to D 7 , data at
even/odd address) is input/output.
Low-order address (LA0 to LA7) is output. Low-order data (D0 to D7, data at
even/odd address) is input/output
(Note 4).
High-order data (D8 to D15, data at
odd address) is input/output.
I/O port pins P20 to P27 (Note 5)
Ready signal RDY is input.
I/O port pin P30 (Note 6)
Read signal RD is output
Write signal BLW (write to even address) is output.
Write signal BLW (write to even/odd
address) is output.
Write signal BHW (write to odd address) is output.
I/O port pin P33 (Note 5)
33
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 6. Relationship between processor modes, memory area, and port function (2)
Single-chip mode
I/O port pin P40
Memory expansion mode
I/O port pin P40
I/O port pin P41
Clock φ1 is output (Note 6).
I/O port pin P42
Address latch enable signal
ALE is output (Note 6).
I/O port pin P41
Clock φ1 is output (Note 6).
I/O port pin P42
I/O port pin P43
Hold acknowledge signal
HLDA is output (Note 6).
I/O port pin P43
Port pin P40
Port pin P41
Port pin P42
Port pin P43
Port pin P44
I/O port pin P44
Port pins P45 to P47 I/O port pins P45 to P47
Hold request signal
HOLD is input (Note 6).
I/O port pin P44
Chip select signal CS0 is output
(Note 7).
I/O port pins P45 to P47
Chip select signals CS1 to CS3 are
output (Note 8).
Microprocessor mode
Address latch enable signal
ALE is output.
I/O port pin P40 (Note 6)
Clock φ1 is output.
I/O port pin P41 (Note 6)
Hold acknowledge signal
HLDA is output.
I/O port pin P42 (Note 6)
Hold request signal
Signal HOLD is input.
I/O port pin P43 (Note 6)
Chip select signal CS0 is output.
I/O port pin P45 to P47
Chip select signals CS1 to CS3 are
output (Note 8).
Notes 1: For details of the processor mode setting, see Table 3.
2: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E16).
3: The middle-order/high-order address output pins in the memory expansion or microprocessor mode can be switched to I/O port pins by the address/port
switch select bits of the port function control register (bits 2 to 0 at address 9216).
4: When the external data bus width for the chip select area, CS2, has been set to 8 bits, only in the access to area CS2, by the multiplexed bus select bit
of the CS2 control register H (bit 5 at address 8516), a multiplexed bus which performs the following operations with the time-sharing method is realized:
• Output of address LA0 to LA7
• Input/Output of data D0 to D7
5: When one of areas CS1/CS2/CS3 is accessed under the following conditions, pins D8 to D15 enter the floating state, and pin BHW outputs “H” level.
(They do not become I/O port pins.)
• Pin BYTE is at Vss level.
• One of bit 2s at addresses 8216, 8416, 8616 (the external data bus width select bit of the CS1/CS2/CS3 control register L) is set to “1” (external data bus
width = 8 bits).
6: In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E16, 5F16), port pins P30, P40 to
P43 can operate as pins for RDY input, ALE output, φ1 output, HLDA output, HOLD input, respectively.
In the microprocessor mode, by the above select bits, the above pins (RDY, ALE, φ1, HLDA, HOLD) can operate as port pins P30, P40 to P43, respectively.
In the single-chip mode, port pin P41 can operate as the φ1 output pin by the above select bits.
7: In the memory expansion mode, port pin P44 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address
8016).
8: In the memory expansion and microprocessor modes, port pins P45 to P47 can operate as the CS1/CS2/CS3 output pins by the CSi output select bits (i =
1 to 3) (bit 7s at addresses 8216, 8416, 8616).
34
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Processor mode register 0
Address
5E16
Processor mode bits (Note 1)
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
External bus cycle select bit 0 (Note 2)
See Figure 18.
Interrupt priority detection time select bits
0 0 : 7 cycles of fsys
0 1 : 4 cycles of fsys
1 0 : 2 cycles of fsys
1 1 : Do not select.
Software reset bit
By a write of “1” to this bit, the microcomputer will be reset, and then, restarted.
Clock φ1 output select bit (Note 3)
0 : φ1 output is disabled. (P41 functions as an programmable I/O port pin.)
1 : φ1 output is enabled. (P41 functions as the clock φ1 output pin.)
Notes 1: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied
to pin MD0, on the other hand, this bit’s state is set to “1” at reset. (Fixed to “1”.)
2: These bits are valid to the external area except for chip select area (area CSi). The bus cycle of area CSi is selected
by the corresponding area CSi bus cycle select bits 0, 1.
3: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied
to pin MD0, on the other hand, this bit’s state is set to “1” at reset.
Fig. 24 Bit configuration of processor mode register 0
35
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Processor mode register 1
Address
5F16
External bus cycle select bit 1 (Note 1)
See Figure 18.
Direct page register switch bit (Note 2)
0 : Only DPR0 is used.
1 : DPR0 to DPR3 are used.
RDY input select bit (Notes 3 to 5)
0 : RDY input is disabled. (P30 functions as a programmable I/O port pin.)
1 : RDY input is enabled. (P30 functions as pin RDY.)
ALE output select bit (Notes 3 and 4)
0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.)
1 : ALE output is enabled. (P40 functions as pin ALE.)
Recovery cycle insert select bit (Notes 3 and 4)
0 : No recovery cycle is inserted at access to the external area.
1 : Recovery cycle is inserted at access to the external area.
HOLD input, HLDA output select bit (Notes 3 to 5)
0 : HOLD input and HLDA output are disabled.
(P43 and P42 function as programmable I/O port pins.)
1 : HOLD input and HLDA output are enabled.
(P43 and P42 function as pins HOLD and HLDA, respectively.)
Recovery-cycle-insert number select bit (Note 6)
0 : 1 cycle
1 : 2 cycles
Internal ROM bus cycle select bit (Note 7)
0 : 3φ
1 : 2φ
Notes 1: This bit is valid to the external area except for chip select areas (area CSi), and the bus cycle of area CSi is independent
of this bit’s contents.
The bus cycle of area CSi is selected by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016,
8216, 8416, 8616; bit 3 at addresses 8116, 8316, 8516, 8716).
2: After reset, this bit’s contents can be switched only once. During the software execution, be sure not to switch this bit’s contents.
3: In the single-chip mode, these bits’ functions are disabled regardless of these bits’ contents.
4: While VSS level voltage is applied to pin MD0, each of these bits is “0” at reset. While VCC level voltage is applied
to pin MD0, on the other hand, each of these bits is “1” at reset.
5: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”.
After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer.
6: The program which switches this bit’s contents must be assigned to the internal area.
7: In the microprocessor mode, this bit is invalid.
When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to “0”.
Fig. 25 Bit configuration of processor mode register 1
36
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
0
0
4
3
2
1
0
Port function control register
Address
9216
At reset
0016
Address/Port switch select bits
000 : A0 to A23 (16 Mbytes)
001 : A0 to A21, P06, P07 (4 Mbytes)
010 : A0 to A19, P04 to P07 (1 Mbytes)
011 : A0 to A17, P02 to P07 (256 Kbytes)
100 : A0 to A15, P00 to P07 (64 Kbytes)
101 : Do not select.
110 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
111 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
Port P0 input level select bit
0 : VIH = 0.7VCC, VIL = 0.2VCC
1 : VIH = 0.43VCC (Note 1), VIL = 0.16VCC
Pins P44–P47 pullup select bit (Notes 2 and 3)
0 : Pins P44–P47 are pulled up.
1 : Pins P44–P47 are not pulled up.
Fix these bits to “0”.
Pin NMI pullup select bit (Note 2)
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up.
Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5VCC.
2: When MD1 = VCC and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are
not pulled up, regardless of these bits’ contents.
3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bit’s contents.
Fig. 26 Bit configuration of port function control register
37
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Chip select wait controller
By the control of the chip select wait controller (CSWC), the chip select function for the maximum of 4 blocks can be set at the bus access to the external area.
Also, by the setting of the CSWC, port pins P44 to P47 can operate
as chip select output pins (CS0 to CS3).
Figure 27 shows a chip select output waveform example.
This chip select function determines the following items of the chip
select area: start address, address’s block size, wait number, external data bus width, RDY control validity, burst ROM specification,
recovery cycle insertion validity, and area multiplication validity.
For the external area except for areas CS0 to CS3, the processor
mode registers 0, 1 determine the above items. After reset is removed, when the microcomputer starts it’s operation in the microprocessor mode, area CS0 is automatically selected.
Table 7 lists the function of areas CS0 to CS3.
Figure 28 shows the bit configuration of the CS0/CS1/CS2/CS3 control register Ls. These registers determine the following items of a
device to be connected: wait number, external data bus width (Note:
The external data bus width of area CS0 is determined by pin BYTE’s
level.), RDY control validity, burst ROM access specification, recovery cycle insertion validity, and output validity of CS0 to CS3.
Figure 29 shows the bit configuration of the CS0/CS1/CS2/CS3 control register Hs. These registers determine block size, etc. of an external area to be connected. For areas CS0 to CS2, by selecting
mode 1 with the area CSk setting mode select bit, an chip select area
can be set to the external area in bank 0.
Figures 30 shows the bit configuration of the area CS0/CS1/CS2/CS3
start address registers. For details of these addresses’ setting, see
Figures 31 to 33.
38
When area CSi is accessed
One access
cycle
φ1
A0 to A23
Address
CSi
ALE
RD,
BLW, BHW
When the same area CSi is accessed sequentially
One access
cycle
One access
cycle
Address
Address + 2
φ1
A0 to A23
CSi
ALE
RD,
BLW, BHW
Fig. 27 Chip select output waveform example
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 7. Function of areas CS0 to CS3
CS0
Mode 0
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Mode 1
Bank 016
CS1, CS2
Mode 0
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Mode 1
Bank 016
CS3
External area except
for CS0 to CS3
Bus cycle
Bus cycle:
•1φ + 1φ
•1φ + 2φ
•1φ + 3φ
•2φ + 2φ
•2φ + 3φ
•2φ + 4φ
•3φ + 3φ
•3φ + 4φ
(Selected by bits 0, 1 at address
8016 and bit 3 at address 8116.)
Bus cycle:
•1φ + 1φ
•1φ + 2φ
•1φ + 3φ
•2φ + 2φ
•2φ + 3φ
•2φ + 4φ
•3φ + 3φ
•3φ + 4φ
(Selected by bits 0, 1 at addresses
8216, 8416 and bit 3 at addresses
8316, 8516.)
External data bus
width
Determined by pin BYTE’s level.
When BYTE = VSS level, 8-bit width
or 16-bit width can be selected
arbitrary (Note 1). (Selected by bit 2
at addresses 8216, 8416.)
RDY control
Valid (Selected by bit 2 at address
5F16 and bit 3 at address 8016.)
Valid (Selected by bit 2 at address
5F16 and bit 3 at addresses 8216,
8416.)
Burst ROM access
(Notes 2, 3)
Recovery cycle
insertion
Area multiplexed bus
access (Note 3)
Address output
selection (Note 5)
Available.
Available.
Banks 216
to FE16
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
Bus cycle:
•1φ + 1φ
•1φ + 2φ
•1φ + 3φ
•2φ + 2φ
•2φ + 3φ
•2φ + 4φ
•3φ + 3φ
•3φ + 4φ
(Selected by bits
0, 1 at address
8616 and bit 3 at
address 8716.)
When BYTE =
VSS level, 8-bit
width or 16-bit
width can be
selected arbitrary
(Note 1).
(Selected by bit 2
at address 8616.)
Valid (Selected by
bit 2 at address
5F16 and bit 3 at
address 8616.)
Available.
Available.
Available.
Available.
Available.
Not available.
CS1: Not available.
CS2: Available. (Note 4)
Available.
Not available.
Not available.
Available.
Available.
Space where start
address can be set
Block size
Available.
128 Kbytes,
256 Kbytes,
512 Kbytes,
1 Mbytes,
2 Mbytes,
4 Mbytes,
or 8 Mbytes
4 Kbytes
or 8 Kbytes
Bus cycle:
•1φ + 1φ
•1φ + 2φ
•1φ + 3φ
•2φ + 2φ
•2φ + 3φ
•2φ + 4φ
•3φ + 3φ
•3φ + 4φ
(Selected by bits
2, 3 at address
5E16 and bit 0 at
address 5F16.)
Determined by
pin BYTE’s level
Valid (Selected by
bit 2 at address
5F16.)
Not available.
Notes 1: When BYTE = Vcc level, the external data bus width is fixed to 8 bits.
2: Burst ROM access is valid only when the external data bus width is 16 bits at instruction prefetch.
3: Burst ROM access and area multiplexed bus access cannot be used at the same time.
4: Valid only when area CS2 is accessed with the 8-bit external data bus width.
5: Selected by the address output select bit (bit 4 at address 6316). The address output selection for each area is not available.
39
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
CS0 control register L
Address
8016
At reset
4216
Area CS0 bus cycle select bit 0
See Figure 18.
External data bus width select bit (Note 1)
0 : 16-bit width
1 : 8-bit width
RDY control bit (Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
“0” at read.
Burst ROM access select bit (Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CS0.
1 : Recovery cycle is inserted at access to area CS0.
CS0 output select bit (Notes 4, 5)
0 : CS0 output is disabled. (P44 functions as a programmble I/O port pin.)
1 : CS0 output is enabled. (P44 functions as pin CS0.)
Notes 1: While VSS level voltage is applied to pin BYTE, this bit’s state is cleared to “0” at reset. While VCC level voltage is
applied to pin BYTE, on the other hand, this bit’s state is set to “1” at reset.
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”.
3: While VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents.
4: In the single-chip mode, this bit’s contents are invalid. (CS0 output is disabled.)
5: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is
applied to pin MD0, on the other hand, this bit’s state is set to “1” at reset. (Fixed to “1”.)
7
6
5
4
3
2
1
0
CS1 control register L
CS2 control register L
CS3 control register L
Address
8216
8416
8616
At reset
4216
4216
4216
Area CSj bus cycle select bit 0 (j = 1 to 3)
See Figure 18.
External data bus width select bit
0 : 16-bit width
1 : 8-bit width (Note 1)
RDY control bit (Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
“0” at reading.
Burst ROM access select bit (Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CSj.
1 : Recovery cycle is inserted at access to area CSj.
CSj output select bit (j = 1 to 3) (Note 4)
0 : CSj output is disabled. (P45 to P47 function as programmable I/O port pins.)
1 : CSj output is enabled. (P45 to P47 function as pin CSj.)
Notes 1: While VCC level voltage is applied to pin BYTE, this bit is fixed to “1” (8-bit width).
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”.
3: When only the external data bus width select bit (bit 2) = “1” or while VCC level voltage is applied to pin BYTE, the
normal access is selected regardless of this bit’s contents.
4: In the single-chip mode, this bit’s contents are invalid. (CS0 output is disabled.)
Fig. 28 Bit configuration of CS0/CS1/CS2/CS3 control register Ls
40
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
CS0 control register H
Address
8116
At reset
8116
Area CS0 block size select bit
When mode 1 is selected
When mode 0 is selected
0 0 0 : 0 byte (Area CS0 is invalid.)
0 0 0 : 0 byte (Area CS0 is invalid.)
0 0 1 : 128 Kbytes
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
1 1 1 : 8 Mbytes
Area CS0 bus cycle select bit 1
See Figure 18.
“0” at read.
Area CS0 setting mode select bit
0 : Mode 0 (A block can be set to 16-Mbyte space.)
1 : Mode 1 (Area CS0 start address can be set to bank 0.)
7
6
5
4
3
2
1
0
Address
8316
CS1 control register H
0
At reset
0016
Area CS1 block size select bit
When mode 0 is selected
When mode 1 is selected
0 0 0 : 0 byte (Area CS1 is invalid.)
0 0 0 : 0 byte (Area CS1 is invalid.)
0 0 1 : 128 Kbytes
0 0 1 : Do not select.
0 1 0 : 256 Kbytes
0 1 0 : Do not select.
0 1 1 : 512 Kbytes
0 1 1 : Do not select.
1 0 0 : 1 Mbytes
1 0 0 : 4 Kbytes
1 0 1 : 2 Mbytes
1 0 1 : 8 Kbytes
1 1 0 : 4 Mbytes
1 1 0 : Do not select.
1 1 1 : 8 Mbytes
1 1 1 : Do not select.
Area CS1 bus cycle select bit 1
See Figure 18.
“0” at read.
Must be fixed to “0”.
Area CS1 setting mode select bit
0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.)
1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.)
7
6
5
4
3
2
1
0
Address
8516
CS2 control register H
At reset
0016
Area CS2 block size select bit
When mode 0 is selected
When mode 1 is selected
0 0 0 : 0 byte (Area CS2 is invalid.)
0 0 0 : 0 byte (Area CS2 is invalid.)
0 0 1 : 128 Kbytes
0 0 1 : Do not select.
0 1 0 : 256 Kbytes
0 1 0 : Do not select.
0 1 1 : 512 Kbytes
0 1 1 : Do not select.
1 0 0 : 1 Mbytes
1 0 0 : 4 Kbytes
1 0 1 : 2 Mbytes
1 0 1 : 8 Kbytes
1 1 0 : 4 Mbytes
1 1 0 : Do not select.
1 1 1 : 8 Mbytes
1 1 1 : Do not select.
Area CS2 bus cycle select bit 1
See Figure 18.
“0” at read.
Multiplexed bus select bit
0 : Separated bus (D0 to D7 are input/output.)
1 : Multiplexed bus (When the CS2 external data bus width = 8 bits
with area CS2 accessed, LA0/D0 to LA7/D7 are input/output.)
Area CS2 setting mode select bit
0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.)
1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.)
7
6
5
4
3
2
1
0
CS3 control register H
Address
8716
At reset
0016
Area CS3 block size select bit
0 0 0 : 0 byte (Area CS3 is invalid.)
0 0 1 : 128 Kbytes
0 1 0 : 256 Kbytes
0 1 1 : 512 Kbytes
1 0 0 : 1 Mbytes
1 0 1 : 2 Mbytes
1 1 0 : 4 Mbytes
1 1 1 : 8 Mbytes
Area CS3 bus cycle select bit 1
See Figure 18.
“0” at read.
Fig. 29 Bit configuration of CS0/CS1/CS2/CS3 control register Hs
41
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Area CS0 start address register
Address
8A16
At reset
1016
“0” at read.
When mode 0 is selected, these bits determine A16 to A23 of the area CS0 start address.
When mode 1 is selected, these bits determine A8 to A15 of the area CS0 start address.
Any of the following values can be set to these bits: “1016”, “2016”, “4016”, and “8016”.
(Bits 0 to 3 are always “0” at read.)
Note: Do not set a value other than “1016”, “2016”, “4016”, and “8016”. See Figure 31.
7
6
5
4
3
2
1
0
Area CS1 start address register
Area CS2 start address register
Address
8C16
8E16
At reset
0016
0016
“0” at read.
When mode 0 is selected, these bits determine A16 to A23 of the area CS1/CS2 start address.
When mode 1 is selected, these bits determine A8 to A15 of the area CS1/CS2 start address.
(Bit 0 is always “0” at read.)
Note: The start address setting depends on the block size, which has been selected by the area CS1/CS2 block size select bits
(bits 0 to 2 at address 8316, bits 0 to 2 at address 8516). See Figures 32 and 33.
7
6
5
4
3
2
1
0
Area CS3 start address register
Address
9016
At reset
0016
“0” at read.
These bits determine A16 to A23 of the area CS3 start address.
(Bit 0 is always “0” at read.)
Note: The start address setting depends on the block size, which has been selected by the area CS3 block size select bits
(bits 0 to 2 at address 8716). See Figure 33.
Fig. 30 Bit configuration of area CS0/CS1/CS2/CS3 start address registers
42
7FFFFF16
3FFFFF16
1FFFFF16
FFFFF16
7FFFF16
3FFFF16
1FFFF16
016
100016
256K
bytes
Block size
512K
bytes
1M
bytes
2M
bytes
4M
bytes
8M
bytes
200016
128K
bytes
256K
bytes
512K
bytes
1M
bytes
Block size
2M
bytes
4M
bytes
Start address : 400016
8M
bytes
400016
256K
bytes
512K
bytes
1M
bytes
Block size
2M
bytes
4M
bytes
Start address : 800016
800016
128K
bytes
Value to be set to area CS0 start
address register = “8016”
8M
bytes
Area CS0 cannot be assigned here.
128K
bytes
Value to be set to area CS0 start
address register = “4016”
Note: When an area where area CS0 and the internal area overlap is accessed, the internal area will be accessed. In this case,
pin CS0 outputs “H” level.
128K
bytes
Start address : 200016
Value to be set to area CS0 start
address register = “2016”
Start address : 100016
Value to be set to area CS0 start
address register = “1016”
256K
bytes
512K
bytes
1M
bytes
Block size
2M
bytes
4M
bytes
8M
bytes
MITSUBISHI MICROCOMPUTERS
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Fig. 31 Area CS0 (mode 1)
43
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block size : 4 Kbytes
Addresses which can be
start address
(Address FFFF16 is not
included; Note 1)
Block size : 8 Kbytes
Addresses which can be
start address
(Address FFFF16 is not
included; Note 1)
016
016
4 Kbytes
8 Kbytes
100016
200016
200016
300016
400016
400016
500016
600016
600016
700016
800016
800016
E00016
F00016
(FFFF16)
Fig. 32 Area CS1/CS2 (mode 1)
44
(FFFF16)
Notes 1: Only A8 to A15 of one of these addresses
can be set to the area CS1/CS2 start address
register. Do not set another address not
shown here.
2: When an area where area CS1/CS2 and the
internal area overlap is accessed, the internal
area will be accessed. In this case, pin CS1/CS2
outputs “H” level.
Block size : 128 Kbytes
Block size : 256 Kbytes
F0000016
(FF000016)
(FFFFFF16)
(FF000016)
(FFFFFF16)
FE000016
(FF000016)
(FFFFFF16)
Block size : 2 Mbytes
E0000016
C0000016
A0000016
80000016
60000016
40000016
20000016
(016)
Addresses which can
be start address
(Addresses 016 and
FF000016 to FFFFFF16
are not included; Note 1)
Block size : 4 Mbytes
(FF000016)
(FFFFFF16)
C0000016
80000016
40000016
(016)
Addresses which can
be start address
(Addresses 016 and
FF000016 to FFFFFF16
are not included; Note 1)
Block size : 8 Mbytes
(FF000016)
(FFFFFF16)
80000016
(016)
Addresses which can
be start address
(Addresses 016 and
FF000016 to FFFFFF16
are not included; Note 1)
Notes 1: Only A16 to A23 of one of these addresses can be set to the area CS0/CS1/CS2/CS3 start
address register. Do not set another address not shown here.
2: When an area where area CS0/CS1/CS2/CS3 and the internal area overlap is accessed,
the internal area will be accessed. In this case, pin CS0/CS1/CS2/CS3 outputs “H” level.
: Reserved area. Do not access this area.
: Area CS0/CS1/CS2/CS3 cannot be assigned here.
(FF000016)
(FFFFFF16)
;;; ;;;;;; ;;; ;;;;;; ;;;
;
E0000016
FC000016
FC000016
(FF000016)
(FFFFFF16)
D0000016
FA000016
C0000016
F8000016
F8000016
F8000016
B0000016
A0000016
90000016
F6000016
12000016
80000016
10000016
10000016
10000016
70000016
E000016
60000016
C000016
C000016
50000016
A000016
40000016
8000016
8000016
30000016
6000016
8000016
(016)
20000016
(016)
Block size : 1 Mbytes
Addresses which can
be start address
(Addresses 016 and
FF000016 to FFFFFF16
are not included; Note 1)
4000016
4000016
Block size : 512 Kbytes
Addresses which can
be start address
(Addresses 016 and
FF000016 to FFFFFF16
are not included; Note 1)
10000016
(016)
Addresses which can
be start address
(Addresses 016 and
FF000016 to FFFFFF16
are not included; Note 1)
2000016
(016)
Addresses which can
be start address
(Addresses 016 and
FF000016 to FFFFFF16
are not included; Note 1)
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 33 Area CS0/CS1/CS2 (mode 0) and area CS3
45
MITSUBISHI MICROCOMPUTERS
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INTERRUPTS
Table 8 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also handled as a type of interrupt in this
section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, NMI, and
address matching detection all have interrupt control registers. Table
9 shows the addresses of the interrupt control registers and Figure
35 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits other than watchdog timer and NMI can be cleared by software.
An NMI interrupt request is a non-maskable interrupt by an external
input and is accepted at the falling edge of an input to pin NMI. Also,
pin NMI has the pullup function. For more details, refer to the section
on input/output pins.
An INTi (i = 0 to 4) interrupt request is generated by an external input.
INT0 to INT2 are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be selected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
For INT3 and INT4, the interrupt signal’s polarity can be change by
the polarity select bit. (This is valid only in the edge sense.)
By pins INT2 to INT4 select bits (bits 4 to 6 at address 9416; see Figure 40.), pin position of INT2 to INT4 can be changed.
When using the following pins as external interrupt input pins, clear
the direction registers of the corresponding multiplexed ports to “0”:
pins P6 2/INT 0 , P6 3 /INT 1, P6 4 (P7 7 )/INT 2, P8 0(P7 4 )/INT 3, and
P84(P75)/INT4.
Furthermore, the INT3 interrupt can function as the key input interrupt. For details, refer to the section on the key input interrupt.
When the external interrupt input read register (address 9516) is read
out, the status of pins INT0 to INT4 and NMI can directly be read.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupt requests are caused
simultaneously is partially fixed by hardware, but, it can also be adjusted by software as shown in Figure 36.
The hardware priority is fixed as the following:
reset > NMI > watchdog timer > other interrupts
Table 8. Interrupt sources and interrupt vector addresses
Interrupts
Vector addresses
Address matching detection interrupt
00FFCA16 00FFCB16
INT4 external interrupt
00FFD016 00FFD116
INT3 external interrupt
00FFD216 00FFD316
A-D conversion
00FFD416
00FFD516
UART1 transmit
00FFD616
00FFD716
UART1 receive
00FFD816
00FFD916
UART0 transmit
00FFDA16 00FFDB16
UART0 receive
00FFDC16 00FFDD16
Timer B2
00FFDE16 00FFDF16
Timer B1
00FFE016
00FFE116
Timer B0
00FFE216
00FFE316
Timer A4
00FFE416
00FFE516
Timer A3
00FFE616
00FFE716
Timer A2
00FFE816
00FFE916
Timer A1
00FFEA16 00FFEB16
Timer A0
00FFEC16 00FFED16
INT2 external interrupt
00FFEE16 00FFEF16
INT1 external interrupt
00FFF016
00FFF116
INT0 external interrupt
00FFF216
00FFF316
NMI external interrupt
00FFF416
00FFF516
Watchdog timer
00FFF616
00FFF716
DBC (Do not select.)
00FFF816
00FFF916
Break instruction (Do not select.)
00FFFA16
00FFFB16
Zero divide
00FFFC16 00FFFD16
Reset
00FFFE16
00FFFF16
7
6
5
4
3
2
1
0
External interrupt input read register
Address
9516
INT0 read bit
INT1 read bit
INT2 read bit
INT3 read bit (Note)
INT4 read bit
NMI read bit
Undefined at read.
Note: When the key input interrupt select bit (bit 0 at address 9416) = “1”,
the status of pin INT3 cannot be read out.
Fig. 34 Bit configuration of external interrupt input read register
46
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Interrupt priority level select bits (Note 1)
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
Interrupt control register bit configuration for A-D converter, UART0, UART1,
timer A0 to timer A4, and timer B0 to timer B2.
7
6
5
4
3
2
1
0
Interrupt priority level select bits (Notes 1, 2)
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
Polarity select bit
0 : Interrupt request bit is set to “1” at “H” level when level sense is selected;
this bit is set to “1” at falling edge when edge sense is selected.
1 : Interrupt request bit is set to “1” at “L” level when level sense is selected;
this bit is set to “1” at rising edge when edge sense is selected.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Interrupt control register bit configuration for INT0– INT2
7
6
5
4
3
2
1
0
Interrupt priority level select bits
Interrupt request bit (Note 1)
0 : No interrupt requested
1 : Interrupt requested
Polarity select bit
0 : Interrupt request bit is set to “1” at falling edge.
1 : Interrupt request bit is set to “1” at rising edge.
Interrupt control register bit configuration for INT3 and INT4
Notes 1: Use the MOVM (MOVMB) instruction or the STA (STAB, STAD) instruction for writing to this bit.
2: Interrupt request bits of INT0 to INT2 are invalid when the level sense is selected.
Fig. 35 Bit configuration of interrupt control register
47
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Addresses
00006E16
00006F16
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
Interrupts caused by the address matching detection and when dividing by zero are software interrupts and are not included in Figure
36.
Other interrupts previously mentioned are A-D converter, UART, etc.
interrupts. The priority of these interrupts can be changed by changing the priority level in the corresponding interrupt control register by
software.
Figure 37 shows a diagram of the interrupt priority detection circuit
When an interrupt is caused, each interrupt device compares its own
priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the priorities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset, NMI,
and watchdog timer interrupts are not affected by the interrupt disable flag I.
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to “0” and enable further interrupts.
For reset, watchdog timer, zero divide, NMI, and address match detection interrupts, which do not have an interrupt control register, the
processor interrupt level (IPL) is set as shown in Table 10.
48
The interrupt request bit and the interrupt priority level of each interrupt source are sampled and latched at each operation code fetch
cycle while fsys is “H”. However, no sampling pulse is generated until
the cycles whose number is selected by software has passed, even
if the next operation code fetch cycle is generated. The detection of
an interrupt which has the highest priority is performed during that
time.
Priority is determined by hardware
Table 9. Addresses of interrupt control registers
Interrupt control registers
INT3 interrupt control register
INT4 interrupt control register
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
➂
➁
➀
Watchdog
timer
NMI
Reset
➃
A-D converter, UART, etc. interrupts
Priority can be changed by software inside ➃.
Fig. 36 Interrupt priority
Level 0
INT4
INT3
A-D
Interrupt request
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Reset
Timer B2
Timer B1
NMI
Timer B0
Timer A4
Timer A3
Watchdog timer
Timer A2
Timer A1
Timer A0
INT2
Interrupt disable flag I
INT1
IPL
Fig. 37 Interrupt priority detection
INT0
MITSUBISHI MICROCOMPUTERS
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As shown in Figure 38, there are three different interrupt priority detection time from which one is selected by software. After the selected time has elapsed, the highest priority is determined and is
processed after the currently executing instruction has been completed.
The time is selected with bits 4 and 5 of the processor mode register
0 (address 5E16) shown in Figure 24. Table 11 shows the relationship between these bits and the number of cycles. After a reset, the
processor mode register 0 is initialized to “0016.” Therefore, the longest time is automatically set, however, the shortest time must be selected by software.
Table 10. Value loaded in processor interrupt level (IPL) during an interrupt
Interrupt types
Reset
Watchdog timer
NMI
Zero divide
Address matching detection
Setting value
0
7
7
Not change value of IPL.
Not change value of IPL.
Table 11. Relationship between interrupt priority detection time select
bit and number of cycles
Priority detection time select bit
Bit 5
Bit 4
0
0
0
1
1
0
Number of cycles (Note)
7 cycles of f sys
4 cycles of f sys
2 cycles of f sys
Note: For system clock fsys, refer to the section on the clock generating circuit.
fsys
Operation code fetch cycle
(Note)
Sampling pulse
b5b4
Priority detection time
Select one between 00 to
10 with bits 4 and 5 of
processor mode register 0
00
01
10
Note: This pulse resides when 2 cycles of fsys is selected.
Fig. 38 Interrupt priority detection time
49
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key Input Interrupt
The INT3 interrupt can function as the key input interrupt by setting
bits 1 to 3 of the external interrupt input control register (address
9416). The key input interrupt uses inputs KI0 to KI3. Figure 39 shows
the block diagram of the INT3/key input interrupt input circuit, and
Figure 40 shows the bit configuration of the external interrupt input
control register.
When bit 0 of the external interrupt input control register (key input
interrupt select bit)= “0”, a signal from pin INT3 is connected to the
INT3 interrupt control circuit, and INT3 external interrupt is normally
performed. When bit 0 = “1”, signals from pins KI0 to KI3, which correspond to ports P54 to P57 pins, are inverted, and then, the logical
sum of these signals is connected to the INT3 interrupt control regis-
P80/INT3
Pin INT3
select bit
0
ter. In this case, the external interrupt which uses pins KI0 to KI3 is
performed.
Bits 2 and 3 of the external interrupt input control register are the key
input interrupt pin select bits. By setting these bits, the combination
of key input interrupt pins can be selected. The interrupt vector addresses and interrupt control register of the key input interrupt are
common to those of the INT3 interrupt. Additionally, pullup resistors
(transistors) can be added to pins KI0 to KI4 by setting as follows:
• Set bit 1 of the external interrupt input control register to “1”.
• Next, select the key input interrupt pins by bits 2 and 3 of the external interrupt input control register.
• Then, clear the contents of the port direction register which corresponds to the selected pins to “0”.
Key input interrupt
select bit
0
Interrupt control circuit
P74/(INT3)
INT3 interrupt request
1
1
Port P57 direction register
Pullup
transistor
Key input interrupt pin
pullup select bit
KI3 enable signal (Note)
INT3 interrupt control register
P57/KI3
Port P56 direction register
Pullup
transistor
Key input interrupt pin
pullup select bit
KI2 enable signal (Note)
P56/KI2
Port P55 direction register
Pullup
transistor
Key input interrupt pin
pullup select bit
KI1 enable signal (Note)
Note: KIi enable signal (i = 0 to 3) means a signal which becomes
“1” when the key input interrupt select bit = “1” and pin KIi is
selected by the key input interrupt pin select bits.
P55/KI1
Port P54 direction register
Pullup
transistor
Key input interrupt pin
pullup select bit
KI0 enable signal (Note)
P54/KI0
Fig. 39 Block diagram of INT3/key input interrupt input circuit
50
• Port P5j direction register
: bit j (j = 4 to 7) at address D16
• INT3 interrupt control register
: address 6E16
• Key input interrupt select bit
: bit 0 at address 9416
• Key input interrupt pin pullup select bit : bit 1 at address 9416
• Pin INT3 select bit
: bit 5 at address 9416
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
0
6
5
4
3
2
1
0
External interrupt input control register
Address
9416
At reset
0016
Key input interrupt select bit
0: INT3 interrupt
1: Key input interrupt
Key input interrupt pin pullup select bit
0: Pins KI0 to KI3 are not pulled up.
1: Pins KI0 to KI3 are pulled up.
Key input interrupt pin select bits (Note 1)
0 0: Pins KI0 to KI3
0 1: Pins KI0 to KI2
1 0: Pins KI0 and KI1
1 1: Pin KI0
Pin INT2 select bit
0: Allocate pin INT2 to P64.
1: Allocate pin INT2 to P77 (Note 2).
Pin INT3 select bit (Note 3)
0: Allocate pin INT3 to P80.
1: Allocate pin INT3 to P74.
Pin INT4 select bit
0: Allocate pin INT4 to P84.
1: Allocate pin INT4 to P75 (Note 4).
Fix this bit to “0”.
Notes 1: When using pin KIi, do not select timer A’s output pins and pulse output pins which are multiplexed with pin KIi.
2: When pin INT2 is allocated to P77, do not use pin AN7/ADTRG. Additionally, clear the D-A1 output enable bit (bit 1 at
address 9616) to “0” (output disabled).
3: When pin INT3 is allocated to P80, clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled).
When pin INT3 is allocated to P74, do not use pin AN4.
4: When pin INT4 is allocated to P75, do not use pin AN5.
Fig. 40 Bit configuration of external interrupt input control register
51
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER
selected by bits 0 and 1 of this register.
There are eight 16-bit timers. They are divided by type into timer A(5)
and timer B(3).
The timer I/O pins are multiplexed with I/O pins for port P5 and P6.
To use these pins as timer input pins, the port direction register bit
corresponding to the pin must be cleared to “0” to specify input
mode.
TIMER A
Figure 41 shows a block diagram of timer A.
Timer A has four modes: timer mode, event counter mode, one-shot
pulse mode, and pulse width modulation mode. The mode is selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4). Each
of these modes is described below.
Figure 42 shows the bit configuration of the timer A clock division select register. Timers A0 to A4 use the count source which has been
Timer A clock
division select bit
f2
(1) Timer mode [00]
Figure 43 shows the bit configuration of the timer Ai mode register
during timer mode. Bits 0, 1 and 5 of the timer Ai mode register must
be “0” in timer mode. The timer A’s count source is selected by bits 6
and 7 of the timer Ai mode register and the contents of the timer A
clock division select register. (See Table 12.)
The counting of the selected clock starts when the count start bit is
“1” and stops when it is “0”.
Figure 44 shows the bit configuration of the count start bit. The
counter is decremented, an interrupt is caused and the interrupt request bit in the timer Ai interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload
register is transferred to the counter and count is continued.
Count source
select bits
f1
f16
f64
Data bus (odd)
f512
Data bus (even)
f4096
(Low-order 8 bits)
• Timer
• One-shot pulse
• Pulse width
(High-order 8 bits)
Reload register(16)
Timer (gate function)
Counter (16)
TAiIN
(i = 0–4)
Polarity
selection
Event counter
Count start register
(Address 4016)
External trigger
Countdown
Up-down register
(Address 4416)
Pulse output
Toggle flip-flop
TAiOUT
(i = 0–4)
Fig. 41 Block diagram of timer A
52
Countup/Countdown switching
“Countdown” is always
selected when not in the
event counter mode.
Addresses
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
4716
4916
4B16
4D16
4F16
4616
4816
4A16
4C16
4E16
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When bit 2 of the timer Ai mode register is “1”, the output is generated from TAiOUT pin. The output is toggled each time the contents
of the counter reaches to 000016. When the contents of the count
start bit is “0”, “L” is output from TAiOUT pin.
When bit 2 is “0”, TAiOUT can be used as a normal port pin. When bit
4 is “0”, TAiIN can be used as a normal port pin.
When bit 4 is “1”, counting is performed only while the input signal
from the TAiIN pin is “H” or “L” as shown in Figure 45. Therefore, this
can be used to measure the pulse width of the TAiIN input signal.
Whether to count while the input signal is “H” or while it is “L” is determined by bit 3. If bit 3 is “1”, counting is performed while the TAiIN
pin input signal is “H” and if bit 3 is “0”, counting is performed while it
is “L”.
Note that, the duration of “H” or “L” on the TAiIN pin must be 2 or
more cycles of the timer count source.
When data is written to timer Ai register with timer Ai halted, the
same data is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The new data is reloaded
from the reload register to the counter at the next reload time and
counting continues. The contents of the counter can be read at any
time.
When the value set in the timer Ai register is n, the timer frequency
division ratio is 1/(n+1).
7
6
5
0
4
3
2
1
0
0
0
7 6 5 4 3 2 1 0
Timer A clock division select register
Address
4516
Timer A clock division select bit
(See Table 12.)
“0” at read.
Fig. 42 Bit configuration of timer A clock division select register
Table 12. Relationship between timer A clock division select bits,
clock source select bits, and count source
Clock source select bits
(bits 7 and 6 at addresses
5616 to 5A16)
00
01
10
11
Timer A clock division select bits
(bits 1 and 0 at address 4516)
00
11
10
01
f2
f1
f1
f16
f64
f16
Do not
f64
f512
select.
f64
f4096
f4096
f512
Note: Timers A0 to A4 use the same clock, which is selected by the
timer A clock division select bits.
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Addresses
5616
5716
5816
5916
5A16
0 0 : Always “00” in timer mode
0 : No pulse output (TAiOUT is normal port pin.)
1 : Pulse output (TAiOUT is pulse output pin.) (Note)
0 × : No gate function (TAiIN is normal port pin.)
1 0 : Count only while TAiIN input is “L”.
1 1 : Count only while TAiIN input is “H”.
0 : Always “0” in timer mode.
Clock source select bits
See Table 12.
Note: When using pins TA2OUT and TA3OUT as pulse output pins, do not select pins KI0 and KI2.
Because they are key input interrupt pins and are multiplexed with pins TA2OUT and TA3OUT.
Fig. 43 Bit configuration of timer Ai mode register during timer mode
53
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
Count start register
(Stop at “0”, Start at “1”)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
Fig. 44 Bit configuration of count start register
Selected clock source fi
TAiIN
Timer mode register
Bit 4
Bit 3
1
0
Timer mode register
Bit 4
Bit 3
1
1
Fig. 45 Count waveform when gate function is available
54
Address
4016
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 46 shows the bit configuration of the timer Ai mode register
during event counter mode. In event counter mode, bit 0 of the timer
Ai mode register must be “1” and bits 1 and 5 must be “0”.
The input signal from the TAiIN pin is counted when the count start
bit shown in Figure 44 is “1” and counting is stopped when it is “0”.
Count is performed at the fall of the input signal when bit 3 is “0” and
at the rise of the signal when it is “1”.
In event counter mode, whether to increment or decrement the count
can be selected with the up-down bit or the input signal from the
TAiOUT pin.
When bit 4 of the timer Ai mode register is “0”, the up-down bit is
used to determine whether to increment or decrement the count
(decrement when the bit is “0” and increment when it is “1”). Figure
47 shows the bit configuration of the up-down register.
When bit 4 of the timer Ai mode register is “1”, the input signal from
the TAiOUT pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be “0” if bit 4 is “1.” It is
because if bit 2 is “1”, TAiOUT pin becomes an output pin to output
pulses.
The count is decremented when the input signal from the TAiOUT pin
is “L” and incremented when it is “H”. Determine the level of the input
signal from the TAiOUT pin before a valid edge is input to the TAiIN
pin.
An interrupt request signal is generated and the interrupt request bit
in the timer Ai interrupt control register is set when the counter
reaches 000016 (decrement count) or FFFF16 (increment count). At
the same time, the contents of the reload register is transferred to the
counter and the count is continued.
When bit 2 is “1,” each time the counter reaches 000016 (decrement
count) or FFFF16(increment count), the waveform’s polarity is reversed and is output from TAiOUT pin.
If bit 2 is “0”, TAiOUT pin can be used as a normal port pin.
However, if bit 4 is “1” and the TAiOUT pin is used as an output pin,
the output from the pin changes the count direction. Therefore, bit 4
must be “0” unless the output from the TAiOUT pin is to be used to select the count direction.
7 6 5 4 3 2 1 0
× × 0
0 1
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Addresses
5616
5716
5816
5916
5A16
0 1 : Always “01” in event counter mode
0 : No pulse output
1 : Pulse output
0 : Count at the falling edge of input signal
1 : Count at the rising edge of input signal
0 : Increment or decrement according
to up/down bit
1 : Increment or decrement according
to TAiOUT pin input signal level
0 : Always “0” in event counter mode
× × : Not used in event counter mode
Note: When using pins TA2OUT and TA3OUT as pulse output pins, do
not select pins KI0 and KI2. Because they are key input interrupt
pins and are multiplexed with pins TA2OUT and TA3OUT.
Fig. 46 Bit configuration of timer Ai mode register during event counter mode
7 6 5 4 3 2 1 0
Up-down register
Address
4416
Timer A0 up-down bit
Timer A1 up-down bit
Timer A2 up-down bit
Timer A3 up-down bit
Timer A4 up-down bit
Timer A2 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A3 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A4 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Fig. 47 Bit configuration of up-down register
55
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Data write and data read are performed in the same way as for timer
mode. That is, when data is written to timer Ai halted, it is also written to the reload register and the counter. When data is written to
timer Ai which is busy, the data is written to the reload register, but
not to the counter. The counter is reloaded with new data from the
reload register at the next reload time. The counter can be read at
any time.
In event counter mode, whether to increment or decrement the
counter can also be determined by supplying two kinds of pulses of
which phases differ by 90° to timer A2, A3, or A4. There are two types
of two-phase pulse processing operations. One uses timers A2 and
A3, and the other uses timer A4. In both processing operations, two
pulses described above are input to the TAjOUT (j = 2 to 4) pin and
TAjIN pin respectively.
When timers A2 and A3 are used, as shown in Figure 48, the count
is incremented when a rising edge is input to the TAkIN pin after the
level of TAkOUT(k=2, 3) pin changes from “L” to “H”, and when the
falling edge is input, the count is decremented.
For timer A4, as shown in Figure 49, when a phase-related pulse
with a rising edge input to the TA4IN pin is input after the level of
TA4OUT pin changes from “L” to “H”, the count is incremented at the
respective rising edge and falling edge of the TA4OUT pin and TA4IN
pin.
When a phase-related pulse with a falling edge input to the TA4OUT
pin is input after the level of TA4IN pin changes from “H” to “L”, the
count is decremented at the respective rising edge and falling edge
of the TA4IN pin and TA4OUT pin. When performing this two-phase
pulse signal processing, timer Aj mode register bit 0 and bit 4 must
be set to “1” and bits 1, 2, 3, and 5 must be “0”. Bits 6 and 7 are ig-
nored. (See Figure 50.) Note that bits 5, 6, and 7 of the up-down register (address 4416) are the two-phase pulse signal processing select bits for timers A2, A3 and A4 respectively. Each timer operates
in normal event counter mode when the corresponding bit is “0” and
performs two-phase pulse signal processing when it is “1”.
Count is started by setting the count start bit to “1”. Data write and
read are performed in the same way as for normal event counter
mode. Note that the direction register of the input port must be set to
input mode because two kinds of pulse signals, described above,
are input. Also, there can be no pulse output in this mode.
7 6 5 4 3 2 1 0
× × 0 1 0 0 0 1
0 1 0 0 : Always “0100” when processing
two-phase pulse signal
× × : Not used in event counter mode
Fig. 50 Bit configuration of timer Aj mode register when performing
two-phase pulse signal processing in event counter mode
TAkIN
(k = 2, 3)
Incrementcount
Incrementcount
Decrementcount
Decrementcount
Decrementcount
Fig. 48 Two-phase pulse processing operation of timers A2 and A3
TA4OUT
Increment-count at each edge
Decrement-count at each edge
TA4IN
Increment-count at each edge
Decrement-count at each edge
Fig. 49 Two-phase pulse processing operation of timer A4
56
Addresses
5816
5916
5A16
0 1 : Always “01” in event counter mode
TAkOUT
Incrementcount
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot pulse mode [10]
Figure 51 shows the bit configuration of the timer Ai mode register
during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5
must be “0” and bit 1 and bit 2 must be “1”.
The trigger is enabled when the count start bit is “1”. The trigger can
be generated by software or it can be input from the TAiIN pin. Software trigger is selected when bit 4 is “0” and the input signal from the
TAiIN pin is used as the trigger when it is “1“.
Bit 3 is used to determine whether to trigger at the fall of the trigger
signal or at the rise. The trigger is at the fall of the trigger signal when
bit 3 is “0” and at the rise of the trigger signal when it is “1”.
Software trigger is generated by setting “1” to a bit in the one-shot
start register. Each bit corresponds to each timer.
Figure 52 shows the bit configuration of the one-shot start register.
As shown in Figure 53, when a trigger signal is received, the counter
counts the clock selected by bits 6 and 7 and the contents of the
timer A clock division select register. (Set Table 12.)
If the contents of the counter is not 000016, the TAiOUT pin goes “H”
when a trigger signal is received. The count direction is decrement.
When the counter reaches 000116, the TAiOUT pin goes “L” and
count is stopped. The contents of the reload register is transferred to
the counter. At the same time, an interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set. This is repeated each time a trigger signal is received.
The output pulse width is
1
pulse frequency of the selected clock
× (counter’s value at the time of trigger).
If the count start flag is “0”, TAiOUT goes “L”. Therefore, the value corresponding to the desired pulse width must be written to timer Ai before setting the timer Ai count start bit.
As shown in Figure 54, a trigger signal can be received before the
operation for the previous trigger signal is completed. In this case,
the contents of the reload register is transferred to the counter by the
trigger and then that value is decremented.
Except when retriggering while operating, the contents of the reload
register are not transferred to the counter by triggering.
When retriggering, there must be at least one timer count source
cycle before a new trigger can be issued.
Data write is performed in the same way as for timer mode.
When data is written in timer Ai halted, it is also written to the reload
register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload time.
Undefined data is read when timer Ai is read.
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
7 6 5 4 3 2 1 0
0
1 1 0
Addresses
5616
5716
5816
5916
5A16
1 0 : Always “10” in one-shot pulse mode
1 : Always “1” in one-shot pulse mode
0 × : Software trigger
1 0 : Trigger at the falling edge of TAiIN
input
1 1 : Trigger at the rising edge of TAiIN
input
0 : Always “0” in one-shot pulse mode
Clock source select bits
(See Table 12.)
Fig. 51 Bit configuration of timer Ai mode register during one-shot
pulse mode
7 6 5 4 3 2 1 0
0
One-shot start register
Address
4216
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Must be fixed to “0”.
Fig. 52 Bit configuration of one-shot start register
57
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selected clock
source fi
TAiIN
(rising edge)
TAiOUT
Example when the contents of the reload register is 000316
Fig. 53 Pulse output example when external rising edge is selected
Selected clock
source fi
TAiIN
(rising edge)
TAiOUT
Example when the contents of the reload register is 000416
Fig. 54 Example when trigger is re-issued during pulse output
58
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(4) Pulse width modulation mode [11]
Figure 55 shows the bit configuration of the timer Ai mode register
during pulse width modulation mode. In pulse width modulation
mode, bits 0, 1, and 2 must be set to “1”.
Bit 5 is used to determine whether to perform 16-bit length pulse
width modulator or 8-bit length pulse width modulator. 16-bit length
pulse width modulator is selected when bit 5 is “0” and 8-bit length
pulse width modulator is selected when it is “1”. The 16-bit length
pulse width modulator is described first.
The pulse width modulator can be started with a software trigger or
with an input signal from a TAiIN pin (external trigger).
The software trigger mode is selected when bit 4 is “0”.
Pulse width modulator is started and a pulse is output from TAiOUT
when the count start bit is set to “1”.
The external trigger mode is selected when bit 4 is “1”.
Pulse width modulation starts when a trigger signal is input from the
TAiIN pin when the count start bit is “1”. Whether to trigger at the fall
or rise of the trigger signal is determined by bit 3. The trigger is at the
fall of the trigger signal when bit 3 is “0” and at the rise when it is “1”.
When data is written to timer Ai with the pulse width modulator
halted, it is written to the reload register and the counter.
Then when the count start bit is set to “1” and a software trigger or
an external trigger is issued to start modulation, the waveform shown
in Figure 56 is output continuously.
Once modulation is started, triggers are not accepted. If the value in
the reload register is m, the duration “H” of pulse is
1
×m
selected clock frequency
The low-order 8 bits function as a prescaler and the high-order 8 bits
function as the 8-bit length pulse width modulator. The prescaler
counts the clock selected by bits 6, 7, and the contents of the timer A
clock division select register. (See Table 12.) A pulse is generated
when the counter reaches 000016 as shown in Figure 57. At the
same time, the contents of the reload register is transferred to the
counter and count is continued.
7 6 5 4 3 2 1 0
1 1 1
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Addresses
5616
5716
5816
5916
5A16
1 1 : Always “11” in pulse width modulation
mode
1 : Always “1” in pulse width modulation
mode
0 × : Software trigger
1 0 : Trigger at the falling of TAiIN input
1 1 : Trigger at the rising of TAiIN input
0 : 16-bit pulse width modulator
1 : 8-bit pulse width modulator
Clock source select bits
(See Table 12.)
Fig. 55 Bit configuration of timer Ai mode register during pulse width
modulation mode
and the output pulse period is
1
× (216 –1).
selected clock frequency
An interrupt request signal is generated and the interrupt request bit
in the timer Ai interrupt control register is set at each fall of the output
pulse.
The width of the output pulse is changed by updating timer data. The
update can be performed at any time. The output pulse width is
changed at the rise of the pulse after data is written to the timer.
The contents of the reload register are transferred to the counter just
before the rise of the next pulse so that the pulse width is changed
from the next output pulse.
Undefined data is read when timer Ai is read.
The 8-bit length pulse width modulator is described next.
The 8-bit length pulse width modulator is selected when the timer Ai
mode register bit 5 is “1”.
The reload register and the counter are both divided into 8-bit
halves.
59
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Therefore, if the low-order 8 bits of the reload register are n, the period of the generated pulse is
high-order 8 bits of the reload register are m, the duration “H” of
pulse is
1
× (n+1) × m.
selected clock frequency
1
× (n+1).
selected clock frequency
The high-order 8 bits function as an 8-bit length pulse width modulator using this pulse as input. The operation is the same as for 16-bit
length pulse width modulator except that the length is 8 bits. If the
And the output pulse period is
1
selected clock frequency
1/fi × (216 – 1)
Selected clock
source fi
TAiIN
(rising edge)
This trigger is not accepted
1/fi × (m)
TAiOUT
Example when the contents of the reload register is 000316
Fig. 56 16-bit length pulse width modulator output pulse example
1/fi × (n + 1) × (28 – 1)
Selected clock
source fi
TAiIN
(falling edge)
1/fi × (n + 1)
Prescaler output
(when n = 2)
1/fi × (n + 1) × (m)
8-bit length pulse
width modulator
output
(when m = 2)
Fig. 57 8-bit length pulse width modulator output pulse example
60
× (n+1) × (28–1).
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
TIMER B
As shown in Figure 44, the timer Bi count start bit is at the same address as the timer Ai count start bit. The count is decremented, an
interrupt occurs, and the interrupt request bit in the timer Bi interrupt
control register is set when the contents becomes 000016. At the
same time, the contents of the reload register is stored in the counter
and count is continued.
Timer Bi does not have a pulse output function or a gate function like
timer A.
When data is written to timer Bi halted, it is written to the reload register and the counter. When data is written to timer Bi which is busy,
the data is written to the reload register, but not to the counter. The
new data is reloaded from the reload register to the counter at the
next reload time and counting continues.
The contents of the counter can be read at any time.
Figure 58 shows a block diagram of timer B.
Timer B has three modes: timer mode, event counter mode, and
pulse period measurement/pulse width measurement mode. The
mode is selected with bits 0 and 1 of the timer Bi mode register (i=0
to 2). Each of these modes is described below.
(1) Timer mode [00]
Figure 59 shows the bit configuration of the timer Bi mode register
during timer mode. Bits 0 and 1 of the timer Bi mode register must
always be “0” in timer mode.
Bits 6 and 7 are used to select the clock source. The counting of the
selected clock starts when the count start bit is “1” and stops when
“0”.
Data bus (odd)
Count source select bits
f2
f16
f64
Data bus (even)
f512
(Low-order 8 bits)
• Timer mode
• Pulse period measurement/Pulse
width measurement mode
TBiIN
Polarity selection
and edge pulse
generator
(High-order 8 bits)
Reload register (16)
• Event counter
mode
Counter (16)
fX32
Timer B2 clock source
select bit (Note 2)
Count start register
Addresses
Timer B0 5116 5016
Timer B1 5316 5216
Timer B2 5516 5416
(Address 4016)
Counter reset
circuit
Timer B2 clock source select bit : Bit 6 at address 6316
Notes 1: Perform a write and read to/from timer Bi register in the condition of 16-bit data length : data length flag (m) = “0”.
2: Only for timer B2, a count source in the event counter mode can be selected.
Fig. 58 Block diagram of timer B
61
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 60 shows the bit configuration of the timer Bi mode register
during event counter mode. In event counter mode, bit 0 in the timer
Bi mode register must be “1” and bit 1 must be “0”.
The input signal from the TBiIN pin is counted when the count start
bit is “1” and counting is stopped when it is “0”.
Count is performed at the fall of the input signal when bits 2, and 3
are “0” and at the rise of the input signal when bit 3 is “0” and bit 2 is
“1”.
When bit 3 is “1” and bit 2 is “0”, count is performed at the rise and
fall of the input signal.
Data write, data read and timer interrupt are performed in the same
way as for timer mode.
Only for timer B2, when the timer B2 clock source select bit of the
particular function select register 1 (bit 6 at address 6316) = “1” in the
event counter mode, fX32 can be selected. (When this bit is “0”, an
input signal from pin TB2IN becomes the count source as described
above.) For the bit configuration of the particular function select register 1, refer to the section on the standby function.
Note: fX32 = f(XIN)/32
(3) Pulse period measurement/Pulse width
measurement mode [10]
Figure 61 shows the bit configuration of the timer Bi mode register
during pulse period measurement/pulse width measurement mode.
In pulse period measurement/pulse width measurement mode, bit 0
must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select the
clock source. The selected clock is counted when the count start bit
is “1” and counting stops when it is “0”.
The pulse period measurement mode is selected when bit 3 is “0”. In
pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the TBiIN pin
to the next fall or at the rise of the input signal to the next rise; the
result is stored in the reload register. In this case, the reload register
acts as a buffer register.
When bit 2 is “0”, the clock is counted from the fall of the input signal
to the next fall. When bit 2 is “1“, the clock is counted from the rise of
the input signal to the next rise.
In the case of counting from the fall of the input signal to the next fall,
counting is performed as follows. As shown in Figure 62, when the
fall of the input signal from TBiIN pin is detected, the contents of the
counter is transferred to the reload register. Next, the counter is
cleared and count is started from the next clock. When the fall of the
next input signal is detected, the contents of the counter is transferred to the reload register once more, the counter is cleared, and
the count is started. The period from the fall of the input signal to the
next fall is measured in this way.
After the contents of the counter is transferred to the reload register,
an interrupt request signal is generated and the interrupt request bit
in the timer Bi interrupt control register is set. However, no interrupt
request signal is generated when the contents of the counter is transferred first to the reload register after the count start bit is set to “1”.
When bit 3 is “1”, the pulse width measurement mode is selected.
Pulse width measurement mode is the same as the pulse period
measurement mode except that the clock is counted from the fall of
the TBiIN pin input signal to the next rise or from the rise of the input
signal to the next fall as shown in Figure 63.
62
7 6 5 4 3 2 1 0
×
× × 0 0
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Addresses
5B16
5C16
5D16
0 0 : Always “00” in timer mode
× × : Not used in timer mode and
may be any
Not used in timer mode
Clock source select bits
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 59 Bit configuration of timer Bi mode register during timer mode
7 6 5 4 3 2 1 0
× × ×
0 1
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Addresses
5B16
5C16
5D16
0 1 : Always “01” in event counter
mode
0 0 : Count at the falling edge of
input signal
0 1 : Count at the rising edge of
input signal
1 0 : Count at the both falling edge
and rising edge of input signal
× × × : Not used in event counter mode
Fig. 60 Bit configuration of timer Bi mode register during event
counter mode
7 6 5 4 3 2 1 0
1 0
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Addresses
5B16
5C16
5D16
1 0 : Always “10” in pulse period
measurement/pulse width
measurement mode
0 0 : Count from the falling edge of
input signal to the next falling one
0 1 : Count from the rising edge of
input signal to the next rising one
1 0 : Count from the falling edge of
input signal to the next rising one
and from the rising edge to the
next falling one
Timer Bi overflow flag
Clock source select bits
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Fig. 61 Bit configuration of timer Bi mode register during pulse period
measurement/pulse width measurement mode
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When timer Bi is read, the contents of the reload register is read.
Note that in this mode, the interval between the fall of the TBiIN pin
input signal to the next rise or from the rise to the next fall must be at
least two cycles of the timer count source.
Timer Bi overflow flag which is bit 5 of timer Bi mode register is set to
“1” when the timer Bi counter reaches 000016, which indicates that a
pulse width or pulse period is longer than that which can be measured by a 16-bit length.
This flag is cleared by writing data to the corresponding timer Bi
mode register. This flag is set to “1”at reset.
Selected clock
source fi
TBiIN
Reload register ← Counter
Counter ← 0
Count start bit
Interrupt request signal
Fig. 62 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one)
Selected clock
source fi
TBiIN
Reload register ← Counter
Counter ← 0
Count start bit
Interrupt request signal
Fig. 63 Pulse width measurement mode operation
63
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SERIAL I/O PORTS
chronous (UART) serial I/O port which uses start and stop bits.
Figures 66 and 67 show the block diagrams of the receiver/transmitter .
Figure 68 shows the bit configuration of the UARTi transmit/receive
control register.
Each communication method is described below.
Two independent serial I/O ports are provided. Figure 64 shows a
block diagram of the serial I/O ports.
Bits 0 to 2 of the UARTi(i = 0,1) transmit/receive mode register
shown in Figure 65 are used to determine whether to use port P8 as
a programmable I/O port, clock synchronous serial I/O port, or asyn-
Data bus (odd)
Data bus (even)
Bit converter
UARTi
D7 D6 D5 D4 D3 D2 D1 D0 receive buffer register
UART0 (Addresses 3716, 3616)
UART1 (Addresses 3F16, 3E16)
0 0 0 0 0 0 0 D8
UARTi receive register
RXDi
BRG count source select bits
f2
f16
BRGi
f64
1/(n + 1) divider
f512
1/16 divider
UART
Clock synchronous
1/16 divider
UART
Clock synchronous
Receive
control
circuit
Transmit
control
circuit
Transfer clock
Transfer clock
Clock synchronous
(Internal clock)
1/2 divider
UARTi transmit register
Clock synchronous
(External clock)
TXDi
Clock synchronous (when internal clock selected)
D8
D7 D6 D5 D4 D3 D2 D1 D0
UARTi
transmit buffer register
UART0 (Addresses 3316, 3216)
UART1 (Addresses 3B16, 3A16)
CLKi
CTSi/CLKi
CTSi
Bit converter
CTSi/RTSi
Data bus (odd)
n = a value set into the UARTi baud rate register (BRGi)
Data bus (even)
Fig. 64 Block diagram of serial I/O port
7 6 5 4 3 2 1 0
UART 0 Transmit/Receive mode register
UART 1 Transmit/Receive mode register
Addresses
3016
3816
Serial I/O mode select bits
0 0 0 : Serial I/O is invalid. (Port P8 functions as a programmable I/O port.)
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal/External clock select bit
0 : Internal clock
1 : External clock
Stop bit length select bit (Valid in UART mode.)
0 : 1 stop bit
1 : 2 stop bits
Odd/Even parity select bit (Valid in UART mode with the parity enable bit = “1”.) (Note)
0 : Odd parity
1 : Even parity
Parity enable bit (Valid in UART mode) (Note)
0 : No parity
1 : With parity
Sleep select bit (Valid in UART mode) (Note)
0 : No sleep
1 : Sleep
Note: In the clock synchronous serial I/O mode, bits 4 to 6 are invalid. (Each of them may be “0” or “1”.) Furthermore, fix bit 7 to “0”.
Fig. 65 Bit configuration of UARTi transmit/receive mode register
64
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data bus (odd)
Data bus (even)
UARTi receive
buffer register
0
0
0
0
0
2SP
R XD i
PAR
D7
D6
D5
D4
D3
D2
D1
D0
8-bit UART
9-bit UART
Synchronous
UART
No
parity
1SP
D8
0
9-bit UART
Parity
SP
SP
0
7-bit UART
7-bit UART
8-bit UART
Synchronous
UARTi receive register
Synchronous
SP : Stop bit
PAR : Parity bit
Fig. 66 Block diagram of receiver
Data bus (odd)
Data bus (even)
UARTi receive transmit register
D8
2SP
SP
SP
D6
D5
D4
D3
D2
D1
D0
8-bit UART
7-bit UART
9-bit UART
9-bit UART
Synchronous Synchronous
Parity
TXDi
UART
PAR
8-bit UART
1SP
D7
No
parity
7-bit UART
UARTi transmit register
Synchronous
0
SP : Stop bit
PAR : Parity bit
Fig. 67 Block diagram of transmitter
65
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7
6
5
4
MSB
CPL
/LSB
3
2
TX
R/C
EPTY
1
0
CS1
CS0
UART0 transmit/receive control register 0
UART1 transmit/receive control register 0
Address
34 16
3C16
BRG count source select bits
0 0 : f2
0 1 : f16
1 0 : f64
1 1 : f512
CTS/RTS function select bit (Note 1)
0 : CTS function is selected.
1 : RTS function is selected.
Transmit register empty flag
0 : Data is present in the transmit register. (Transmission is in progress.)
1 : No data is present in the transmit register. (Transmission is completed.)
CTS/RTS enable bit
0 : CTS, RTS function is enabled.
1 : CTS, RTS function is disabled.
UARTi receive interrupt mode select bit
0 : Reception interrupt
1 : Reception error interrupt
CLK polarity select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 2)
0 : At the falling edge of a transfer clock, transmit data is output;
at the rising edge, receive data is input.
When not in transfer, pin CLK’s level is “H”.
1 : At the rising edge of a transfer clock, transmit data is output;
at the falling edge, receive data is input.
When not in transfer, pin CLK’s level is “L”.
Transfer format select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 2)
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
7
6
5
4
SUM PER FER OER
3
2
1
0
RI
RE
TI
TE
UART0 transmit/receive control register 1
UART1 transmit/receive control register 1
Transmit enable bit
Transmit buffer empty flag
Receive enable bit
Receive complete flag
Overrun error flag
Framing error flag (Note 3)
Parity error flag (Note 3)
Error sum flag (Note 3)
Notes 1: Valid when the CTS/RTS enable bit (bit 4) = “0”.
2: Fix these bits to “0” in UART mode or when serial I/O is invalid.
3: Valid in UART mode.
Fig. 68 Bit configuration of UARTi transmit/receive control register
66
Address
3516
3D16
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK SYNCHRONOUS SERIAL COMMUNICATION
A case where communication is performed between two clock synchronous serial I/O ports as shown in Figure 69 will be described.
(The transmission side will be denoted by subscript j and the receiving side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk transmit/receive mode register must be set to “1” and bits 1 and 2 must be
“0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock sending side is cleared to “0” to select the internal clock. Bit 3 of the
UARTk transmit/receive mode register of the clock receiving side is
set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the
clock-sending-side UARTj transmit/receive control register 0. As
shown in Figure 64, the selected clock is divided by (n+1), then by 2,
is passed through a transmission control circuit, and is output as
transmission clock CLKj. Therefore, when the selected clock is fi,
Bit Rate = fi/ {(n + 1) × 2}
TxDj
On the clock receiving side, the CS0 and CS1 bits of the UARTk
transmit/receive control register 0 are ignored because an external
clock is selected.
_______
_______
Both of UART0 and UART1 can use CTS and RTS functions.
Bit 4 of the UARTi transmit/receive
control register 0 is used to de_______
_______
termine
whether to use CTS or RTS signal. Bit 4 _______
must be “0”
when
_______
_______
_______
CTS or RTS signal is used._______
Bit 4 must
be
“1”
when
CTS
and
RTS
sig_______
_______
nals
are
not
used.
When
CTS
and
RTS
signals
are
not
used,
CTS/
_______
RTS pin can be used
as a normal port pin.
_______ _______
When using pin CTS/RTS, :
• If bit _______
2 of the UARTi transmit/receive control register 0 is cleared to
“0”, CTS input is selected.
_______
• If bit 2 is set to “1”,
RTS output
is selected.
_______
_______
The case using CTS and RTS signals are explained below. As
shown in Figure 76, bits 2 and 3 of the serial I/O pin control register
can determine whether port pins P83 and P87 are used as pins TxDi
or as port pins. When bits 2 and 3 are “0”, P83 and P87 function as
pins TxDi; when bits 2 and 3 are “1”, P83 and P87 function as port
pins. Therefore, in the input-only system where pins TxDi are not
used, pins TxDi can function as port pins.
TxDk
UARTj transmit register
UARTk transmit register
UARTj transmit buffer register
UARTk transmit buffer register
UARTj receive buffer register
UARTk receive buffer register
RxDj
RxDk
UARTk receive register
UARTj receive register
UARTk Transmit/Receive mode register
UARTj Transmit/Receive mode register
0
0
0
0
1
0
CLKj
RE
TI
0
1
UARTk Transmit/Receive control
register 0
TX
MSB
/LSB CPL
EPTY 1
CTSj
RTSk
UARTk Transmit/Receive control
register 1
UARTj Transmit/Receive control
register 1
RI
0
CLKk
UARTj Transmit/Receive control
register 0
TX
MSB
CS1 CS0
/LSB CPL
EPTY 0
SUM PER FER OER
1
TE
SUM PER FER OER
RI
RE
TI
TE
Fig. 69 Clock synchronous serial communication
67
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Transmission
Transmission is started when bit 0 (TEj flag: transmit enable bit) of
UARTj transmit/receive
control register 1 is “1”, bit 1 (TIj flag) of one
________
is “0”, and CTSj input is “L”. The TIj flag indicates whether the transmit buffer register is empty or not. It is cleared to “0” when data is
written in the transmit buffer register ; it is set to “1” when the contents of the transmit buffer register is transferred to the transmit register and the transmit buffer register becomes empty.
When all of the transmit conditions are satisfied, the transmit data in
the transmit buffer register are transferred to the transmit register,
and transmission starts. As shown in Figure 70, data is output from
TXDj pin each time when transmission clock CLKj changes from “H”
to “L”. (In the clock synchronous serial I/O mode, the polarity of a
transfer clock can be changed. For details, refer to the section on the
selection of the transfer clock polarity.) The data is output from the
least significant bit.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmission start
condition is satisfied. The next transmission is performed
succeedingly. Once transmission has started, the TEj flag, TIj flag,
and CTSj signals are ignored until data transmission
completes.
________
Therefore, transmission is not interrupt when CTSj input is changed
to “H” during transmission.
The transmission start condition indicated by TEj flag, TIj flag, and
________
CTSj is checked while the TENDj signal (shown in Figure 70) is “H”.
Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIj flag is
cleared to “0” before theTENDj signal goes “H”.
Bit 3 (TXEPTYj flag) of UARTj transmit/receive control register 0
changes to “1” at the next cycle just after the TENDj signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission has completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit in
the UARTj transmit interrupt control register is set to “1”.
Receive
When bit 2 of the UARTk transmit/receive control register 1 is set to
“1”, reception becomes enabled. In this case, when the CLKk signal
is input,
the receive operation starts simultaneously with this signal.
__________
The RTSk output
is “H” when the REK flag is “0”. When the REK flag
__________
is set to “1”, the RTSk output becomes “L”. This informs the transmitter side that reception
becomes enabled. When the receive opera__________
tion starts, the RTSk output automatically becomes “H”.
When the receive operation starts, the receiver takes data from pin
RxDk each time when the transmit clock (CLKj) turns from “L” to “H”.
Simultaneously with reception, the contents of the receiver register
is shifted bit by bit.
(Note that, in the clock synchronous serial communication, the polarity of a transfer clock can be inverted. For details, refer to the section
on the polarity of the transfer clock.) When an 8-bit data is received,
the contents of the receive register is transferred to the receive buffer
register and bit 3 (RIk flag) of UARTk transmit/receive control register 1 is set to “1”. In other words, the setting “1” to the RIk flag indicates that the receive buffer register contains the received data. At
this time, if the low-order byte of the UARTk receive buffer register is
_____
read out, the RTSk output turns back to “L”. This indicates that the
68
next data reception becomes enabled. Bit 4 (OERk flag) of UARTk
transmit/receive control register 1 is set to “1” when the next data is
transferred from the receive register to the receive buffer register
while RIk flag is “1”, and indicates that the next data was transferred
to the receive register before the contents of the receive buffer register was read. (In other words, this indicates that an overrun error has
occurred.) RIk flag is automatically cleared to “0” when the low-order
byte of the receive buffer register is read or when the REk flag is
cleared to “0”. The OERk flag is cleared when the REk flag is
cleared. Bit 5 (FERk flag), bit 6 (PERk flag), and bit 7 (SUMk flag) are
ignored in clock synchronous mode.
As shown in Figure 64, with clock synchronous serial communication, data cannot be received unless the transmitter is operating because the receive clock is created from the transmission clock.
Therefore, the transmitter must be operating even when there is no
need to sent data from UARTk to UARTj.
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1/fi × (n + 1) × 2
Transmission
clock
TEj
TIj
Write in transmit buffer register
Transmit register ←Transmit buffer register
CTSj
1/fi × (n + 1) × 2
Stopped because TEj = “0”
CLKj
TENDj
TXDj
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TXEPTYj
Fig. 70 Clock synchronous serial I/O timing
Interrupt request at completion of reception
When the RIk flag changes from “0” to “1”, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to “1”.
The timing when this interrupt request bit is to be set to “1” can be
selected from the following:
• Each reception
• When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UART receive interrupt mode select bit) is cleared to “0”, the interrupt request
bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt request bit is set to “1” only when an error occurs. (In the clock synchronous serial communication, only when an overrun error occurs,
the interrupt request bit is set to “1”.)
Polarity of transfer clock
In the clock synchronous serial communication, by bit 6 of the UARTj
transmit/receive control register 0 (CPL), the polarity of a transfer
clock can be selected.
As shown in Figure 71, when bit 6 = “0”, the polarity is as follows:
• In transmission, transmit data is output at the falling edge of CLKj.
• In reception, receive data is input at the rising edge of CLKk.
• When not in transfer, CLKi is at “H” level.
When bit 6 = “1”, the polarity is as follows:
• In transmission, transmit data is output at the rising edge of CLKj.
• In reception, receive data is input at the rising edge of CLKk.
• When not in transfer, CLKi is at “L” level.
69
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
■ CLK polarity select bit = 0
CLKi
TxDi
D0
D1
D2
D3
D4
D5
D6
D7
RxDi
D0
D1
D2
D3
D4
D5
D6
D7
❇ Transmit data is output to pin TxDi at the falling edge of transfer clock, and receive data is input from pin
RxDi at the rising edge of transfer clock.
When not in transfer, pin CLKi’s level is “H”.
■ CLK polarity select bit = 1
CLKi
TxDi
D0
D1
D2
D3
D4
D5
D6
D7
RxDi
D0
D1
D2
D3
D4
D5
D6
D7
❇ Transmit data is output to pin TxDi at the rising edge of transfer clock, and receive data is input from pin
RxDi at the falling edge of transfer clock.
When not in transfer, pin CLKi’s level is “L”.
Fig. 71 Polarity of transfer clock
70
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Selection of transfer format
In clock synchronous serial communication, transfer format can be
selected by bit 7 of the transmit/receive control register 0. When bit 7
is “0”, transfer format is LSB first. When bit 7 is “1”, transfer format is
MSB first.
This function is realized by changing connection relation between
Bit 7 in transmit/receive
control register 0
Write to transmit
buffer register
Data bus
0
(LSB first)
Read from receive
buffer register
Transmit buffer
register
Data bus
Receive buffer
register
DB7
D7
DB7
D7
DB6
D6
DB6
D6
DB5
D5
DB5
D5
DB4
D4
DB4
D4
DB3
D3
DB3
D3
DB2
D2
DB2
D2
DB1
D1
DB1
D1
DB0
D0
DB0
D0
Data bus
1
(MSB first)
the transmit buffer register and the receive buffer register when writing transmit data to the transmit buffer register or reading receive
data from the receive buffer register. Accordingly, the transmitter’s
operation is the same in both transfer formats.
Figure 72 shows the connection relation.
Transmit buffer
register
Data bus
Receive buffer
register
DB7
D7
DB7
D7
DB6
D6
DB6
D6
DB5
D5
DB5
D5
DB4
D4
DB4
D4
DB3
D3
DB3
D3
DB2
D2
DB2
D2
DB1
D1
DB1
D1
DB0
D0
DB0
D0
Fig. 72 Connection relation between transmit buffer register, receive buffer register, and data bus
Precautions for clock synchronous serial
communication
________ ________
When using pin CTS0/RTS0, be sure to clear the D-A2 output enable
clock
bit (bit 2 at address 9616) to “0” (output disabled). Also, in the _______
synchronous
serial
communication,
the
separate
function
for
CTSi/
_______
RTSi cannot
be selected. Furthermore, when an internal clock
is se_______
_______
lected, RTS output is undefined. Therefore, do not use the RTS function.
Before transmit operation is performed, be sure to clear bits 2 and 3
of the serial I/O pin control register (address AC16) to “00”.
71
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ASYNCHRONOUS
SERIAL COMMUNICATION
Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits.
Bit 5 is a select bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of 1s
in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1s in the data and parity bit is always even.
Bit 6 is the parity bit select bit which indicates whether to add parity
bit or not.
Bits 4 to 6 must be set or reset according to the data format used in
the communicating devices.
Bit 7 is the sleep select bit. The sleep mode is described later.
Figure 76 shows the bit configuration of the serial I/O pin control
reg________ ________
ister. By bits 0 and 1 of the serial I/O pin _______
control
register (CTSi/RTSi
_______
separate select bits), the function of the CTS/RTS pin can be separated into two functions, and each function can be assigned to two
different pins. When bits 0 and 1 = “11”, the above separation is performed. When bits 0 and 1 = “00”, no separation
is performed.
_______ _______
Table 13 lists the selection methods of the CTS/RTS function.
Asynchronous serial communication can be performed using 7-, 8-, or
9-bit length data. The operation is the same for all data lengths. The
following is the description for 8-bit asynchronous communication.
With 8-bit asynchronous communication, bit 0 of UARTi transmit/receive mode register is “1”, bit 1 is “0”, and bit 2 is “1”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, bit 0 (CS0) and bit 1 (CS1)
of UARTi transmit/receive control register 0 are used to select the
clock source. When an internal clock is selected for asynchronous
serial communication, the CLKi pin can be used as a normal I/O pin.
The selected internal or external clock is divided by (n+1), then by
16, and is passed through a control circuit to create the UART transmission clock or UART receive clock.
Therefore, the transmission speed can be changed by changing the
contents (n) of the bit rate generator. If the selected clock is an internal clock Pfi or an external clock fEXT,
Bit Rate = (fi or fEXT) / {(n+1)×16}
(1/fi or 1/fEXT) × (n + 1) × 16
Transmission clock
TEi
TIi
Transmit register ← Transmit
buffer register
Written in transmit buffer register
CTSi
TENDi
Start bit
TXDi
Stopped because TEi = “0”
Parity bit Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP ST D0 D1 D2 D3 D4 D5 D6 D7
P SP
ST D0 D1
TXEPTYi
Fig. 73 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected
(1/fi or 1/fEXT) × (n + 1) × 16
Transmission clock
TEi
TIi
Transmit register ← Transmit
buffer register
Written in transmit buffer register
TENDi
Start bit
TX Di
Stop bit
Stop bit
Stopped because TEi = “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
TXEPTYi
Fig. 74 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected
72
ST D0 D1 D2
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transmission
________
Transmission is started when bit 0 (TEi flag transmit enable flag) of
UARTi
transmit/receive control register 1 is “1”, bit 1 (TIi flag) is “0”,
________
and CTSi input (in other words, transmit enable signal input from receiver) is “L.” The TIi flag indicates whether the transmit buffer is
empty or not. It is cleared to “0” when data is written in the transmit
buffer; it is set to “1” when the contents of the transmit buffer register
is transferred to the transmit register.
When all of the transmission conditions are satisfied, transmit data
is transferred to the transmit register, and transmit operation starts.
As shown in Figures 73 and 74, data is output from the TXDi pin with
the stop bit or parity bit specified by bits 4 to 6 of UARTi transmit/receive mode register. The data is output from the least significant bit.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmit start condition is satisfied. Then, the next transmission is performed
succeedingly.
Once transmission has started, the TEi flag, TIi flag, and CTSi signal
are ignored until data transmission is completed.
Therefore, transmission does not stop until it completes event if, during transmission, the TEi flag is cleared to “0” or CTSi input is set to
“1”.
The
transmission start condition indicated by TEi flag, TIi flag, and
________
CTSi is checked while the TENDi signal shown in Figure 73 is “H”.
Therefore, data can be transmitted continuously if the next transmission data is written in the transmit buffer register and TIi flag is
cleared to “0” before the TENDi signal goes “H”.
Bit 3 (TXEPTYi flag) of UARTi transmit/receive control register 0
changes to “1” at the next cycle just after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmit interrupt control register is set to “1”.
fi or fEXT
REi
Stop bit
RXDi
Start bit
Check to be “L” level
Receive
clock
D1
D0
Start bit
D7
Data fetched
Starting at the falling
edge of start bit
RIi
RTSi
Fig. 75 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected
73
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 13. Selection methods of CTS/RTS function
CTS/RTS
enable bit
0
1
Functions
CTSi/RTSi
CTS/RTS
separate select bit function select bit Pin P80/CTS0/RTS0 (Note 1) Pin P81/CTS0/CLK0
Pin P85/CTS1/CLK1
Pin P84/CTS1/RTS1
0
CTS1
CTS0
P85 or CLK1
P81 or CLK0
0
1
RTS1
RTS0
P85 or CLK1
P81 or CLK0
1
✕
RTS1
RTS0
CTS1 (Notes 2 and 3)
CTS0 (Notes 2 and 3)
✕
✕
P84
P85 or CLK1
P81 or CLK0
P80
✕: It may be “0” or “1”.
Notes 1: When using the CTS0/RTS0 pin, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0”.
2: When using the CTS function, be sure to clear the corresponding bit of the port P8 direction register to “0”.
3: When CTSi and RTSi has been separated, the CLKi pin cannot be used. Therefore, in the clock synchronous serial communication, CTSi and RTSi
cannot be separated. Also, when CTSi and RTSi are separated in UART mode, be sure to select an internal clock.
Receive
7 6 5 4 3 2 1 0
Address At reset
Serial I/O pin control register AC16
X016
CTS0/RTS0 separate select bit
0 : CTS0/RTS0 are used together.
1 : CTS0/RTS0 are separated.
CTS1/RTS1 separate select bit
0 : CTS1/RTS1 are used together.
1 : CTS1/RTS1 are separated.
TxD0/P83 switch bit
0 : Functions as TxD0.
1 : Functions as P83.
TxD1/P87 switch bit
0 : Functions as TxD1.
1 : Functions as P87.
Fig. 76 Bit configuration of serial I/O pin control register
74
Receive is enabled when bit 2 (REi flag) of UARTi transmit/receive
control register 1 is set to “1.” As shown in Figure 75, the frequency
divider circuit (1/16) at the receiving side begin to work when a start
bit________
arrives and the data is received.
If RTSi output is selected by________
setting bit 2 of UARTi transmit/receive
control register 0 to “1”, the RTSi output is “H”
when the REi flag is
________
“0”. When the REi flag changes to “1”, the RTSi output goes “L” to
inform the receiver that reception
has become enabled. When the
________
receive operation starts, the RTSi output automatically becomes “H”.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 66. At this
point, the contents of the receive register is transferred to the receive
buffer register and bit 3 (Rli flag) of UARTi transmit/receive control
register 1 is set to “1.” In other words, the RIi flag indicates that the
receive buffer register contains data when it is set to “1.” At this time,
when
the low-order byte of the UARTk receive buffer register is read
________
out, RTSi output goes back to “L” to indicate that the register is ready
to receive the next data.
Bit 4 (OERi flag) of UARTi transmit/receive control register 1 is set to
“1” when the next data is transferred from the receive register to the
receive buffer register while the RIi flag is “1”, in other words, when
an overrun error occurs. If the OERi flag is “1”, it indicates that the
next data has been transferred to the receive buffer register before
the contents of the receive buffer register has been read.
Bit 5 (FERi flag) is set to “1” when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set to “1” when a parity error occurs.
Bit 7 (SUMi flag) is set to “1” when either the OERi flag, FERi flag, or
the PERi flag is set to “1.” Therefore, the SUMi flag can be used to
determine whether there is an error.
The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is
performed while transferring the contents of the receive register to
the receive buffer register.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The FERi, PERi, and SUMi flags are cleared to “0” when reading the
low-order byte of the receive buffer register or when writing “0” to the
REi flag.
The OERi flag is cleared to “0” when writing “0” to the REi flag.
Interrupt request at completion of reception
When the RIk flag changes from “0” to “1”, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to “1”.
The timing when this interrupt request bit is to be set to “1” can be
selected from the following:
• Each reception
• When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UART receive interrupt mode select bit) is cleared to “0”, the interrupt request
bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt
request bit is set to “1” only when an error occurs. (In the clock asynchronous serial communication, when an overrun error, framing error, or parity error occurs, the interrupt request bit is set to “1”.)
Sleep mode
The sleep mode is used to communicate only between certain microcomputers when multiple microcomputers are connected through
serial I/O.
The microcomputer enters the sleep mode when bit 7 of UARTi
transmit/receive mode register is set to “1.”
The operation of the sleep mode for an 8-bit asynchronous communication is described below.
When sleep mode is selected, the contents of the receive register is
not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asynchronous communication and bit 8 if 9-bit asynchronous communication) of the received data is “0”. Also the RIi, OERi, FERi, PERi,
and the SUMi flags are unchanged. Therefore, the interrupt request
bit of the UARTi receive interrupt control register is also unchanged.
Normal receive operation takes place when bit 7 of the received data
is “1”.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data: bit 7 is “1” and bits 0 to 6
are set to the address of the subordinate microcomputer to be communicated with. Then all subordinate microcomputers receive this
data. Each subordinate microcomputer checks the received data,
clears the sleep bit to “0” if bits 0 to 6 are its own address and sets
the sleep bit to “1” if not. Next, the main microcomputer sends data
with bit 7 cleared. Then the microcomputer which cleared the sleep
bit will receive the data, but the microcomputers which set the sleep
bit to “1” will not. In this way, the main microcomputer is able to communicate only with the designated microcomputer.
Precautions for clock asynchronous (UART)
serial communication
________ ________
When using pin CTS0/RTS0, be sure to clear the D-A2 output enable
_______
bit (bit
2 at address 9616) to “0” (output disabled). Also, when CTSi
_______
and
RTSi are
separated, pin CLKi cannot be used. Therefore, when
_______
_______
CTSi and RTSi are separated in UART mode, be sure to select an
internal clock.
Before transmit operation is performed, be sure to clear bits 2 and 3
of the serial I/O pin control register (address AC16) to “00”.
75
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D converter is a 10-bit successive approximation converter.
Figure 77 shows the block diagram of the A-D converter, Figure 78
shows the bit configuration of the A-D control register 0 (address
1E16), and Figure 79 shows the bit configuration of the A-D control
register 1 (address 1F16).
A-D conversion accuracy
Bit 3 of A-D control register 1 is used to select whether to regard the
conversion result as 10-bit or as 8-bit data. The conversion result is
regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3
is “0”.
When the conversion result is used as 10-bit data, the low-order 8
bits of the conversion result is stored in the even address of the corresponding A-D register and the high-order 2 bits are stored in bits 0
and 1 at the odd address of the corresponding A-D register. Bits 2 to
7 of the A-D register odd address are “0000002” when read.
When the conversion result is used as 8-bit data, the conversion result are stored in even address of the corresponding A-D register. In
this case, the value at the A-D register’s odd address is “0016” when
read.
A-D conversion frequency
An operation clock (φAD) of an A-D converter can be selected with bit
7 of the A-D control register 0 and bit 4 of the A-D control register 1.
When bit 4 of the A-D control register 1 is “0”, φAD becomes f2/4
when bit 7 of the A-D control register 0 is “0”, φAD becomes f2/2 when
bit 7 of the A-D control register 0 is “1”.
When bit 4 of the A-D control register 1 is “1”, φAD becomes f2 when
bit 7 of the A-D control register 0 is “0”, φAD becomes f1 when bit 7 of
the A-D control register 0 is “1”. Note that φAD = f1 (in other words,
the fastest speed) can be selected only in the 8-bit mode.
φAD during A-D conversion must be 250 kHz or more because the
comparator uses a capacity coupling amplifier.
A-D conversion
frequency selection
(1,1)
f1
(1,0)
(0,1)
1/2
f2
1/2
VREF connection select bit
VREF
AVSS
(0,0)
A-D conversion frequency
(φAD) select bit 1,0
0
1
φAD
Resistor ladder network
Vref
Successive
approximation register
A-D control register 1
A-D control register 0
A-D register 0
A-D register 1
Comparator
A-D register 2
A-D register 3
Decoder
A-D register 4
A-D register 5
A-D register 6
A-D register 7
Data bus (odd)
Data bus (even)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7/ADTRG
Selector
Fig. 77 Block diagram of A-D converter
76
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Trigger
A-D conversion can be started by an internal trigger or by an external trigger.
An internal trigger is selected when bit 5 of A-D control register 0 is
“0” and an external trigger is selected when it is “1”. When trigger is
selected, A-D conversion is started when bit 6 (A-D conversion start
bit) is set to “1.”
When an external trigger is selected, the polarity of a trigger input
can be selected by bit 5 of the A-D control register 1. When bit 5 =
“0”, a falling edge is selected, and when bit 5 = “1”, a rising edge is
selected.
A-D conversion starts when the A-D conversion start bit is “1” and the
______
ADTRG input changes from “H” to “L” (or “L” to “H.”) In this case, the
pins that can be used for A-D conversion are AN0 to AN6 because the
______
ADTRG pin is multiplexed with an analog voltage input pin, AN7. If an
7
6
5
4
3
2
1
external trigger is selected, even when the A-D conversion is completed, the A-D conversion start bit keeps “1”. Also, a retrigger can be
available even when A-D conversion is in progress.
VREF connection
Whether to connect the reference voltage input (VREF) with the resistor ladder network or not depends on bit 6 of the A-D control register
1. The VREF pin is connected when bit 6 is “0” and is disconnected
when bit 6 is “1” (High impedance state).
When A-D conversion is not performed, current from the VREF pin to
the resistor ladder network can be cut off by disconnecting resistor
ladder network from the VREF pin.
Before starting A-D conversion, wait for 1 µs or more after clearing
bit 6 to “0”.
0
A-D control register 0
Address
1E16
Analog input select bits (Note 1)
(Valid in the one-shot and repeat modes.)
0 0 0 : Select AN0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN4 (Note 2)
1 0 1 : Select AN5 (Note 3)
1 1 0 : Select AN6 (Note 4)
1 1 1 : Select AN7 (Note 5)
A-D operation mode select bits
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode
Trigger select bit
0 : Internal trigger
1 : External trigger due to ADTRG input (Note 6)
A-D conversion start bit (Note 7)
0 : Stop A-D conversion
1 : Start A-D conversion
A-D conversion frequency (φAD) select bit 0
Notes 1: Ignored in the single sweep and repeat sweep modes. (Each of these bits may be “0” or “1”.)
2: When using the AN4 pin, be sure to clear the INT3 pin select bit (bit 5 at address 9416) to “0”.
3: When using the AN5 pin, be sure to clear the INT4 pin select bit (bit 6 at address 9416) to “0”.
4: When using the AN6 pin, be sure to clear the D-A0 output enable bit (bit 0 at address 9616) to “0” (output disabled).
5: When using the AN7 pin, be sure to clear both of the INT2 pin select bit (bit 4 at address 9416) and the D-A1
output enable bit (bit 1 at address 9616) to “0”.
6: When using an external trigger, be sure to clear the INT2 pin select bit (bit 4 at address 9416) and D-A1 output
enable bit (bit 1 at address 9616) to “0”.
7: For writing to this bit, use the MOVM (MOVMB) instruction, or the STA (STAB, STAD) instruction.
8: Rewriting to each bit of the A-D control register 0 (except for bit 6) must be performed while A-D conversion is stopped.
Fig. 78 Bit configuration of A-D control register 0
77
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7
6
5
4
3
2
0
1
0
A-D control register 1
Address
1F16
A-D sweep pin select bits (Note 1)
(Valid in the single sweep mode and repeat sweep mode.)
0 0 : AN0, AN1
(2 pins)
0 1 : AN0–AN3
(4 pins)
1 0 : AN0–AN5
(6 pins) (Notes 2, 3)
1 1 : AN0–AN7
(8 pins) (Notes 2 to 5)
Must be “0”.
Resolution select bit
0: 8-bit mode
1: 10-bit mode
A-D conversion frequency (φAD) select bit 1
External trigger polarity select bit
(Valid when external trigger is selected.)
0: Falling edge of input signal to the ADTRG pin
1: Rising edge of input signal to the ADTRG pin
VREF connection select bit (Note 6)
0 : VREF is connected.
1 : VREF is not connected.
“0” at read.
A-D conversion frequency (φAD) select bit
Bit 1
Bit 0
0
0
1
0
1
0
1
1
φAD
f2/4
f2/2
f2
f1 (Selectable only in 8-bit mode)
Notes 1: Ignored in the one-shot and repeat modes. (Each of these bits may be “0” or “1”.)
2: When using the AN4 pin, be sure to clear the INT3 pin select bit (bit 5 at address 9416) to “0”.
3: When using the AN5 pin, be sure to clear the INT4 pin select bit (bit 6 at address 9416) to “0”.
4: When using the AN6 pin, be sure to clear the D-A0 output enable bit (bit 0 at address 9616) to
“0” (output disabled).
5: When using the AN7 pin, be sure to clear both of the INT2 pin select bit (bit 4 at address 9416)
and the D-A1 output enable bit (bit 1 at address 9616) to “0”. When an external trigger is selected,
the AN7 pin cannot be used as an analog input pin.
6: Once this bit is cleared from “1” to “0”, it is necessary to wait for 1 µs or more before the A-D or
D-A conversion starts.
7: Rewriting to each bit of the A-D control register 1 must be performed while A-D conversion is stopped.
Fig. 79 Bit configuration of A-D control register 1
78
MITSUBISHI MICROCOMPUTERS
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Operation mode
The operation mode is selected by bits 3 and 4 of A-D control register 0. The available operation modes are one-shot, repeat, single
sweep, and repeat sweep. Analog input port pins are multiplexed
with port P7 pins. Therefore, bits which correspond to pins for A-D
conversion must be “0” (input mode).
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register
0 are “0” is “0”. The A-D conversion pins are selected with bits 0 to 2
of A-D control register 0. A-D conversion can be started by a software trigger or by an external trigger.
When an internal trigger is selected, A-D conversion is started when
bit 6 (A-D conversion start bit) is set to “1.”
When bit 3 of the A-D control register 1 is “1”, A-D conversion ends
after 59 φAD cycles, and the interrupt request bit of the A-D interrupt
control register is set to “1.” At the same time, A-D control register 0
bit 6 (A-D conversion start bit) is cleared to “0” and A-D conversion
stops. The result of A-D conversion is stored in the A-D register corresponding to the selected pin.
If an external trigger is selected, A-D conversion starts when the A-D
conversion start bit is “1” and a valid edge is input to the ADTRG pin,
This operation is the same as that for internal trigger except that
the A-D conversion start bit is not cleared after A-D conversion and
a retrigger can be available during A-D conversion.
(2) Repeat mode
Repeat mode is selected when bit 3 of A-D control register 0 is “1”
and bit 4 is “0”.
The operation of this mode is the same as the operation of one-shot
mode except that when A-D conversion of the selected pin is complete and the result is stored in the A-D register, conversion does not
stop, but is repeated.
No interrupt request is generated in this mode. Furthermore, if an
external trigger is selected, the A-D conversion start bit is not
cleared.
The contents of the A-D register can be read at any time.
When A-D conversion of all selected pins end, the interrupt request
bit of the A-D conversion interrupt control register is set to “1.” At the
same time, A-D conversion start bit is cleared to “0” and A-D conversion stops.
When an external trigger is selected, A-D conversion starts when the
A-D conversion start bit is “1” and a valid edge is input to the ADTRG
pin. In this case, the A-D conversion result which is stored in the A-D
register 7 becomes invalid.
The operation by external trigger is the same as that by an internal
trigger except that the A-D conversion start bit is not cleared to “0”
after A-D conversion and a retrigger can be available during A-D
conversion.
(4) Repeat sweep mode
Repeat sweep mode is selected when bit 3 of A-D control register 0
is “1” and bit 4 is “1”.
The difference from the single sweep mode is that A-D conversion
does not stop after conversion for all selected pins, but repeats again
from the AN0 pin. The repeat is performed among the selected pins.
Also, no interrupt request is generated. Furthermore, if an internal
trigger is selected, the A-D convension start bit is not cleared. The
A-D register can be read at any time.
Precautions for A-D conversion interrupt
function
Clear the interrupt request bit of the A-D interrupt control register (bit
3 at address 7016) before using the A-D interrupt. It is because the
interrupt request bit is undefined just after reset.
(3) Single sweep mode
Single sweep mode is selected when bit 3 of A-D control register 0 is
“0” and bit 4 is “1”.
In the single sweep mode, the number of analog input pins to be
swept can be selected. Analog input pins are selected by bits 1 and
0 of the A-D control register 1 (address 1F16). Two pins, four pins, six
pins, or eight pins can be selected as analog input pins, depending
on the contents of these bits.
A-D conversion is performed only for selected input pins. After A-D
conversion is performed for input of AN0 pin, the conversion result is
stored in A-D register 0, and in the same way, A-D conversion is performed for selected pins one after another. After A-D conversion is
performed for all selected pins, the sweep is stopped.
A-D conversion can be started with an internal trigger or with an external trigger input. An internal trigger is selected when bit 5 of the AD control register 0 (address 1E16) is “0” and an external trigger is
selected when it is “1”.
When an internal trigger is selected, A-D conversion is started when
A-D control register 0 bit 6. (A-D conversion start bit) is set to “1.”
79
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A CONVERTER
Three independent D-A converters are included in this microcomputer, and each D-A converter adopts an 8-bit R-2R method. Figure
80 shows the block diagram of the D-A converter, Figure 81 shows
the bit configuration of the A-D control register 1, and Figure 82
shows the bit configuration of the D-A control register.
D-A conversion is performed by writing a value to the corresponding
D-A register i. Whether to output the analog voltage or not is determined by bits 0 to 2 of the D-A control register. When any of bits 0 to
2 = “1”, the corresponding pin (D-A0 to D-A2) outputs the analog voltage.
This analog voltage (V) is determined according to value n. (“n” =
decimal number. This has been set in the D-A register.)
with pin D-Ai.
Also, when not using the D-A converter, be sure to clear the contents
of the corresponding D-A output enable bit and D-A register to “0”.
7 6 5 4 3 2 1 0
✕
✕ ✕ ✕ ✕ ✕ ✕
A-D control register 1
Not used for D-A converter.
VREF connection select bit (Note)
0: Connected.
1: Disconnected.
Note: When bit 6 has been cleared to “0” from “1”, insert a waiting time
of 1 µs or more, and then, start the D-A or A-D conversion.
V = VREF ✕ n/256 (n = 0 to 255)
VREF : Reference voltage
Fig. 81 Bit configuration of A-D control register 1
The contents of the corresponding D-A output enable bit and D-A
register are cleared to “0” at reset. Whether to connect the reference
voltage input (VREF) with the ladder network or not depends on bit 6
of the A-D control register 1. Pin VREF is connected with the ladder
network when bit 6 = “0” and is disconnected when bit 6 = “1” (high
impedance state). When not performing the A-D or D-A conversion,
current from pin VREF to the ladder network can be cut off by disconnecting ladder network from pin VREF.
Before starting A-D or D-A conversion, be sure to clear bit 6 to “0”,
and then, insert a waiting time of 1 µs or more.
An external buffer is necessary when connecting a low impedance
load with the D-A converter. It is because that a D-A output pin
doesn’t include a buffer.
Pin D-Ai is multiplexed with I/O port pins, analog input pins, serial
I/O pins, and external interrupt input pins. When a D-Ai output enable
bit = “1” (in other words, output is enabled.), however, the corresponding pin cannot function as another I/O pin, which is multiplexed
7 6 5 4 3 2 1 0
D-A control register
D-A1 output enable bit (Note)
0: Output is disabled.
1: Output is enabled.
D-A2 output enable bit (Note)
0: Output is disabled.
1: Output is enabled.
Note: Pin D-Ai is multiplexed with I/O port pins, analog input pins, serial
I/O pins, and external interrupt input pins. When a D-Ai output
enable bit = “1” (in other words, output is enabled.), however, the
corresponding pin cannot function as another I/O pin, which is
multiplexed with pin D-Ai.
Fig. 82 Bit configuration of D-A control register
VREF connection
select bit
D-A register i (i = 0 to 2)
(Addresses 9816 to 9A16)
0
1
AVSS
R-2R ladder
network
D-Ai output enable bit
Pin D-Ai
Fig. 80 Block diagram of D-A converter
80
Address
9616
D-A0 output enable bit (Note)
0: Output is disabled.
1: Output is enabled.
Data bus
VREF
Address
1F16
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REAL-TIME OUTPUT
The real-time output function enables to change the output level of
several pins simultaneously with a specified timer’s counting.
Whether to use the real-time output function is decided by the waveform output select bits of the 8-bit real-time output control register
(bits 0 and 1 at address A016). (See Figure 83.) Also, the real-time
output controlled by the pulse output mode select bit of the real-time
output control register (bit 2 at address A016) and is used in one of
the following ways:
• 4 bits ✕ 2 channels
• 6 bits ✕ 1 channel + 2 bits ✕ 1 channels
(low-order 4 bits at address A216), which corresponds to RTP03 to
RTP00, is output to these ports each time when the contents of timer
A0 counter becomes “000016”.
When “0” is written to a specified bit of the pulse output data register,
a low-level signal is output to a pulse output port if the counter contents of the timer which corresponds to the bit becomes “000016”:
when “1” is written to the bit, a high-level signal is output to a pulse
output port which corresponds to the bit at the same timing.
7
6
5
4
3
2
1
0
(1) Pulse mode 0
Real-time output register
When the pulse output mode select bit is cleared to “0”, the microcomputer enters pulse output port is controlled by 2 groups of 4 bits.
Figures 84 and 85 show the bit configuration of the pulse output data
register 0/1 (address A216/A416) and real-time output structure in
pulse mode 0, respectively.
When the waveform output select bits are set to “01” (bit 1 = “0” and
bit 0 = “1”), RTP03 to RTP00 become pulse output port pins, in other
words, RTP0 is selected.
When the waveform output select bits are set to “10” (bit 1 = “1” and
bit 0 = “0”), RTP13 to RTP10 become pulse output port pins, in other
words, RTP1 is selected.
When the waveform output select bits are set to “11” (bit 1 = “1” and
bit 0 = “1”), two groups consisting of RTP13 to RTP10 and RTP03 to
RTP00 become pulse output port pins, in other words, RTP1 and
RTP0 are selected.
When the waveform output select bits are set to “00” (bit 1 = bit 0 =
“0”), port P5 pins become normal programmable I/O port pins.
The contents of the pulse output data register 1 (high-order 4 bits at
address A416), which corresponds to RTP13 to RTP10, is output to
these ports each time when the contents of timer A1 counter becomes “000016”. The contents of the pulse output data register 0
7
6
5
4
3
2
1
Address
0
Pulse output data register 0
A216
RTP00 pulse output data bit
RTP01 pulse output data bit
RTP02 pulse output data bit (Note 1)
RTP03 pulse output data bit (Note 1)
Address
A016
Waveform output select bits
00 : Programmable I/O port
01 : RTP0 selected
When pulse mode 0 is selected:
RTP0
When pulse mode 1 is selected:
RTP01, RTP00
10 : RTP1 selected
When pulse mode 0 is selected:
RTP1
When pulse mode 1 is selected:
RTP1, RTP03, RTP02
11 : RTP1 and RTP0 selected
When pulse mode 0 is selected:
RTP1 and RTP0
When pulse mode 1 is selected:
RTP1, RTP03, RTP02 and
RTP01, RTP00
Pulse output mode select bit
0 : Pulse mode 0
1 : Pulse mode 1
“0” at read.
Fig. 83 Bit configuration real-time output control register
7
6
5
4
3
2
1
Address
0
Pulse output data register 1
A416
RTP02 pulse output data bit (Note 2)
RTP03 pulse output data bit (Note 2)
RTP10 pulse output data bit
RTP11 pulse output data bit
RTP12 pulse output data bit
RTP13 pulse output data bit
Note 1: Used only in pulse mode 0
2: Used only in pulse mode 1
Fig. 84 Bit configuration of pulse output data register
81
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A2
Pulse output mode select bit
(Address A016)
Pulse output data register 1
(Address A416)
D7
D6
Data bus (Even)
D5
D4
T
D Q
T
D Q
T
D Q
T
D Q
0
a
P57/RTP13
a
P56/RTP12
a
P55/RTP11
a
P54/RTP10
Waveform output select bit (Address A016)
D3
D2
D1
D0
D Q
T
D Q
T
D Q
T
D Q
T
a
P53/RTP03
a
P52/RTP02
a
P51/RTP01
a
bit 1
P50/RTP00
Waveform output select bit (Address A016)
bit 0
Pulse output data register 0
(Address A216)
Timer A0
a
Port P5i direction register
(Address D16)
“1”
Port P5i latch
(i = 7 to 0) (Address B16)
“0”
Fig. 85 Real-time output structure in pulse mode 0
(2) Pulse mode 1
When the pulse output mode select bit is set to “1”, the microcomputer enters pulse mode 1, and a pulse output port pins are separately controlled (6 bits and 2 bits).
Figures 86 shows the real-time output structure in pulse mode 1.
When the waveform output select bits are set to “01” (bit 1 = “0” and
bit 0 = “1”), RTP13 to RTP10, RTP03, and RTP02 become programmable I/O port pins. Simultaneously, RTP01 and RTP00 become
pulse output port pins.
When the waveform output select bits are set to “10” (bit 1 = “1” and
bit 0 = “0”), RTP13 to RTP10, RTP03, and RTP02 become pulse output port pins. At this time, RTP01 and RTP00 become programmable
I/O port pins.
When the waveform output select bits are set to “11” (bit 1 = bit 0 =
82
“1”), pulse output port pins are divided into two groups; one consists
of RTP13 to RTP10, RTP03, RTP02 and the other consists of RTP01
and RTP00.
When the waveform output select bits are set to “00” (bit 1 = bit 0 =
“0”), port P5 pins become normal programmable I/O port pins.
RTP13 to RTP10, RTP03, and RTP02 are controlled by timer A2.
Also, RTP01 and RTP00 are controlled by timer A0.
The contents of the pulse output data register 1 (high-order 6 bits at
address A416), which corresponds to RTP13 to RTP10, RTP03, and
RTP02, are output to this port each time when the contents of timer
A2 counter becomes “000016”. The contents of the pulse output data
register 0 (low-order 2 bits at address A216), which corresponds to
RTP01 and RTP00, are output to this port each time when the contents of timer A0 counter become “000016”.
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A2
Pulse output mode select bit
(Address A016)
Pulse output data register 1
(Address A416)
D7
D6
D5
Data bus (Even)
D4
D3
D2
T
D Q
T
D Q
T
D Q
T
D Q
T
D Q
T
D Q
1
a
P57/RTP13
a
P56/RTP12
a
P55/RTP11
a
P54/RTP10
a
P53/RTP03
a
P52/RTP02
Waveform output select bit (Address A016)
D1
D0
D Q
T
D Q
T
a
P51/RTP01
a
P50/RTP00
Pulse output data register 0
(Address A216)
Timer A0
bit 1
Waveform output select bit (Address A016)
a
bit 0
Port P5i direction register
(Address D16)
“1”
Port P5i latch
(i = 7 to 0)
“0”
(Address B16)
Fig. 86 Real-time output structure in pulse mode 1
Table 14 lists the port P5/RTP pin output when all of the port P5 direction registers are set to the output mode.
Precautions for real-time output function
After reset, the port P5 direction register is set to the input mode, and
port P5i (i = 0 to 7) pins function as normal I/O port pins. When using
these pins as real-time output port pins, set the corresponding bits of
the port P5 direction register to the output mode. Additionally, by
reading the real-time output port’s value from the port P5 register,
output level of pins can be read out.
Table 14 Port P5/RTP pin output
Real-time output
control register
(Address A016)
bit
bit
bit
2
1
0
0
0
1
0
0
0
1
1
1
0
0
1
0
1
0
1
1
1
Store address for port P5/RTP pin output data
bit
7
0B
0B
A4
A4
0B
0B
A4
A4
bit
6
0B
0B
A4
A4
0B
0B
A4
A4
bit
5
0B
0B
A4
A4
0B
0B
A4
A4
bit
4
0B
0B
A4
A4
0B
0B
A4
A4
bit
3
0B
A2
0B
A2
0B
0B
A4
A4
bit
2
0B
A2
0B
A2
0B
0B
A4
A4
bit
1
0B
A2
0B
A2
0B
A2
0B
A2
bit
0
0B
A2
0B
A2
0B
A2
0B
A2
Address 0B16: Port P5
Address A216: Pulse output data register 0
Address A416: Pulse output data register 1
83
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
comes “0” and an interrupt is generated.
The microcomputer can generate a reset pulse by writing “1” to bit 6
(software reset bit) of processor mode register 0 in an interrupt routine and can be restarted.
The watchdog timer can also be used to return from the STP state,
where a clock has stopped its operation owing to the STP instruction
execution. For details, refer to the sections on the clock generating
circuit and standby function.
The watchdog timer stops its operation in the following cases, and at
this time, input to the watchdog timer is disabled:
• When the external area is accessed in the hold state
• In the wait mode
• In the stop mode
The watchdog timer is used to detect unexpected execution sequence caused by software runaway and others. Figure 87 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf32, which is obtained by dividing
the peripheral devices’ clock f2 by 16; or clock Wf512, which is obtained by doing it by 256. Bit 0 of the watchdog timer frequency select register (watchdog timer frequency select bit) shown in Figure 88
selects which clock is to be counted.
Wf512 is selected when this bit 0 is “0”, and Wf32 is selected when bit
0 is “1”. Bit 0 is cleared to “0” after reset.
FFF16 is set in the watchdog timer when “L” level voltage is applied
to pin RESET, STP instruction is executed, data is written to the
watchdog timer register (address 6016), or the most significant bit of
the watchdog timer becomes “0”.
After FFF16 is set in the watchdog timer, when the watchdog timer
counts Wf32 or Wf512 by 2048 counts, the most significant bit of
watchdog timer becomes “0”, the watchdog timer interrupt request
bit is set to “1”, and FFF16 is set again in the watchdog timer.
In program coding, make sure that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“0”. If this routine is not executed owing to unexpected program execution or others, the most significant bit of the watchdog timer be-
7
6
5
4
3
2
1
0
Watchdog timer frequency select register
Address
6116
Watchdog timer frequency select bit
0 : W f512
1 : W f32
Watchdog timer clock source select bits at STP
state termination
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
Fig. 88 Bit configuration of watchdog timer frequency select register
Access to
external area
HLDA
f2
Wf32
1/16
Wait mode
1/16
1
Wf512
Divided f(XIN)
Watchdog timer
frequency select bit
0
fX16
fX32
fX64
fX128
Watchdog timer
interrupt request
Watchdog timer
❈
Stop mode
“FFF16” is set.
Disables watchdog
timer (Note).
Watchdog timer clock source select
bits at STP state termination
Writing to watchdog
timer register
RESET
STP instruction
• Watchdog timer register: address 6016
• Watchdog timer frequency select register: bit 0 at address 6116
• Watchdog timer clock source select bits at STP state termination: bits 6, 7 at address 6116
❈ When the most significant bit of the watchdog timer becomes “0”, this signal will be generated.
Note: During the stop mode and until the stop mode is terminated, setting for disabling the
watchdog timer is ignored.
Fig. 87 Block diagram of watchdog timer
84
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
How to disable watchdog timer
When not using the watchdog timer, it can be disabled. When the
watchdog timer is disabled, it’s operation stops and no watchdog
timer interrupt has been generated.
Setting for disabling the watchdog timer is possible by writing “7916”
and “5016” to the particular function select register 2 (address 6416)
sequentially with the following instructions:
• MOVMB/STAB instruction, or
• MOVM/STA instruction (m = 1)
If any method other than above has been adopted in order to access
(in other words, read/write) the particular function select register 2,
the watchdog timer will not be disabled until reset operation is performed. (Also, reset is the only one method to remove the setting for
disabling the watchdog timer.)
Moreover, this setting for disabling the watchdog timer is ignored at
return from the STP mode, and the watchdog timer operates. (For
details, refer to the section on the standby function.)
85
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INPUT/OUTPUT PINS
Ports P0 to P8, P10, P11 all have the direction register, and each bit
can be programmed for input or output. A pin becomes an output pin
when the corresponding bit of direction register is “1”, and an input
pin when it is “0”.
When a pin is programmed for output, the data is written to its port
latch and it is output to the output pin. When a pin is programmed for
output, the contents of the port latch is read instead of the value of
the pin. Accordingly, a previously output value can be read correctly
even when the output “H” voltage is lowered or the output “L” voltage
is raised owing to an external load, etc.
A pin programmed as an input pin is in the flooting state, and the
value input to the pin can be read. When a pin is programmed as an
input pin, the data is written only in the port latch and the pin remains
floating.
Each of Figures 89 and 90 shows the block diagram for each port pin
and pin NMI. Figure 91 shows the bit configuration of the port function control register.
Bit 3 of the port function control register serves as the port P0 input
level select bit, which selects the VIH/VIL level under the condition
that port P0 is used as an input port.
Bit 4 of the port function control register serves as the P44–P47
7
6
5
0
0
4
3
2
1
pullup connection select bit. This bit determines whether port pins
P44–P47, which are multiplexed with chip select pins, are to be
pulled up or not. At reset, this bit 4 = “0” and P4–P47 are pulled up.
The pullup function is valid only when the corresponding port is used
an input port.
Bit 7 of the port function control register serves as the NMI pullup
connection select bit. At reset, this bit 7 = “0” and pin NMI is pulled
up. The pullup function is valid only when the corresponding port is
used as an input port.
When using port pins P54–P57 as the key input interrupt input pins
(KI0 to KI3), the pullup function can be selected, also. For details,
refer to the section on interrupts.
When using a port pin as an internal peripheral device’s input pin,
clear the corresponding port direction register’s bit to “0”. When using a port pin as an internal peripheral device’s output pin, the port
direction register’s bit may be “0” or “1”.
In the memory expansion or microprocessor mode, port pins of P0 to
P4, P10, P11 become I/O pins, and the their functions as I/O port
pins are invalid. Note that, however, some port pins can function as
port pins by the special setting. For details, refer to the section on the
processor modes.
0
Port function control register
Address
9216
At reset
0016
Address/Port switch bits
000 : A0 to A23 (16 Mbytes)
001 : A0 to A21, P06, P07 (4 Mbytes)
010 : A0 to A19, P04 to P07 (1 Mbytes)
011 : A0 to A17, P02 to P07 (256 Kbytes)
100 : A0 to A15, P00 to P07 (64 Kbytes)
101 : Do not select.
110 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
111 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
Port P0 input level select bit
0 : VIH = 0.7VCC, VIL = 0.2VCC
1 : VIH = 0.43VCC (Note 1), VIL = 0.16VCC
Pins P44–P47 pullup connection select bit (Notes 2 and 3)
0 : Pins P44–P47 are pulled up.
1 : Pins P44–P47 are not pulled up.
Fix these bits to “0”.
Pin NMI pullup connection select bit (Note 2)
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up.
Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5VCC.
2: When MD1 = VCC and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are
not pulled up, regardless of these bits’ contents.
3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bit’s contents.
Fig. 91 Bit configuration of port function control register
86
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[Inside dotted-line not included]
P00 to P07, P10 to P17, P20 to P27,
P31 to P33, P100 to P107,
P110 to P117
Direction register
Data bus
Port latch
[Inside dotted-line included]
P30 /RDY, P4 3/HOLD,
P6 1/TA4IN,
P6 2/INT0, P6 3/INT1, P64/INT2,
P6 5/TB0IN, P6 6/TB1IN, P67 /TB2IN,
P8 2/RXD0, P8 6/RXD1
[Inside dotted-line not included]
P40/ALE, P41/φ1, P42/HLDA,
P83/TXD0, P87/TXD1
Pullup selection
Pullup
transistor
Direction register
1
[Inside dotted-line included]
P60 /TA4OUT
Output(Internal peripheral devices)
Data bus
Port latch
[Shaded area included]
P44 /CS0, P45/CS1,
P46 /CS2, P47 /CS3
[Shaded area not included]
P5 1/TA0IN/RTP01,
P5 3/TA1IN/RTP03
[Shaded area included]
P5 5/TA2IN/RTP11/KI1,
P57 /TA3IN/RTP13/KI3
Pullup selection
Direction register
Data bus
Port latch
Latch
Timer
underflow signal
[Shaded area not included]
P5 0/TA0OUT/RTP00,
P5 2/TA1OUT/RTP02
[Shaded area included]
P5 4/TA2OUT/RTP10/KI0,
P5 6/TA3OUT/RTP12/KI2
Pullup
transistor
T
Q
CK
Pullup selection
Pullup
transistor
Direction register
1
Output (Internal peripheral devices)
Data bus
Port latch
Latch
Timer
underflow signal
T
Q
CK
Fig. 89 Block diagram for each port pin and pin NMI (1)
87
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[Inside dotted-line not included]
P70/AN0, P71/AN1,
P72/AN2, P73/AN3
[Inside dotted-line included]
P74/AN4/(INT3),
P75/AN5/(INT4)
Direction register
Data bus
Port latch
Analog input
P81/CTS0/CLK0,
P84/CTS1/RTS1/INT4,
P85/CTS1/CLK1
1
0
Direction register
Output (Internal peripheral devices)
Data bus
[Inside dotted-line not included]
P76/AN6/DA0
[Inside dotted-line included]
P7 7/AN7/ADTRG/DA1/(INT2)
Port latch
Direction register
Data bus
Port latch
Analog input
Analog output
Enable D-A output
1
P80/CTS0/RTS0/DA2/INT3
0
Direction register
Output (Internal peripheral devices)
Data bus
Port latch
Analog output
Enable D-A output
NMI
Pullup selection
Fig. 90 Block diagram for each port pin and pin NMI (2)
88
Pullup
transistor
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
While the power source voltage satisfies the recommended operating condition, reset state is removed if pin RESET’s level returns
from the stabilized “L” level to the “H” level. As a result, program execution starts from the reset vector address. This reset vector address is expressed as shown below:
• A23 to A16 = 0016
• A15 to A8 = Contents at address FFFF16
• A7 to A0 = Contents at address FFFE16
Figures 92 and 93 show the microcomputer internal register’s status
at reset, and Figure 94 shows an operation example of the reset circuit. Apply “L” level voltage to pin RESET for a period (2 µs or more)
under the following conditions:
• Pin Vcc’s level satisfies the recommended operating condition.
• Oscillator’s operation has been stabilized.
VCC level
VCC
0V
RESET
0.2VCC level
2 µs
0V
XIN
0V
Power on
Fig. 94 Operation example of reset circuit (Note that proper evaluation is necessary in the system development stage.)
Address
CS0 control register L
(8016)···
CS0 control register H
Oscillation stabilized
Address
1 0
D-A register 0
(9816)···
0016
(8116)··· 1
0 0 0 1
D-A register 1
(9916)···
0016
CS1 control register L
(8216)··· 0 1 0
0
D-A register 2
(9A16)···
0016
CS1 control register H
(8316)··· 0
0 0 0 0
Flash memory control register
(9E16)···
0 0 0 0 0 1
CS2 control register L
(8416)··· 0 1 0
0
Real-time output control register
(A016)···
0 0 0
CS2 control register H
(8516)··· 0
0 0 0 0
Serial I/O pin control register
(AC16)···
0 0 0 0
CS3 control register L
(8616)··· 0 1 0
0
Clock control register
(BC16)··· 0 0 0 0 0 1 1 1
CS3 control register H
(8716)···
0 0 0 0
Processor status register PS
0 0 0 ? ? 0 0 0 1 ? ?
Area CS0 start address register
(8A16)··· 0 0 0 1 0 0 0 0
Program bank register PG
Area CS1 start address register
(8C16)··· 0 0 0 0 0 0 0 0
Program counter PCH
Contents at address FFFF16
Area CS2 start address register
(8E16)··· 0 0 0 0 0 0 0 0
Program counter PCL
Contents at address FFFE16
Area CS3 start address register
(9016)··· 0 0 0 0 0 0 0 0
Direct page registers DPR0 to DPR3
Port function control register
(9216)··· 0 0 0 0 0 0 0 0
Data bank register DT
(Note 2)
1 0
0
0
0
(Note 3)
(Note 3)
(Note 3)
(Note 3)
1 0
1 0
1 0
External interrupt input control register (9416)··· 0 0 0 0 0 0 0 0
D-A control register
(9616)···
Stack pointer
0016
000016
0016
FFF16
0 0 0
Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software.
2: While Vss level voltage is applied to pin MD0, this bit is “0”. While Vcc level voltage is applied to pin MD0, on the other hand, this bit is “1”.
3: While Vss level voltage is applied to pin BYTE, these bits are “0”. While Vcc level voltage is applied to pin BYTE, on the other hand, these bits are “1”.
Fig. 93 Microcomputer internal register’s status at reset (2)
89
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address
Port P0 direction register
Address
(0416)···
0016
Timer B1 mode register
(5C16)··· 0 0 ?
0 0 0 0
(5D16)··· 0 0 ?
0 0 0 0
Port P1 direction register
(0516)···
0016
Timer B2 mode register
Port P2 direction register
(0816)···
0016
Processor mode register 0
(5E16)··· (Note 2) 0 0 0 1 0
Port P3 direction register
(0916)···
Processor mode register 1
(5F16)··· 0 0
Port P4 direction register
(0C16)···
0016
Watchdog timer
Port P5 direction register
(0D16)···
0016
Watchdog timer frequency select register
(6116)··· 0 0
Port P6 direction register
(1016)···
0016
Particular function select register 0
(6216)··· 0
Port P7 direction register
(1116)···
0016
Particular function select register 1
(6316)···
Port P8 direction register
(1416)···
0016
Debug control register 0
(6616)··· 1
Port P10 direction register
(1816)···
0016
Debug control register 1
(6716)··· 0 0 0
Port P10 direction register
(1916)···
0016
INT3 interrupt control register
(6E16)···
0 0 0 0 0
A-D control register 0
(1E16)··· 0 0 0 0 0 ? ? ?
INT4 interrupt control register
(6F16)···
0 0 0 0 0
A-D control register 1
(1F16)···
A-D conversion interrupt control register
(7016)···
? 0 0 0
UART 0 Transmit/Receive mode register
(3016)···
0016
UART 0 transmit interrupt control register
(7116)···
0 0 0 0
UART 1 Transmit/Receive mode register
(3816)···
0016
UART 0 receive interrupt control register
(7216)···
0 0 0 0
UART 0 Transmit/Receive control register 0
(3416)··· 0 0 0 0 1 0 0 0
UART 1 transmit interrupt control register
(7316)···
0 0 0 0
UART 1 Transmit/Receive control register 0
(3C16)··· 0 0 0 0 1 0 0 0
UART 1 receive interrupt control register
(7416)···
0 0 0 0
UART 0 Transmit/Receive control register 1
(3516)··· 0 0 0 0 0 0 1 0
Timer A0 interrupt control register (7516)···
0 0 0 0
UART 1 Transmit/Receive control register 1
(3D16)··· 0 0 0 0 0 0 1 0
Timer A1 interrupt control register (7616)···
0 0 0 0
Count start register
(4016)···
0016
Timer A2 interrupt control register (7716)···
0 0 0 0
One-shot start register
(4216)··· 0
0 0 0 0 0
Timer A3 interrupt control register (7816)···
0 0 0 0
Up-down register
(4416)···
0016
Timer A4 interrupt control register (7916)···
0 0 0 0
Timer A clock frequency select register
(4516)···
Timer B0 interrupt control register (7A16)···
0 0 0 0
Timer A0 mode register
(5616)···
0016
Timer B1 interrupt control register (7B16)···
0 0 0 0
Timer A1 mode register
(5716)···
0016
Timer B2 interrupt control register (7C16)···
0 0 0 0
Timer A2 mode register
(5816)···
0016
INT0 interrupt control register
(7D16)···
0 0 0 0 0 0
Timer A3 mode register
(5916)···
0016
INT1 interrupt control register
(7E16)···
0 0 0 0 0 0
Timer A4 mode register
(5A16)···
0016
INT2 interrupt control register
(7F16)···
0 0 0 0 0 0
Timer B0 mode register
(5B16)··· 0 0 ?
0 0 0 0
0 0 0 0 0 1 1
0 0
(Note 2)
(6016)···
(Note 2)
0
0 0
FFF16
0
0
0
0 0
0 0 0
(Note 3)
(Note 3)
(Note 3)
0 0 0
(Note 3)
0 0 0 0
Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software.
2: While Vss level voltage is applied to pin MD0, these bits are “0”. While Vcc level voltage is applied to pin MD0, on the other hand, these bits are “1”.
3: At power-on reset, these bits are clear to “0”. At hardware or software reset, on the other hand, these bits retain the value just before reset.
Fig. 92 Microcomputer internal register’s status at reset (1)
90
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OSCILLATION CIRCUIT
An oscillation circuit locates between pins XIN and XOUT, and Figure
95 shows a circuit example with a oscillator (an external ceramic
resonator or quartz crystal oscillator). The constants such as capacitance etc. depend on a oscillator. Therefore, for these constants,
adopt the oscillator manufacturer’s recommended values.
Figure 96 shows a circuit example with an external clock source.
When an external clock is input, be sure to leave pin XOUT open.
Also, in this case, when the external clock input select bit (bit 1 of the
particular function select register 0; See Figure 100.) is set to “1”, the
oscillation circuit stops it’s operation, and the current dissipation is
reduced. Moreover, this bit has another function, which selects the
return condition from the stop mode. For details, refer to the section
on the standby function.
On the other hand, the PLL (Phase Locked Loop) frequency multiplier (hereafter, referred as PLL circuit.) is included, also. This PLL
circuit uses an clock input from pin XIN and generates a multiplied
clock. When using the PLL circuit, be sure to connect pin VCONT with
an external filter circuit. (See Figure 97.) When not using the PLL circuit, be sure to leave pin VCONT open.
When not using the PLL circuit, be sure to clear the PLL circuit operation enable bit (bit 1 of the clock control register; See Figure 99.),
so that the PLL circuit will stop it’s operation.
M37902
XIN
XOUT
Rf
Rd
COUT
CIN
Fig. 95 Circuit example with external ceramic resonator or quartz crystal oscillator
M37902
XIN
XOUT
Left open.
External clock source
Vcc
Vss
Fig. 96 Circuit example with external clock source
M37902
VCONT
1 KΩ
220 pF
0.1 µF
Note: Make the wiring length as short as possible,
and shield it with the GND line which
surrounds this circuit. Also, for the clock
supply to pin XIN, see Figures 95 and 96.
Fig. 97 Circuit example with pin VCONT and PLL circuit
91
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Figure 98 shows the block diagram of the clock generating circuit.
The clock generating circuit consists of the clock oscillation circuit,
PLL frequency multiplier (PLL circuit), system clock switch circuit,
peripheral devices’ clock switch circuit, clock divider, standby control
circuit, etc. As control registers for the clock generating circuit, also,
the clock control register (address BC16), particular function select
register 0 (address 6216) are provided. (See Figures 99 and 100.)
As shown in Figure 98, clocks used in the CPU, BIU, peripheral devices, watchdog timer (in other words, clocks φCPU, φBIU, f1 to f4096,
Wf32, Wf512) are made from system clock fsys. System clock fsys can
be selected between fXIN (in other words, a clock input from pin XIN)
and fPLL (in other words, an output clock generated by the PLL circuit). By setting the clock φ1 output select bit (bit 7 of the processor
mode register 0) to “1”, also, system clock fsys can be output from
port pin P41, as clock φ1.
The PLL circuit’s operation, system clock (fsys) selection, and divide
ratio selection for peripheral devices’ clocks (f1 to f4096) are controlled by the clock control register. The following describes about
these control.
Bit 1 of the clock control register (the PLL circuit operation enable bit)
selects the PLL circuit’s operation (stopped/active). When this bit is
set to “1”, pin VCONT will becomes valid, and the PLL circuit will operate. At reset, the PLL circuit operation enable bit becomes “1”. (In this
case, the PLL circuit operates.) When not using the PLL circuit, be
sure to clear the PLL circuit operation enable bit to “0” (stopped). At
the STP instruction execution or while the flash memory parallel I/O
mode is set, the PLL circuit stops its operation, and pin VCONT is in-
valid, regardless of this bit 1’s status.
Bits 2 and 3 of the clock control register (the PLL multiplication ratio
select bits) select the ratio of fPLL/fXIN. The PLL multiplication ratio
must be set so that the frequency of the PLL output clock (fPLL) must
be in the range from 10 MHz to 26 MHz. At reset, the PLL multiplication ratio select bits become “0,1” (✕ 2). The change of the multiplication ratio must be performed while input clock fXIN is set as system
clock. (In this case, bit 5 of the clock control register = “0”.) After that,
be sure to wait that the operation-stabilizing time of the PLL circuit
has passed, and switch the system clock to the PLL output clock
(fPLL). (In other words, set bit 5 to “1”.) Note that, after reset, the PLL
multiplication ratio select bits are allowed to be changed only once.
Bit 5 of the clock control register is the system clock select bit, and
fXIN is selected as the system clock when bit 5 = “0”. On the other
hand, when bit 5 = “1”, the PLL output clock (fPLL) is selected. At reset, the system clock select bit becomes “0”. When selecting fPLL, be
sure that the PLL circuit’s operation has been stabilized properly, and
then, set the system clock select bit to “1”. Also, when the PLL circuit
operation enable bit is cleared to “0” (the PLL circuit is stopped.), the
system clock select bit will automatically be cleared to “0”. Note that
a value of “1” cannot be written to the system clock select bit while
the PLL circuit operation enable bit =“0”.
Table 15 lists the fsys selection.
Bits 6 and 7 of the clock control register are the peripheral devices’
clock select bits 0, 1, and these bits select the multiplication ratio of
(f1 to f4096)/(fsys).
Table 16 lists the internal peripheral devices’ operation clock frequency. At reset, these bits become “0, 0”.
Table 15. fsys selection
System clock select bit PLL circuit operation enable bit PLL multiplication ratio select bits
(Bit 5)
(Bits 3, 2) (Note)
(Bit 1)
0
01 (✕ 2)
1
1
10 (✕ 3)
11 (✕ 4)
System clock fsys
Clock source
fXIN
fPLL
fPLL
fPLL
Frequency (Note)
f(XIN)
f(XIN) ✕ 2
f(XIN) ✕ 3
f(XIN) ✕ 4
Note: The PLL multiplication ratio must be set so that the frequency of the PLL output clock (fPLL) must be in the range from 10 MHz to 26 MHz.
f(XIN) means the frequency of the input clock from pin XIN (fXIN). After reset, the PLL multiplication ratio select bits are allowed to be
changed only once.
Table 16. Internal peripheral devices’ operation clock frequency
Internal peripheral devices’
operation clock
f1
f2
f16
f64
f512
f4096
Peripheral devices’ clock select bits 1, 0 (bits 7, 6)
00
fsys
fsys/2
fsys/16
fsys/64
fsys/512
fsys/4096
0 1 (Note)
fsys
fsys
fsys/8
fsys/32
fsys/256
fsys/2048
10
11
fsys/2
fsys/4
fsys/32
fsys/128
fsys/1024
fsys/8192
Do not select.
Note: When selecting the peripheral devices’ clock select bits 1, 0 = “012”, be sure that system clock fsys does not exceed 13 MHz.
92
R
S
Q
WIT
instruction
Interrupt
request
R
S
Q
External clock
input select bit
STP
instruction
Interrupt
request
Wait mode
XIN
XOUT
fXIN
f/n
STP
instruction
R
S
Q
0
1
1
0
System clock
frequency select bit
Wait mode
fsys
1/2
1/2
BIU : Bus interface Unit
CPU : Central Processing Unit
❈
: Signal generated when the watchdog timer’s most significant bit becomes “0”.
: bit 0 at address 6116
: bits 6, 7 at address 6116
: bit 1 at address 6216
: bit 3 at address 6316
: bit 1 at address BC16
: bits 2, 3 at address BC16
: bit 5 at address BC16
: bits 6, 7 at address BC16
CPU wait request
1
0
Peripheral
device’s clock
select bit 0
Access to Wait mode
external area
HLDA
1
0
Peripheral
device’s clock
select bit 1
• Watchdog timer frequency select bit
• Watchdog timer clock source select bit at stop state termination
• External clock input select bit
• System clock stop select bit at WIT
• PLL circuit operation enable bit
• PLL multiplication ratio select bits
• System clock select bit
• Peripheral device’s clock select bit 0, 1
Reset
VCONT
fX16
fX32
fX64
fX128
fPLL
PLL circuit operation enable bit
PLL frequency
multiplier
PLL multiplication ratio select bits
System clock stop select bi at WIT
Wait mode
φ1
f4096
1/16
0
1
Wf512
Wf32
Watchdog timer
frequency select bit
1/8
fX16
fX32
fX64
fX128
External clock input select bit
(Clock for CPU)
φ CPU
(Clock for BIU)
φ BIU
1/8
Watchdog timer clock source select
bit at stop state termination
1/16
1/4
System clock frequency select bit
1/8
f1
f2
f16
f64
f512
0
1
❈
Watchdog
timer
Interrupt
request
Operating clock for timer A
Operating clock for
serial I/O, timer B
A-D conversion frequency
(φAD) clock source
Peripheral device’s clocks
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 98 Block diagram of clock generating circuit
93
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
5
4
3
2
1
0
0
1
Clock control register
Address
BC16
At reset
0716
Fix this bit to “1”.
PLL circuit operation enable bit (Note 1)
0: PLL frequency multiplier is stopped, and pin VCONT is invalid (floating state).
1: PLL frequency multiplier is operating, and pin VCONT is valid.
PLL multiplication ratio select bits (Note 2)
00: Do not select.
01: Double
10: Triple
11: Quadruple
Fix this bit to “0”.
System clock select bit (Note 3)
0: fXIN
1: fPLL
Peripheral device’s clock select bits 1, 0
See Table 16.
Notes 1: When not using the PLL frequency multiplier, clear this bit to “0”. In the stop mode or in
the flash memory parallel I/O mode, the PLL circuit stops it’s operation regardless of this
bit’s contents; at this time, pin VCONT is invalid.
2: When rewriting this bit, be sure to clear bit 5 to “0” simultaneously. Also, after this bit is
rewritten, insert a waiting time of 2 ms, and then set bit 5 to “1”.
3: When the PLL circuit operation enable bit (bit 1) has been cleared to “0”, this bit will also
be cleared to “0”. Also, bit 1 = “0”, nothing can be written to this bit. (Fixed to be “0”.)
Fig. 99 Bit configuration of clock control register
7
0
6
5
4
0
0
3
2
1
0
Particular function select register 0
Address
6216
STP instruction invalidity select bit (Note)
0: STP instruction is valid.
1: STP instruction is invalid.
External clock input select bit (Note)
0: Oscillation circuit is active. (Oscillator is connected.)
Watchdog timer is used at stop mode termination.
1: Oscillation circuit is inactive. (External clock is input.)
When the system clock select bit = “0”,
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1”,
watchdog timer is used at stop mode termination.
Fix this bit to “0”.
Note: Writing to these bits requires the following procedure:
• Write “5516” to this register. (The bit status does not change only by this writing.)
• Succeedingly, write “0” or “1” to each bit.
Also, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction
Fig. 100 Bit configuration of particular function select register 0
94
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STANDBY FUNCTION
STP mode
The standby function provides the stop (hereafter called STP) and
the wait (hereafter called WIT) mode. These modes are used to save
the power dissipation of the system, by stopping oscillation or system clock in the case that the CPU needs not be operating.
The microcomputer enters the STP or WIT mode by executing the
STP or WIT instruction, and either mode is terminated by acceptance
of an interrupt request or reset.
To terminate the STP or WIT mode by an interrupt request, the interrupt to be used for termination of the STP or WIT mode must be enabled in advance to execution of the STP or WIT instruction. The
interrupt priority level of this interrupt is required to be higher than the
processor interrupt priority level (IPL) of the routine where the STP
or WIT instruction will be executed.
Figures 100 to 102 show the bit configurations of the particular function select registers 0, 1, and watchdog timer frequency select register respectively. Setting the STP instruction invalidity select bit (bit 0
of the particular function select register 0) to “1” invalidates the STP
instruction, and the STP instruction will be ignored. Since the above
bit is cleared to “0” after reset is removed, however, the STP instruction is valid.
The STP- or the WIT-instruction-execution status bit (bit 0 or 1 of the
particular function select register 1) is set to “1” by the execution of
the STP or the WIT instruction, and so, after the STP or WIT mode
has been terminated, each bit will indicate that the STP or WIT instruction has been executed. Accordingly, each of these bits must be
cleared to “0” by software at termination of the STP or the WIT mode.
Table 17 explains the microcomputer’s operation in the STP and WIT
modes.
The external bus fixation function can also be provided. This function
enables the user to specify the states of the external bus and the bus
control signals in the memory expansion and the microprocessor
mode in the STP or WIT mode. For more information, refer to the
section on the power saving function.
The execution of the STP instruction stops the oscillation circuit and
PLL circuit. It also stops input clock fXIN, system clock fsys, φBIU,
φCPU, and peripheral devices’ clocks f1 to f4096, Wf32 and Wf512 in
the “L” state, and divide clocks fX16 to fX128 in the “H” state. In the
watchdog timer, “FFF16” is automatically set. As shown in Figure 98,
any one of divide clocks fX16 to fX128, which is selected by the
watchdog timer clock source select bits at STP termination (bits 6
and 7 of the watchdog timer frequency select register), becomes the
watchdog timer’s clock source.
In the STP mode, the A-D converter and watchdog timer, which uses
peripheral devices’ clocks f1 to f4096, Wf32 and Wf512, are stopped.
At this time, timers A and B operate only in the event counter mode,
and serial I/O communication is active while an external clock is selected.
The STP mode is terminated by acceptance of an interrupt request
or reset, and the oscillation circuit and PLL circuit restart their operations. Input clock fXIN, system clock fsys, and peripheral devices’
clocks f1 to f4096, Wf32 and Wf512 are also supplied.
When the STP mode is terminated by reset, supply of φBIU and φCPU
starts immediately after the oscillation circuit and PLL circuit restart
their operations. Therefore, the reset input must be raised “H” after
the operation-stabilizing time for these circuits has passed.
The following two modes are available in order to terminate the STP
mode by an interrupt:
(1) The watchdog timer is used in order to measure the period from
the operation restart of the oscillation circuit and PLL circuit until
the supply start of φBIU and φCPU.
(2) The supply of φBIU and φCPU is started immediately after the operation restart of the oscillation circuit and PLL circuit.
When the external clock input select bit (bit 1 of the particular function select register 0) = “0” or the system clock select bit (bit 5 of the
clock control register) = “1”, the watchdog timer will start counting
Table 17. Microcomputer’s operation in STP and WIT modes
Mode
STP
System clock
stop select bit
at WIT
Oscillation
PLL circuit
circuit
Operations of function while WIT, STP modes
fsys, φ1,
Wf32, Wf512 φBIU, φCPU Peripheral devices using f1 to f4096, Wf32, Wf512
f1 to f4096
—
Stopped
Stopped
Stopped
(“L”)
Stopped
(“L”)
Stopped
(“L”)
“0”
Active
(Note 1)
Active
(Note 2)
Active
Stopped
(“L”)
Stopped
(“L”)
WIT
“1”
Active
(Note 1)
Active
(Note 2)
Stopped
(“L”)
Stopped
(“L”)
Stopped
(“L”)
Timers A, B: Operation is enabled only in the event
counter mode.
Serial I/O: Operation is enabled only while an external
clock is selected.
A-D converter: Stopped.
(Watchdog timer: Stopped.)
Timers A, B, Serial I/O, A-D converter: Operation is enabled.
(Watchdog timer: Stopped.)
Timers A, B: Operation is enabled only in the event
counter mode.
Serial I/O: Operation is enabled only while an external
clock is selected.
A-D converter: Stopped.
(Watchdog timer: Stopped.)
Notes 1: When the external clock input select bit = “1”, the oscillation circuit stops. Also, clock input from pin XIN is available.
2: When the PLL operation enable bit = “0”, the PLL circuit stops.
95
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
down with one of the above divide clocks, fX16 to fX128, after the oscillation circuit and PLL circuit have been restarted their operations
owing to an interrupt. The most significant bit of the watchdog timer
reaching “0”, supply of φBIU and φCPU restarts.
On the other hand, when the external clock input select bit = “1 ” and
the system clock select bit = “0”, supply of φBIU and φCPU will restart
immediately after the oscillation circuit has been restarted their operations owing to an interrupt. (In actual fact, after the selected one
of the above divide clocks, fX16 to fX128, has been changed from “H”
to “L”, this supply will restart.)
7
6
5
4
3
2
1
0
Particular function select register 1
Address
6316
STP-instruction-execution status bit (Note 1)
0: Normal operation.
1: STP instruction has been executed.
WIT-instruction-execution status bit (Note 1)
0: Normal operation.
1: WIT instruction has been executed.
Standby state select bit
0: External bus
1: Programmable I/O port
System clock stop select bit at WIT (Note 2)
0: In wait mode, system clock fsys is active.
1: In wait mode, system clock fsys is stopped.
Address output select bit
0: Address changes depending on bus access.
1: Address changes only at access to external address.
Timer B2 clock source select bit
In event counter mode:
0: Clock input from pin TB2IN is counted.
1: fX32 (f(XIN)/32) is counted.
Notes 1: At power-on reset, this bit becomes “0”. At hardware reset or software reset, this bit
retains the value just before reset. Even when “1” is written, the bit status will not change.
2: Setting this bit to “1” must be performed just before execution of the WIT instruction.
Also, after the wait state is terminated, this bit must be cleared to “0” immediately.
Fig. 101 Bit configuration of particular function select register 1
7
6
5
4
3
2
1
0
Watchdog timer frequency select register
Address
6116
Watchdog timer frequency select bit
0 : Select W f512
1 : Select W f32
Watchdog timer clock source select bits at STP termination
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
Fig. 102 Bit configuration of watchdog timer frequency select register
96
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WIT mode
When the WIT instruction is executed with the system clock stop select bit at WIT (bit 3 of the particular function select register 1 in Figure 101) being “0”, φBIU, φCPU, and divide clocks Wf32 and Wf512 are
stopped in the “L“ state. However, the oscillation circuit, PLL circuit,
input clock fXIN, system clock fsys, φ1, and peripheral devices’ clock
f1 to f4096 remain operating. Therefore, BIU and CPU are stopped,
whereas timers A and B, serial I/O, and the A-D converter, which use
the peripheral devices’ clocks f1 to f4096, are still operating. Note that
the watchdog timer is stopped.
On the other hand, when the WIT instruction is executed with the
system clock stop select bit at WIT being “1”, the oscillation circuit,
PLL circuit, and input clock fXIN are operating, while system clock
fsys, φBIU, φCPU, and peripheral devices’ clocks stop operating. As a
result, the A-D converter and watchdog timer, which use peripheral
devices’ clocks f1 to f4096, Wf32 and Wf512, are stopped. At this time,
timers A and B operate only in the event counter mode, and serial
I/O communication is active only while an external clock is selected.
If the internal peripheral devices are not used in the WIT mode, the
latter is better because the current dissipation is more saved. Note
that the system clock stop select bit at WIT is to be set to “1” immediately before execution of the WIT instruction and cleared to “0” immediately after the WIT mode is terminated.
The WIT state is terminated by acceptance of an interrupt request,
and then, supply of φBIU and φCPU will restart. Since the oscillation
circuit, PLL circuit, and clock input fXIN are operating in the WIT
mode, an interrupt processing can be executed just after the WIT
mode termination.
97
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
POWER SAVING FUNCTION
The following functions can save the power dissipation of the whole
system.
mode, owing to an interrupt request occurrence. Therefore, an instruction can be executed just after the termination of the stop mode.
For details, refer to the section on the clock generating circuit and
standby function.
(1) External bus fixation in standby state
By setting the standby state select bit (bit 2 of the particular function
select register 1) to “1”, in the stop or wait mode, the I/O pins of the
external buses and bus control signals can be switched to programmable I/O port pins. By setting these pins’ state with the corresponding port registers and port direction registers, unnecessary current
will not flow between the microcomputer and external devices. As a
result, in the stop or wait mode, the power dissipation of the whole
system can be lowered. Table 18 lists the correspondence between
the external buses, bus control signals, and programmable I/O port
pins.
This function is valid only in the stop or wait mode. At termination of
the stop or wait mode, the original function of external buses and bus
control signals become valid.
Table 18. Correspondence between external buses, bus control signals, and programmable I/O port pins
Standby state select bit
External buses,
Bus control signals
0
1
A0 to A7,
A8 to A15,
A16 to A23
A0 to A7,
A8 to A15,
A16 to A23
P100 to P107,
P110 to P117,
P00 to P07
D0 to D7,
D8 to D15
D0 to D7,
D8 to D15 (Note)
P10 to P17,
P20 to P27
RD, BLW,
BHW
RD, BLW,
BHW (Note)
P31, P32, P33
CS0
CS0
P90
Note: When the external data bus width = 8 bits (BYTE = VCC level),
this becomes a programmable I/O port pin, regardless of the
standby state select bit’s contents.
(2) Stop of system clock in wait mode
In the wait mode, if the internal peripheral devices need not to operate, the system clock stop select bit at WIT (bit 3 of the particular
function select register 1) = “1”, both of system clock fsys and peripheral devices’ clock stop their operations, and the power dissipation
can be saved.
For details, refer to the section on the standby function.
(3) Stop of oscillation circuit
When an externally-generated-stable clock is input to pin XIN, the
power dissipation can be saved if both of the following conditions are
met:
• the external clock input select bit (bit 1 of the particular function
select register 0) = “1”.
• the oscillation driver between pins XIN and XOUT stops its operation.
At this time, the output level at pin XOUT is fixed to “H”. When not using a PLL output clock, also, the supply of φBIU and φCPU restarts
their operations just after the microcomputers returns from the stop
98
(4) Disconnection from pin VREF
When not using the A-D converter and D-A converter, by setting the
VREF connection select bit (bit 6 of the A-D control register 1) to “1”,
the resistor ladder network of the A-D converter will be disconnected
from the reference voltage input pin (VREF). In this case, no current
flows from pin VREF to the resistor ladder network, and the power dissipation can be saved. Note that, after the VREF connection select bit
changes from “1” (VREF disconnected) to “0” (VREF connected), be
sure that a waiting time of 1 µs of more has passed before the A-D
conversion starts. For details, refer to the sections on the A-D converter and D-A converter.
(5) Address output selection
In the memory expansion mode or microprocessor mode, when the
address output select bit (bit 4 of the particular function select register 1) becomes “1”, the unnecessary change of address pins’ state
will be avoided, without output of an address at access to the internal area.
For details, refer to the section on the BIU.
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DEBUG FUNCTION
When the CPU fetches an instruction code, an interrupt request will
be generated if a selected condition is satisfied, as a resultant of
comparison between a specified address and the start address
where the instruction code is stored (the contents of PG and PC).
The decision whether this condition is satisfied or not is called address matching detection, and the interrupt generated by this detection is called an address matching detection interrupt. (For interrupt
vector addresses, refer to the section on interrupts.)
In the address matching detection, a non-maskable interrupt routine
is proceeded without execution of the original instruction which has
been allocated to the target address.
The debug function provides the following two modes:
• the address matching detection mode, which is used to avoid the
area where program exists or modify a program.
• the out-of-address-area detection mode, which is used to detect a
program runaway.
Figures 103 shows the block diagram of the debug function. Figures
104 and 105 show the bit configurations of the debug control registers 0, 1, and address compare registers 0,1, respectively.
The detect condition select bits of the debug control register 0 can
select one condition between the following 4 conditions. When the
selected address condition is satisfied, an address matching detection interrupt request will be generated:
(1) Address matching detection 0
The contents of PG and PC match with the address which has
been set in the address compare register 0.
(2) Address matching detection 1
The contents of PG and PC match with the address which has
been set in the address compare register 1.
(3) Address matching detection 2
The contents of PG and PC match with the address which has
been set in either of the address compare register 0 or address
compare register 1.
(4) Out-of-address-area detection
The contents of PG and PC are less than the address which has
been set in the address compare register 0 or larger than the address which has been set in the address compare register 1.
By setting the detect enable bit of the debug control register 0 to “1”,
an address matching detection interrupt request will be generated if
any one of the above address conditions is satisfied. Clearing the
detect enable bit to “0” generates no interrupt request even if any of
the above address conditions is satisfied.
The address compare register access enable bit of the debug control register 1 must be set to “1” by the instruction just before the access operation (read/write). Then, this bit must be cleared to “0”
(disabled) by the next instruction. While this bit = “0”, the address
compare registers 0, 1 cannot be accessed.
The address-matching-detection 2 decision bit of the debug control
register 1 decides, whether the address which has been set in the
address compare register 0 or 1 matches with the contents of PG,
PC, when the address matching detection 2 is selected. The contents of this bit is invalid when address matching detection 0 or 1 is
selected.
In order to use the debug function to avoid the area where program
exists or modify a program, perform the necessary processing within
an address matching interrupt routine. As a result, the contents of
PG, PC, PS at acceptance of an address matching detection interrupt request (i.e. the address at which an address matching detection condition is satisfied) have been pushed on to the stack. If a
return destination address after the interrupt processing is to be altered, rewrite the contents of the stack, and then return by the RTI
instruction.
To use the debug function to detect a program runaway, set an address area where no program exists into the address compare registers 0 and 1 by using the out-of-address-area detection. When the
CPU fetches instruction codes from this address area and executes
them, an address matching detection interrupt request will be generated.
The above debug function cannot be evaluated by a debugger, so
that the debug function must not be used while a debugger is running.
Internal data bus (DB0 to DB15)
Debug control register 0
Address compare register 0
Address compare register 1
Debug control register 1
Matching • Compare register
Matching • Compare register
Address matching
detect circuit
Address matching
detection interrupt
CPU bus (Address)
Fig 103. Block diagram of debug function
99
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
7
6
1
0
5
4
3
0
0
2
1
0
Debug control register 0
Address
6616
Detect condition select bits (Note 1)
000: Do not select.
001: Address matching detection 0
010: Address matching detection 1
011: Address matching detection 2
100: Do not select.
101: Out-of-address-area detection
110: Do not select.
111: Do not select
Fix this bit to “0” (Note 1).
Detect enable bit (Note 1)
0: Detection disabled.
1: Detection enabled.
Fix this bit to “0” (Note 1).
“1” at read.
7
0
6
5
4
3
0
1
2
1
0
Debug control register 1
0
Address
6716
Fix this bit to “0” (Note 1).
“0” at read (Note 1).
Address compare register access enable bit (Note 2)
0: Disabled
1: Enabled
Fix this bit to “1” when using the debug function.
Fix this bit to “0” (Note 1).
While debugger is not used, “0” at read.
While debugger is used, “1” at read.
Address-matching-detection 2 decision bit
❈ Valid when address matching detection 2 is selected.
0: Matches with the contents of the address compare register 0.
1: Matches with the contents of the address compare register 1.
“0” at read.
Notes 1: At power-on reset, these bits = “0”; at hardware reset or software reset, these bits retain
the value just before reset.
2: Set this bit to “1” with the instruction just before the address compare register 0, 1
(addresses 6816 to 6D16) is accessed. And then, clear this bit to “0” with the instruction
just after the access.
Fig. 104 Bit configuration of debug control register 0, 1
(23)
7
(16) (15)
0 7
(8)
0 7
0
Address compare register 0
Address compare register 1
Address
6816, 6916, 6A16
6B16, 6C16, 6D16
The address to be detected (in other words, the start address of instruction) is set here.
Fig. 105 Bit configuration of address compare register 0, 1
100
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLASH MEMORY MODE
These microcomputers contain the DINOR (DIvided bit line NOR)type flash memory; and single-power-supply reprogramming is available to this. These microcomputers have the following three modes,
enabling reading/programming/erasure for the flash memory:
• Flash memory parallel I/O mode and Flash memory serial I/O
mode, where the flash memory is handled by using an external programmer.
• CPU reprogramming mode, where the flash memory is handled by
the central processing unit (CPU).
As shown in Figures 106 to 108, the flash memory is divided into
several blocks, and erasure per block is possible.
Each of these blocks is provided with a lock bit, which determines the
validity of erasure/program execution. Therefore, data protection per
block is possible.
This internal flash memory has the boot ROM area storing the reprogramming control software for reprogramming in the CPU reprogramming mode and flash memory serial I/O mode, as well as the
user ROM area storing a certain control software for the normal operation in the microcomputer mode.
Although our reprogramming control firmware for the flash memory
serial I/O mode has been stored into this boot ROM area on shipment, the user-original reprogramming control software which is
more appropriate for the user’s system is reprogrammable into this
area, instead. Note that the reprogramming for the boot ROM area is
enabled only in the flash memory parallel I/O mode.
User ROM area
Byte Address
Word Address
00380016
003FFF16
00400016
005FFF16
00600016
007FFF16
00800016
001C0016
001FFF16
00200016
002FFF16
00300016
003FFF16
00400016
00000016
003FFF16
001FFF16
8 Kbytes
007FFF16
00800016
00FFFF16
01000016
64 Kbytes
02FFFF16
03000016
00000016
16 Kbytes
8 Kbytes
64 Kbytes
01FFFF16
02000016
Word Addresses
2 Kbytes
32 Kbytes
00FFFF16
01000016
Boot ROM area
Byte Addresses
017FFF16
01800016
Notes 1: In the flash memory mode, the read/programming/erase
operation cannot be performed for areas except for the
internal flash memory area.
2: The boot ROM area can be reprogrammed only in the
flash memory parallel I/O mode. When the boot ROM
area is read out by the CPU, these addresses are shifted
to addresses 00C00016–00FFFF16 (byte addresses).
3: The reserved area for the serial programmer is assigned
to addresses FFB016–FFBF16 (byte addresses). When
the flash memory serial I/O mode is used, do not
program to this area.
64 Kbytes
03FFFF16
04000016
01FFFF16
02000016
64 Kbytes
04FFFF16
05000016
027FFF16
02800016
64 Kbytes
05FFFF16
06000016
02FFFF16
03000016
64 Kbytes
06FFFF16
07000016
037FFF16
03800016
64 Kbytes
07FFFF16
03FFFF16
Total 498 Kbytes
Fig 106. M37902FJCHP: block configuration of internal flash memory
101
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User ROM area
Boot ROM area
Byte Address
Word Address
Byte Addresses
00200016
00100016
00000016
00000016
003FFF16
00400016
005FFF16
00600016
007FFF16
00800016
001FFF16
00200016
002FFF16
00300016
003FFF16
00400016
003FFF16
001FFF16
8 Kbytes
8 Kbytes
007FFF16
00800016
64 Kbytes
01FFFF16
16 Kbytes
8 Kbytes
32 Kbytes
00FFFF16
01000016
Word Addresses
00FFFF16
Total 120 Kbytes
Notes 1: In the flash memory mode, the read/programming/erase
operation cannot be performed for areas except for the
internal flash memory area.
2: The boot ROM area can be reprogrammed only in the
flash memory parallel I/O mode. When the boot ROM
area is read out by the CPU, these addresses are shifted
to addresses 00C00016–00FFFF16 (byte addresses).
3: The reserved area for the serial programmer is assigned
to addresses FFB016–FFBF16 (byte addresses). When
the flash memory serial I/O mode is used, do not
program to this area.
Fig 107. M37902FCCHP: block configuration of internal flash memory
User ROM area
Boot ROM area
Byte Address
Word Address
Byte Addresses
00200016
00100016
00000016
003FFF16
00400016
005FFF16
00600016
007FFF16
00800016
001FFF16
00200016
002FFF16
00300016
003FFF16
00400016
8 Kbytes
003FFF16
007FFF16
00800016
00FFFF16
01000016
Notes 1: In the flash memory mode, the read/programming/erase
operation cannot be performed for areas except for the
internal flash memory area.
2: The boot ROM area can be reprogrammed only in the
flash memory parallel I/O mode. When the boot ROM
area is read out by the CPU, these addresses are shifted
to addresses 00C00016–00FFFF16 (byte addresses).
3: The reserved area for the serial programmer is assigned
to addresses FFB016–FFBF16 (byte addresses). When
the flash memory serial I/O mode is used, do not
program to this area.
64 Kbytes
02FFFF16
03000016
017FFF16
01800016
64 Kbytes
03FFFF16
01FFFF16
Total 248 Kbytes
Fig 108. M37902FGCHP: block configuration of internal flash memory
102
001FFF16
8 Kbytes
64 Kbytes
01FFFF16
02000016
00000016
16 Kbytes
8 Kbytes
32 Kbytes
00FFFF16
01000016
Word Addresses
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory Parallel I/O Mode
User ROM Area and Boot ROM Area
The flash memory parallel I/O mode is used to manipulate the internal flash memory with a parallel programmer. This parallel programmer uses the software commands listed in Table 19 to do the flash
memory manipulations, such as read/programming/erase operations.
In the flash memory parallel I/O mode, each block can be protected
from erasing/programming (in other words, block lock).
The user ROM area and boot ROM area can be reprogrammed in
the flash memory parallel I/O mode.
The programming and block erase operations can be performed only
to these areas.
The boot ROM area, 16 Kbytes in size, is assigned to addresses
000016–3FFF16 (byte addresses), so that programming and block
erase operations can be performed only to this area. (Access to any
address out of this area is prohibited).
The erasable block in the boot ROM area is only one block, consisting of 16 Kbytes. The reprogramming control firmware to be used in
the flash memory serial I/O mode has been stored to this boot ROM
area on our shipment. Therefore, do not reprogram the boot ROM
area if the user uses the flash memory serial I/O mode.
Addresses FFB016 to FFBF16 are the reserved area for the serial
programmer. Therefore, when the user uses the flash memory serial
I/O mode, do not program to this area.
Note that, when the boot ROM area is read out from the CPU in the
CPU reprogramming mode, described later, its addresses will be
shifted to C00016—FFFF16 (byte addresses).
Table 19. Software commands (flash memory parallel I/O mode)
Software Command
Read Array
Read Status Register
Clear Status Register
Page Programming (Note)
Block Erase
Erase All Unclocked Block
Lock Bit Programming
Read Lock Bit Status
Note: Programming is performed in a unit of 256 bytes, with the low-order
address assigned in the range of 0016—FF16 (byte addresses).
103
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Flash Memory Serial I/O Mode
In the flash memory serial I/O mode, addresses, data, and software
commands, which are required to read/program/erase the internal
flash memory, are serially input and output with a fewer pins and the
dedicated serial programmer.
In this mode, being different from the flash memory parallel I/O
mode, the CPU controls reprogramming of the flash memory (using
the CPU reprogramming mode), serial input of the reprogramming
data, etc.
The reprogramming control firmware for the flash memory serial I/O
mode has been stored in the boot ROM area on shipment of the
product from us. Note that, then, the flash memory serial I/O mode
will become unavailable if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode.
Note that, also, this reprogramming control firmware for the flash
memory serial I/O mode is subject to change.
Figure 112 shows the pin connection in the flash memory serial I/O
mode.
The three pins, SCLK, SDA, and BUSY, are used to input and output
serial data.
The SCLK pin is the input pin of external transfer clocks. The SDA
pin is the I/O pin of transmit and receive data, and its output acts as
the N-channel open-drain output. To the SDA pin, connect an external pullup resistor (about 1 kΩ). The BUSY pin is the output pin of the
BUSY flag (CMOS output) and goes “H” during BUSY periods owing
to a certain operation, such as transmit, receive, erase, programming, etc.
Transmit and receive data are serially transferred 8 bits at a time.
In the flash memory serial I/O mode, only the user ROM area can be
reprogrammed; the boot ROM area is not accessible.
Addresses FFB016 to FFBF16 are the reserved area for the serial
programmer. Therefore, when the user uses the flash memory serial
I/O mode, do not program to this area.
104
BUSY
SDA
SCLK
P70/AN0
P67/TB2IN
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN/RTP13/KI3
P56/TA3OUT/RTP12/KI2
P55/TA2IN/RTP11/KI1
P54/TA2OUT/RTP10/KI0
P53/TA1IN/RTP03
P52/TA1OUT/RTP02
P51/TA0IN/RTP01
P50/TA0OUT/RTP00
P47/CS3
P46/CS2
P45/CS1
P44/CS0
P43/HOLD
P42/HLDA
P41/φ1
P40/ALE
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
AVSS
VSS
NMI
P80/CTS0/RTS0/DA2/INT3
P77/AN7/ADTRG/DA1/(INT2)
P76/AN6/DA0
P75/AN5/(INT4)
P74/AN4/(INT3)
P73/AN3
P72/AN2
P71/AN1
2
1
VCC
P103/A3
P102/A2
P101/A1
P100/A0
P87/TXD1
P86/RXD1
P85/CTS1/CLK1
P84/CTS1/RTS1/INT4
P83/TXD0
P82/RXD0
P81/CTS0/CLK0
VCC
AVCC
VREF
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
M37902FCCHP
M37902FGCHP
M37902FJCHP
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
P104/A4
P105/A5
P106/A6
P107/A7
P110/A8
P111/A9
P112/A10
P113/A11
P114/A12
P115/A13
P116/A14
P117/A15
P00/A16
P01/A17
P02/A18
P03/A19
P04/A20
P05/A21
P06/A22
P07/A23
VSS
MD1
P10/D0/LA0
P11/D1/LA1
P12/D2/LA2
MD1
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P13/D3/LA3
P14/D4/LA4
P15/D5/LA5
P16/D6/LA6
P17/D7/LA7
P20/D8
P21/D9
P22/D10
P23/D11
P24/D12
P25/D13
P26/D14
P27/D15
VCC
XOUT
XIN
VSS
MD0
RESET
VCONT
BYTE
P30/RDY
P31/RD
P32/BLW
P33/BHW
✼
RESET
VSS
✼: Connect to the ceramic oscillation circuit.
Output 100P6Q-A
Fig.112 Pin connection of M37902FxCHP in flash memory serial I/O mode
105
MITSUBISHI MICROCOMPUTERS
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CPU Reprogramming Mode
The CPU reprogramming mode is used to perform the operations for
the internal flash memory (reading, programming, erasing) under
control of the CPU.
In this mode, only the user ROM area can be reprogrammed; the
boot ROM area cannot be reprogrammed.
The user-original reprogramming control software for the CPU reprogramming mode can be stored in either the user ROM area or the
boot ROM area. Because the CPU cannot read out the flash memory
in the CPU reprogramming mode, the above software must be transferred to the internal RAM in advance to be executed.
Boot Mode
The user-original reprogramming control software for the CPU reprogramming mode must be stored into the user ROM area or the
boot ROM area in the flash memory parallel I/O mode in advance. (If
this program has been stored into the boot ROM area, the flash
memory serial I/O mode will become unavailable).
Note that addresses of the boot ROM area depend on the accessing
ways to the boot ROM area, When accessing in the flash memory
7
6
5
4
3
2
1
parallel I/O mode, these addresses will be shifted to 0000 16 to
3FFF16 (byte address). On the other hand, when accessing with the
CPU, these addresses will be shifted to C00016 to FFFF16 (byte
address).
Reset removal with both of the MD0 and MD1 pins held “L” invokes
the normal microcomputer mode, and the CPU operates using the
control software stored in the user ROM area. In this case, the boot
ROM area is not accessible.
Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the
CPU starts its operation using the reprogramming control software
stored in the boot ROM area. This mode is called the boot mode. The
reprogramming control software in the boot ROM area can also reprogram the user ROM area.
After reset removal, be sure not to change the status at pins MD0
and MD1.
0
0
Flash memory control register
Address
9E16
RY/BY status bit
0: Busy (Programming or erasing is active.)
1: Ready
CPU reprogramming mode select bit (Note 2)
0: Normal mode (Software commands are ignored.)
1: CPU reprogramming mode (Software commands are acceptable.)
Lock bit invalidity select bit (Note 3)
0: Block lock by lock bit data is valid.
1: Block lock by lock bit data is invalid.
Flash memory reset bit (Note 4)
0: Normal operation
1: Reset
Must be “0”.
User ROM area select bit (Note 5)
(Valid only in the boot mode.)
0: Boot ROM area access
1: User ROM area access
Notes 1: The contents of the flash memory control register after reset is removed are “XX0000012”.
2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1
must be performed by the user-original reprogramming control software in the internal RAM.
3: To set “1”, writing of “0” to bit 2 and subsequent writing of “1” to bit 2 are necessary while bit 1 = “1”.
4: Valid only when bit 1 = “1”. Set bit 3 to “1” (reset), and then clear to “0”. This bit 3 must be controlled
with bit 1 = “1”.
5: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal
RAM.
Fig. 114 Bit configuration of flash memory control register
106
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Function overview (CPU reprogramming mode)
The CPU reprogramming mode is available in the single-chip mode,
memory expansion mode, and boot mode to reprogram the user
ROM area only.
In the CPU reprogramming mode, the CPU erases, programs, and
reads the internal flash memory by writing software commands. Note
that the user-original reprogramming control software must be transferred to the internal RAM in advance to be executed.
The CPU reprogramming mode becomes active when “1” is written
into the flash memory control register’s bit 1 (the CPU reprogramming mode select bit) shown in Figure 114, and software commands
become acceptable.
In the CPU reprogramming mode, software commands and data are
all written to and read from even addresses (Note that address A0 in
byte addresses = “0”.) 16 bits at a time. Therefore, a software command consisting of 8 bits must be written to an even address; therefore, any command written to an odd address will be invalid. Since
the write data at the 2nd cycle of a programming command consists
of 16 bits, this data must be written to even and odd addresses.
The write state machine (WSM) in the flash memory controls the
erase and programming operations. What the status of the WSM
operation is and whether the programming or erase operation has
been completed normally or terminated by an error can be examined
by reading the status register.
Figure 114 shows the bit configuration of the flash memory control
register.
Bit 0 (the RY/BY status bit) is a read-only bit for indicating the WSM
operation. This bit goes to “0” (BUSY) while the automatic programming/erase operation is active and goes to “1” (READY) during the
other operations.
Bit 1 serves as the CPU reprogramming mode select bit. Writing of
“1” to this bit selects the CPU reprogramming mode, and software
commands will be acceptable. Because the CPU cannot directly access the internal flash memory in the CPU reprogramming mode,
writing to this bit 1 must be performed by the user-original reprogramming control software which has been transferred to the internal RAM in advance. To set bit 1 to “1”, it is necessary to write “0” and
“1” to this bit 1 successively. On the other hand, to clear this bit to “0”,
it is sufficient only to write “0”.
Bit 2 serves as the lock bit invalidity select bit, and setting this bit to
“1” invalidates the protection by a lock bit against erasing and programming (block lock). The lock bit invalidity select bit can invalidates the lock bit function but set no lock bit itself. However, if erasing
is performed with this bit = “1”, a lock bit with value “0” (the locked
state) will be set to “1” (the unlocked state) after the erasing has
been completed. To set the lock bit invalidity select bit to “1”, write “0”
and “1” to this bit 2 successively with the CPU reprogramming mode
select bit = “1”. The manipulation of bit 2 is allowed only when the
CPU reprogramming mode select bit = “1”.
Bit 3 (the flash memory reset bit) resets the control circuit of the internal flash memory and is used when the CPU reprogramming
mode is terminated or when an abnormal access to the flash
memory happens. Writing of “1” to bit 3 with the CPU reprogramming
mode select bit = “1” preforms the reset operation. To remove the
reset, write “0” to bit 3 subsequently.
Bit 5 serves as the user ROM area select bit and is valid only in the
boot mode. Setting this bit to “1” in the boot mode switches an acces-
sible area from the boot ROM area to the user ROM area. To use the
CPU reprogramming mode in the boot mode, set this bit to “1”. Note
that when the microcomputer is booted up in the user ROM area,
only the user ROM area is accessible and bit 5 is invalid; on the other
hand, when the microcomputer is in the boot mode, bit 5 is valid independent of the CPU reprogramming mode. To rewrite bit 5, execute the user-original reprogramming control software transferred
to the internal RAM in advance.
Figure 115 shows the CPU reprogramming mode set/termination
flowchart, and be sure to follow this flowchart. As shown in Note 1 of
Figure 115, before selecting the CPU reprogramming mode, set the
processor mode register 1’s bit 7 (the internal ROM bus cycle select
bit) to “0” and set flag I to “1” to avoid an interrupt request input.
When an NMI interrupt or a watchdog timer interrupt request is generated in the CPU reprogramming mode, when an input to the
RESET pin is “L”, or when the software reset is performed, the flash
memory control circuit and flash memory control register will be reset.
When the flash memory is reset during the erase or programming
operation, this operation is cancelled and the target block’s data will
be invalid. Just before writing a software command related to the
erase/programming operation, be sure to write to the watchdog
timer. Also, be sure to set the NMI pin to “H” to avoid an NMI interrupt
request occurrence. In the CPU reprogramming mode, be sure not
to use the STP and WIT instructions.
107
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Start
Single-chip mode,
Memory expansion mode,
or Boot mode
The processor mode register 1 is set (Note 1).
Flag I is set to “1”.
Table 20 lists the software commands.
By writing a software command after the CPU reprogramming select
bit has been set to “1”, erasing, programming, etc. can be specified.
Note that, at software commands’ input, the high-order byte (D8–
D15) is ignored. (Except for the write data at the 2nd cycle of a page
programming command.)
Software commands are explained as below.
Read Array Command (FF16)
The user-original reprogramming control software
for the CPU reprogramming mode is transferred to
the internal RAM.
By writing command code “FF16” at the 1st bus cycle, the microcomputer enters the read array mode. If an address to be read is input in
the next or the following bus cycles, the contents at the specified address are output to the data bus (D0 to D15) in a unit of 16 bits.
The read array mode is maintained until writing of another software
command.
Jump to the above software in the internal RAM.
(The operations shown below will be executed by
the above software in this RAM.)
Read Status Register Command (7016)
(Only in the boot mode.)
The user ROM area select bit is set to “1”.
Writing command code “7016” at the 1st bus cycle outputs the contents of the status register to the data bus (D0-D7) by a read at the
2nd bus cycle.
The status register is explained later.
Clear Status Register Command (5016)
Writing of “1” to the CPU reprogramming mode select bit.
(Writing of “0” → Writing of “1”)
Operations such as erasing, programming are
executed by using software commands.
(If necessary, the lock bit invalidity select bit is set.)
Read array command is executed, or reset is
performed by setting the flash memory reset bit.
(Writing of “1” → Writing of “0”) (Note 2)
Writing of “0” to the CPU reprogramming mode
select bit.
(Only in the boot mode.)
Writing of “0” to user ROM area select bit (Note 3).
Completed
Notes 1: The processor mode register 1’s bit 7 (address 5F16, the
internal ROM bus cycle select bit) must be “0” (bus cycle
= 3φ).
2: To terminate the CPU reprogramming mode after the
erase and programming operations have been
completed, be sure to execute the read array command
or perform the flash memory reset operation.
3: This bit may remain “1”. However, if this bit is “1”, the
user ROM area access is specified.
Fig. 115 CPU reprogramming mode set/termination flowchart
108
This command clears three status bits (SR.3–5) each of which is set
to “1” to indicate that the operation has been terminated by an error.
To clear these bits, write command code “5016” at the 1st bus cycle.
Page Programming Command (4116)
Page programming facilitates quick programming of 128 words (a
page = 256 bytes) at a time. To initiate page programming, write
command code “4116” at the 1st bus cycle; then, program a series of
data, in a unit of 16 bits, sequentially from the 2nd to the 129th bus
cycle. It is necessary, at this time, to increment address A0–A7 from
"0016" to “FE16” by +2. (Programmed to even addresses.)
Upon completion of data loading, automatic programming (data programming and verification) operation is started.
The completion of the automatic programming operation is recognized by a read of the status register or a read of the flash memory
control register. As the automatic programming operation starts, the
microcomputer enters the read status register mode automatically to
allow reading out the contents of the status register. Bit 7 of the status register (SR.7) is cleared to “0” simultaneously with the start of
the automatic programming operation; and also, bit 7 returns to “1”
by the end of it. Until writing of the read array command (FF16), writing of the read lock bit status command (7116), or performing the reset operation with the flash memory reset bit, this read status register
mode is maintained. In continuous programming, if there is no programming error, page programming commands can be executed
with the read status register mode kept.
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 20. Software commands (CPU reprogramming mode)
1st cycle
Command
Read Array
Read Status Register
Clear Status Register
Page Programming (Note 3)
Block Erase
Erase All Unclocked Block
Lock Bit Programming
Read Lock Bit Status
3rd cycle
2nd cycle
Mode
Address
Data
(D0 to D7)
Mode
Address
Write
Write
Write
Write
Write
Write
Write
Write
X (Note 2)
X
X
X
X
X
X
X
FF16
7016
5016
4116
2016
A716
7716
7116
—
Read
—
Write
Write
Write
Write
Read
—
X
—
Data
—
SRD (Note 3)
—
WA0 (Note 4) WD0 (Note 4)
BA (Note 5)
D016
X
D016
BA
D016
BA
D6 (Note 6)
Mode
Address
Data
—
—
—
—
—
WA1
—
—
—
—
—
—
—
WD1
—
—
—
—
—
Write
—
—
—
—
Notes 1: At software commands’ input, the high-order byte of data (D8–D15) is ignored.
2: X = An arbitrary address in the user ROM area. (Note that A0 = “0”.)
3: SRD = Status register data.
4: WA = Write address, WD = Write data (16 bits).
WA and WD must be set from “0016” to “FE16”. (Byte addresses. Incremented by +2. Address A0 = “0”.) Page size = 128 words (128 ✕ 16 bits).
5: Block address: the maximum address of each block must be input. Note that address A0 = “0”.
6: D6 indicates the block lock status.
“1” = unlocked. “0” = locked.
The RY/BY status bit of the flash memory control register goes “0”
during the automatic programming operation; and also, it goes “1” after the end of it, the same way as bit 7 of the status register.
Before execution of the next command, be sure to verify that bit 7 of
the status register (SR.7) or the RY/BY status bit is set to “1”
(READY). During the automatic programming operation, writing of
commands and access to the flash memory must not be performed.
Reading out the status register after the automatic programming operation is completed reports the result of it. For details, refer to the
section on the status register.
Figure 116 shows an example of the page programming flowchart.
Note that each block can be protected from programming by using a
lock bit. For details, refer to the section on the data protect function.
Additional programming to any page that has already been programmed is prohibited.
the status register (SR.7) or the RY/BY status bit is set to “1”
(READY). During the automatic erase operation, writing of commands and access to the flash memory must not be performed.
Reading out the status register after the automatic erase operation
is completed reports the result of it. For details, refer to the section
on the status register.
Figure 117 shows an example of the block erase flowchart.
Note that each block can be protected from erasing by using a lock
bit. For details, refer to the section on the data protect function.
Block Erase Command (2016/D016)
Writing command code “2016” at the 1st bus cycle and writing verify
command code “D016” and the maximum address of the block (Note
that address A0 = “0”.) at the subsequent 2nd bus cycle initiate the
automatic erase (erasing and erase verification) operation for the
specified block.
The completion of the automatic erase operation is verified by a read
of the status register or a read of the flash memory control register.
As the automatic erase operation starts, the microcomputer enters
the read status register mode automatically to allow reading out the
contents of the status register. Bit 7 of the status register (SR.7) is
cleared to “0” simultaneously with the start of the automatic erase
operation; and also, it returns to “1” by the end of it. The read status
register mode is maintained until writing of the read array command
(FF16), writing of the read lock bit status command (7116), or performing the reset operation with the flash memory reset bit.
The RY/BY status bit of the flash memory control register goes “0”
during the automatic erase operation; and also, it goes “1” after the
end of it, the same way as bit 7 of the status register.
Before execution of the next command, be sure to verify that bit 7 of
109
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Start
Start
Write 4116
Write 7716
n=0
Write
Addressn, Datan
n = FE16
n=n+2
Write D016
Block Address
NO
SR.7 = 1?
YES
Status Register
Read
NO
YES
SR.4 = 0?
SR.7 = 1?
NO
NO
Lock Bit Programming
Error
YES
YES
Lock Bit Programming
Completed
Full status check
Page programming
completed
Fig. 116 Page programming flowchart
Fig. 118 Lock bit programming flowchart
Start
Write 2016
Start
Write D016
Block Address
Write 7116
Status Register
Read
Block Address
SR.7 = 1?
NO
YES
Full Status Check
D6 = 0?
NO
YES
Block: locked
Block Erase Completed
Fig. 117 Block erase flowchart
110
Fig. 119 Read lock bit status flowchart
Block: unlocked
MITSUBISHI MICROCOMPUTERS
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Erase All Unlocked Block Command (A716/D016)
Writing command code “A716” at the 1st bus cycle and writing verify
command code “D016” at the subsequent 2nd bus cycle initiate the
continuous block erase (chip erase) operations for all the blocks.
The completion of the chip erase operation, as well as of the block
erase operation, is verified by a read of the status register or a read
of the flash memory control register. The result of the automatic
erase operation is also reported by a read of the status register.
During the automatic erase operation (when the RY/BY status bit =
“0”), writing of commands and access to the flash memory must not
be performed.
When the lock bit invalidity select bit = “1”, all the blocks are erased
regardless of the status of their lock bits. When the lock bit invalidity
select bit = “0”, on the contrary, the status of each lock bit becomes
valid, so only the blocks in the unlocked state (lock bit = “1”) are
erased.
Lock Bit Programming Command (7716/D016)
By writing of command code “7716” at the 1st bus cycle and writing
of verify command code “D016” and the block’s maximum address
(Note that address A0 = “0”.) at the subsequent 2nd bus cycle, “0”
(the locked state) is written into the lock bit of the specified block.
Figure 118 shows an example of the lock bit programming flowchart.
The status of the lock bit can be read out by the read lock bit status
command.
The completion of the lock bit programming operation, as well as of
the page programming operation, is verified by a read of the status
register or a read of the flash memory control register.
For details of the lock bit’s function and the method of reset, refer to
the section on the data protect function.
completion of the erase operation, and the locked state by the
lock bit is terminated.
To perform erase or programming, be sure to do one of the following.
• By executing the read lock bit status command, verify that the lock
of the target block is invalid.
• Set the lock bit invalidity select bit to “1” to invalidate the lock.
When the block erase or programming is performed with the lock
valid, the erase status bit (SR.5) and programming status bit (SR.4)
are set to “1” (terminated by error).
Status Register
The status register is used to indicate what the status of the write
state machine (WSM) operation is and whether the programming/
erase operation has been completed normally or terminated by an
error. By writing the read status register command (7016), the contents of the status register can be read out; by writing the clear status register command (5016), the contents of the status register can
be cleared.
Table 21 lists the definition of each bit of the status register.
The status register outputs “8016” after reset is removed.
The status of each bit is described below.
Read Lock Bit Status Command (7116)
By writing of command code “7116” at the 1st bus cycle and writing of
the block’s maximum address (Note that address A0 = “0”.) at the
subsequent 2nd bus cycle, the status of the lock bit of the specified
block is output to the data bus (D6).
Figure 119 shows an example of the read lock bit programming flowchart.
Data Protect Function (Block Lock)
Each block is implemented with a nonvolatile lock bit to protect the
block from erasing/programming (block lock). A “0” (the locked state)
can be written to a lock bit using the lock bit programming command,
and the lock bit of each block can be read out by using the read lock
bit status command.
Whether a block lock is valid or invalid is determined by the status of
the lock bit and the lock bit invalidity select bit of the flash memory
control register.
(1) When the lock bit invalidity select bit = “0”, a lock bit determines
whether to lock or unlock the corresponding block. A block with
its lock bit = “0” is locked and inhibited from erasing and programming. On the other hand, a block with its lock bit = “1” remains unlocked and allows to be erased/programmed.
(2) When the lock bit invalidity select bit = “1”, all the blocks are unlocked and allows to be erased/programmed regardless of the
values of their lock bits. In this case, a lock bit with a value “0”
(the locked state) is set to “1” (the unlocked state) after
111
MITSUBISHI MICROCOMPUTERS
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Write State Machine (WSM) Status Bit (SR.7)
This bit reports the operation status of the WSM. This bit is set to “1”
(READY) after the system power is turned on or after reset is removed.
During the automatic programming or erase operation, this bit is
cleared to “0” (BUSY), however, set to “1” upon completion of them.
Erase Status Bit (SR.5)
This bit reports the status of the automatic erase operation. This bit
is set to “1” if an erase error occurs and returns to “0” if one of the
following conditions is satisfied:
• the system power is turned on.
• reset is removed.
• the clear status register command (5016) is executed.
Under the condition that any of SR.5, SR.4 and SR.3 = “1”, none of
the page programming, block erase, erase all unlocked block, and
lock bit programming commands can be accepted. To execute these
commands, in advance, execute the clear status register command
(5016) to clear the status register.
Both of SR.4 and SR.5 are set to “1” under the following conditions
(Command Sequence Error):
(1) when data other than “D016” and “FF16” is written to the data in
the 2nd bus cycle of the lock bit programming command (7716/
D016)
(2) when data other than “D016” and “FF16” is written to the data in
the 2nd bus cycle of the block erase command (2016/D016)
(3) when data other than “D016” and “FF16” is written to the data in
the 2nd bus cycle of the erase all unlocked block command
(A716/D016)
Programming Status Bit (SR.4)
This bit reports the status of the automatic programming operation.
This bit is set to “1” if a programming error occurs and returns to “0”
if one of the following conditions is satisfied:
• the system power is turned on.
• reset is removed.
• the clear status register command (5016) is executed.
Note that, writing of “FF16” forces the microcomputer into the read
array mode. Simultaneously with this, the command written in the 1st
bus cycle will be canceled.
Block Status After Programming Bit (SR.3)
Full Status Check
This bit is set to “1”, upon completion of the page programming operation, if the excessive programming (Note) occurs. That is, the status register becomes “8016” when the programming operation is
terminated normally, “9016” when the programming operation is
failed, and “8816” when the excessive programming occurs.
The full status check reports the results of the erase or programming
operation.
Figure 120 shows the full status check flowchart and actions to be
taken if an error has occurred.
Note: The excessive programming means the status that memory
cells are too depleted, so data cannot be read out correctly.
Table 21. Bit definition of status register
Symbol
SR.7 (D7)
SR.6 (D6)
SR.5 (D5)
SR.4 (D4)
SR.3 (D3)
SR.2 (D2)
SR.1 (D1)
SR.0 (D0)
112
Status
Write State Machine (WSM) Status
Reserved
Erase Status
Programming Status
Block Status After Programming
Reserved
Reserved
Reserved
Definition
“1”
“0”
Ready
Busy
Terminated by error.
Terminated by error.
Terminated by error.
Terminated normally.
Terminated normally.
Terminated normally.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register Read
SR.4 = 1
and
SR.5 = 1
?
YES
Command Sequence
Error
Execute the clear status register command (5016) to clear the status register.
After verifying the command to be correctly input, start the operation again.
NO
NO
Block Erase
Error
SR.5 = 0?
YES
NO
SR.4 = 0?
Programming Error
(Page, Lock bit)
YES
NO
SR.3 = 0?
Programming Error
(Block)
Examine whether a lock is active or not by executing the read lock bit status
command (7116). After removing the lock, perform block erase again. If the
same error still occurs, this page cannot be used.
Examine whether a lock is active or not by executing the read lock bit status
command (7116). After removing the lock, perform programming again. If the
same error still occurs, this page cannot be used.
After erasing the block where an error has occured, perform programming again.
If the same error still occurs, this block cannot be used.
YES
End
(Block erase, Programming)
Note: Under the condition that any of SR.5, SR.4 and SR.3 = “1”, none of the page programming, block erase,
erase all unlocked block, and lock bit programming commands can be accepted. To execute these
commands, in advance, execute the clear status register command (5016).
Fig. 120 Full status check flowchart and actions to be taken if an error has ocurred
DC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 26 MHz (Note))
Symbol
Icc1
Icc2
Icc3
Icc4
Parameter
Min.
VCC power source current (at read)
VCC power source current (at write)
VCC power source current (at programming)
VCC power source current (at erasing)
Limits
Typ.
30
Max.
48
48
54
54
Unit
mA
mA
mA
mA
Limits of VIH, VIL, VOH, VOL, IIH, and IIL for each pin are the same as those in the microcomputer mode.
Note: f(fsys) indicates the system clcok (fsys) frequency.
AC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 26 MHz (Note))
Parameter
Min.
Page programming time
Block erase time
Erase all unlocked block time
Lock bit programming time
Limits
Typ.
Max.
8
120
50
600
50 ✕ n 600 ✕ n
8
120
Unit
ms
ms
ms
ms
n = Number of blocks to be erased
The limits of parameters other than the above are same as those in the microcomputer mode.
Note: f(fsys) indicates the system clock (fsys) frequency.
113
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
AVCC
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Analog power source voltage
Input voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117,
VREF, XIN, RESET, BYTE, MD0, MD1, NMI, VCONT
Output voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87, P100–P107,
P110–P117, XOUT
Power dissipation
Operating ambient temperature
Storage temerature
Ratings
–0.3 to 6.5
–0.3 to 6.5
Unit
V
V
–0.3 to VCC+0.3
V
–0.3 to VCC+0.3
V
400
–20 to 85
–40 to 150
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VCC
AVCC
VSS
AVSS
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
f(XIN)
f(fsys)
Parameter
Power source voltage
Analog power source voltage
Power source voltage
Analog power source voltage
High-level input voltage XIN, RESET, BYTE, MD0, MD1
High-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
High-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
High-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
High-level input voltage D0–D7, D8–D15
High-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
High-level input voltage SCLK, SDA (Note 1)
Low-level input voltage XIN, RESET, BYTE, MD0, MD1
Low-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87, P100–P107, P110–P117
Low-level input voltage P00–P07 (When the port P0 input level select bit = “0”)
Low-level input voltage P00–P07 (When the port P0 input level select bit = “1”)
Low-level input voltage D0–D7, D8–D15
Low-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT–TA4OUT,
TB0IN–TB2IN, KI0–KI3, INT0–INT4, NMI, ADTRG, CTS0,
CTS1, CLK0, CLK1, RxD0, RxD1
Low-level input voltage SCLK, SDA (Note 1)
High-level peak output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87,
P100–P107, P110–P117
High-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level peak output current
P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
Low-level average output current P00–P07, P10–P17, P20–P27, P30–P33,
P40–P47, P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107, P110–P117
External clock input frequency (Note 2)
System clock frequency
Min.
4.5
Typ.
5.0
VCC
0
0
Max.
5.5
Unit
0.8 Vcc
0.7 VCC
Vcc
VCC
V
V
V
V
V
V
0.7 Vcc
0.43 Vcc
0.43 Vcc
0.43 Vcc
Vcc
Vcc
Vcc
Vcc
V
V
V
V
0.43 Vcc
0
0
Vcc
0.2 VCC
0.2 VCC
V
V
V
0
0
0
0
0.2 VCC
0.16 VCC
0.16 VCC
0.16 VCC
V
V
V
V
0
0.16 VCC
–10
V
mA
–5
mA
10
mA
5
mA
26
26
MHz
MHz
Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode.
2: When using the PLL frequency multiplier, be sure that f(fsys) = 26 MHz or less.
3: Average output current is the average value of an interval of 100 ms.
4: The sum of IOL(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0–P2, P8, P10, and P11 must be 80
mA or less, the sum of IOL(peak) for ports P3–P7 must be 80 mA or less, the sum of IOH(peak) for ports P3–P7 must be 80 mA or less.
114
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DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz (Note))
Symbol
VOH
VOH
VOH
VOL
VOL
VOL
VT+ —VT–
VT+ —VT–
VT+ —VT–
IIH
IIL
IIL
VRAM
ICC
Parameter
Test conditions
High-level output voltage P00–P07, P10–P17,
IOH = –10 mA
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
High-level output voltage P00–P07, P10–P17,
IOH = –400 µA
P20–P27, P40, P42, P44–P47,
P100–P107, P110–P117
High-level output voltage P31–P33
IOH = –10 mA
IOH = –400 µA
Low-level output voltage P00–P07, P10–P17,
IOL = 10 mA
P20–P27, P30, P40–P47,
P50–P57, P60–P67,
P70–P77, P80–P87,
P100–P107, P110–P117
Low-level output voltage P00–P07, P10–P17,
IOL = 2 mA
P20–P27, P40, P42,
P44–P47, P100–P107,
P110–P117
Low-level output voltage P31–P33
IOL = 10 mA
IOL = 2 mA
Hysteresis RDY, HOLD, TA0IN–TA4IN,
TA0OUT–TA4OUT, TB0IN–TB2IN,
KI0–KI3, INT0–INT4, NMI, ADTRG,
CTS0, CTS1, CLK0, CLK1, RxD0, RxD1
Hysteresis RESET
Hysteresis XIN
High-level input current P00–P07, P10–P17,
VI = 5.0 V
P20–P27, P30–P33, P40–P47,
P50–P57, P60–P67, P70–P77,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1, NMI
Low-level input current P00–P07, P10–P17,
VI = 0 V
P20–P27, P30–P33, P40–P43,
P50–P53, P60–P67, P70–P77,
P80–P87, P100–P107,
P110–P117, XIN, RESET,
BYTE, MD0, MD1
Low-level input current P44–P47, P54–P57, NMI
VI = 0 V, No pullup transistor
VI = 0 V, Pullup transistor used
RAM hold voltage
When clock is stoped.
Power source current
Output-only pins f(fsys) = 26 MHz.
are open, and the CPU operates.
other pins are connected to Vss or
Vcc. An external Ta = 25 °C when
square-waveform clock is stopped.
clock is input. (Pin
XOUT is open.) The
PLL frequency Ta = 85 °C when
multiplier stops its clock is stopped.
operation.
Min.
3
Limits
Typ.
Max.
Unit
V
4.7
V
3.4
4.8
V
2
V
0.45
V
1.6
0.4
0.7
V
1.5
0.3
5
V
V
µA
–5
µA
–0.7
–5
–1.1
30
54
µA
mA
V
mA
1
µA
0.2
0.5
0.1
–0.4
2
V
20
115
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
—————
—————
RLADDER
Parameter
Resolution
VREF = VCC
Ladder resistance
VREF = VCC
Conversion time
VREF
VIA
Reference voltage
Analog input voltage
Max.
Min.
VREF = VCC
Absolute accuracy
tCONV
Limits
Test conditions
f(fsys) ≤ 26 MHz
10
±3
±2
10-bit resolution mode
8-bit resolution mode
10-bit resolution mode
8-bit resolution mode
5
4.54
1.89 (Note)
2.7
0
Unit
Bits
LSB
LSB
kΩ
µs
VCC
VREF
V
V
Note: This is applied when A-D conversion freguency (φAD) = f1.
D-A CONVERTER CHARACTERISTICS
(VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
——
——
tsu
RO
IVREF
Test conditions
Parameter
Resolution
Absolute accuracy
Set time
Output resistance
Reference power source input current
Min.
1
Limits
Typ.
2.5
(Note)
Max.
8
± 1.0
3
4
3.2
Unit
Bits
%
µs
kΩ
mA
Note: The test conditions are as follows:
• One D-A converter is used.
• The D-A register value of the unused D-A converter is “0016.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded.
RESET INPUT
Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Symbol
tw(RESETL)
RESET input low-level pulse width
RESET input
tw(RESETL)
116
Min.
2
Limits
Typ.
Max.
Unit
µs
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PERIPHERAL DEVICE INPUT/OUTPUT TIMING
(VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz unless otherwise noted)
For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 26 MHz are shown in ( ).
∗
Timer A input (Count input in event counter mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Limits
Parameter
Min.
80
40
40
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Max.
Unit
ns
ns
ns
Timer A input (Gating input in timer mode)
Symbol
Parameter
tc(TA)
TAiIN input cycle time
f(fsys) ≤ 26 MHz
tw(TAH)
TAiIN input high-level pulse width
f(fsys) ≤ 26 MHz
tw(TAL)
TAiIN input low-level pulse width
f(fsys) ≤ 26 MHz
Limits
Min.
16 × 109
(615)
f(fsys)
9
8 × 10
(307)
f(fsys)
9
8 × 10
(307)
f(fsys)
Max.
Unit
ns
ns
ns
Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 26 MHz.
Timer A input (External trigger input in one-shot pulse mode)
Symbol
Limits
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
tw(TAL)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Min.
f(fsys) ≤ 26 MHz
8 × 109
f(fsys)
Max.
(307)
Unit
ns
80
80
ns
ns
Timer A input (External trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
Parameter
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
80
80
Max.
Unit
ns
ns
Timer A input (Up-down input and Count input in event counter mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
Parameter
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Limits
Min.
2000
1000
1000
400
400
Max.
Unit
ns
ns
ns
ns
ns
117
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A input (Two-phase pulse input in event counter mode)
Symbol
tc(TA)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
Limits
Parameter
Min.
800
200
200
TAiIN input cycle time
TAjIN input setup time
TAjOUT input setup time
• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
• Up-down and Count input in event counter mode
tc(UP)
tw(UPH)
TAiOUT input
(Up-down input)
tw(UPL)
TAiOUT input
(Up-down input)
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When count by falling)
TAiIN input
(When count by rising)
• Two-phase pulse input in event counter mode
tc(TA)
TAjIN input
tsu(TAjIN-TAjOUT)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
TAjOUT input
tsu(TAjOUT-TAjIN)
Test conditions
• VCC = 5 V±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 0.8 V, VIH = 2.15 V
118
Max.
Unit
ns
ns
ns
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time (one edge count)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
Limits
Min.
80
40
40
160
80
80
Max.
Unit
ns
ns
ns
ns
ns
ns
Timer B input (Pulse period measurement mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time
f(fsys) ≤ 26 MHz
tw(TBH)
TBiIN input high-level pulse width
f(fsys) ≤ 26 MHz
tw(TBL)
TBiIN input low-level pulse width
f(fsys) ≤ 26 MHz
Limits
Min.
16 × 109
(615)
f(fsys)
8 × 109
(307)
f(fsys)
9
8 × 10
(307)
f(fsys)
Max.
Unit
ns
ns
ns
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 26 MHz.
Timer B input (Pulse width measurement mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time
f(fsys) ≤ 26 MHz
tw(TBH)
TBiIN input high-level pulse width
f(fsys) ≤ 26 MHz
tw(TBL)
TBiIN input low-level pulse width
f(fsys) ≤ 26 MHz
Limits
Min.
16 × 109
(615)
f(fsys)
8 × 109
(307)
f(fsys)
9
8 × 10
(307)
f(fsys)
Max.
Unit
ns
ns
ns
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 26 MHz.
A-D trigger input
Symbol
tc(AD)
tw(ADL)
Parameter
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
Limits
Min.
1000
125
Max.
Unit
ns
ns
119
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Limits
Parameter
Min.
200
100
100
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Max.
80
0
20
90
Unit
ns
ns
ns
ns
ns
ns
ns
External interrupt (INTi) input, NMI input, Key input interrupt (KIi) input
Symbol
tw(INH)
tw(INL)
Limits
Parameter
Min.
250
250
INTi input/NMI input/KIi input high-level pulse width
INTi input/NMI input/KIi input low-level pulse width
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi input
tw(CKL)
th(C - Q)
TxDi output
td(C - Q)
tsu(D - C)
RxDi input
tw(INL)
INTi input,
NMI input,
KIi input
Test conditions
• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 0.8 V, VIH = 2.15 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF
120
tw(INH)
th(C - D)
Max.
Unit
ns
ns
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
READY, HOLD TIMING
Timing requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Symbol
tsu(RDY-φ1)
tsu(HOLD-φ1)
th(φ1-RDY)
th(φ1-HOLD)
Parameter
RDY input setup time
HOLD input setup time
RDY input hold time
HOLD input hold time
Switching characteristics
Max.
Unit
ns
ns
ns
ns
(VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Symbol
Parameter
td(φ1-HLDAL)
HLDA output delay time
td(RDH-HLDAL) HLDA low-level output delay time after read
td(BXWH-HLDAL) HLDA low-level output delay time after write
tpxz(HLDAL-RDZ)
tpxz(HLDAL-BXWZ)
tpxz(HLDAL-CSiZ)
tpxz(HLDAL-ALEZ)
tpxz(HLDAL-AZ)
tpzx(HLDAL-RDZ)
tpzx(HLDAL-BXWZ)
tpzx(HLDAL-CSiZ)
tpzx(HLDAL-ALEZ)
tpzx(HLDAL-AZ)
Limits
Min.
40
40
0
0
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating start delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Floating release delay time
Limits
Min.
Max.
20
–15
–15
–15
–15
0
ns
ns
tc –15 (Note)
tc –15 (Note)
–15
Unit
10
10
10
10
10
ns
ns
ns
ns
ns
ns
0
ns
ns
0
ns
0
ns
0
ns
Note: tc = 1/f(fsys).
121
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
RDY input
φ1
RD,
BLW,
BHW
tsu (RDY-φ1)
th (φ1-RDY)
RDY input
: Wait inserted by software (The above is applied when bus cycle = 1φ + 2φ)
: Wait inserted by ready function
HOLD input
φ1
tsu (HOLD-φ1)
th (φ1-HOLD)
HOLD input
td (φ1-HLDAL)
td (φ1-HLDAL)
HLDA output
td (RDH-HLDAL) tpxz (HLDAL-RDZ)
tpzx (HLDAL-RDZ)
Hi-Z
RD
td (BXWH-HLDAL)
tpxz (HLDAL-BXWZ)
tpzx (HLDAL-BXWZ)
Hi-Z
BLW
BHW
tpxz (HLDAL-CSiZ)
tpzx (HLDAL-CSiZ)
Hi-Z
CSi
tpxz (HLDAL-ALEZ)
tpzx (HLDAL-ALEZ)
Hi-Z
ALE
tpxz (HLDAL-AZ)
A0–A23 output
Test conditions
• VCC = 5 V ± 0.5 V, Ta= –20 to 85 °C
• RDY input, HOLD input : VIL = 0.8V, VIH = 2.15 V
• HLDA output
: VOL = 0.8V, VOH = 2.0 V, CL = 50 pF
122
tpzx (HLDAL-AZ)
Hi-Z
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
External bus timing
For limits depending on f(fsys), their calculation formulas are shown below.
Bus cycle
1φ +1φ
1φ +2φ
1φ +3φ
2φ +2φ
WH
WL
1
1
1
2
1
2
3
2
Bus cycle
WH
WL
2
2
3
3
3
4
3
4
2φ +3φ
2φ +4φ
3φ +3φ
3φ +4φ
tc = 1/f(fsys).
Timing Requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 26 MHz, unless otherwise noted)
Symbol
tc(in)
tw(half)
tw(H)
tw(L)
tr
tf
ta(A-D)
ta(A-D)
ta(CSiL-D)
ta(RDL-D)
tsu(D-RDL)
th(RDH-D)
ta(BA-D)
th(BA-D)
ta(LA-D)
Limits
Parameter
Min.
38
0.45 tc
0.5 tc – 6
External clock input cycle time
External clock input pulse width with half input-volage
External clock input high-level pulse width
External clock input low-level pulse width
External clock input rise time
External clock input fall time
Address access time (the address output select bit = 0)
Address access time (the address output select bit = 1)
Chip select access time
Read access time
Read data setup time
Data input hold time after read
Address access time at burst ROM access
Data hold time after address at burst ROM access
Address access time (the multiplexed bus select bit = 1)
Max.
0.55 tc
0.5 tc – 6
6
6
(WH + WL) tc-45
(WH + WL-0.5) tc-35
(WH + WL-0.5) tc-35
WL ✕ tc-30
15
0
WL ✕ tc-35
8
(WH + WL-0.5)tc-35 (Note)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: This is independent of the address output select bit’s contents.
External clock input
tw(L)
tw(H)
tr
tf
tc(in)
tw(half)
XIN
Test conditions
• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
• Output timing voltage : 2.5 V (tc(in), tw(half))
123
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Symbol
td(φ1-RDL)
td(φ1-RDH)
td(φ1-BXWL)
td(φ1-BXWH)
td(φ1L-CSiL)
td(φ1L-CSiH)
td(φ1H-A)
td(φ1L-A)
tw(ALEH)
td(A-ALEL)
tw(RDL)
tw(RDH)
td(RDH-BXWH)
td(A-RDH)
td(A-RDH)
th(RDH-A)
th(RDH-A)
td(RDH-ALEL)
td(ALEL-RDH)
Parameter
Read low-level output delay time
Read high-level output delay time
Write low-level output delay time
Write high-level output delay time
Chip select low-level output delay time
Chip select high-level output delay time
Address output delay time (the address output select bit = 0)
Address output delay time (the address output select bit = 1)
ALE pulse width
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
Bus cycle = 2φ + 2φ
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
ALE completion delay time
after address stabilization
(when the address output
select bit = 0)
ALE completion delay time Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ
after address stabilization Bus cycle = 2φ + 2φ
(when the address output
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
select bit = 1)
Read output pulse width
Read output high-level width (Note 1)
Write disable valid time after read (Note 2)
Address valid time before read (when the address output select bit = 0)
Address valid time before read (when the address output select bit = 1)
Address hold time after read (when the address output select bit = 0) (Note 2)
Address hold time after read (when the address output select bit = 1) (Note 2)
ALE completion delay time after read start
Bus cycle = 2φ + 2φ
Read disable valid time
after ALE completion
Bus cycle = 3φ + 3φ, 3φ + 4φ
td(CSiL-RDH)
td(CSiL-RDL)
th(RDH-CSiL)
td(RDH-D)
tw(BXWL)
tw(BXWH)
td(BXWH-RDH)
td(A-BXWH)
td(A-BXWH)
th(BXWH-A)
th(BXWH-A)
td(BXWH-ALEL)
td(ALEL-BXWH)
Chip select valid time before read
Chip select output valid time before read completion
Chip select hold time after read
Next write cycle data output delay time after read (Note 2)
Write output pulse width
Write output high-level width (Note 1)
Read disable valid time after write (Note 2)
Address valid time before write (when the address output select bit = 0)
Address valid time before write (when the address output select bit = 1)
td(CSiL-BXWH)
td(CSiL-BXWL)
th(BXWH-CSiL)
td(D-BXWL)
th(BXWH-D)
tpxz(BXWH-DZ)
Chip select valid time before write
Chip select output valid time before write completion
Chip select hold time after write
Data output valid time before write completion
Data hold time after write (Note 3)
Floating start delay time after write (Note 3)
Address hold time after write (when the address output select bit = 0) (Note 2)
Address hold time after write (when the address output select bit = 1) (Note 2)
ALE completion delay time after write start
Write disable valid time
Bus cycle = 2φ + 2φ
after ALE completion
Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ
Limits
Min.
–18
–18
–18
–18
–20
–22
–5
–20
0.5tc-19
tc-20
1.5tc-20
Max.
0
0
0
0
0
10
25
16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc-30
ns
1.5tc-30
2tc-30
ns
0.5tc-19
ns
tc-20
ns
1.5tc-20
ns
WL ✕ tc-15
ns
WH ✕ tc-15
ns
tc-15
WH ✕ tc-30
ns
(WH-0.5)tc-19
ns
8
0.5tc-10
ns
ns
ns
ns
20
ns
0.5tc-19
tc-15
ns
(WH-0.5)tc-19
ns
(WH + WL-0.5)tc-20
ns
0.5tc-14
tc-15
ns
WL ✕ tc-15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WH ✕ tc-15
tc-15
WH ✕ tc-30
(WH-0.5)tc-19
8
0.5tc-10
20
0.5tc-19
tc-15
(WH-0.5)tc-19
(WH + WL-0.5)tc-20
0.5tc-14
WL ✕ tc-20
0.5tc-10
0.5tc + 10
Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.).
2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.).
3: This parameter is extended by tc (ns) when both of the following conditions are satisfied:
• When accessing the area where the recovery cycle insertion is selected.
• When two recovery cycles are inserted.
124
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted)
Symbol
td(LA-RDH)
td(LA-ALEL)
th(ALEL-LA)
tpxz(RDH-LAZ)
td(LA-BXWH)
tpzx(RDH-DZ)
Parameter
Address valid time before read
ALE completion delay time Bus cycle = 2φ + 2φ
after address stabilization
Bus cycle = 3φ + 3φ, 3φ + 4φ
Address hold time after
Bus cycle = 2φ + 2φ
ALE completion
Bus cycle = 3φ + 3φ, 3φ + 4φ
Floating start delay time
Address valid time before write
Floating release delay time
Limits
Min.
Max.
(WH-0.5)tc-19 (Note)
tc-20 (Note)
1.5tc-20 (Note)
0.5tc-19
tc-15
5
(WH-0.5)tc-19 (Note)
0.5tc-19 (Note)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Note: This is independent of the address output select bit’s contents.
125
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ+ 3φ,
2φ + 3φ, or 2φ + 4φ
tc
fsys
Bus cycle
<At read>
td(φ1L-CSiL)
td(φ1L-CSiH)
φ1
td(φ1H-A)
td(φ1-RDL)
tw(ALEH)
td(φ1L-A)
td(φ1-RDH)
ALE
td(A-ALEL)
tw(RDH)
tw(RDL)
RD
td(RDH-ALEL)
td(RDH-BXWH)
BLW
BHW
th(RDH-A)
td(A-RDH)
A0–A23
(when the address output select bit = 0)
td(A-ALEL)
td(A-RDH)
th(RDH-A)
A0–A23
(when the address output select bit = 1)
td(CSiL-RDH)
td(CSiL-RDL)
th(RDH-CSiL)
CSi
ta(A-D)
ta(A-D)
ta(CSiL-D)
ta(RDL-D)
td(RDH-D)
tsu(D-RDL) th(RDH-D)
D0–D7, D8–D15
Test conditions
• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi)
126
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ,
2φ + 3φ, or 2φ + 4φ
tc
fsys
<At write>
Bus cycle
td(φ1L-CSiL)
td(φ1L-CSiH)
φ1
td(φ1H-A)
td(φ1L-A)
td(φ1-BXWL)
tw(ALEH)
td(φ1-BXWH)
ALE
td(A-ALEL)
td(BXWH-RDH)
RD
tw(BXWH)
tw(BXWL)
BLW
BHW
td(A-BXWH)
td(BXWH-ALEL)
th(BXWH-A)
A0–A23
(when the address output select bit = 0)
A0–A23
(when the address output select bit = 1)
td(A-ALEL)
td(A-BXWH)
td(CSiL-BXWH)
td(CSiL-BXWL)
th(BXWH-A)
th(BXWH-CSiL)
CSi
td(D-BXWL)
th(BXWH-D)
D0–D7, D8–D15
tpxz(BXWH-DZ)
Test conditions
• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi)
127
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
tc
fsys
<At read>
Bus cycle
td(φ1L-CSiL)
td(φ1L-CSiH)
φ1
td(φ1H-A)
td(φ1L-A)
tw(ALEH)
td(φ1-RDL)
td(φ1-RDH)
td(ALEL-RDH)
ALE
td(A-ALEL)
tw(RDH)
tw(RDL)
RD
td(RDH-BXWH)
BLW
BHW
A0–A23
(when the address output
select bit = 0)
A0–A23
(when the address output
select bit = 1)
td(A-RDH)
th(RDH-A)
td(A-ALEL)
td(A-RDH)
th(RDH-A)
td(CSiL-RDH)
td(CSiL-RDL)
th(RDH-CSiL)
CSi
ta(A-D)
ta(A-D)
D0–D7, D8–D15
(when the multiplexed
bus select bit = 0)
ta(CSiL-D)
ta(RDL-D)
td(RDH-D)
tsu(D-RDL) th(RDH-D)
ta(RDL-D)
tsu(D-RDL) th(RDH-D)
td(LA-RDH)
tpzx(RDH-DZ)
ta(LA-D)
LA0/D0–LA7/D7
(when the multiplexed
bus select bit = 1, Note)
Address
td(LA-ALEL)
Input data
tpxz(RDH-LAZ)
th(ALEL-LA)
Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits.
Test conditions
• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi)
128
Address
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ
tc
fsys
<At write>
Bus cycle
td(φ1L-CSiL)
φ1
td(φ1H-A)
td(φ1L-CSiH)
td(φ1L-A)
tw(ALEH)
td(φ1-BXWH)
td(φ1-BXWL)
ALE
td(ALEL-BXWH)
td(A-ALEL)
td(BXWH-RDH)
RD
tw(BXWH)
tw(BXWL)
BLW
BHW
th(BXWH-A)
td(A-BXWH)
A0–A23
(when the address output
select bit = 0)
A0–A23
(when the address output
select bit = 1)
td(A-ALEL)
td(A-BXWH)
th(BXWH-A)
td(CSiL-BXWH)
th(BXWH-CSiL)
td(CSiL-BXWL)
CSi
td(D-BXWL)
D0–D7, D8–D15
(when the multiplexed
bus select bit = 0)
td(D-BXWL)
td(LA-BXWH)
LA0/D0–LA7/D7
(when the multiplexed
bus select bit = 1, Note)
Address
td(LA-ALEL)
th(BXWH-D)
tpxz(BXWH-DZ)
th(BXWH-D)
Output data
th(ALEL-LA)
tpxz(BXWH-DZ)
Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits.
Test conditions
• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi)
129
130
ta(A-D)
ta(A-D)
ta(RDL-D)
ta(CSiL-D)
td(CSiL-RDH)
td(RDH-ALEL)
ta(BA-D)
th(BA-D)
Test conditions
• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL=0.8 V, VOH=2.0 V, CL=50 pF (except for CSi)
D0–D7, D8–D15
CSi
A0–A23
(when the address output select bit = 1)
td(A-RDH)
td(A-RDH)
td(A-ALEL)
td(A-ALEL)
tw(RDH)
A0–A23
(when the address output select bit = 0)
BLW
BHW
RD
ALE
tw(ALEH)
Burst ROM access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, 2φ + 3φ, 2φ + 4φ
th(BA-D)
ta(BA-D)
th(BA-D)
ta(BA-D)
th(RDH-D)
th(RDH-CSiL)
th(RDH-A)
th(RDH-A)
td(RDH-BXWH)
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
LQFP100-P-1414-0.50
Weight(g)
Lead Material
Cu Alloy
MD
e
JEDEC Code
–
b2
ME
HD
D
100
76
I2
75
1
Symbol
HE
E
Recommended Mount Pad
51
25
26
50
A
L1
F
b
y
A1
c
A2
e
L
Detail F
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
1.7
–
0.1
0.2
0
1.4
–
–
0.13
0.18
0.28
0.105
0.125
0.175
13.9
14.0
14.1
13.9
14.0
14.1
0.5
–
–
15.8
16.0
16.2
15.8
16.0
16.2
0.3
0.5
0.7
1.0
–
–
–
0.1
–
0°
10°
–
–
0.225
–
1.0
–
–
–
14.4
–
–
14.4
–
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit
application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to
change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making
a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
•
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective Jun., 2000.
Specifications subject to change without notice.
Revision History
Rev.
No.
M37902FxCHP Datasheet
Revision Description
Rev.
date
1.0
First Edition
990305
2.0
Refer to Corrections and Supplementary Explanation for “M37902FxC Datasheet (REV.A)”.
990625
3.0
The following are revised/added points in this edition:
• Figure 26 in page 40; the bit’s name (bit 7) of the port function control register
<Error> Pin NMI pullup connection select bit (Note 2)
<Correction> Pin NMI pullup select bit (Note 2)
• Page 95; CLOCK GENERATING CIRCUIT, Right column, line 10
<Error> ••••• the PLL output clock (fPLL). (In other words, set bit 5 to “1”.)
<Correction> ••••• the PLL output clock (fPLL). (In other words, set bit 5 to “1”.) Note that,
after reset, the PLL multiplication ratio select bits are allowed to be changed
only once.
• Table 15 in page 95; Note is revised.
<Error> ••••• f(XIN) means the frequency of the input clock from pin XIN f(XIN).
<Correction> ••••• f(XIN) means the frequency of the input clock from pin XIN f(XIN). After
reset, the PLL multiplication ratio select bits are allowed to be changed only
once.
• Page 120; RECOMMENDED OPERATING CONDITIONS
<Error>
f(fsys)
External clock input frequency (Note 2) •••••••••••
<Correction>
f(XIN)
External clock input frequency (Note 2) •••••••••••
990917
4.0
The following are revised/added points in this edition:
• Page 83; D-A CONVERTER, Left column, line 15
<Error> The D-A output enable bit is cleared to “0” at reset. ••••
<Correction> The contents of the corresponding D-A output enable bit and D-A register are
cleared to “0” at reset. ••••
• Page 83; D-A CONVERTER, Right column, line 1
<Error> with pin D-Ai.
<Correction> with pin D-Ai. Also, when not using the D-A converter, be sure to clear the
contents of the corresponding D-A output enable bit and D-A register to “0”.
Refer to Corrections and Supplementary Explanation for “M37902FxC Datasheet (REV.B)”.
991008
5.0
Notes 1: ★ represents the new information added in Rev.5.0.
2: The revised/added points informed in Rev.3.0 and Rev.4.0 are included in Corrections and Supplementary Explanation for “M37902FxC Datasheet (REV.B)”.
(1/1)
000629
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.1
Page
★
All pages,
Header
Error
Correction
PRELIMINARY
(Deleted)
Notice: This is not a final specification.
Some parametric limits are subject to change.
M37902F8CGP, M37902F8CHP, M37902FCCGP,
M37902FCCHP, M37902FECGP, M37902FECHP,
M37902FGCGP, M37902FGCHP, M37902FHCGP,
M37902FHCHP, M37902FJCGP, M37902FJCHP
★
Page 1,
DISTI NCTIVE
FEAT URES ;
Memory
M37902FCCHP, M37902FGCHP, M37902FJCHP
[M37902F8CGP, M37902F8CHP]
Flash memory (User ROM area) ......................60 Kbytes
RAM.................................................................2048 bytes
[M37902FCCGP, M37902FCCHP]
Flash memory (User ROM area) ....................120 Kbytes
RAM.................................................................4096 bytes
(Deleted)
[M37902FCCHP]
Flash memory (User ROM area) ....................120 Kbytes
RAM.................................................................4096 bytes
[M37902FECGP, M37902FECHP]
Flash memory (User ROM area) ....................184 Kbytes
RAM.................................................................6144 bytes
[M37902FGCGP, M37902FGCHP]
Flash memory (User ROM area) ....................248 Kbytes
RAM.................................................................6144 bytes
(Deleted)
[M37902FGCHP]
Flash memory (User ROM area) ....................248 Kbytes
RAM.................................................................6144 bytes
[M37902FHCGP, M37902FHCHP]
Flash memory (User ROM area) ....................370 Kbytes
RAM...............................................................12288 bytes
[M37902FJCGP, M37902FJCHP]
Flash memory (User ROM area) ....................498 Kbytes
RAM...............................................................12288 bytes
★
Page 1, Control devices for personal computer peripheral equipAPPLICATION
★
★
ment such as CD-ROM drives, DVD-ROM drives, hard
disk drives, high density FDD, printers
Control devices for office equipment such as copiers and
facsimiles
Control devices for industrial equipment such as communication and measuring instruments
[M37902FJCHP]
Flash memory (User ROM area) ....................498 Kbytes
RAM...............................................................12288 bytes
Control devices for personal computer peripheral equipment such as CD-ROM drives, DVD-ROM drives, hard
disk drives, high density FDD, printers
M37902FxCGP PIN CONFIGURATION (TOP VIEW)
Page 2,
PIN
CONFIGURATION
(Type)
Fig. 112,
Pin connection of
M3790 2FxCHP in
flash memory
Page 3,
BLOCK
DIAGRAM,
Note:
Page 4,
Chip-select
wait control
(Deleted)
P63/INT2
Page 105,
★
(Deleted)
P64/INT2
(Type)
M37902F8CHP
M37902FCCHP
M37902FECHP
M37902FGCHP
M37902FHCHP
M37902FJCHP
Note:
M37902F8C GP,M37902F8C HP
M37902FC CGP,M3790 2FCCHP
M37902FECGP,M37902FECHP
M37902FGCGP, M37902FG CHP
M37902FH CGP,M3790 2FHCHP
M37902FJC GP,M37902FJCH P
M37902FCCHP
M37902FGCHP
M37902FJCHP
Note:
Flash memory
RAM
60 Kbytes
2048 bytes
120 Kbytes
4096 bytes
184 Kbytes
6144 bytes
248 Kbytes
6144 bytes
370 Kbytes
12288 bytes
498 Kbytes
12288 bytes
Chip select area ✕ 4 (CS0–CS3). A wait number and
bus width can be set for each chip select area.
(1/11)
M37902FC CHP
M37902FGCH P
M37902FJC HP
Flash memory
RAM
120 Kbytes
4096 bytes
248 Kbytes
6144 bytes
498 Kbytes
12288 bytes
Chip select area ✕ 4 (CS0–CS3). A bus cycle type
and bus width can be set for each chip select area.
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.2
Page
★
★
Error
Page 4,
Parameter
Page 4,
Note:
★
Page 5,
Notes 1:
Operating temperature range
Correction
••••••
Note:
•••••
Note:
60 Kbytes
Flash memory M37902F8C GP,M37902F8C HP
M37902FC CGP,M3790 2FCCHP 120 Kbytes
(User ROM
M37902FECGP,M37902FECHP 184 Kbytes
area)
M37902FGCGP, M37902FG CHP 248 Kbytes
M37902FH CGP,M3790 2FHCHP 370 Kbytes
M37902FJC GP,M37902FJCH P
498 Kbytes
M37902F8C GP,M37902F8C HP
2048 bytes
RAM
M37902FC CGP,M3790 2FCCHP 4096 bytes
M37902FECGP,M37902FECHP
6144 bytes
M37902FGCGP, M37902FG CHP 6144 bytes
M37902FH CGP,M3790 2FHCHP 12288 bytes
M37902FJC GP,M37902FJCH P
12288 bytes
User ROM
area
Operating ambient temperature range
M37902F8C GP, M37902F8CH P
4 blocks ••••••
M37902FCCGP, M37902FCCHP 5 blocks ••••••
M37902FECGP, M37902FECHP 6 blocks ••••••
M37902FGCGP, M37902 FGCHP 7 blocks ••••••
Flash memory
(User ROM
area)
RAM
User ROM
area
M37902FCCHP
M37902FGCHP
M37902FJCHP
M37902FCCHP
M37902FGCHP
M37902FJCHP
M37902FC CHP
M37902FGCHP
M37902FJCHP
120 Kbytes
248 Kbytes
498 Kbytes
4096 bytes
6144 bytes
12288 bytes
5 blocks ••••••
7 blocks ••••••
11 blocks •••••
M37902FHCGP, M37902FHCHP 9 blocks ••••••
M37902FJC GP, M37902FJCHP 11 blocks •••••
★
Page 6,
P40–P47
Page 9,
MEMORY,
Line 2
★
•••••••••••••••
■ In microprocessor mode
••••••••. According to the register setting, P40–P44
also ••••••••••
•••••••••••••••
■ In microprocessor mode
••••••••. According to the register setting, P40–P43
also ••••••••••
•••••••••. The address space is 16 Mbytes from
address 016 to FFFFFF16. •••••••••
•••••••••. The address space is 16 Mbytes from
addresses 016 to FFFFFF16. •••••••••
Memory map of M37902F8CGP and M37902F8CHP
(Single-chip mode)
★
Page 9,
Fig. 1
Fig. 2. Memory map of M37902FCCGP and
M37902FCCHP (Single-chip mode)
(Deleted)
Fig. 1. Memory map of M37902FCCHP (Single-chip
mode)
00200016
00200016
00FFC016
00FFC016
00FFFF16
00FFFF16
Internal
flash memory
120 Kbytes
(User ROM area)
★
Internal
flash memory
120 Kbytes
(User ROM area)
Memory map of M37902FECGP and M37902FECHP
(Single-chip mode)
(Deleted)
Memory map of M37902FHCGP and M37902FHCHP
(Single-chip mode)
(Deleted)
(2/11)
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.3
Page
Error
★
Page 10,
Fig. 2
Correction
Fig. 4. Memory map of M37902FGCGP and
M37902FGCHP (Single-chip mode)
Fig. 2. Memory map of M37902FGCHP (Single-chip
mode)
00380016
00380016
00FFC016
00FFC016
00FFFF16
00FFFF16
Internal
flash memory
248 Kbytes
(User ROM area)
★
Page 10,
Fig. 3
Internal
flash memory
248 Kbytes
(User ROM area)
Fig. 6. Memory map of M37902FJCGP and
M37902FJCHP (Single-chip mode)
Fig. 3. Memory map of M37902FJCHP (Single-chip
mode)
00380016
00380016
00FFC016
00FFC016
00FFFF16
00FFFF16
Internal
flash memory
498 Kbytes
(User ROM area)
Page 11,
Fig. 7
★
address
0016, 0116
Internal
flash memory
498 Kbytes
(User ROM area)
00000016
00000016
00000116
00000116
Reserved area (Note)
Reserved area (Note)
00001916
Port P11 direction register
address
1916
00001916
Port 011 direction register
00001A16
00001A16
Page 12,
Fig. 8
0000A616
★
address
A616
Reserved area (Note)
(Deleted)
0000A716
address
AC16, AD16
0000AC16
Serial I/O control register
0000AC16
0000AD16
0000AD16
(3/11)
Serial I/O pin control register
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.4
Page
★
Page 18,
Table 1
Error
Correction
Temporarity stores an instruction which ••••••••.
Temporarily stores an instruction which ••••••••.
Temporarity stores data which has been ••••••••,
and external areas by the BIU or which is to be
writeen to internal memory, •••••••• .
Temporarily stores data which has been ••••••••,
and external areas by the BIU; or temporarily
stores data which is to be written to internal
memory, •••••••• .
Instruction
queue buffer
Data buffer
★
Page 18,
Fig. 11
Page 26,
Fig. 18,
Notes 1
Page 31,
Right column
Line 5
b31
b0
★
Page 36,
Fig. 25
Data buff er
Notes 1: The bus cycle type is determined by the
following bits:
••••••••••••
••••••••. Therefore, ports P0 or P4, P10, P11 function as I/O pins for the address bus, ••••••••
••••••••. Therefore, ports P0 to P4, P10, P11 function as I/O pins for the address bus, ••••••••
Pin MD0
Mode
(Note 1)
Page 35,
Fig. 24,
Note
b0
DQ
No tes 1: The number of bus cycles is determined by the following bits:
••••••••••••
Page 33,
Table 5
★
b31
Data buff er
DB
Pin MD0
Mode
Processor
mode bi ts
(Note 1)
(Note 2)
Processor mode
(Note 2)
No tes 1: While VSS •••••, bit 1 is cleared to “0”.
While VCC •••••, bit 1 is set to “1” at reset.
(Fixed to “1”.)
Notes 1: While VSS •••••, this bit’s state is cleared
to “0” at reset. While VCC •••••, this bit’s
state is set to “1” at reset. (Fixed to “1”.)
3: While VSS •••••, bit 7 is cleared to “0”.
While VCC •••••, bit 7 is set to “1” at reset.
3: While VSS •••••, this bit’s state is cleared
to “0” at reset. While VCC •••••, this bit’s
state is set to “1” at reset.
7
6
5
4
3
2
1
0
7
Processor mode regi ster 1
6
5
4
3
2
1
0
Processor mode regi ster 1
•
•
•
•
•
•
Recovery-cycle-i nsert select bit
••••
Internal ROM bus cycle select
bit (Note 6)
••••
Recovery-cycle-i nsert select bit
(Note 6)
••••
Internal ROM bus cycle select
bit (Note 7)
••••
2: After reset, this bit can be set only once. During the
software execution, be sure not to change this bit.
2: After reset, this bit’s contents can be switched only
once. During the software execution, be sure not to
switch this bit’s contents.
4: While VSS •••••, these bits are cleared to “0”. While
VCC •••••, on the other hand, these bits are set to “1”.
4: While VSS •••••, each of these bits is “0” at reset. While
VCC •••••, on the other hand, each of these bits is “1”
at reset.
5: After reset, these bits can be set to “1” only once.
Once these bits have been cleared to “0” from “1”,
they cannot be set to “1” again. (Fixed to “0”.)
5: In the memory expansion or microprocessor mode, if
this bit’s contents is switched from “1” to “0”, this bit
will be cleared to “0”. After this clearance, this bit
cannot return to “1”. If it is necessary to set this bit to
“1”, be sure to reset the microcomputer.
(4/11)
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.5
Page
★
Error
Correction
Page 36,
Fig. 25
6: The program which switches this bit’s contents must
be assigned to the internal area.
6: In the microprocessor mode, this bit is invalid.
Page 37,
Fig. 26,
bit 4
7
4
7: In the microprocessor mode, this bit is invalid.
When the internal flash memory is reprogrammed in
the CPU reprogramming mode, be sure to clear this
bit to “0”.
7
4
Pins P44–P47 pullup connectio n select bit
••••
Pins P44–P47 pullup select bit • •••
••••
Pin NMI pull up connect ion select bit
(Note 2)
••••
Pin NMI pull up select bit (Note 2)
••••
Page 39,
Table 7
A rea multiplexe d bus
address (Note 3)
★
Page 40,
Fig. 28,
CS0 control
register L;
Note
★
Page 42,
Fig. 30,
Area multiplexed bus
access (Note 3)
Notes 1: While VSS •••••, this bit is cleared to “0”.
While VCC •••••, this bit is set to “1” at
reset.
Notes 1: While VSS •••••, this bit’s state is cleared
to “0” at reset. While VCC •••••, this bit’s
state is set to “1” at reset.
5: While VSS •••••, this bit is cleared to “0”.
While VCC •••••, this bit is set to “1” at
reset. (Fixed to “1”.)
5: While VSS •••••, this bit’s state is cleared
to “0” at reset. While VCC •••••, this bit’s
state is set to “1” at reset. (Fixed to “1”.)
2
1
0
Area CSx start address register
(x = 0 to 2)
Area CSx start
address register
(x = 0 to 3)
2
1
0
When mode 0 is •••••
Area CSx start address register
(x = 0 to 2)
“0” at read.
•
•
When mode 0 is •••••
•
•
2
1
0
2
1
0
Area CS3 start address register
Area CS3 start address register
These bits determine •••••
“0” at read.
•
•
These bits determine •••••
•
•
Page 43,
Fig. 31
Start address : 4000 16
Start address : 4000 16
FFFFF16
FFFFF16
256 K
bytes
1FFFFF16
1FFFFF16
(5/11)
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.6
Page
Page 44,
Fig. 32
Error
Correction
Block size : 4 Kbytes
Addresses which can be •••••
(Address FFFFF16 is not
included; Note 1)
Block size : 8 Kbytes
Addresses which can be •••••
(Address FFFFF16 is not
included; Note 1)
Block size : 4 Kbytes
Addresses which can be •••••
(Address FFFF16 is not
included; Note 1)
Block size : 8 Kbytes
Addresses which can be •••••
(Address FFFF16 is not
included; Note 1)
016
016
016
016
800016
800016
800016
800016
E000016
E00016
F000016
F00016
(FFFFF16)
Page 45,
Fig. 33
(FFFFF16)
(FFFF16)
(FFFF16)
Block size : 8 Mbytes
Block size : 8 Mbytes
Addresses which can be •••••
(Addresses 016 and FF000016
are not included; Note 1)
Addresses which can be •••••
(Addresses 016 and FF000016
to FFFFFF16 are not
included; Note 1)
016
016
Page 45,
Fig. 33, title
Fig. 33 Area CS0/CS1/CS2 (mode 1) and area CS3
Fig. 33 Area CS0/CS1/CS2 (mode 0) and area CS3
Page 46,
Left column,
Line 2
Table 8 shows the interrupt types and the ••••••••
Table 8 shows the interrupt sources and the ••••••••
Page 46,
Table 8, title
Table 8. Interrupt types and the interrupt vector
addresses
Table 8. Interrupt sources and interrupt vector
addresses
Page 52,
Left column,
Line 5
To use these pins as timer input pins, the data direction
register •••••
To use these pins as timer input pins, the port direction
register •••••
Page 55,
Fig. 46,
bit 4
★
★
Page 59,
Left column,
Lines 14, 17,
22
Page 62,
(2) Event counter
mode [01]
Page 64,
Fig. 64
4
4
0 : Increment or decrement according to
up/down flag
1 : •••••••• ••••• ••
0 : Increment or decrement according to
up/down bit
1 : •••••••• ••••• ••
••••• timer Ai start bit •••••
••••• count start bit •••••
(Line 15)
(Line 15)
particular function select register 1 (bit 7 at address
6316) •••••
particular function select register 1 (bit 6 at address
6316) •••••
UART
1/16 divider
Clock synchronous
Clock synchronous
(External clock)
1/2 divider Clock synchronous
Transmit
control
circui t
(External clock)
UART
1/16 divider
Clock synchronous
Clock synchronous
(Internal clock)
1/2 divider Clock synchronous
(External clock)
(6/11)
Transmit
control
circui t
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.7
Page
Page 64,
Fig. 65,
bits 2 to 0,
bit 5, bit 6
Page 66,
Fig. 68,
UART0/1
transmit/receive
control register 0,
bit 6
Page 68,
Left column,
Last line
Page 70,
Fig. 71
Error
6 5
Correction
2 1 0
6 5
2 1 0
Serial I/O mode select bits
0 0 0 : Serial I/O mode is invalid. •••••••••
0 0 1 : •••••••••••••••
Serial I/O mode select bits
0 0 0 : Serial I/O is invalid. •••••••••
0 0 1 : •••••••••••••••
Even/O dd parity select bit •••••••
0 : •••••
Odd/Even parity select bit •••••••
0: •••••
Parity enable sele ct bit •••••••
0 : •••••
Parity enable bit •••••••
0: •••••
6
6
CPL
CPL
CLK polarity select bit •••••
0 : At the falling •• ••, receive data is input.
read out the RTSk output turns back to “L”. •••••••
CLK polarity select bit •••••
0 : At the falling ••••, receive data is input.
When not in transfer, pin CLK’s level
is “H”.
read out the RTSk output turns back to “L”. •••••••
■ CLK porarity select bit = 0
■ CLK porarity select bit = 1
••••
••••
•
•
•
•
■ CLK porarity select bit = 0
■ CLK porarity select bit = 1
••••
••••
•
•
★
Page 74,
Table 13
Functions
Pin P80/CTS0/RTS0 (Note 1) Pin P81/•••
CTS2
★
Page 76,
Fig. 77
•
•
P81 or CLK0
Ladder network
Functions
Pin P80/CTS0/RTS0 (Note 1) Pin P81/•••
CTS0
P81 or CLK0
Resistor ladder network
Page 77,
Left column,
Line 12
ADTRG input changes from “H” to “L” (or “L” to “H”.) ••••••
ADTRG input changes from “H” to “L” (or “L” to “H”.) ••••••
Page 77,
Left column,
Line 14
ADTRG pin is multiplexed with an analog voltage ••••••
ADTRG pin is multiplexed with an analog voltage ••••••
★
Page 77,
Right column,
Lines 5 to 6
••••••• the ladder network or not •••••••••••
••••••• the resistor ladder network or not •••••••••••
★
Page 77,
Right column,
Line 10
the ladder network can be cut off by disconnecting ladder
network •••••••
the resistor ladder network can be cut off by disconnecting resistor ladder network •••••••
★
Page 80,
Left column,
Line 10
•••••••, the corresponding pin (DA0 to DA2) outputs •••••••
•••••••, the corresponding pin (D-A0 to D-A2) outputs •••••••
(7/11)
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.8
Page
Error
Page 80,
Left column,
Line 15
Page 80,
Right column,
Line 1
The D-A output enable bit is cleared to “0” at reset.•••••••
The contents of the corresponding D-A output enable bit
and D-A register are cleared to “0” at reset.•••••••
with pin D-Ai.
with pin D-Ai.
Also, when not using the D-A converter, be sure to clear
the contents of the corresponding D-A output enable bit
and D-A register to “0”.
Page 81,
Fig. 83,
bits 1 and 0
★
Page 82,
Right column,
Lines 1 to 3
Page 86,
Fig. 91,
bits 2 to 0
Page 87,
Fig. 89,
2nd diagram
Correction
1 0
1 0
Waveform output select bits
•••••••• •••••
11 : RTP1 and RTP0 selected
When pulse mode 0 is selected:
RTP1 and RTP1
•••• ••••••• ••
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), RTP13 to RTP10 and RTP03 to RTP00
become pulse output port pins.
When the waveform output •••••••••
2 1 0
Address/Port switch select bits
0 0 0 : •••••••••
[Inside dotted-line not included]
P40/ALE, P41/φ1, P42/HLDA,
•••••••••••
Page 89,
Fig. 93,
Output (Internal peripher al devices)
Port latch
[Inside dotted-line not included]
P77/AN7/ADTRG/DA1/(INT2)
CS0 control regi ster H
Address/Port switch bits
0 0 0 : •••••••••
[Inside dotted-line not included]
P40/ALE, P41/φ1, P42/HLDA,
•••••••••••
Output
★
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), pulse output port pins are divided into two
groups; one consists of RTP13 to RTP10, RTP03, RTP02
and the other consists of RTP01 and RTP00.
When the waveform output •••••••••
2 1 0
Port latch
Page 88,
Fig. 90,
3rd diagram
Waveform output select bits
•••••••• •••••
11 : RTP1 and RTP0 selected
When pulse mode 0 is selected:
RTP1 and RTP0
•••• ••••••• ••
(8116) ••••
[Inside dotted-line included]
P77/AN7/ADTRG/DA1/(INT2)
0
0 0 0 0
CS0 control regi ster H
(8116) ••••
1
0 0 0 0
address 8116
Page 90,
Fig. 92,
A-D interrup t control register
(7016) ••••
? 0 0 0
A-D conversion interrupt control register (7016) •••
? 0 0 0
address 7016
★
Page 91,
Left column,
Lines 11, 12
•••••••, the oscillation circuit stops it’s operation and resumes the current dissipation.
•••••••, the oscillation circuit stops it’s operation, and the
current dissipation is reduced.
★
Page 91,
Left column,
Line 17
••••••• from pin XIN and output a multiplied clock.
••••••• from pin XIN and generates a multiplied clock.
Page 92,
Right column,
Lines 4 to 5
••••••• In this selection, be sure that multiplied f(XIN) does
not exceed 26 MHz. •••••••••
••••••• The PLL multiplication ratio must be set so that the
frequency of the PLL output clock (fPLL) must be in the
range from 10 MHz to 26 MHz. ••••••••
Page 92,
Right column,
Lines 10 to 11
••••• the PLL output clock (fPLL). (In other words, set bit 5
to “1”.)
••••• the PLL output clock (fPLL). (In other words, set bit 5
to “1”.) Note that, after reset, the PLL multiplication ratio
select bits are allowed to be changed only once.
(8/11)
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.9
Page
Page 92,
Table 15,
Note
Error
Correction
Note: Be sure that system clock fsys does not exceed 26
MHz. f(XIN) means the frequency of the input clock
from pin XIN (fXIN).
Note: The PLL multiplication ratio must be set so that the
frequency of the PLL output clock (fPLL) must be in
the range from 10 MHz to 26 MHz. f(XIN) means the
frequency of the input clock from pin XIN (fXIN). After
reset, the PLL multiplication ratio select bits are
allowed to be changed only once.
••••• the oscillation circuit and PLL circuit have been
restarted ••••••
••••• the oscillation circuit has been restarted ••••••
★
Page 96,
Left column,
Line 7
★
Page 98,
Right column,
Line 8
the ladder network of the A-D converter will •••••
the resistor ladder network of the A-D converter will •••••
★
Page 98,
Right column,
Line 10
pin VREF to the ladder network, and the power dissipation
•••••
pin VREF to the resistor ladder network, and the power
dissipation •••••
★
Page 101,
Fig. 106
Fig. 106. M37902FJCGP, M37902FJCHP : block configuration of internal flash memory
Fig. 106. M37902FJCHP : block configuration of internal flash memory
★
M37902F8CGP, M37902F8CHP : block configuration of
internal flash memory
(Deleted)
M37902FECGP, M37902FECHP : block configuration
of internal flash memory
(Deleted)
★
Page 102,
Fig. 107
Fig. 108. M37902FCCGP, M37902FCCHP : block configuration of internal flash memory
Fig. 107. M37902FCCHP : block configuration of internal flash memory
★
Page 102,
Fig. 108
Fig. 110. M37902FGCGP, M37902FGCHP : block configuration of internal flash memory
Fig. 108. M37902FGCHP : block configuration of internal flash memory
★
★
M37902FHCGP, M37902FHCHP : block configuration
of internal flash memory
Page 103,
Right column,
Lines 15 to 17
★
area if the user uses the flash memory serial I/O mode.
Note that, when the boot ROM area is read •••••••••
Pin connection of M37902FxCGP in flash memory
serial I/O mode
(Deleted)
area if the user uses the flash memory serial I/O mode.
Addresses FFB016 to FFBF16 are the reserved area for
the serial programmer. Therefore, when the user uses
the flash memory serial I/O mode, do not program to this
area.
Note that, when the boot ROM area is read •••••••••
(Deleted)
★
Page 106,
Right column,
After line 13
program the user ROM area.
program the user ROM area.
After reset removal, be sure not to change the status at
pins MD0 and MD1.
★
Page 106,
Fig. 114,
Notes 4
4: Valid only ••••• clear to “0”.
4: Valid only ••••• clear to “0”. This bit 3 must be controlled with bit 1 = “1”.
★
Page 107,
Left column,
Lines 16 to 20
••••• command consists of 8-bit units must be written only
to an even address; therefore, any data written to an odd
address will be invalid.
The write state ••••••
••••• command consisting of 8 bits must be written to an
even address; therefore, any command written to an odd
address will be invalid. Since the write data at the 2nd
cycle of a programming command consists of 16 bits, this
data must be written to even and odd addresses.
The write state ••••••
★
Page 107,
Right column,
After line 24
request occurrence.
request occurrence. In the CPU reprogramming mode,
be sure not to use the STP and WIT instructions.
(9/11)
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.10
Page
★
Error
Correction
Page 108,
Fig. 115
The CPU reprogramming mode select bit is set to “1”.
(Writing of “0” → Writing of “1”)
★
★
Page 108,
Software
Commands
Page 108,
Page
programming
Command
★
Page 109,
Page
programming
Command
★
★
(Lines 6, 7)
••••••• (D8–D15) is ignored.
••••••• (D8–D15) is ignored. (Except for the write data at
the 2nd cycle of a page programming command.)
(Titlle)
(Titlle)
Page Program Command (4116)
Page Programming Command (4116)
(After line 20)
(After line 20)
••••••• mode is maintained.
••••••• mode is maintained. In continuous programming,
if there is no programming error, page programming
commands can be executed with the read status register
mode kept.
(Lines 4 to 7)
(Lines 4 to 7)
•••••••, the same way as bit 7 of the status register.
Reading out the •••••••
•••••••, the same wayas bit 7 of the status register.
Before execution of the next command, be sure to verify
that bit 7 of the status register (SR.7) or the RY/BY
status bit is set to “1” (READY). During the automatic
programming operation, writing of commands and
access to the flash memory must not be performed.
Reading out the •••••••
Page 109,
(Lines 20 to 23)
(Lines 20 to 23)
•••••••, the same way as bit 7 of the status register.
Reading out the •••••••
•••••••, the same way as bit 7 of the status register.
Before execution of the next command, be sure to verify
that bit 7 of the status register (SR.7) or the RY/BY
status bit is set to “1” (READY). During the automatic
erase operation, writing of commands and access
to the flash memory must not be performed.
Reading out the •••••••
Page 111,
(Lines 9 to 11)
(Lines 9 to 11)
••••••• is also reported by a read of the status register.
When the lock bit •••••••
••••••• is also reported by a read of the status register.
During the automatic erase operation (when the RY/BY
status bit = “0” ), writing of commands and access to the
flash memory must not be performed.
When the lock bit •••••••
(After line 20)
(After line 20)
lock bit is terminated.
lock bit is terminated.
To perform erase or programming, be sure to do one of
the following.
• By executing the read lock bit status command, verify
that the lock of the target block is invalid.
• Set the lock bit invalidity select bit to “1” to invalidate
the lock.
When the block erase or programming is performed with
the lock valid, the erase status bit (SR.5) and programming status bit (SR.4) are set to “1” (terminated by error).
Page 111,
Data Protect
Function
(Block Lock)
★
(Lines 6, 7)
Block Erase
Command
Erase All
Unlocked Block
Command
★
Writing of “1” to the CPU reprogramming mode select
bit.
(Writing of “0” → Writing of “1”)
Page 114,
ABSOLUTE
MAXIMUM
RATINGS
Symbol
Pd
Topr
Parameter
Power di sspation
Operating t emperature
Ratings
300
Unit
mW
(10/11)
Symbol
Pd
Topr
Parameter
Power di sspation
Operating ambien t
temperature
Ratings
400
Unit
mW
Corrections and Supplementary Explanation for M37902FxC Datasheet (REV.B) NO.11
Page
Error
Correction
Page 114,
RECOMMENDED
OPERATING
CONDITIONS
★
★
f(XIN) External clcok input frequency (Note 2) ••••••••
f(sys)
f(fsys) System clcok frequency
System clcok frequency
••••••••
••••••••
Page 123,
Timing
Requirements
★
f(fsys) External clcok input frequency (Note 2) ••••••••
Page 131,
PACKEGE
OUTLINE
tw(harf)
External clock ••••••••
••••••
tw(half)
External clock ••••••••
(Deleted)
100P6S-A packege outline
(11/11)
••••••