STMICROELECTRONICS M41ST87WMX6TR

M41ST87Y
M41ST87W
5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC
and NVRAM Supervisor with Tamper Detection
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
5.0, 3.3, OR 3.0V OPERATING VOLTAGE
SERIAL INTERFACE SUPPORTS I2C BUS
(400kHz)
NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
AUTOMATIC SWITCH-OVER AND
DESELECT CIRCUITRY
CHOICE OF POWER-FAIL DESELECT
VOLTAGES
– M41ST87Y:
VCC = 4.75 to 5.5V;
THS Bit = '1': 4.50V ≤ VPFD ≤ 4.75V
VCC = 4.5 to 5.5V;
THS Bit = '0': 4.20V ≤ VPFD ≤ 4.50V
– M41ST87W:
VCC = 3.0 to 3.6V;
THS Bit = '1': 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7 to 3.6V;
THS Bit = '0': 2.55V ≤ VPFD ≤ 2.70V
TWO INDEPENDENT POWER-FAIL
COMPARATORS (1.25V REFERENCE)
COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY
128 BYTES OF GENERAL PURPOSE RAM
PROGRAMMABLE ALARM AND
INTERRUPT FUNCTION (VALID EVEN
DURING BATTERY BACK-UP MODE)
PROGRAMMABLE WATCHDOG TIMER
UNIQUE ELECTRONIC SERIAL NUMBER
(8-BYTE)
32kHz FREQUENCY OUTPUT AVAILABLE
UPON POWER-ON
MICROPROCESSOR POWER-ON RESET
BATTERY LOW FLAG
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (TYP)
SECURITY FEATURES
■
■
■
■
TAMPER INDICATION CIRCUITS WITH
TIMESTAMP AND RAM CLEAR
LPSRAM CLEAR FUNCTION (TPCLR)
PACKAGING INCLUDES A 28-LEAD,
EMBEDDED CRYSTAL SOIC
OSCILLATOR STOP DETECTION
Figure 1. Package
EMBEDDED Crystal
28-pin, (300mil)
SOX28 (MX)
Rev 6
March 2006
1/42
M41ST87Y, M41ST87W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3. 28-pin, 300mil SOIC (MX) Connections. . . . . . . . . . . . . . . . . . . . . .
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
......
......
......
......
......
......
......
......
......
......
......
......
.....5
.....6
.....6
.....6
.....7
.....8
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.WRITE Cycle Timing: RTC & External SRAM Control Signals . . . . . . . . . . . . . . . . . . . . 14
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tamper Detection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tamper Register Bits (Tamper 1 and Tamper 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14.Tamper Detect Connection Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Tamper Detection Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15.Tamper Detect Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16.Basic Tamper Detect Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Tamper Detection Current (Normally Closed - TCMX = '0') . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17.Tamper Detect Sampling Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18.Tamper Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19.Tamper Output Timing (with CLR1EXT or CLR2EXT = '1') . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Tamper Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20.RAM Clear Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Tamper Detection Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Internal Tamper Pull-up/down Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Avoiding Inadvertent Tampers (Normally Closed Configuration). . . . . . . . . . . . . . . . . . . . . . . 23
Figure 21.Low Pass Filter Implementation for Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/42
M41ST87Y, M41ST87W
Table 6. Calculated Cut-off Frequency for Typical Capacitance and Resistance Values . . . . . . . 23
Tamper Event Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-Down Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 23.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25.Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Full-time 32kHz Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 26.RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power-fail Comparators (1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power-fail Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
trec Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Electronic Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 11. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. trec Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 18. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3/42
M41ST87Y, M41ST87W
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 29.SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal Outline. . . . . . . . . 39
Table 19. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mechanical Data 39
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4/42
M41ST87Y, M41ST87W
SUMMARY DESCRIPTION
The M41ST87Y/W Serial TIMEKEEPER®/Controller SRAM is a low power 1280-bit, static CMOS
SRAM organized as 160 bytes by 8 bits. A built-in
32.768 kHz oscillator (internal crystal-controlled)
and 8 bytes of the SRAM (see Table 7., page 25)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 11 bytes of RAM provide calibration,
status/control of Alarm, Watchdog, Tamper, and
Square Wave functions. 8 bytes of ROM and finally 128 bytes of User RAM are also provided. Addresses and data are transferred serially via a two
line, bi-directional I2C interface. The built-in address register is incremented automatically after
each WRITE or READ data byte. The M41ST87Y/
W has a built-in power sense circuit which detects
power failures and automatically switches to the
battery supply when a power failure occurs. The
energy needed to sustain the SRAM and clock operations can be supplied by a small lithium buttoncell supply when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, Alarm interrupts,
Tamper Detection, Watchdog Timer, and programmable Square Wave output. Other features
include a Power-On Reset as well as two additional debounced inputs (RSTIN1 and RSTIN2) which
can also generate an output Reset (RST). The
eight clock address locations contain the century,
year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30 and 31
day months are made automatically.
Security Features
Two fully independent Tamper Detection Inputs allow monitoring of multiple locations within the system. Programmable bits provide both, “Normally
Open” and “Normally Closed” switch monitoring.
Time Stamping of the tamper event is automatically provided. There is also an option allowing data
stored in either internal memory (128 bytes), and/
or external memory to be cleared, protecting sensitive information in the event tampering occurs.
By embedding the 32kHz crystal in the package,
the clock is completely isolated from external tampering. An Oscillator Fail Bit (OF) is also provided
to ensure correct operation of the oscillator.
The M41ST87Y/W is supplied in a 28-pin, 300mil
SOIC package (MX) which includes an embedded
32kHz crystal.
The SOIC package is shipped in plastic anti-static
tubes or in Tape & Reel form.
The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile operation.
5/42
M41ST87Y, M41ST87W
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
ECON
Conditioned Chip Enable Output
EX
External Chip Enable
IRQ/OUT(1)
Interrupt/Out Output
(Open drain)
RST(1)
PFI1
Power Fail Input 1
IRQ/OUT(1)
PFI2
Power Fail Input 2
SQW/FT(2)
PFO1(2)
Power Fail Output 1
PFO1(2)
PFO2(2)
Power Fail Output 2
PFO2(2)
RST(1)
Reset Output (Open Drain)
VOUT
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
SCL
Serial Clock Input
SDA
Serial Data Input/Output
SQW/FT(2)
Square Wave Output/Frequency
Test
WDI
Watchdog Input
VCC
Supply Voltage
VOUT
Voltage Output
VSS
Ground
F32k(1)
32kHz Square Wave Output
(Open drain)
TP1IN
Tamper Pin 1 Input
TP2IN
Tamper Pin 2 Input
TPCLR
Tamper Pin RAM Clear
VBAT
Positive Battery Pin Input
NF(3)
No Function
NC(3)
No Connect
VBAT
SCL
ECON
SDA
EX
RSTIN1
RSTIN2
WDI
M41ST87Y
M41ST87W
PFI1
PFI2
(1)
F32k
TP1IN
TPCLR
TP2IN
VSS
AI07023
Note: 1. Open drain output
2. Programmable output (Open drain or Full-CMOS)
Figure 3. 28-pin, 300mil SOIC (MX)
Connections
NF
NF
NF
NF
NC
NC
PFO2
SQW/FT
WDI
RSTIN1
RSTIN2
PFO1
PFI2
VSS
28
1
2
27
3
26
4
25
5
24
6
23
7
22
M41ST87Y
8 M41ST87W 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
EX
IRQ/OUT
VOUT
TP2IN
PFI1
SCL
F32k
TP1IN
RST
TPCLR
SDA
ECON
VBAT
AI07025b
Note: No Function (NF) and No Connect (NC) pins should be tied
to VSS. Pins 1, 2, 3, and 4 are internally shorted together.
6/42
Note: 1. Open drain output
2. Programmable output (Open drain or Full-CMOS)
3. Should be connected to VSS.
M41ST87Y, M41ST87W
Figure 4. Block Diagram
REAL TIME CLOCK
CALENDAR
128 BYTES
USER RAM
SDA
I2C
INTERFACE
8 BYTES ROM
OFIE
RTC w/ALARM
& CALIBRATION
SCL
WATCHDOG
32KHz
OSCILLATOR
Crystal
AFE
WDS
(2)
SQUARE WAVE
TIEX
CLRX
VOUT
TAMPER
WDI
TPXIN
VCC
IRQ/OUT(1)
CLRXEXT
SQW/FT
TPCLR
VOUT
F32k(1)
VBAT
VBL
COMPARE
VSO
COMPARE
VPFD
COMPARE
BL
POR
RST(1)
RSTIN1
RSTIN2
ECON
EX
PFI1
COMPARE
PFO1(2)
COMPARE
PFO2(2)
1.25V
(Internal)
PFI2
1.25V
(Internal)
AI07026
Note: 1. Open drain output.
2. Programmable output (Open drain or Full-CMOS); if open drain option is selected and if pulled-up to supply other than VCC, this
supply must be equal to, or less than 3.0V when VCC = 0V (during battery back-up mode).
7/42
M41ST87Y, M41ST87W
Figure 5. Hardware Hookup
M41ST87Y/W
Inhibit
Unregulated
Voltage
VIN
VCC
5V
Regulator
VCC
TP1IN
TP2IN
Inhibit
VCC
3.3V
Regulator
VIN
For monitoring
of additional
voltage sources
R1
Pushbutton
Reset
R3
VOUT
VCC
ECON
E
EX
Low-Power
SRAM
SCL
WDI
SDA
RSTIN1
RST
RSTIN2
SQW/FT
PFO1
PFI1
R2
TPCLR
To RST
To LED Display
To NMI
PFO2
PFI2
VSS
R4
VBAT
IRQ/OUT
F32k
To INT
To 32kHz
AI07027
8/42
M41ST87Y, M41ST87W
OPERATING MODES
The M41ST87Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the
correct slave address (D0h). The 160 bytes contained in the device can then be accessed sequentially in the following order:
00h.
Tenths/Hundredths of a Second Register
01h.
Seconds Register
02h.
Minutes Register
03h.
Century/Hours Register
04h.
Day Register
05h.
Date Register
06h.
Month Register
07h.
Year Register
08h.
Control Register
09h.
Watchdog Register
0Ah-0Eh. Alarm Registers
0Fh.
Flag Register
10h-12h. Reserved
13h.
Square Wave
14h.
Tamper Register 1
15h.
Tamper Register 2
16h-1Dh. Serial Number (8 bytes)
1Eh-1Fh. Reserved (2 bytes)
20h-9Fh. User RAM (128 bytes)
The M41ST87Y/W clock continually monitors VCC
for an out-of-tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
VCC rises above VSO , the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches VPFD
(min) plus trec (min).
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
9/42
M41ST87Y, M41ST87W
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 7. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
10/42
M41ST87Y, M41ST87W
Figure 8. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
SR
P
AI00589
Table 2. AC Characteristics
Parameter(1)
Symbol
fSCL
SCL Clock Frequency
tBUF
Time the bus must be free before a new transmission can start
tEXPD
tF
tHD:DAT(2)
EX to ECON Propagation Delay
Min
Max
Unit
0
400
kHz
1.3
M41ST87Y
10
ns
M41ST87W
15
ns
300
ns
SDA and SCL Fall Time
0
µs
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
µs
tHD:STA
tR
Data Hold Time
µs
SDA and SCL Rise Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
11/42
M41ST87Y, M41ST87W
READ Mode
In this mode the master reads the M41ST87Y/W
slave after setting the slave address (see Figure
9., page 12). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master transmitter becomes the master receiver.
The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The
address pointer is only incremented on reception
of an Acknowledge Clock. The M41ST87Y/W
slave transmitter will now place the data byte at
address An+1 on the bus, the master receiver
reads and acknowledges the new byte and the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure
10., page 13).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41ST87Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure
11., page 13).
Figure 9. Slave Address Location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
12/42
M41ST87Y, M41ST87W
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. READ Mode Sequence
STOP
SLAVE
ADDRESS
P
AI00899
NO ACK
DATA n+X
STOP
R/W
SLAVE
ADDRESS
DATA n+X
P
NO ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 11. Alternate READ Mode Sequence
AI00895
13/42
M41ST87Y, M41ST87W
WRITE Mode
In this mode the master transmitter transmits to
the M41ST87Y/W slave receiver. Bus protocol is
shown in Figure 12., page 14. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST87Y/W slave receiver will send
an acknowledge clock to the master transmitter after it has received the slave address (see Figure
9., page 12) and again after it has received the
word address and each data byte.
STOP
SLAVE
ADDRESS
DATA n+X
AI00591
Figure 13. WRITE Cycle Timing: RTC & External SRAM Control Signals
EX
tEXPD
tEXPD
ECON
AI03663
14/42
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 12. WRITE Mode Sequence
M41ST87Y, M41ST87W
Data Retention Mode
With valid VCC applied, the M41ST87Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST87Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when VCC falls between VPFD (max) and
VPFD (min) (see Figure 28., page 38, Table
18., page 38). This is accomplished by internally
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is
within 0.2 volts of the VBAT. ECON will remain at
this level as long as VCC remains at an out-of-tolerance condition. When VCC falls below the Battery Back-up Switchover Voltage (VSO), power
input is switched from the VCC pin to the battery,
and the clock registers and external SRAM are
maintained from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100µA (for M41ST87W) or
150µA (for M41ST87Y) of current to the attached
memory with less than 0.3 volts drop under this
condition. On power up, when VCC returns to a
nominal value, write protection continues for trec
by inhibiting ECON. The RST signal also remains
active during this time (see Figure 28., page 38).
Note: Most low power SRAMs on the market today can be used with the M41ST87Y/W RTC SUPERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the
M41ST87Y/W and SRAMs to be “Don’t Care”
once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to
VCC=2.0 volts. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data retention current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST87Y/W to determine the total current requirements for data retention. The available battery capacity for the battery of your choice can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calculations, please see Application Note AN1012.
Tamper Detection Circuit
The M41ST87Y/W provides two independent input pins, the Tamper Pin 1 Input (TP1IN) and
Tamper Pin 2 Input (TP2IN), which can be used to
monitor two separate signals which can result in
the associated setting of the Tamper Bits (TB1
and/or TB2, in Flag Register 0Fh) if the Tamper
Enable Bits (TEB1 and/or TEB2) are enabled, for
the respective Tamper 1 or Tamper 2. The TP1IN
Pin or TP2 IN Pin may be set to indicate a tamper
event has occurred by either 1) closing a switch to
ground or VOUT (Normally Open), or by 2) opening
a switch that was previously closed to ground or
VOUT (Normally Closed), depending on the state
of the TCMX Bits and the TPMX Bits in the Tamper
Register (14h and/or 15h).
Tamper Register Bits (Tamper 1 and Tamper 2)
Tamper Enable Bits (TEB1 and TEB2). When
set to a logic '1,' this bit will enable the Tamper Detection Circuit. This bit must be set to '0' in order to
clear the associated Tamper Bits (TBX, in 0Fh).
Note: TEBX should be reset whenever the Tamper
Detect condition is modified.
Tamper Bits (TB1 and TB2). If the TEBX Bit is
set, and a tamper condition occurs, the TBX Bit will
be set to '1.' This bit is “Read-only” and is reset
only by setting the TEBX Bit to '0.' These bits are
located in the Flags Register 0Fh.
Tamper Interrupt Enable Bits (TIE1 and TIE2).
If this bit is set to a logic '1,' the IRQ/OUT pin will
be activated when a tamper event occurs. This
function is also valid in battery back-up if the ABE
Bit (Alarm in Battery Back-up) is also set to '1' (see
Figure 15., page 17).
Note: In order to avoid an inadvertent activation of
the IRQ/OUT pin due to a prior tamper event, the
Flag Register (0Fh) should be read prior to resetting the TEBX Bit.
15/42
M41ST87Y, M41ST87W
Tamper Connect Mode Bit (TCM1 and TCM2).
This bit indicates whether the position of the external switch selected by the user is in the Normally
or
Normally
Closed
Open
(TCMX = '1')
(TCMX = '0') position (see Figure 14., page 16 and
Figure 16., page 17).
Tamper Polarity Mode Bits (TPM1 and TPM2).
The state of this bit indicates whether the Tamper
Pin Input will be taken high (to VOUT if TPMX = '1')
or low (to VSS if TPMX = '0') during a tamper event
(see
Figure
14., page 16
and
Figure
16., page 17).
Figure 14. Tamper Detect Connection Options
TAMPER LO
(TPMX = 0)
TAMPER HI
(TPMX = 1)
I.
II.
VOUT(1)
NORMALLY
OPEN
(TCMX = 1)
TPIN
TPIN
III.
IV.
VOUT(2)
VCC
TPIN
NORMALLY
CLOSED
(TCMX = 0)
(3)
TCHI/TCLO = 1
TCHI/TCLO = 0
VOUT (Int)
1MΩ
TCHI/TCLO = 1
10MΩ
TCHI/TCLO = 0
10MΩ
1MΩ
AI07075
Note: These options are connected to those in Table 3.
Note: 1. If the CLRXEXT Bit is set, a second Tamper to VOUT (TPM2 = '1') during tCLR will not be detected.
2. If the CLRXEXT Bit is set, a second Tamper to VOUT (TPM2 = '1') will trigger automatically.
3. Optional external resistor to VCC allows the user to bypass sampling when power is “on.”
Table 3. Tamper Detection Truth Table
Option
Mode
TPMX
I
Normally Open/Tamper to GND(1)
1
0
II
Normally Open/Tamper to VOUT(1)
1
1
III
Normally Closed/Tamper to GND
0
0
IV
Normally Closed/Tamper to VOUT
0
1
Note: 1. No battery current drawn during battery back-up.
16/42
TCMX
M41ST87Y, M41ST87W
Figure 15. Tamper Detect Output Options
User
Configuration
TIE1
IRQ - Interrupt the
processor on tamper
CLR1EXT
TPCLR - Clear external
RAM on tamper
TP1
CLR1
RESET OUT
(other reset sources)
TEB1
CLR - Clear 128 bytes
internal RAM on tamper
Time stamp tamper
event (to RTC)
TIE2
TP2
CLR2EXT
TEB2
CLR2
AI07821
Figure 16. Basic Tamper Detect Options
Triggering Event
Tamper Event Output
VCC (VOUT)
TCMX, TPMX = 1,1
TIEX
TAMPER HI,
NORMALLY OPEN
IRQ - Interrupt the
processor on tamper
VCC (VOUT)
TCMX, TPMX = 0,0
User
Configuration
TAMPER LO,
NORMALLY CLOSED
TCMX, TPMX = 1,0
CLRXEXT
TPCLR - Clear external
RAM on tamper
CLRX
TAMPER LO,
NORMALLY OPEN
CLR - Clear internal
RAM on tamper
VCC (VOUT)
TCMX, TPMX
Time stamp tamper
event
TCMX, TPMX = 0,1
TAMPER HI,
NORMALLY CLOSED
AI07818
17/42
M41ST87Y, M41ST87W
Tamper Detect Sampling (TDS1 and TDS2).
This bit selects between a 1Hz sampling rate or
constant monitoring of the Tamper Input Pin(s) to
detect a tamper event when the Normally Closed
switch mode is selected. This allows the user to reduce the current drain when the TEBX Bit is enabled while the device is in battery backup (see
Table 4., page 18 and Figure 17., page 19). Sampling is disabled if the TCMX Bit is set to logic '1'
(Normally Open). In this case the state of the
TDSX Bit is a “Don’t care.”
Note: The crystal oscillator must be “On” for sampling to be enabled.
Tamper Current Hi/Tamper Current Lo (TCHI/
TCLO1 and TCHI/TCLO2). This bit selects the
strength of the internal pull-up or pull-down used
during the sampling of the Normally Closed condition. The state of the TCHI/TCLOX Bit is a “Don’t
care” for Normally Open (TCMX = '1') mode (see
Figure 18., page 19).
RAM Clear (CLR1 and CLR2). When either of
these bits and the TEBX Bit are set to a logic '1,'
the internal 128 bytes of user RAM (see Figure
15., page 17) will be cleared to all zeros in the
event of a tamper condition. The 128 bytes of user
RAM will be deselected (invalid data will be read)
until the corresponding TEBX Bit is reset to '0.'
RAM Clear External (CLR1EXT and CLR2EXT).
When either of these bits are set to a logic '1' and
the TEBX Bit is also set to logic '1,' the external
SRAM will be cleared and the RST output enabled
(see
Figure
15., page 17
and
Figure
20., page 21).
Note: The reset output resulting from a tamper
event will be the same as a reset resulting from a
power-down condition, a watchdog time-out, or a
manual reset (RSTIN1 or RSTIN2).
This is accomplished by forcing TPCLR high, which
if used to control the inhibit pin of the DC regulator
(see Figure 20., page 21) will also switch off VOUT,
depriving the external SRAM of power to the VCC
pin. VOUT will automatically be disconnected from
the battery if the tamper occurs during battery
back-up (see Figure 19., page 20). By inhibiting
the DC regulator, the user will also prevent other
inputs from sourcing current to the external SRAM,
allowing it to retain data.
The user may optionally connect an inverting
charge pump to the VCC pin of the external SRAM
(see Figure 20., page 21). Depending on the process technology used for the manufacturing of the
external SRAM, clearing the memory may require
varying durations of negative potential on the VCC
pin. This device configuration will allow the user to
program the time needed for their particular application. Control Bits CLRPW0 and CLRPW1 determine the duration TPCLR will be enabled (see
Figure 19., page 20 and Table 5., page 20).
Note: When using the inverting charge pump, the
user must also provide isolation in the form of two
additional small-signal power MOSFETs. These
will isolate the VOUT pin from both the negative
voltage generated by the charge pump during a
tamper condition, and from being pulled to ground
by the output of the charge pump when it is in shutdown mode (SHDN = logic low). The gates of both
MOSFETs should be connected to TPCLR as
shown in Figure 20., page 21. One n-channel enhancement MOSFET should be placed between
the output of the inverting charge pump and the
VOUT of the M41ST87. The other MOSFET should
be an enhancement mode p-channel, and placed
between VOUT of the M41ST87 and VCC of the external SRAM. When TPCLR goes high after a
tamper condition occurs, the n-channel MOSFET
will turn on and the p-channel will turn off. During
normal operating conditions, TPCLR will be low
and the p-channel will be on, while the n-channel
will be off.
Table 4. Tamper Detection Current (Normally Closed - TCMX = '0')
Current at 3.0V (typ)(1,2)
Unit
Continuous Monitoring / 10MΩ pull-up/-down
0.3
µA
1
Continuous Monitoring / 1MΩ pull-up/-down
3.0
µA
1
0
Sampling (1Hz) / 10MΩ pull-up/-down
0.3
nA
1
1
Sampling (1Hz) / 1MΩ pull-up/-down
3.0
nA
TDSX
TCHI/TCLOX
0
0
0
Tamper Circuit Mode
Note: 1. When calculating battery lifetime, this current should be added to IBAT current listed in Table 17., page 37.
2. Per Tamper Detect Input
18/42
M41ST87Y, M41ST87W
Figure 17. Tamper Detect Sampling Options
VCC (VOUT)
CONTINUOUS
MONITORING
TAMPER HI,
NORMALLY OPEN
VCC (VOUT)
CONTINUOUS
MONITORING
SAMPLED
MONITORING
TAMPER LO,
NORMALLY CLOSED
TDSX = 0
User
Configuration
TDSX = 1
TCMX, TPMX
CONTINUOUS
MONITORING
TAMPER LO,
NORMALLY OPEN
VCC (VOUT)
CONTINUOUS
MONITORING
SAMPLED
MONITORING
TAMPER HI,
NORMALLY CLOSED
TDSX = 0
TDSX = 1
AI07819
Figure 18. Tamper Current Options
VCC (VOUT)
CONTINUOUS
MONITORING
TAMPER HI,
NORMALLY OPEN
VCC (VOUT)
CONTINUOUS
MONITORING
TAMPER LO,
NORMALLY CLOSED
TCHI/TCLO = 1
1MΩ
TCHI/TCLO = 0
10MΩ
SAMPLED
MONITORING
TDSX = 0
User
Configuration
TDSX = 1
User Configuration
TCMX, TPMX
TPX (TP1, TP2)
CONTINUOUS
MONITORING
TAMPER LO,
NORMALLY OPEN
VCC (VOUT)
1MΩ
TCHI/TCLO = 1
TAMPER HI,
NORMALLY CLOSED
10MΩ
TCHI/TCLO = 0
User Configuration
CONTINUOUS
MONITORING
SAMPLED
MONITORING
TDSX = 0
TDSX = 1
AI07820
19/42
M41ST87Y, M41ST87W
Figure 19. Tamper Output Timing (with CLR1EXT or CLR2EXT = '1')
TPCLR
tCLRD
tCLR
trec
RST
VOUT(1)
High-Z(2)
(3)
IRQ/OUT
(4)
High-Z
ECON
Tamper
Event
(TB Bit set)
AI07083
Note: 1. If connected to a negative charge pump device, this pin must be isolated from the charge pump by using both n-channel and pchannel MOSFETs as illustrated in Figure 20., page 21.
2. If the device is in battery back-up; NOT on VCC (see RAM Clear External (CLR1EXT and CLR2EXT), page 18).
3. If TIEX = '1.'
4. If ABE = '1.'
Table 5. Tamper Detect Timing
Symbol
Parameter
CLRPW1
CLRPW0
Min
Typ
Max
Unit
tCLRD(1)
Tamper RAM Clear Ext Delay
X
X
1.0(2)
1.5
2.0
ms
0
0
1
s
0
1
4
s
1
0
8
s
1
1
16
s
tCLR
Tamper Clear Timing
Note: 1. With input capacitance = 70pF and resistance = 50Ω.
2. If the OF Bit is set, tCLRD(min) = 0.5ms.
20/42
M41ST87Y, M41ST87W
Figure 20. RAM Clear Hardware Hookup
Inverting
Charge
Pump
IN
Negative Output
(–1 x VIN)
OUT
SHDN
Inhibit
VIN
VCC
5V
Regulator
(1)
M41ST87Y/W
VCC
TPCLR
CAP+ CAP–
TP1IN
(2)
TP2IN
VOUT
VCC
SCL
ECON
E
WDI
SDA
RSTIN1
RST
RSTIN2
SQW/FT
EX
Pushbutton
Reset
PFO1
PFI1
Low-Power
SRAM
To RST
To LED Display
To NMI
PFO2
PFI2
VSS
VBAT
IRQ/OUT
F32k
To INT
To 32kHz
AI07804
Note: 1. Most inverting Charge Pumps drive OUT to Ground when device shut down is enabled (SHDN = logic low). Therefore, an n-channel
enhancement mode MOSFET should be used to isolate the OUT pin from the VOUT of the M41ST87.
2. In order to avoid turning on an on-chip parasitic diode when driving VOUT negative, a p-channel enhancement mode MOSFET
should be used to isolate the VOUT pin from the negative voltage generated by the inverting Charge Pump.
21/42
M41ST87Y, M41ST87W
Tamper Detection Operation
Sampling
The Tamper Pins are triggered based on the state
of an external switch. Two switch mode options
are available, “Normally Open” or “Normally
Closed,” based on the setting of the Tamper Connect Mode Bit (TCMX). If the selected switch mode
is Normally Open (TCMX = '1'), the Tamper Pin will
be triggered by being connected to VSS (if the
TPMX Bit is set to '0') or to VCC (if the TPMX Bit is
set to '1'), through the closing of the external
switch. When the external switch is closed, the
Tamper Bit will be immediately set, allowing the
user to determine if the device has been physically
tampered with. If the selected switch mode is Normally Closed (TCMX = '0'), the Tamper Pin will be
triggered by being pulled to VSS or to VOUT (depending on the state of the TPMX Bit), through an
internal pull-up/pull-down resistor as a result of
opening the external switch.
When a tamper event occurs, the Tamper Bits
(TB1 and/or TB2) will be immediately set if TEBX =
'1.'
If the Tamper Interrupt Enable Bit (TIEX) is set to a
'1,' the IRQ/OUT pin will also be activated. The
IRQ/OUT output is cleared by a READ of the Flags
Register (as seen in Figure 24., page 28), a reset
of the TIE Bit to '0,' or the RST output is enabled.
Note: In order to avoid an inadvertent activation of
the IRQ/OUT pin due to a prior tamper event, the
Flag Register (0Fh) should be read prior to resetting the TEBX Bit.
The Tamper Bits are “Read only” bits and are reset
only by writing the Tamper Enable Bit (TEBX) to '0.'
The Tamper Detect function operates both under
normal power, and in battery back-up. Even if the
trigger event occurs during a power-down condition, the bit will be set correctly.
As the Switch Mode Normally Closed (TCMX = '0')
requires a greater amount of current to maintain
constant monitoring, the M41ST87Y/W offers a
programmable Tamper Detect Sampling Bit
(TDSX) to reduce the current drawn on VCC or
VBAT (see Figure 17., page 19). When enabled,
the sampling frequency is once per second (1Hz),
for approximately 1ms.
When TEBX is disabled, no current will be drawn
by the Tamper Detection Circuit. After a tamper
event has been detected, no additional current will
be drawn.
Note: The oscillator must be running for Tamper
Detection to operate in the sampling mode. If the
oscillator is stopped, the Tamper Detection Circuit
will revert to constant monitoring.
Note: Sampling in the Tamper High Mode
(TPMX = '1') may be bypassed while on VCC by
connecting the TPXIN pin to VCC through an external resistor. This will allow constant monitoring
when VCC is “On” and revert to sampling when in
battery back-up (see Figure 14., page 16).
22/42
Internal Tamper Pull-up/down Current
Depending on the capacitive and resistive loading
of the Tamper Pin Input (TPXIN), the user may require more or less current from the internal pull-up/
down used when monitoring the Normally Closed
switch mode. The state of the Tamper Current Hi/
Tamper Current Low Bit (TCHI/TCLOX) determines the sizing of the internal pull-up/-down.
TCHI/TCLOX = '1' uses a 1MΩ pull-up/-down resistor, while TCHI/TCLOX = '0' uses a 10MΩ pullup/-down resistor (see Figure 18., page 19).
M41ST87Y, M41ST87W
Avoiding Inadvertent Tampers (Normally
Closed Configuration)
In some applications it may be necessary to use a
low pass filter to reduce electrical noise on the
Tamper Input pin when the TCMX Bit = 0 (Normally
Closed). This is especially true if the tamper detect
switch is located some distance (> 6”) from the
Tamper Input pin. A low pass filter can prevent unwanted, higher frequency noise from inadvertently
being detected as a tamper condition caused by
the “antenna-effect” (produced by a longer signal
wire or mesh). This low pass filter can be constructed using a series resistor (R) in conjunction
with a capacitor (C) on the Tamper Input pin.
The cut-off frequency fc is determined according to
the formula:
Figure 21. Low Pass Filter Implementation for
Noise Immunity
TPIN
To Tamper Detect Switch
R
C
AI11185
f c = 1 ⁄ ( 2 ⋅ Pi ⋅ R ⋅ C )
Table 6. Calculated Cut-off Frequency for Typical Capacitance and Resistance Values
R (Ω)
C (F)
fc
1/fc (s)
1000
1.00E-09
15.9MHz
6.28µs
1000
1.00E-06
159.2Hz
6.28ms
5000
1.00E-09
31.8kHz
31.4µs
5000
1.00E-06
31.8Hz
31.4ms
10000
1.00E-09
15.9kHz
62.8µs
10000
1.00E-06
15.9Hz
62.8ms
Tamper Event Time-Stamp
Regardless of which tamper occurs first, not only
will the appropriate Tamper Bit be set, but the
event will also be automatically time-stamped.
This is accomplished by freezing the normal update of the clock registers (00h through 07h) immediately following a tamper event. Thus, when
tampering occurs, the user may first read the time
registers to determine exactly when the tamper
event occurred, then re-enable the clock update to
the current time (and reset the Tamper Bit, TBX) by
resetting the Tamper Enable Bit (TEBX).
The time update will then resume and the clock
can be read to determine the current time. Both
Tamper Enable Bits (TEBX) must always be set to
'0' in order to read the current time.
In the event of multiple tampers, the Time-Stamp
will reflect the initial tamper event.
Note: If the TEBX Bit is set, the Tamper Event
Time-Stamp will take precedence over the Power
Down Time-Stamp (see Power-Down TimeStamp, page 24) and the HT Bit (Halt Update) will
not be set during the power-down event. If both
are needed, the Power Down Time-Stamp may be
accomplished by writing the time into the General
Purpose RAM memory space when PFO is asserted.
23/42
M41ST87Y, M41ST87W
CLOCK OPERATION
The eight byte clock register (see Table
7., page 25) is used to both set the clock and to
read the date and time from the clock, in a binary
coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained
within the first four registers.
Note: A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY Bit 0 (CB0)
and CENTURY Bit 1 (CB1). Bits D0 through D2 of
Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of
month), Month, and Years. The ninth clock register
is the Control Register (this is described in the
Clock Calibration section). Bit D7 of Register 01h
contains the STOP Bit (ST). Setting this bit to a '1'
will cause the oscillator to stop. If the device is expected to spend a significant amount of time on
the shelf, the oscillator may be stopped to reduce
current drain. When reset to a '0' the oscillator restarts within one second (typical).
Note: A WRITE to ANY location within the first
eight bytes of the clock register (00h-07h), including the OFIE Bit, CLRPW0 Bit, CLRPW1 Bit, THS
Bit, and so forth, will result in an update of the system clock and a reset of the divider chain. This
could result in a significant corruption of the current time, especially if the HT Bit (see “Power
Down Time-Stamp” section) has not been previously reset. These non-clock related bits should
be written prior to setting the clock, and remain unchanged until such time as a new clock time is also
written.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of
data during the READ.
24/42
Power-Down Time-Stamp
Upon power-up following a power failure, the Halt
Update Bit (HT) will automatically be set to a '1.'
This will prevent the clock from updating the TIMEKEEPER® registers, and will allow the user to read
the time of the power-down event.
Note: When the HT Bit is set or a tamper event occurs, the Tenths/Hundredths of a Second Register
(00h) will automatically be reset to a value of “00.”
All other date and time registers (01h - 07h) will retain the value last updated prior to the power-down
or tamper event. The internal clock remains accurate and no time is lost as a result of the zeroing of
the Tenth/Hundredths of a Second Register.
When updates are resumed (due to resetting the
HT Bit or TEB Bit), the correct time will be displayed.
Resetting the HT Bit to a '0' will allow the clock to
update the TIMEKEEPER registers with the current time.
Note: If the TEB Bit is set, the Power Down TimeStamp will be disabled, and the Tamper Event
Time-Stamp will take precedence (see Tamper
Detection Operation, page 22).
TIMEKEEPER ® Registers
The M41ST87Y/W offers 22 internal registers
which contain Clock, Control, Alarm, Watchdog,
Flag, Square Wave, and Tamper data. The Clock
registers are memory locations which contain external (user accessible) and internal copies of the
data (usually referred to as BiPORT™ TIMEKEEPER cells). The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or
clock) chain will be reset upon the completion of a
WRITE to any clock address (00h to 07h).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD format. Control, Watchdog and Square Wave
Registers store data in Binary Format.
M41ST87Y, M41ST87W
Table 7. TIMEKEEPER® Register Map
Addr
Data
D7
00h
D6
D5
D4
D3
D2
0.1 Seconds
D1
D0
Function/Range
BCD Format
0.01 Seconds
10s/100s
Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
OFIE
10 Minutes
Minutes
Minutes
00-59
03h
CB1
CB0
10 Hours
Hours (24 Hour Format)
Century/
Hours
0-1/
00-23
04h
TR
THS
CLRPW1 CLRPW0
05h
PFOD
0
10 Date
06h
0
0
07h
0
32kE
Day
01-7
Date: Day of Month
Day of Week
Date
01-31
Month
Month
01-12
Year
Year
00-99
10M
10 Years
08h
OUT
FT
S
Calibration
09h
WDS
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
ABE
Al 10M
BMB1
BMB0
Control
RB1
RB0
Alarm Month
Watchdog
Al Month
01-12
0Bh
RPT4
RPT5
AI 10 Date
Alarm Date
Al Date
01-31
0Ch
RPT3
HT
AI 10 Hour
Alarm Hour
Al Hour
00-23
0Dh
RPT2
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
0Eh
RPT1
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
0Fh
WDF
AF
0
BL
0
OF
TB1
TB2
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
SQWOD
0
0
0
SQW
14h
TEB1
TIE1
TCM1
TPM1
TDS1
TCHI/
TCLO1
CLR1EXT
CLR1
Tamper1
15h
TEB2
TIE2
TCM2
TPM2
TDS2
TCHI/
TCLO2
CLR2EXT
CLR2
Tamper2
16h-1Dh
ROM
1Eh-1Fh
Reserved
20h-9Fh
Keys: 0 = Must be set to zero
32kE = 32kHz Output Enable Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
AF = Alarm flag (Read only)
AFE = Alarm Flag Enable Bit
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
CLR (1 and 2) = RAM Clear Bits
CLR (1 and 2)EXT = RAM Clear External Bits
CLRPW0 = RAM Clear Pulse Width 0 Bit
CLRPW1 = RAM Clear Pulse Width 1 Bit
FT = Frequency Test Bit
HT = Halt Update Bit
OF = Oscillator Fail Bit
OFIE = Oscillator Fail Interrupt Enable Bit
OUT = Output level
PFOD = Power-fail Output Open Drain Bit
Serial
Number
8-Byte
2-Byte
128 User
Bytes
RB0-RB1 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency
S = Sign Bit
SQWE = Square Wave Enable
SQWOD = Square Wave Open Drain Bit
ST = Stop Bit
TB (1 and 2) = Tamper Bits (Read only)
TCHI/TCLO (1 and 2) = Tamper Current Hi/Tamper Current
Low Bits
TCM (1 and 2) = Tamper Connect Mode Bits
TDS (1 and 2) = Tamper Detect Sampling Bits
TEB (1 and 2) = Tamper Enable Bits
THS = Threshold Bit
TIE (1 and 2) = Tamper Interrupt Enable Bits
TPM (1 and 2) = Tamper Polarity Mode Bits
TR = trec Bit
WDS = Watchdog Steering Bit
WDF = Watchdog flag (Read only)
25/42
M41ST87Y, M41ST87W
Calibrating the Clock
The M41ST87Y/W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are tested not exceed ±35 ppm (parts
per million) oscillator frequency error at 25oC,
which equates to about ±1.53 minutes per month.
When the Calibration circuit is properly employed,
accuracy improves to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 22., page 27). Therefore, the
M41ST87Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure
23., page 27. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register (08h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
26/42
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST87Y/W may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEPER ® CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
SQW/FT pin. The pin will toggle at 512Hz, when
the Stop Bit (ST) is '0,' the Frequency Test Bit (FT)
is '1,' and SQWE is '0.'
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequency.
If the SQWOD Bit = '1,' the SQW/FT pin is an open
drain output which requires a pull-up resistor to
VCC for proper operation. A 500 to10k resistor is
recommended in order to control the rise time. The
FT Bit is cleared on power-down.
M41ST87Y, M41ST87W
Figure 22. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
∆F = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 23. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
27/42
M41ST87Y, M41ST87W
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be programmed to go off while the M41ST87Y/W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5–RPT1 put the alarm in the repeat mode
of operation. Table 8., page 28 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5–RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activates the IRQ/OUT pin as shown in Figure
25., page 29. To disable alarm, write '0' to the
Alarm Date Register and to RPT5–RPT1.
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm con-
dition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different address. It should also be noted that if the last address written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
The IRQ/OUT output is cleared by a READ to the
Flags Register. A subsequent READ of the Flags
Register is necessary to see that the value of the
Alarm Flag has been reset to '0.'
The IRQ/OUT pin can also be activated in the battery back-up mode. The IRQ/OUT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M41ST87Y/W was in the deselect mode
during power-up. Figure 25., page 29 illustrates
the back-up mode alarm timing.
Figure 24. Alarm Interrupt Reset Waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/OUT
AI07086
Table 8. Alarm Repeat Modes
28/42
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
M41ST87Y, M41ST87W
Figure 25. Back-Up Mode Alarm Waveform
VCC
VPFD
VSO
trec
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/OUT
HIGH-Z
HIGH-Z
AI07087
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of timeout is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds).
Note: The accuracy of the timer is within ± the selected resolution.
If the processor does not reset the timer within the
specified period, the M41ST87Y/W sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/OUT pin
when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for trec. The Watchdog register, FT, AFE, ABE
and SQWE Bits will reset to a '0' at the end of a
Watchdog time-out when the WDS Bit is set to a
'1.'
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over.
Note: The WDI pin should be tied to VSS if not
used.
In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, either a
transition of the WDI pin, or a value of 00h needs
to be written to the Watchdog Register in order to
clear the IRQ/OUT pin. This will also disable the
watchdog function until it is again programmed
correctly. A READ of the Flags Register will reset
the Watchdog Flag (Bit D7; Register 0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared.
29/42
M41ST87Y, M41ST87W
Square Wave Output
The M41ST87Y/W offers the user a programmable square wave function which is output on the
SQW/FT pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 9. Once the selection
of the SQW frequency has been completed, the
SQW/FT pin can be turned on and off under software control with the Square Wave Enable Bit
(SQWE) located in Register 0Ah.
The SQW/FT output is programmable as an Nchannel, open drain output driver, or a full-CMOS
output driver. By setting the Square Wave Open
Drain Bit (SQWOD) to a '1,' the output will be configured as an open drain (with IOL as specified in
Table 17., page 37). When SQWOD is set to '0,'
the output will be configured as full-CMOS (sink
and source current as specified in Table
17., page 37).
Note: When configured as open drain (SQWOD =
'1'), the SQW/FT pin requires an external pull-up
resistor.
Table 9. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
Full-time 32kHz Square Wave Output
The M41ST87Y/W offers the user a special 32kHz
square wave function which defaults to output on
the F32k pin (Pin 21) as long as VCC ≥ VSO, and the
oscillator is running (ST Bit = '0'). This function is
available within one second (typ) of initial powerup and can only be disabled by setting the 32kE
30/42
Bit to '0' or the ST Bit to '1.' If not used, the F32k pin
should be disconnected and allowed to float.
Note: The F32k pin is an open drain which requires
an external pull-up resistor.
M41ST87Y, M41ST87W
Power-on Reset
Reset Inputs (RSTIN1 & RSTIN2)
The M41ST87Y/W continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for trec after VCC passes VPFD(max).
The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control
rise time.
Note: A Power-on Reset will result in resetting the
following control bits to '0': OFIE, AFE, ABE,
SQWE, FT, WDS, BMB0-BMB4, RB0, RB1, TIE1,
and TIE2 (see Table 13., page 34).
The M41ST87Y/W provides two independent inputs which can generate an output reset. The
function of these resets is identical to a reset generated by a power cycle. Table 10 and Figure 26
illustrate the AC reset characteristics of this function. Pulses shorter than tR1 and tR2 will not generate a reset condition. RSTIN1 and RSTIN2 are
each internally pulled up to VCC through a 100kΩ
resistor.
Figure 26. RSTIN1 & RSTIN2 Timing Waveforms
RSTIN1
tR1
RSTIN2
tR2
Hi-Z
Hi-Z
RST
trec
trec
AI07072
Table 10. Reset AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tR1(2)
RSTIN1 Low to RST Low (min pulse width)
100
200
ns
tR2(2)
RSTIN2 Low to RSTIN2 High (min pulse width)
100
200
ns
trec(3)
RSTIN1 or RSTIN2 High to RST High
96
98(3)
ms
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Pulse widths of less than 100ns will result in no RESET (for noise immunity).
3. Programmable (see Table 12., page 33). Same function as Power-on Reset.
31/42
M41ST87Y, M41ST87W
Power-fail Comparators (1 and 2)
Two Power-Fail Inputs (PFI1 and PFI2) are compared to an internal reference voltage (1.25V). If
either PFI1 or PFI2 is less than the power-fail
threshold (VPFI), the associated Power-Fail Output
(PFO1 or PFO2) will go low. This function is intended for use as an under-voltage detector to signal a
failing power supply. Typically PFI1 and PFI2 are
connected through external voltage dividers (see
Figure 5., page 8) to either the unregulated DC input (if it is available) or the regulated output of the
VCC regulator. The voltage divider can be set up
such that the voltage at PFI1 or PFI2 falls below
VPFI several milliseconds before the regulated
VCC input to the M41ST87Y/W or the microprocessor drops below the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO1 and PFO2 go (or remain) low.
This occurs after VCC drops below VPFD(min).
When power returns, PFO1 and PFO2 are forced
high, irrespective of VPFI for the write protect time
(trec), which is the time from VPFD(max) until the inputs are recognized. At the end of this time, the
power-fail comparator is enabled and PFO1 and
PFO2 follow PFI1 and PFI2. If the comparator is
unused, PFI1 or PFI2 should be connected to VSS
and the associated PFO1 or PFO2 left unconnected.
Power-fail Outputs
The PFO1 and PFO2 outputs are programmable
as N-channel, open drain output drivers, or fullCMOS output drivers. By setting the Power-fail
Output Open Drain Bit (PFOD) to a '1,' the output
will be configured as open drain (with IOL as specified in Table 17., page 37). When PFOD is set to
'0,' the outputs will be configured as full-CMOS
(sink and source current as specified in Table
17., page 37).
Note: When configured as open drain (PFOD =
'1'), PFO1 and PFO2 will require an external pullup resistor.
Century Bits
These two bits will increment in a binary fashion at
the turn of the century, and handle leap years correctly. See Table 11., page 33 for additional explanation.
Output Driver Pin
When the TIE Bit, OFIE Bit, AFE Bit, and watchdog register are not set to generate an interrupt,
the IRQ/OUT pin becomes an output driver that re-
32/42
flects the contents of D7 of the Control Register. In
other words, when D7 (OUT Bit) is a '0,' then the
IRQ/OUT pin will be driven low. With the ABE Bit
set to '1,' the OUT pin will continue to be driven low
in battery back-up.
Note: The IRQ/OUT pin is an open drain which requires an external pull-up resistor.
Battery Low Warning
The M41ST87Y/W automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The battery may be replaced while VCC is applied to the device.
The M41ST87Y/W only monitors the battery when
a nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
trec Bit
Bit D7 of Clock Register 04h contains the trec Bit
(TR). trec refers to the automatic continuation of
the deselect time after VCC reaches VPFD. This allows for a voltage settling time before WRITEs
may again be performed to the device after a power-down condition. The trec Bit will allow the user to
set the length of this deselect time as defined by
Table 12., page 33.
M41ST87Y, M41ST87W
Electronic Serial Number
The M41ST87Y/W has a unique 8-Byte lasered,
serial number with parity. This serial number is
“Read only” and is generated such that no two devices will contain an identical number.
Oscillator Stop Detection
If the Oscillator Fail (OF) Bit is internally set to a '1,'
this indicates that the oscillator has either stopped,
or was stopped for some period of time and can be
used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator
stops. The following conditions can cause the OF
Bit to be set:
– The first time power is applied (defaults to a '1'
on power-up).
– The voltage present on VCC or battery is insufficient to support oscillation.
– The ST Bit is set to '1.'
If the Oscillator Fail Interrupt Enable Bit (OFIE) is
set to a '1,' the IRQ/OUT pin will also be activated.
The IRQ/OUT output is cleared by resetting the
OF Bit to '0,' resetting the OFIE Bit to '0,' or the
RST output is enabled (NOT by reading the Flag
Register).
The OF Bit will remain set to '1' until written to logic
'0.' The oscillator must start and have run for at
least 4 seconds before attempting to reset the OF
Bit to '0.' This function operates both under normal
power and in battery back-up. If the trigger event
occurs during a power-down condition, this bit will
be set correctly.
Note: The ABE Bit must be set to '1' for the IRQ/
OUT pin to be activated in battery back-up.
Initial Power-on Defaults
See Table 13., page 34.
Table 11. Century Bits Examples
CB0
CB1
Leap Year?
Example(1)
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
Note: 1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions
are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
Table 12. t rec Definitions
trec Bit (TR)
trec Time
STOP Bit (ST)
Units
Min
Max
0
0
96
98(1)
ms
0
1
40
200
ms
1
X
50
2000
µs
Note: 1. Default Setting
33/42
M41ST87Y, M41ST87W
Table 13. Default Values
Condition
Initial Power-up
Subsequent Power-up (with
battery back-up)(1,2)
TR
ST
OF
OFIE
HT(3)
Out
FT
AFE
0
0
1
0
1
1
0
0
UC
UC
UC
0⇑
1⇓
UC
0⇓
0⇑
ABE
SQWE
SQWOD
PFOD
WATCHDOG Register(4)
0
0
1
1
0
Subsequent Power-up (with
battery back-up)(1,2)
0⇑
0⇑
UC
UC
0⇓
Condition
32kE
THS
TEB1 and 2
TCM1 and 2
TPM1 and 2
TDS1 and 2
Initial Power-up
1(5)
0
0
0
0
0
Subsequent Power-up (with
battery back-up)(1)
UC
UC
UC
UC
UC
UC
TIE1 and 2
CLRPW0
CLRPW1
CLR1EXT
and
CLR2EXT
Condition
Initial Power-up
Condition
TCHI/TCLO1
CLR1 and 2
and 2
Initial Power-up
Subsequent Power-up (with
battery back-up)(1)
0
0
0
0
0
0
UC
UC
0⇑
UC
UC
UC
Note: All other control bits are undetermined.
Note: 1.
2.
3.
4.
5.
34/42
UC = Unchanged.
⇑ = VCC rising; ⇓ = VCC falling.
When TEBX is set to '1,' the HT Bit will not be set on power-down (Tamper Time-Stamp will have precedence).
WDS, BMB0-BMB4, RB0, RB1.
32kHz output valid only on VCC.
M41ST87Y, M41ST87W
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 14. Absolute Maximum Ratings
Symbol
TSTG
TSLD(1)
Parameter
Value
Unit
–55 to 125
°C
240
°C
–0.3 to VCC+0.3
V
M41ST87Y
–0.3 to 7.0
V
M41ST87W
–0.3 to 4.6
V
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltage
VCC
Supply Voltage
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Reflow at peak temperature of 240°C (total thermal budget not to exceed 180°C between 90 to 150 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
35/42
M41ST87Y, M41ST87W
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 15. DC and AC Measurement Conditions
Parameter
M41ST87Y
M41ST87W
VCC Supply Voltage
4.5 to 5.5V
2.7 to 3.6V
Ambient Operating Temperature
–40 to 85°C
–40 to 85°C
Load Capacitance (CL)
100pF
50pF
Input Rise and Fall Times
≤ 50ns
≤ 50ns
Input Pulse Voltages
0.2 to 0.8VCC
0.2 to 0.8VCC
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
0.3 to 0.7VCC
Note: Output High Z is defined as the point where data is no longer driven.
Figure 27. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Note: 50pF for M41ST87W.
Table 16. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input Capacitance
7
pF
Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs are deselected.
36/42
M41ST87Y, M41ST87W
Table 17. DC Characteristics
Sym
IBAT
(2)
ICC1
Parameter
Battery Current
OSC ON
Battery Current
OSC OFF
Supply Current
Supply Current
(Standby)
Input Leakage
Current
ILI(3)
Input Leakage
Current (PFI)
Output
Leakage
ILO(4) Current
VOUT Current
IOUT1(5)
(Active)
VOUT Current
IOUT2
(Battery Back-up)
ICC2
Test Condition(1)
Min
M41ST87Y
Typ
Max
500
TA = 25°C, VCC = 0V,
VBAT = 3V
0.50
mA
0V ≤ VIN ≤ VCC
±1
±1
µA
25
nA
–25
VPFI1
PFI Input Threshold
PFI Hysteresis
VPFI2
VSO
RSW
PFI Input Threshold
PFI Hysteresis
Battery Back-up
Switchover
Switch Resistance
on Tamper Pin
2
25
–25
2
0V ≤ VIN ≤ VCC
±1
±1
µA
VOUT1 > VCC – 0.3V
175
100
mA
VOUT2 > VBAT – 0.3V
100
100
µA
Battery Voltage
Power Fail Deselect
nA
1
–0.3
VPFD
50
nA
mA
Input Low Voltage
Pull-up Supply
Voltage (Open
Drain)
V
OH (Battery BackVOHB(8)
up)
Output Low Voltage
VOL
Output Low Voltage
(Open Drain)(10)
700
0.75
VIL
Output High Voltage
500
1.4
0.7VCC
VOH
700
Unit
f = 400kHz
SCL, SDA = VCC –
0.3V
Input High Voltage
(7)
M41ST87W
Typ
Max
50
VIH
VBAT
Min
2.5
IOH = –1.0mA
VCC +
0.3
0.3VCC
3.0
(6)
3.5
2.4
VCC +
0.3
0.3VCC
0.7VCC
–0.3
2.5
3.0
2.4
IRQ/OUT, RST, F32k
3.6
2.9
V
V
V
5.5
IOUT2 = –1.0µA(9)
3.5
(6)
V
2.9
V
V
IOL = 3.0mA
0.4
0.4
V
IOL = 10mA
0.4
0.4
V
THS Bit = 0
THS Bit = 1
VCC = 5V(Y)
VCC = 3V(W)
PFI Rising
VCC = 5V(Y)
VCC = 3V(W)
PFI Rising
4.20
4.50
4.35
4.60
4.50
4.75
2.55
2.80
2.62
2.88
2.70
3.00
V
V
1.225
1.250
1.275
1.225
1.250
1.275
V
20
70
20
70
mV
1.250
1.275
1.250
1.275
V
20
70
20
70
mV
1.225
2.5
1.225
2.5
500
V
500
Ω
Note: 1.
2.
3.
4.
5.
6.
7.
8.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
Measured with VOUT and ECON open. Not including Tamper Detection Current (see Table 4., page 18).
RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
Outputs Deselected.
External SRAM must match RTC SUPERVISOR chip VCC specification.
For rechargeable back-up, VBAT (max) may be considered VCC.
For PFO1 and PFO2 (if PFOD = '0'), SQW/FT (if SQWOD = '0'), and TPCLR pins (CMOS).
Conditioned output (ECON) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will reduce battery life.
9. TPCLR output can source –300µA (typ) for VBAT = 2.9V.
10. For IRQ/OUT, SQW/FT (if SQWOD = '1'), PFO1 and PFO2 (if PFOD = '1'), RST, SDA, and F32k pins (Open Drain).
37/42
M41ST87Y, M41ST87W
Figure 28. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
trec
tPD
PFO
VALID
VALID
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
ECON
AI07085
Table 18. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
tF(2)
VPFD(max) to VPFD(min) VCC Fall Time
300
µs
tFB(3)
VPFD(min) to VSS VCC Fall Time
10
µs
tPD
EX at VIH before Power Down
0
µs
tPFD
PFI to PFO Propagation Delay
15
25
µs
tR
VPFD(min) to VPFD(max) VCC Rise Time
10
µs
tRB
VSS to VPFD(min) VCC Rise Time
1
µs
trec
Power up Deselect Time
96
98(4)
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until
200µs after VCC passes VPFD(min).
3. VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. Programmable (see Table 12., page 33)
38/42
ms
M41ST87Y, M41ST87W
PACKAGE MECHANICAL INFORMATION
Figure 29. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal Outline
D
14
h x 45°
1
C
E
15
H
28
A2
A
B
ddd
A1
e
A1
α
L
SO-E
Note: Drawing is not to scale.
Table 19. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Mechanical Data
Symbol
millimeters
Typ
inches
Min
Max
A
2.44
A1
Min
Max
2.69
0.096
0.106
0.15
0.31
0.006
0.012
A2
2.29
2.39
0.090
0.094
B
0.41
0.51
0.016
0.020
C
0.20
0.31
0.008
0.012
D
17.91
18.01
0.705
0.709
7.57
7.67
–
–
H
10.16
L
ddd
Typ
0.10
E
0.004
0.298
0.302
–
–
10.52
0.400
0.414
0.51
0.81
0.020
0.032
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
39/42
M41ST87Y, M41ST87W
PART NUMBERING
Table 20. Ordering Information Scheme
Example:
M41ST
87Y
MX
6
Device Type
M41ST
Supply Voltage and Write Protect Voltage
87Y = VCC = 4.75 to 5.5V
THS Bit = '1': 4.50V ≤ VPFD ≤ 4.75V
VCC = 4.5 to 5.5V
THS Bit = '0': 4.20V ≤ VPFD ≤ 4.50V
87W = VCC = 3.0 to 3.6V;
THS Bit = '1': 2.80V ≤ VPFD ≤ 3.00V
VCC = 2.7 to 3.6V;
THS Bit = '0': 2.55V ≤ VPFD ≤ 2.70V
Package
MX(1,2) = SOX28
Temperature Range
6 = –40 to 85°C
Shipping Method
blank = Tubes
TR = Tape & Reel
Note: 1. The SOX28 package includes an embedded 32,768Hz crystal.
2. Lead-free second level interconnect and RoHS compliant (by exemption).
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
40/42
M41ST87Y, M41ST87W
REVISION HISTORY
Table 21. Document Revision History
Date
Version
Revision Details
May 2002
1.0
First issue
23Apr-03
2.0
Document promoted to Preliminary Data
10-Jul-03
2.1
Update tamper information (Figure 4, 5, 14, 15, 16; Table 17, 4, 12)
11-Sep-03
2.2
Update Electrical, Charge Pump, and Clock information (Table 17; Figure 5, 19, 20)
15-Jun-04
3.0
Reformatted; added Lead-free information; updated characteristics (Figure 3; Table 1, 14,
17, 20)
7-Sep-04
4.0
Update Maximum Ratings (Table 14)
29-Jun-05
5
28-mar-06
6
Clarify NC connections, add Inadvertent Tamper, update MX attribute (Figure 3, 21; Table
1, 6, 20)
Update to “Avoiding Inadvertent Tamper paragraph“ paragraph
41/42
M41ST87Y, M41ST87W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
42/42