STMICROELECTRONICS M48T129Y

M48T129Y
M48T129V
5.0 or 3.3V, 1 Mbit (128 Kbit x 8) TIMEKEEPER® SRAM
FEATURES SUMMARY
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INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
YEAR 2000 COMPLIANT
BCD CODED CENTURY, YEAR, MONTH,
DAY, DATE, HOURS, MINUTES, AND
SECONDS
BATTERY LOW WARNING FLAG
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
TWO WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage)
– M48T129Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– M48T129V: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE OF
POWER
SELF CONTAINED BATTERY AND
CRYSTAL IN DIP PACKAGE
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
PROGRAMMABLE ALARM OUTPUT
ACTIVE IN BATTERY BACK-UP MODE
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
SNAPHAT HOUSING (BATTERY/CRYSTAL)
IS REPLACEABLE
EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 44-PIN M48T201Y/
V AND A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT® Top to be ordered separately)
February 2005
Figure 1. 32-pin Module
32
1
PMDIP32 (PM)
Module
1/30
M48T129Y, M48T129V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Figure 5.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-pin Module Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Hookup for Equivalent Surface-mount (SMT) Solution . .
......
......
......
......
......
......
......
......
......
......
.....4
.....4
.....5
.....5
.....6
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . 8
Figure 7. Address Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. WRITE Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Alarm Repeat Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13.Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/30
M48T129Y, M48T129V
Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17.PMDIP32 – 32-pin Plastic DIP Module, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. PMDIP32 – 32-pin Plastic DIP Module, Package Mechanical Data . . . . . . . . . . . . . . . . 24
Figure 18.SOH44 – 44-lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Outline 25
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Data . . 25
Figure 19.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 26
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 26
Figure 20.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 27
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 27
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 19. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
M48T129Y, M48T129V
DESCRIPTION
The M48T129Y/V TIMEKEEPER® RAM is a
128 Kb x 8 non-volatile static RAM and real-time
clock with programmable alarms and a watchdog
timer. The special DIP package provides a fully integrated battery back-up memory and real-time
clock solution. The M48T129Y/V directly replaces
industry standard 128 Kb x 8 SRAM. It also provides the non-volatility of Flash without any requirement for special WRITE timing or limitations
on the number of WRITEs that can be performed.
For surface-mount environments ST provides an
equivalent SMT solution consisting of a 44-pin,
330mil SOIC TIMEKEEPER SUPERVISOR
(M48T201V/Y) and a 32-pin, (TSOP, 8 x 20mm)
1Mb LPSRAM.
The 44-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT® housing containing the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC package after the completion of the surface-mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel
form. The part number is “M4Txx-BR12SH1” (see
Table 18., page 28).
The 32-pin, 600mil DIP Hybrid houses a controller
chip, SRAM, quartz crystal, and a long life lithium
button cell in a single package.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
A0-A16
DQ0-DQ7
17
8
A0-A16
W
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
DQ0-DQ7
M48T129Y
M48T129V
E
RST
IRQ/FT
G
VSS
AI02260
4/30
Address Inputs
RST
Reset Output (open drain)
IRQ/FT
Interrupt / Frequency Test
Output (open drain)
VCC
Supply Voltage
VSS
Ground
M48T129Y, M48T129V
Figure 3. 32-pin Module Connections
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
30
3
29
4
28
5
27
6
7
26
8 M48T129Y 25
9 M48T129V 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
A15
IRQ/FT
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02261
Figure 4. Block Diagram
16 x 8
TIMEKEEPER
REGISTERS
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
RST
IRQ/FT
POWER
A0-A16
131,056 x 8
SRAM ARRAY
LITHIUM
CELL
DQ0-DQ7
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VCC
E
VPFD
W
G
VSS
AI02583
5/30
M48T129Y, M48T129V
Figure 5. Hardware Hookup for Equivalent Surface-mount (SMT) Solution
SNAPHAT(2)
BATTERY/CRYSTAL
A0-A16
32,768 Hz
CRYSTAL
A0-A16
VOUT
VCC
0.1µF
5V
LITHIUM
CELL
M48T201Y/V(1,2)
VCC
0.1µF
1Mb LPSRAM
A17
A18
E
ECON
W
W
G
WDI
GCON
RSTIN1
RST
RSTIN2
IRQ/FT
VSS
E
SQW
DQ0-DQ7
G
VSS
DQ0-DQ7
AI03632
Notes:For pin connections, see individual data sheet for M48T201Y/V www.st.com.
The chip enable access time of the external SRAM will be the combination of the chip enable access for the SRAM itself, plus the chip
enable propagation delay tEPD for the M48T201Y/V.
1. For 5V, M48T129Y (M48T201Y + 5V 1Mb LPSRAM). For 3.3V, M48T129V (M48T201V + 3V 1Mb LPSRAM).
2. SNAPHAT Top ordered separately.
6/30
M48T129Y, M48T129V
OPERATING MODES
Figure 4., page 5 illustrates the static memory array and the quartz controlled clock oscillator. The
clock locations contain the century, year, month,
date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year valid until 2100), 30, and 31 day months are made
automatically. The nine clock bytes (1FFFFh1FFF9h and 1FFF1h) are not the actual clock
counters, they are memory locations consisting of
BiPORT™ READ/WRITE memory cells within the
static RAM array.
The M48T129Y/V includes a clock control circuit
which updates the clock bytes with current information once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
1FFF8h is the clock control register. This byte controls user access to the clock information and also
stores the clock calibration setting.
Byte 1FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watchdog Steering Bit (WDS). Bytes 1FFF6h-1FFF2h
include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 1FFF1h contains century information. Byte 1FFF0h contains additional flag information pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T129Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
VCC is out of tolerance, the circuit write protects
the TIMEKEEPER ® register data and external
SRAM, providing data security in the midst of unpredictable system operation. As VCC falls below
Battery Back-up Switchover Voltage (VSO), the
control circuitry automatically switches to the battery, maintaining data and clock operation until
valid power is restored.
Table 2. Operating Modes
Mode
VCC
Deselect
WRITE
READ
4.5 to 5.5V
or
3.0 to 3.6V
READ
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 12., page 23 for details.
7/30
M48T129Y, M48T129V
READ Mode
The M48T129Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Address Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Address Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or Output Enable Access Time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV
VALID
A0-A16
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Figure 7. Address Controlled, READ Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
DATA VALID
AI02324
8/30
M48T129Y, M48T129V
Table 3. READ Mode AC Characteristics
Symbol
Parameter
M48T129Y
M48T129V
–70
–85
(1)
Min
Max
Min
Unit
Max
tAVAV
READ Cycle Time
tAVQV
Address Valid to Output Valid
70
85
ns
tELQV
Chip Enable Low to Output Valid
70
85
ns
tGLQV
Output Enable Low to Output Valid
40
55
ns
70
85
ns
tELQX(2)
Chip Enable Low to Output Transition
5
5
ns
tGLQX(2)
Output Enable Low to Output Transition
5
5
ns
tEHQZ(2)
Chip Enable High to Output Hi-Z
25
30
ns
tGHQZ(2)
Output Enable High to Output Hi-Z
25
30
ns
tAXQX
Address Transition to Output Transition
5
5
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
9/30
M48T129Y, M48T129V
WRITE Mode
Chip Enable or tWHAX from WRITE Enable prior to
the initiation of another READ or WRITE cycle.
Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
The M48T129Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E
or W must return high for a minimum of tEHAX from
Figure 8. WRITE Enable Controlled, WRITE AC Waveforms
tAVAV
VALID
A0-A16
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02382
Figure 9. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
VALID
A0-A16
tAVEL
tELEH
tEHAX
E
tAVWL
W
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02582
10/30
M48T129Y, M48T129V
Table 4. WRITE Mode AC Characteristics
Symbol
M48T129Y
M48T129V
–70
–85
(1)
Parameter
Min
Max
Min
Unit
Max
tAVAV
WRITE Cycle Time
70
85
ns
tAVWL
Address Valid to WRITE Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLWH
WRITE Enable Pulse Width
50
60
ns
tELEH
Chip Enable Low to Chip Enable High
55
65
ns
tWHAX
WRITE Enable High to Address Transition
5
5
ns
tEHAX
Chip Enable High to Address Transition
10
15
ns
tDVWH
Input Valid to WRITE Enable High
30
35
ns
tDVEH
Input Valid to Chip Enable High
30
35
ns
tWHDX
WRITE Enable High to Input Transition
5
5
ns
tEHDX
Chip Enable High to Input Transition
10
15
ns
tWLQZ(2,3)
WRITE Enable Low to Output Hi-Z
25
30
ns
tAVWH
Address Valid to WRITE Enable High
60
70
ns
tAVEH
Address Valid to Chip Enable High
60
70
ns
WRITE Enable High to Output Transition
5
5
ns
tWHQX(2,3)
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
11/30
M48T129Y, M48T129V
Data Retention Mode
With valid VCC applied, the M48T129Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when
VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all
inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the current addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M48T129Y/V may respond to transient noise spikes on VCC that cross
12/30
into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the
power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T129Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
tREC after VCC reaches VPFD (max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
M48T129Y, M48T129V
CLOCK OPERATIONS
TIMEKEEPER ® Registers
Setting the Clock
The M48T129Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
referred to as BiPORT TIMEKEEPER cells). The
external copies are independent of internal functions except that they are updated periodically by
the simultaneous transfer of the incremented internal copy. TIMEKEEPER and Alarm Registers
store data in BCD.
Bit D7 of the Control Register (1FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD
format (see Table 5., page 14).
Resetting the WRITE Bit to a '0' then transfers the
values of all time registers (1FFFFh-1FFF9h,
1FFF1h) to the actual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE Bit is reset, the next clock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (1FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second after the READ Bit is reset to a '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within 1FFF9h. Setting it to
a '1' stops the oscillator. When reset to a '0', the
M48T129Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
13/30
M48T129Y, M48T129V
Table 5. TIMEKEEPER® Register Map
Data
Address
D7
1FFFFh
D6
D5
D4
D3
D2
10 Years
D0
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Day of Week
Day
01-07
Hours (24 Hour Format)
Hours
00-23
1FFFEh
0
0
1FFFDh
0
0
1FFFCh
0
FT
1FFFBh
0
0
1FFFAh
0
10 Minutes
Minutes
Minutes
00-59
1FFF9h
ST
10 Seconds
Seconds
Seconds
00-59
1FFF8h
W
R
S
1FFF7h
WDS
BMB4
BMB3
BMB2
1FFF6h
AFE
0
ABE
Al 10M
1FFF5h
RPT4
RPT5
1FFF4h
RPT3
0
1FFF3h
RPT2
1FFF2h
RPT1
1FFF1h
1FFF0h
0
D1
Function/Range
BCD Format
10 Date
0
0
0
10 Hours
Calibration
BMB1
RB1
RB0
Watchdog
A Month
01-12
Al 10 Date
Alarm Date
Al Date
01-31
Al 10 Hours
Alarm Hours
A Hours
00-23
Al 10 Minutes
Alarm Minutes
A Min
00-59
Al 10 Seconds
Alarm Seconds
A Sec
00-59
100 Year
Century
00-99
1000 Year
WDF
BMB0
Control
Alarm Month
AF
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
Y = '1' or '0‘
BL = Battery Low (Read only)
14/30
10 M
0
BL
Y
Y
Y
Y
Flag
AF = Alarm Flag (Read only)
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
M48T129Y, M48T129V
Calibrating the Clock
The M48T129Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53
minutes per month (see Figure 10., page 16).
When the Calibration circuit is properly employed,
accuracy improves to better than +1/–2 ppm at
25°C. The oscillation rate of crystals changes with
temperature. The M48T129Y/V design employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Figure 11., page 16.
The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration
bits occupy the five lower order bits (D4-D0) in the
Control Register 1FFF8h. These bits can be set to
represent any value between 0 and 31 in binary
form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles.
If a binary '1' is loaded into the register, only the
first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration
register. Assuming that the oscillator is running at
exactly 32,768Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month. Figure
11., page 16 illustrates a TIMEKEEPER® calibration waveform.
Two methods are available for ascertaining how
much calibration a given M48T129Y/V may require. The first involves setting the clock, letting it
run for a month and comparing it to a known accurate reference and recording deviation over a fixed
period of time.
Calibration values, including the number of seconds lost or gained in a given period, can be found
in the application note “AN934, TIMEKEEPER
CALIBRATION.”
This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop Bit (ST, D7 of 1FFF9h) is '0,' the Frequency
Test Bit (FT, D6 of 1FFFCh) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of 1FFF6h) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 1FFF7h) is '1'
or the Watchdog Register (1FFF7h = 0) is reset.
Note: A 4 second settling time must be allowed
before reading the 512Hz output.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (WR001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT Bit is cleared on power-up.
15/30
M48T129Y, M48T129V
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
–120
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 11. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
16/30
M48T129Y, M48T129V
Setting the Alarm Clock
Registers 1FFF6h-1FFF2h contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every month, day,
hour, minute, or second. It can also be programmed to go off while the M48T129Y/V is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 6., page 17 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
Note: User must transition address (or toggle Chip
Enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date register and RPT1-5.
The IRQ/FT output is cleared by a READ to the
Flags Register as shown in Figure 12. A subsequent READ of the Flags Register is necessary to
see that the value of the Alarm Flag has been reset to '0.'
The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T129Y/V was in the deselect mode
during power-up. Figure 13., page 18 illustrates
the back-up mode alarm timing.
Figure 12. Alarm Interrupt Reset Waveform
15ns Min
ADDRESS 1FF0h
AD0-AD7
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI02581
Table 6. Alarm Repeat Mode
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Activated
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
17/30
M48T129Y, M48T129V
Figure 13. Back-up Mode Alarm Waveforms
tREC
VCC
VPFD (max)
VPFD (min)
VSO
AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI01678C
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
1FFF7h. Bits BMB4-BMB0 store a binary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is a function of the selected resolution.
If the processor does not reset the timer within the
specified period, the M48T129Y/V sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 1FFF0h). The
most significant bit of the Watchdog Register is the
Watchdog Steering Bit (WDS). When set to a '0,'
the watchdog will activate the IRQ/FT pin when
timed-out. When WDS is set to a '1,' the watchdog
will output a negative pulse on the RST pin for 40
to 200 ms. The Watchdog register and the FT Bit
will reset to a '0' at the end of a Watchdog time-out
when the WDS Bit is set to a '1.'
18/30
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI); or
2. the microprocessor can perform a WRITE of
the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
“00h” needs to be written to the Watchdog Register in order to clear the IRQ/FT pin. This will also
disable the watchdog function until it is again programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
1FFF0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
M48T129Y, M48T129V
Power-on Reset
VCC Noise And Negative Going Transients
The M48T129Y/V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC after VCC passes VPFD (max).
The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be chosen to
control the rise time.
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 14.) is
recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface-mount).
Battery Low Warning
The M48T129Y/V automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 1FFF0h, will be asserted if the battery
voltage is found to be less than approximately
2.5V.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied.
The M48T129Y/V only monitors the battery when
a nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
Figure 14. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
Initial Power-on Defaults
Upon application of power to the device, the following register bits are set to a '0' state: WDS,
BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.
AI02169
19/30
M48T129Y, M48T129V
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 7. Absolute Maximum Ratings
Symbol
TA
TSTG
TSLD(1,2,3)
Parameter
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
–0.3 to VCC +0.3
V
M48T129Y
–0.3 to 7.0
V
M48T129V
–0.3 to 4.6
V
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltages
VCC
Supply Voltage
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds). No preheat above 150°C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium
battery.
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
20/30
M48T129Y, M48T129V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 8. Operating and AC Measurement Conditions
Parameter
M48T129Y
M48T129V
Unit
4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load Capacitance (CL)
100
50
pF
Input Rise and Fall Times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 15. AC Testing Load Circuit
650Ω
DEVICE
UNDER
TEST
CL = 100pF
or 50pF
CL includes JIG capacitance
1.75V
AI01803C
Note: Excluding open drain output pins; 50pF for M48T129V.
Table 9. Capacitance
Symbol
CIN
CIO(3)
Parameter(1,2)
Min
Max
Unit
Input Capacitance
20
pF
Input / Output Capacitance
20
pF
Note: 1. Effective capacitance measured with power supply at 5V (M48T129Y) or 3.3V (M48T129V); sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
21/30
M48T129Y, M48T129V
Table 10. DC Characteristics
Symbol
Parameter
M48T129Y
M48T129V
–70
–85
(1)
Test Condition
Min
ILI(2)
Input Leakage Current
ILO(2)
Output Leakage Current
Max
Min
Unit
Max
0V ≤ VIN ≤ VCC
±2
±2
µA
0V ≤ VOUT ≤ VCC
±2
±2
µA
ICC
Supply Current
Outputs open
95
50
mA
ICC1
Supply Current
(Standby) TTL
E = VIH
8
4
mA
ICC2
Supply Current
(Standby) CMOS
E = VCC – 0.2V
4
3
mA
VIL
Input Low Voltage
–0.3
0.8
–0.3
0.4
V
VIH
Input High Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
0.4
2.4
2.2
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. Outputs deselected.
22/30
V
M48T129Y, M48T129V
Figure 16. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
INPUTS
tRB
tREC
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
RST
AI01805
Table 11. Power Down/Up AC Characteristics
Parameter(1)
Symbol
Min
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
tFB(3)
VPFD (min) to VSS VCC Fall Time
Max
Unit
300
µs
M48T129Y
10
µs
M48T129V
150
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
0
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
VPFD (max) to RST High
40
tREC
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 12. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter(1,2)
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)
Expected Data Retention Time
Min
Typ
Max
Unit
M48T129Y
4.2
4.35
4.5
V
M48T129V
2.7
2.9
3.0
V
M48T129Y
3.0
M48T129V
VPFD –100mV
10
V
YEARS
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
3. At 25°C; VCC = 0V.
23/30
M48T129Y, M48T129V
PACKAGE MECHANICAL INFORMATION
Figure 17. PMDIP32 – 32-pin Plastic DIP Module, Package Outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note: Drawing is not to scale.
Table 13. PMDIP32 – 32-pin Plastic DIP Module, Package Mechanical Data
mm
inches
Symb
Typ
24/30
Min
Max
A
9.27
A1
Typ
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
34.29
41.91
1.350
1.650
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
32
M48T129Y, M48T129V
Figure 18. SOH44 – 44-lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.46
0.014
0.018
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
44
e
CP
0.81
0.032
44
0.10
0.004
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M48T129Y, M48T129V
Figure 19. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
eA
A2
A3
A
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm
inches
Symb
Typ
Min
A
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
26/30
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M48T129Y, M48T129V
Figure 20. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
eA
A2
A3
A
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
.0335
A2
7.24
8.00
0.285
0.315
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
.0710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
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M48T129Y, M48T129V
PART NUMBERING
Table 17. Ordering Information Scheme
Example:
M48T
129Y
–70
PM
1
Device Type
M48T
Supply Voltage and Write Protect Voltage
129Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
129V = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V
Speed
–70 = 70ns (for M48T129Y)
–85 = 85ns (for M48T129V)
Package(1)
PM = PMDIP32
Temperature Range
1 = 0 to 70°C
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT ®) which is ordered separately under the part number
“M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 18. SNAPHAT Battery Table
Part Number
28/30
Description
Package
M4T28-BR12SH
Lithium Battery (48mAh) SNAPHAT
SH
M4T32-BR12SH
Lithium Battery (120mAh) SNAPHAT
SH
M48T129Y, M48T129V
REVISION HISTORY
Table 19. Revision History
Date
Version
Revision Details
April 2000
1.0
Chipset data sheet - First Issue
22-Jun-01
2.0
Reformatted; added temperature information (Table 9, 10, 3, 4, 11, 12)
01-Aug-01
2.1
Added value to AC Testing Load Circuit (Figure 15)
06-Aug-01
2.2
Fix text and table for “Setting the Alarm Clock” (Table 6)
13-Aug-01
2.3
Fix error in “Setting the Alarm Clock” text
07-Nov-01
2.4
Remove chipset option from Ordering Information (Table 17)
26-Mar-02
2.5
Replace “chipset” term with “solution,” as well as related changes throughout the
document
20-May-02
2.6
Modify reflow time and temperature footnotes (Table 7)
18-Nov-02
2.7
Modified SMT text (Figure 2, 5)
24-Oct-03
2.8
Remove references to M68Zxxx (obsolete) parts (Figure 5); corrected footnote (Table 11)
22-Feb-05
3.0
Reformatted; IR reflow, SO package updates (Table 7)
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M48T129Y, M48T129V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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