M48T58 M48T58Y 5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM FEATURES SUMMARY ■ INTEGRATED, ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY ■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS ■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS ■ FREQUENCY TEST OUTPUT FOR REAL TIME CLOCK ■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION ■ WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): – M48T58: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V – M48T58Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V SELF-CONTAINED BATTERY and CRYSTAL IN THE CAPHAT™ DIP PACKAGE ■ ■ PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT® TOP (to be Ordered Separately) ■ SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT HOUSING CONTAINING THE BATTERY and CRYSTAL ■ PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 8 Kb x 8 SRAMs Figure 1. 28-pin PCDIP, CAPHAT™ Package 28 1 PCDIP28 (PC) Battery/Crystal CAPHAT Figure 2. 28-pin SOIC Package SNAPHAT (SH) Battery/Crystal 28 1 SOH28 (MH) May 2002 1/27 M48T58, M48T58Y TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Logic Diagram (Figure 3.) . . . . . . . Signal Names (Table 1.) . . . . . . . . DIP Connections (Figure 4.) . . . . . SOIC Connections (Figure 5.) . . . . Block Diagram (Figure 6.) . . . . . . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....5 .....5 .....5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC Measurement Load Circuit (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating Modes (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ Mode AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 WRITE Enable Controlled, WRITE AC Waveform (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 WRITE Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Down/Up AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Down/Up Trip Points DC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/27 M48T58, M48T58Y CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register Map (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Crystal Accuracy Across Temperature (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock Calibration (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VCC Noise And Negative Going Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Supply Voltage Protection (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SNAPHAT Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3/27 M48T58, M48T58Y SUMMARY DESCRIPTION The M48T58/Y TIMEKEEPER® RAM is a 8Kb x 8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8Kb x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600mil DIP CAPHAT™ houses the M48T58/Y silicon with a quartz crystal and a long life lithium button cell in a single package. Figure 3. Logic Diagram The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic antistatic tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28BR12SH” (see Table 13, page 21). Table 1. Signal Names VCC A0-A12 DQ0-DQ7 13 8 Data Inputs / Outputs FT Frequency Test Output (Open Drain) E1 Chip Enable 1 E2 Chip Enable 2 G Output Enable E2 W WRITE Enable G VCC Supply Voltage VSS Ground A0-A12 DQ0-DQ7 W E1 M48T58 M48T58Y FT VSS AI01374B 4/27 Address Inputs M48T58, M48T58Y Figure 4. DIP Connections FT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 5. SOIC Connections 28 1 27 2 26 3 25 4 24 5 23 6 7 M48T58 22 8 M48T58Y 21 20 9 19 10 18 11 17 12 13 16 14 15 VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 FT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 27 2 26 3 25 4 24 5 23 6 22 7 M48T58Y 21 8 20 9 19 10 18 11 17 12 16 13 15 14 AI01375B VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 AI01376B Figure 6. Block Diagram FT OSCILLATOR AND CLOCK CHAIN 8 x 8 BiPORT SRAM ARRAY 32,768 Hz CRYSTAL A0-A12 POWER 8184 x 8 SRAM ARRAY LITHIUM CELL DQ0-DQ7 E1 VOLTAGE SENSE AND SWITCHING CIRCUITRY VCC E2 VPFD W G VSS AI01377C 5/27 M48T58, M48T58Y MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol TA TSTG TSLD(1,2) Parameter Value Unit Ambient Operating Temperature 0 to 70 °C –40 to 85 °C 260 °C Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). 2. For SO package: Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 6/27 M48T58, M48T58Y DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M48T58 M48T58Y Unit 4.75 to 5.5 4.5 to 5.5 V 0 to 70 0 to 70 °C Load Capacitance (CL) 100 100 pF Input Rise and Fall Times ≤5 ≤5 ns 0 to 3 0 to 3 V 1.5 1.5 V Max Unit Input Capacitance 10 pF Output Capacitance 10 pF Supply Voltage (VCC) Ambient Operating Temperature (TA) Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 7. AC Measurement Load Circuit 5V 1.9kΩ DEVICE UNDER TEST OUT 1kΩ CL = 100pF or 5pF CL includes JIG capacitance AI01030 Table 4. Capacitance Symbol CIN COUT(3) Parameter(1,2) Min Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs deselected. 7/27 M48T58, M48T58Y Table 5. DC Characteristics Symbol ILI ILO(2) Parameter Input Leakage Current Output Leakage Current Test Condition(1) M48T58 M48T58Y Unit Min Max Min Max 0V ≤ VIN ≤ VCC ±1 ±1 µA 0V ≤ VOUT ≤ VCC ±1 ±1 µA Outputs open 50 50 mA ICC Supply Current ICC1 Supply Current (Standby) TTL E1 = VIH E2 = VIO 3 3 mA ICC2 Supply Current (Standby) CMOS E1 = VCC – 0.2V E2 = VSS + 0.2V 3 3 mA VIL(3) Input Low Voltage –0.3 0.8 –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V VOL VOH Note: 1. 2. 3. 4. 8/27 Output Low Voltage IOL = 2.1mA 0.4 0.4 Output Low Voltage (FT)(4) IOL = 10mA 0.4 0.4 Output High Voltage IOH = –1mA 2.4 2.4 Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). Outputs deselected. Negative spikes of –1V allowed for up to 10ns once per Cycle. The FT pin is Open Drain. V V M48T58, M48T58Y OPERATION MODES As Figure 6, page 5 shows, the static memory array and the quartz controlled clock oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format (except for the century). Corrections for 28, 29 (leap year valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/write memory cells. The M48T58/Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T58/Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out-of-tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 6. Operating Modes Mode VCC Deselect Deselect WRITE READ 4.75 to 5.5V or 4.5 to 5.5V READ E1 E2 G W DQ0-DQ7 Power VIH X X X High Z Standby X VIL X X High Z Standby VIL VIH X VIL DIN Active VIL VIH VIL VIH DOUT Active VIL VIH VIH VIH High Z Active Deselect VSO to VPFD (min)(1) X X X X High Z CMOS Standby Deselect ≤ VSO(1) X X X X High Z Battery Back-up Mode Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 10, page 16 for details. 9/27 M48T58, M48T58Y READ Mode The M48T58/Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the Chip En- able Access times (tE1LQV or tE2HQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E1, E2 and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. Figure 8. READ Mode AC Waveforms tAVAV VALID A0-A12 tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ E2 tE2HQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI00962 Note: WRITE Enable (W) = High. 10/27 M48T58, M48T58Y Table 7. READ Mode AC Characteristics Parameter(1) Symbol M48T58/Y Unit Min Max tAVAV READ Cycle Time tAVQV Address Valid to Output Valid 70 ns tE1LQV Chip Enable 1 Low to Output Valid 70 ns tE2HQV Chip Enable 2 High to Output Valid 70 ns tGLQV Output Enable Low to Output Valid 35 ns 70 ns tE1LQX(2) Chip Enable 1 Low to Output Transition 5 ns tE2HQX(2) Chip Enable 2 High to Output Transition 5 ns tGLQX(2) Output Enable Low to Output Transition 5 ns tE1HQZ(2) Chip Enable 1 High to Output Hi-Z 25 ns tE2LQZ(2) Chip Enable 2 Low to Output Hi-Z 25 ns tGHQZ(2) Output Enable High to Output Hi-Z 25 ns tAXQX Address Transition to Output Transition 10 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF. 11/27 M48T58, M48T58Y WRITE Mode The M48T58/Y is in the WRITE Mode whenever W and E1 are low and E2 is high. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls. Figure 9. WRITE Enable Controlled, WRITE AC Waveform tAVAV VALID A0-A12 tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI00963 12/27 M48T58, M48T58Y Figure 10. Chip Enable Controlled, WRITE AC Waveforms tAVAV A0-A12 VALID tAVE1H tAVE1L tE1LE1H tE1HAX E1 tAVE2L tAVE2H tE2HE2L tE2LAX E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L AI00964B 13/27 M48T58, M48T58Y Table 8. WRITE Mode AC Characteristics Parameter(1) Symbol tAVAV WRITE Cycle Time tAVWL M48T58/Y Unit Min Max 70 ns Address Valid to WRITE Enable Low 0 ns tAVE1L Address Valid to Chip Enable 1 Low 0 ns tAVE2H Address Valid to Chip Enable 2 High 0 ns tWLWH WRITE Enable Pulse Width 50 ns tE1LE1H Chip Enable 1 Low to Chip Enable 1 High 55 ns tE2HE2L Chip Enable 2 High to Chip Enable 2 Low 55 ns tWHAX WRITE Enable High to Address Transition 0 ns tE1HAX Chip Enable 1 High to Address Transition 0 ns tE2LAX Chip Enable 2 Low to Address Transition 0 ns tDVWH Input Valid to WRITE Enable High 30 ns tDVE1H Input Valid to Chip Enable 1 High 30 ns tDVE2L Input Valid to Chip Enable 2 Low 30 ns tWHDX WRITE Enable High to Input Transition 5 ns tE1HDX Chip Enable 1 High to Input Transition 5 ns tE2LDX Chip Enable 2 Low to Input Transition 5 ns tWLQZ(2,3) Write Enable Low to Output Hi-Z 25 ns tAVWH Address Valid to WRITE Enable High 60 ns tAVE1H Address Valid to Chip Enable 1 High 60 ns tAVE2L Address Valid to Chip Enable 2 Low 60 ns 5 ns tWHQX(2,3) WRITE Enable High to Output Transition Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. CL = 5pF. 3. If E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state. 14/27 M48T58, M48T58Y Data Retention Mode With valid VCC applied, the M48T58/Y operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as “don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T58/Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T58/Y for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tREC (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume tREC after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012. Figure 11. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tF tR tFB tDR tPD INPUTS tRB RECOGNIZED tREC DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID (PER CONTROL INPUT) VALID (PER CONTROL INPUT) AI01168C 15/27 M48T58, M48T58Y Table 9. Power Down/Up AC Characteristics Parameter(1) Symbol Min tPD E1 or W at VIH or E2 at VIL before Power Down tF(2) VPFD (max) to VPFD (min) VCC Fall Time tFB(3) VPFD (min) to VSS VCC Fall Time Max Unit 0 µs 300 µs M48T58 10 µs M48T58Y 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs tREC VPFD (max) to Inputs Recognized 40 200 ms Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 10. Power Down/Up Trip Points DC Characteristics Symbol Parameter(1,2) VPFD Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR(3) Expected Data Retention Time Min Typ Max Unit M48T58 4.5 4.6 4.75 V M48T58Y 4.2 4.35 4.5 V 3.0 7 Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. All voltages referenced to VSS. 3. At 25°C. 16/27 V YEARS M48T58, M48T58Y CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER® registers (see Table 11) should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 1FF8h. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' Setting the Clock Bit D7 of the Control register (1FF8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER ® registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 11, page 17). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. The bits marked as '0' in Table 11, page 17 must be written to '0' to allow for normal TIMEKEEPER and RAM operation. After the WRITE Bit is reset, the next clock update will occur within one second. See the Application Note AN923 “TIMEKEEPER Rolling Into the 21st Century” for information on Century Rollover. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T58/Y is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T58/Y oscillator starts within 1 second. Table 11. Register Map Data Address D7 1FFFh D6 D5 D4 D3 10 Years 0 10 M D2 D1 D0 Function/Range BCD Format Year Year 00-99 Month Month 01-12 Date Date 01-31 Century/Day 0-1/1-7 Hours Hours 00-23 1FFEh 0 0 1FFDh BLE BL 1FFCh 0 FT 1FFBh 0 0 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W 10 Date CEB CB 10 Hours R Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit S 0 Day Calibration Control 0 = Must be set to '0' BLE = Battery Low Enable Bit BL = Battery Low Bit (Read only) CEB = Century Enable Bit CB = Century Bit Note: When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century (dependent upon the initial value set). When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to CEB. 17/27 M48T58, M48T58Y Calibrating the Clock The M48T58/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T58/Y improves to better than +1/–2 ppm at 25°C. The oscillation rate of any crystal changes with temperature (see Figure 12, page 19). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T58/Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 13, page 20. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register 1FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is 18/27 +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T58/Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of some test equipment. When the Frequency Test (FT) Bit (D6 in the Day Register) is set to a '1,' and D7 of the Seconds Register is a '0' (Oscillator Running), The Frequency Test (Pin 1) will toggle at 512Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the Calibration Byte for correction. The Frequency Test pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10kΩ resistor is recommended in order to control the rise time. For more information on calibration, see Application Note AN934, “TIMEKEEPER® Calibration.” M48T58, M48T58Y Battery Low Flag The M48T58/Y automatically performs periodic battery voltage monitoring upon power-up and at factory-programmed time intervals of 24 hours (at day rollover) as long as the device is powered and the oscillator is running. The Battery Low flag (BL), Bit D6 of the flags Register 1FFDh, will be asserted high if the internal or SNAPHAT® battery is found to be less than approximately 2.5V and the Battery Low Enable (BLE) Bit has been previously set to '1.' The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery voltage is below 2.5V (approximately), which may be insufficient to maintain data integrity. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data has not been compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, it is recommended that the battery be replaced. The SNAPHAT top may be replaced while VCC is applied to the device. Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. Note: Battery monitoring is a useful technique only when performed periodically. The M48T58/Y only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. Century Bit Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Note: The WRITE Bit must be set in order to write to the CENTURY Bit. Figure 12. Crystal Accuracy Across Temperature ppm 20 0 -20 -40 ∆F = -0.038 ppm (T - T )2 ± 10% 0 F C2 -60 T0 = 25 °C -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C AI02124 19/27 M48T58, M48T58Y Figure 13. Clock Calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A bypass capacitor value of 0.1µF (as shown in Figure 14) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. 20/27 Figure 14. Supply Voltage Protection VCC VCC 0.1µF DEVICE VSS AI02169 M48T58, M48T58Y PART NUMBERING Table 12. Ordering Information Scheme Example: M48T 58 –70 MH 1 TR Device Type M48T Supply Voltage and Write Protect Voltage 58(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 58Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Speed –70 = 70ns Package PC = PCDIP28 MH(2) = SOH28 Temperature Range 1 = 0 to 70°C Shipping Method for SOIC blank = Tubes TR = Tape & Reel Note: 1. The M48T58 part is offered with the PCDIP28 (e.g., CAPHAT™) package only. 2. The SOIC package (SOH28) requires the battery package (SNAPHAT ®) which is ordered separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form. Caution: Do not place the SNAPHAT battery package “M4TXX-BR00SH” in conductive foam as it will drain the lithium button-cell battery. For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 13. SNAPHAT Battery Table Part Number Description Package M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH 21/27 M48T58, M48T58Y PACKAGE MECHANICAL INFORMATION Figure 15. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline A2 A1 B1 B A L C e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 14. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data mm inches Symb Typ 22/27 Min Max A 8.89 A1 Typ Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 28 M48T58, M48T58Y Figure 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 15. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 e CP 1.27 0.050 28 0.10 0.004 23/27 M48T58, M48T58Y Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline A1 eA A2 A A3 B L eB D E SHTK-A Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data mm inches Symb Typ Min A Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 24/27 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48T58, M48T58Y Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline A1 eA A2 A A3 B L eB D E SHTK-A Note: Drawing is not to scale. Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data mm inches Symb Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 25/27 M48T58, M48T58Y REVISION HISTORY Table 18. Document Revision History Date Revision Details July 1999 First Issue 07/27/00 Century Bit and Battery Low Flag Paragraphs added Power Down/Up AC Characteristics Table and Waveforms changed (Table 9, Figure 11) 06/04/01 Reformatted; temperature information added (Tables 5, 7, 8, 9, 10) 07/31/01 Formatting changes from recent document review findings 05/20/02 Modify reflow time and temperature footnotes (Table 2) 26/27 M48T58, M48T58Y Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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