M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS LOW POWER DISSIPATION: 0.5mW POWER DOWN 70mW OPERATING EXCELLENT POWER SUPPLY REJECTION DESCRIPTION The M5913 is fully integrated PCM (pulse code modulation) codecs and transmit/receive filter using CMOS silicon gate technology. The primary applications for the M5913 are telephone systems : - Switching - M5913-Digital PBX’s and Central DIP 20 ORDERING NUMBER: M5913B1 Office Switching Systems - Concentration - M5913 Subscriber Carrier and Concentrators. The wide dynamic range (78dB) and the minimal conversion time make it ideal products for other applications such as: - Voice Store and Forward - Secure Communications Systems - Digital Echo Cancellers - Satellite Earth Stations. BLOCK DIAGRAM December 1993 1/17 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M5913 ABSOLUTE MAXIMUM RATINGS Symbol VCC Value Unit With Respect GRDD, GRDA = 0V Parameter – 0.6 to 7 V With Respect GRDD, GRDA = 0V - 0.6 to – 7 V GRDD, GRDA In Such Case : 0 ≤ VCC ≤ + 7V, – 7V ≤ VBB ≤ 0V ± 0.3 V VI/O Analog Inputs, Analog Outputs and Digital Inputs VBB – 0.3 ≤ VIN/VOUT ≤ VCC + 0.3 V VBB VO DIG Digital Outputs Ptot Total Power Dissipation Tstg Storage Temperature Range GRDD – 0.3 ≤ VOUT ≤ VCC + 0.3 V 1 W -65 to 150 °C PIN CONNECTION (Top view) PIN NAMES Symbol VBB PWRO+, PWRO- Power Amplifier Outputs GSR Gain Setting Input for receive Channel PDN CLKSEL Symbol Parameter GSX Gain Control VFXI-, VFXI+ Analog Inputs GRDA Analog Ground Power Pown Select NC No Connected Master Clock Select SIG X Transmit Digital Signaling Input LOOP Analog Loop Back ASEL µ or A-law Select SIG R Signaling Bit Output DCLKR Receive Data Rate Clock TSX DCLKX Digital Output - Timeslot Strobe Transmit Data Rate Clock DR Receive Channel Input DX Transmit (Digital) Output FSR Receive Frame Synchronization Clock FSX Transmit Frame Synchronization Clock GRDD VCC 2/17 Parameter Power (-5V) Digital Ground CLKX Transmit Master Clock Power (+5V) CLKR Receive Master Clock M5913 PIN DESCRIPTION Symbol VBB Function Most Negative Supply. Input voltage is -5 volts ±5%. PWRO+ Non-inverting Output of Power Amplifier. Can drive transformer hybrids or high impedance loads directly in either a differential or single ended configuration. PWRO - Inverting Output of Power Amplifier. Functionally identical and complementary to PWRO+. GSR Input to the gain Setting Network on the Output Power Amplifier, Transmission level can be adjusted over a 12dB range depending on the voltage at GSR. PDN Power Down Select. When PDN is TTL high, the device is active.When low, the device is powered down. CLKSEL input which must be pinstrapped to reflect the master clock frequency at CLKX, CLKR. CLKSEL = VBB 2.048MHz CLKSEL = GRDD 1.544MHz CLKSEL = VCC 1.536MHz LOOP Analog Loopback. When this pin is TTL high, the receive output (PWRO+) is internally connected to VFXI+, GSR is internally connected to PWRO-, and VFXI- is internally connected to GSX. A 0dBm0 digital signal input at DR is returned as a +3dBm0 digital signal output at DX. SIGR Signalling Bit Output, Receive Channel. In fixed data rate mode. SIGR outputs the logical state of the eighth bit of the PCM word in the most recent signaling frame. DCLKR Selects the fixed or variable data rate mode. When DCLKR is connected to VBB, the fixed data rate mode is selected. When DCLKR is not connected to VBB, the device operates in the variable data rate mode. In this mode DCLKR becomes the receive data clock wich operates at TTL levels from 64kB to 4.096MB data rates DR Receive PCM Input. PCM data is clocked in on this lead on eight consecutive negative transitions of the receive data clock: CLKR in the fixed data rate mode and DCLKR in variable data rate mode. FSR 8kHz frame synchronization clock input/timeslot enable, receive channel. A multifunction input which in fixed data rate mode distinguishes between signaling and non-signaling frames by means of a double or single wide pulse respectively. In variable data rate mode this signal must remain high for the entire length of the timeslot. The receive channel enters the standby state whenever FSR is TTL low for 30 miliseconds GRDD Digital Ground for all Internal Logic Circuits. Not internally tied to GRDA. CLKR Receive master and data clock for the fixed data rate mode; receive master clock only in variable data rate mode. CLKX Transmit master and data clock for the fixed data rate mode; transmit master clock only in variable data rate mode. FSX 8kHz frame synchronization clock input/timeslot enable, transmit channel. Operates independently but in an analogous manner to FSR. The transmit channel enters the standby state whenever FSX is TTL low for 30 milliseconds. DX Transmit PCM Output. PCM data is clocked out on this lead on eight consecutive positive transitions of the transmit data clock : CLK in fixed data rate mode and DCLKX in variable data rate mode. TSX/DCLKX Transmit channel timeslot strobe (output) or data clock (input) for the transmit channel. In fixed data rate mode, this pin becomes the transmit data clock which operates at TTL levels from 64kB to 4.096MB data rates. SIG X/ASEL A dual purpose selects µ-law and pin. When connected to VBB. A law operation is selected. When it is not connected to VBB pin is a TTL level input for signaling operation. This input is transmitted as the eighth bit of the PCM word during signaling frames on the DX lead. NC Not Connected. GRDA Analog ground return for all internal voice circuits. Not internally connected to GRDD. VFXI+ Non inverting analog input to uncommitted transmit operational amplifier. VFXI- Inverting analog input to uncommitted transmit operational amplifier. GSX Output terminal of on-chip uncommitted op amp. Internally, this is the voice signal input to the transmit filter. VCC Most positive supply ; input voltage is + 5 volts ±5% 3/17 M5913 FUNCTIONAL DESCRIPTION The M5913 provides the analog-to-digital and the digital-to-analog conversion and the transmit and receive filtering necessary to interface a full duplex (4 wires) voice telephone circuit with the PCM highway of a time division multiplexed (TDM) system. It is intended to be used at the analog termination of a PCM line. The following major functions are provided : Bandpass filtering of the analog signals prior to encoding and after decoding Encoding and decoding of voice and call progress information Encoding and decoding of the signaling and supervision information GENERAL OPERATION System Reliability Features The combo-chip can be powered up by pulsing FSX and/or FSR while a TTL high voltage is applied to PDN, provided that all clocks and supplies are connected. The M5913 has internal resets on power up (or when VBB or VCC are re-applied) in order to ensure validity of the digital outputs and thereby maintain integrity of the PCM highway. On the transmit channel, digital outputs DX and TS X are held in a high impedance state for approximately four frames (500µs) after power up or application of VBB or VCC. After this delay, DX and TSX will be functional and will occur in the proper timeslot. The analog circuits on the transmit side require approximately 40 milliseconds to reach their equilibrium value due to the autozero circuit setting time. Thus, valid digital information, such as for on/off hook detection, is available almost immediately, while analog information is available after some delay. On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power up or application of VBB or VCC, SIGR will remain low thereafter until it is updated by a signaling frame. To further enhance system reliability, TS X and DX will be placed in a high impedance state approximately 20µs after an interruption of CLKX. Simi- larly SIGR will be held low approximately 20µs after an interruption of CLKR. These interruptions could possibly occur with some kind of fault condition. Power Down And Standby Modes To minimize power consumption, two power down modes are provided in which most M5913 functions are disabled. Only the power down, clock, and frame sync buffers, which are required to power up the device, are enabled in these modes. As shown in table 1, the digital outputs on the appropriate channels are placed in a high impedance state until the device returns to the active mode. The Power Down mode utilizes an external control signal to the PDN pin. In this mode, power consumption is reduced to an average of 0.5mW. The device is active when the signal is high and inactive when it is low. In the absence of any signal, the PDN pin floats to TTL high allowing the device to remain active continuously. The Standby mode leaves the user an option of powering either channel down separately or powering the entire down by selectively removing FSX and/or FSR. With both channels in the standby state, power consumption is reduced to an average of 1mW. If transmit only operation is desired, FSX should be applied to the device while FSR is held low. Similarly, if receive only operation is desired, FSR should be applied while FSX is held low. Fixed Data Rate Mode Fixed data rate timing, is selected by connecting DCLKR to VBB. It employs master clock CLKX, and CLKR, frame synchronization clocks FSX and FSR , and output TS X. CLKX, and CLKR, serve both as the master clock to operate the codec and filter sections and bit clocks to clock the data in and out from the PCM highway. FSX and FSR are 8kHz inputs which set the sampling frequency and distinguish between signaling and non-signaling frames by thir pulse width. A frame synchronization pulse which is one master clock wide designates a non-signaling frame, while a double wide sync pulse enables Table 1: Power Down Methods Device Status Power Down Methods Digital Outputs Status Power Down Mode PDN = TTL low TSX and DX are placed in a high impedance state and SIG R is placed in a TTL low state within 10µs. Stand-by Mode FSX and FSR are TTL low TSX and DX are placed in a high impedance state and SIG R is placed in a TTL low state 30ms after FSX and FSR are removed. Only transmit is on stand-by FSX is TTL low TSX and DX are placed in a high impedance state within 30ms. Only receive is on stand-by FSR is TTL low SIG R is placed in a TTL low state within 30ms. 4/17 M5913 the signaling function. TSX is a timeslot strobe/buffer enable output which gates the PCM word onto the PCM highway when an external buffer is used to drive the line. Data is transmitted on the highway at DX on the first eight positive transitions of CLKX following the rising edge of FSX. Similarly, on the receive side, data is received on the first eight falling edges of CLKR. The frequency of CLKX and CLKR is selected by the CLKSEL pin to be either 1.536, 1.544 or 2.048MHz. No other frequency of operation is allowed in the fixed data rate mode. Variable Data Rate Mode Variable data rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather than to VBB. It employes master clocks CLKX and CLKR, bit clocks DCLKR and DCLKX and frame synchronization clocks FSR and FSX. Variable data rate timing allows for a flexible data frequency. It provides the ability to vary the frequency of the bit clocks, from 64kHz to 4096MHz. Master clocks inputs are still restricted to 1.536, 1.544, or 2.048MHz. In this mode, DCLKR and DCLKX become the data clocks for the receive and transmit PCM highways. While FSX is high, PCM data from DX is transmitted onto the highway on the next eight consecutive positive transitions of DCLKX. Similarly, while FSR is high, each PCM bit from the highway is received by D R on the next eight consecutive negative transitions of DCLKR. On the transmit side, the PCM word will be repeated in all remaining timeslots in the 125µs frame as long as DCLKX is pulsed and FSX is held high. This feature allows the PCM word to be transmitted to the PCM highway more than once per frame, if desired, and is only available in the variable data rate mode. Conversely, signaling is only allowed in the fixed data rate mode since the variable mode provides no means with which to specify a signaling frame. Precision Voltage References No external components are required with the combochip to provide the voltage reference function. Voltage references are generated on-chip and are calibrated during the manufacturing process. The technique use the bandgap principle to derive a temperature and bias stable reference voltage. These references determine the gain and dynamic range characteristics of the device. Separate references are supplied to the transmit and receive sections. Transmit and receive section are trimmed independently in the filter stages to a final precision value. With this method the combochip can achieve manufacturing tolerances of typically ± 0.04dB in absolute gain for each half channel, providing the user a significant margin for error in other board components. Conversion Laws The M5913 is designed to operate in both µ-law and A-law systems. The user can select either conversion law according to the voltage present on the SIGX/ASEL pin . In each case the coder and decoder process a companded 8-bit PCM word following CCITT recommandation G.711 for µ-law and A-law conversion. If A-law operation is desired, SIGX should be tied to VBB. Thus, signaling is not allowed during A-law operation. If µ = 255-law operation is selected, then SIGX is a TTL level input which modifies the LSB on the PCM output in signaling frames TRANSMIT OPERATION Transmit Filter The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational amplifier. This operational amplifier has a common mode range of 2.17V, a maximum DC offset of 25mV, a minimum voltage gain of 5000, and a unity gain bandwidth of typically 1MHz. Gain of up to 20dB can be set without degrading the performance of the filter. The load impedance to ground (GRDA) at the amplifier output (GSX) must be greater than 10kΩ in parallel high less than 50pF. The input signal on lead VFXI+ can be either AC or DC coupled. The input op amp can also be used in the inverting mode or differential amplifier mode (see figure 3). A low pass anti-aliasing section is included onchip. This section typically provides 35dB attenuation at the sampling frequency. No external components are required to provide the necessary anti-aliasing function for the switched capacitor section of the transmit filter. The passband section provides flatness and stopband attenuation which fulfills the AT&T D3/D4 channel bank transmission specification and CCITT recommendation G.712. The M5913 specifications meet or exceed digital class 5 central office switching systems requirements. The transmit filter transfer characteristics and specifications will be within the limits shown the relative table. A high pass section configuration was chosen to reject low frequency noise from 50 and 60Hz power lines, 17Hz European electric railroads, ringing frequencies and their harmonics, and other low frequency noise. Even though there is high rejection at these frequencies, the sharpness of the band edge gives low attenuation at 200Hz. This feature allows the use of low-cost transformer hybrids without external components. 5/17 M5913 Figure 3: Transmit Filter Gain Adjustment. an internal sample and hold capacitor. This sample is then transferred to the receive filter. Receive Filter The receive section of the filter provides passband flatness and stopband rejection which fulfills both the AT&T D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the (sin X)/X response of such decoders. The receive filter characteristics and specifications are shown in the relative table. Encoding The encoder internally samples the output of the transmit filter and holds each sample on an internal sample and hold capacitor. The encoder then performs an analog to digital conversion on a switched capacitor array. Digital data representing the sample is transmitted on the first eight data clock bits of the next frame. An on-chip autozero circuit corrects for DC-offset on the input signal to the encoder. This autozero circuit uses the sign bit averaging technique. In this way, all DC offset is removed from the encoder input waveform. RECEIVE OPERATION Decoding The PCM word at the DR lead is serially fetched on the first eight data clock bits of the frame. A D/A conversion is performed on the digital word and the corresponding analog sample is held on Figure 4: Gain Setting Configuration. 6/17 Receive Output Power Amplifiers A balanced output amplifier is provided in order to allow maximum flexibility in output configuration. Either of the two outputs can be used single ended (referenced to GRDA) to drive single ended loads. Alternatively, the differential output will drive a bridged load directly. The output stage is capable of driving loads as low as 300 ohms single ended to a level of 12dBm or 600 ohms differentially to a level of 15dBm. The receive channel transmission level may be adjusted between specified limits by manipulation of the GSR input. GSR is internally connected to an analog gain setting network. When GSR is strapped to PWRO–, the receive level is minimized; when it is tied to PWRO+, the level is minimized. The output transmission level interpolates between 0 and -12dB as GSR is interpolated (with potentiometer) between PWRO- and PWRO+. The use of the output gain set is illustrated in figure 4. Transmission levels are specified relative to the receive channel output under digital milliwatt conditions, that is, when the digital input at DR is the eight-code sequence specified in CCITT recommendation G.711. M5913 OUTPUT GAIN SET: DESIGN CONSIDERATIONS (refer to figure 4) PWRO+ and PWRO– are low impedance complementary outputs. The voltages at the nodes are: VO at PWRO+ VO at PWRO VO = VO+ VO– (total differential response) R1 and R2 are a gain setting resistor network with the center tap connected to the GSR input. A value greater than 10KΩ and less than 100KΩ for R1 + R2 is recommended because: a) The parallel combination of R1 + R2 and RL sets the total loading. b) The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant which has to be minimized to avoid inaccuracies. If VA represents the output voltage without any gain setting network connected, you can have: VO = AVA 1 + (R1 / R2) where A = 4 + (R1 / R2) For design purposes, a useful form is R1/R2 as a function of A. 4A – 1 R1 / R2 = 1 –A (allowable values for A are those which make R1/R2 positive) Examples are: If A = 1 (maximum output), then R1/R2 = ∞ or V(GSR) = VO; i.e., GSR is tied to PWRO+ If A = 1/2. then R1/R2 = 2 If A = 1/4 (minimum output) then R1/R2 = 0 or V(GSR ) = VO+; i.e., GSR is tied to PWRO+ DC CHARACTERISTICS (Tamb = 0 to 70oC, VCC = +5V ± 5%, VBB = – 5V ± 5%, GRDA = 0V,unless otherwise specified) Typical values are for Tamb = 25oC and nominal power supply values. Symbol Parameter Test Conditions Min. Typ. Max. Unit DIGITAL INTERFACE IIL Low Level Input Current GRDD ≤ VIN ≤ VIL (note 1) 10 µA IIH High Level Input Current VIH ≤ VIN ≤ VCC 10 µA VIL Input Low Voltage, Except CLKSEL VIH Input High Voltage, Except CLKSEL VOL Output Low Voltage IOL = 3.2mA at DX, TSX and SIGR VOH Output High Voltage IOH = 9.6mA at DX IOH = 1.2mA at SIGR VILO Input Low Voltage, CLKSEL (note 2) VBB VBB + 0.5 V VIIO Input Intermediate Voltage, CLKSEL GRDD -0.5 0.5 V VIHO Input High Voltage, CLKSEL VCC 0.5 VCC V C OX Digital Output Capacitance (note 3) 5 C IN Digital Input Capacitance 5 10 pF 0.8 2.0 V V 0.4 2.4 V V pF Notes: 1. VIN is the voltage on any digital pin. 2. SIGX and DCLKR are TTL level inputs between GRDD and VCC; they are also pinstraps for mode selection when tied to VBB. Under these conditions VILO is the input low voltage requirement. 3. Timing parameters are guaranteed based on a 100pF load capacitance. Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance of 60pF. 7/17 M5913 DC CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max Unit POWER DISSIPATION All measurements made at fDCLK = 2.048MHz, outputs unloaded ICC1 VCC Operating Current 6 10 mA IBB1 VBB Operating Current 6 9 mA ICC0 VCC Power Down Current PDN ≤ VIL ; after 10µs 40 300 µA IBB0 VBB Power Down Current PDN ≤ VIL ; after 10µs 40 300 µA ICCS VCC Standby Current FSX, FSR ≤ VIL ; after 30ms 300 600 µA IBBS VBB Standby Current FSX, FSR ≤ VIL ; after 30ms 40 300 µA PD1 Operating Power Dissipation 60 100 mW PD0 Power Down Dissipation PDN ≤ VIL ; after 10µs 0.4 3 mW PST Standby Power Dissipation FSX, FSR ≤ VIL ; after 30ms 1.7 5 mW 100 nA ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE IBX1 Input Leakage Current, VFXI+, VFXI- R IXI Input Resistance, VFXI+, VFXI- -2.17V ≤ VIN ≤ 2.17V 10 VOSXI Input Offset Voltage, VFXI+, VFXI- CMRR Common Mode Rejection, VFXI+, VFXI- -2.17V ≤ VIN ≤ 2.17V DC Open Loop Voltage Gain, GSX RL = 10K 5000 RL ≥ 10kΩ – 2.17 AVOL fC 55 Open Loop Unity Gain Bandwidth, GSX VOXI Output Voltage Swing GSX CLXI Load Capacitance, GSX RLXI Minimum Load Resistance, GSX MΩ 25 mV dB 20.000 1 MHz 2.17 V 50 pF 10 kΩ ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE R ORA Output Resistance, PWRO+, PWRO- VOSRA Single-ended Output DC Offset, PWRO+, PWRO- C LRA Load Capacitance, PWRO+, PWRO- Ω 1 Relative to GRDA -150 75 150 mV 100 pF AC CHARACTERISTICS - TRANSMISSION PARAMETERS Unless otherwie noted, the analog input is a 0dBm0, 1020Hz sine wave1. Input amplifier is set for unity gain, noninverting. The digital inputs is a PCM bit stream generated by passing a 0dBm0, 1020Hz sine wave through an ideal encoder. Receive output is measured single ended, maximum gain configuration2. All output levels are (sin X)/X corrected. Symbol Parameter Test Conditions Min. Typ. Max. Unit ± 0.04 +0.15 dBm0 +0.12 dB +0.15 dBm0 +0.08 dB GAIN AND DYNAMIC RANGE Encoder Milliwatt Response (transmit gain tolerance) Tamb = 25°C, VBB = – 5V, VCC = + 5V -0.15 EmW Variation with Temperature and Supplies ± 5% Supplies, 0 to 70°C Relative to Nominal Conditions -0.12 Digital Milliwatt Response (receive gain tolerance) Tamb = 25°C ; VBB = – 5V, VCC = + 5V -0.15 DmW TS DmW Variation with Temperature and Supplies ± 5%, 0 to 70°C -0.08 0TLP 1X Zero Transmission Level Point Transmit Channel (0dBm0) µ-law Referenced to 600Ω Referenced to 900Ω + 2.76 + 1.00 dBm dBm 0TLP 2X Zero Transmission Level Point Transmit Channel (0dBm0) A-law Referenced to 600Ω Referenced to 900Ω + 2.79 + 1.03 dBm dBm 0TLP1R Zero Receive Level Point Receive Channel (0dBm0) µ-law Referenced to 600Ω Referenced to 900Ω + 5.76 + 4.00 dBm dBm 0TLP2R Zero Transmission Level Point Transmit Channel (0dBm0)) A-law Referenced to 600Ω Referenced to 900Ω + 5.79 + 4.03 dBm dBm EmW EmWTS DmW 8/17 ± 0.04 M5913 AC CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min. Typ. Max. Unit GAIN TRACKING Reference Level = – 10dBm0 GT1X Transmit Gain Tracking Error Sinusoidal Input; µ-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB GT2X Transmit Gain Tracking Error Sinusoidal Input; A-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB GT1R Receive Gain Tracking Error Sinusoidal Input; µ-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB GT2R Receive Gain Tracking Error Sinusoidal Input; A-law + 3 to – 40dBm0 – 40 to – 50dBm0 – 50 to – 55dBm0 ± 0.2 ± 0.4 ± 1.0 dB dB dB NOISE N XC1 Transmit Noise, C-message Weighted VFXI+ = GRDA, VFXI– = GSX 0 13 dBrnc0 N XC2 Transmit Noise, C-message Weighted with Eighth Bit Signaling VFXI+ = GRDA, VFXI– = GSX 6 th Frame Signaling 13 18 dBrnc0 NXP Transmit Noise, Psophometrically Weighted VFXI+ = GRDA, VFXI– = GSX (note 3) – 80 dBrnc0 NRC1 Receive Noise, C-message Weighted: Quiet Code D R = 11111111 Measure at PWRO+ 1 9 dBrnc0 NRC2 Receive Noise, C-message Weighted: Sign Bit Toggle Input to D R is 0 code with Sign Bit Toggle at 1KHz Rate 1 10 dBm0p NRP Receive Noise, Psophometrically Weighted D R = Lowest Positive Decode Level -90 – 81 dB0p N SF Single Frequency NOISE End to End Measurement CCITT G.712.4.2 – 50 dBm0 PSRR1 VCC Power Supply Rejection, Transmit Channel Idle Channel ; 200mV P-P Signal on Supply ; 0 to 50kHz, Measure at DX – 40 dB PSRR2 VBB Power Supply Rejection, Transmit Channel Idle Channel ; 200mV P-P Signal on Supply ; 0 to 50kHz, Measure at DX – 40 dB PSRR3 VCC Power Supply Rejection, Receive Channel Idle Channel ; 200mV P-P Signal on Supply ; Measure Narrow Band at PWRO+ Single Ended, 0 to 50kHz – 40 dB PSRR4 VBB Power Supply, Rejection Receive Channel Idle Channel ; 200mV P-P Signal on Supply ; Measure Narrow Band at PWRO+ Single Ended, 0 to 50kHz – 40 dB CTTR Crosstalk, Transmit to Receive, Single Ended Outputs VFXI+ = 0dBm0, 1.02kHz, D R = Lowest Positive Decode Level, Measure at PWRO+ – 80 dB CTRT Crosstalk, Receive to Transmit, Single Ended Outputs D B = 0dBm0, 1.02kHz, VFXI+ = GRDA, Measure at DX – 80 dB Notes: 1. 0dBm0 is defined as the zero reference point of the channel under test (0TLP). This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrmst (µLaw) dual 1.068 Vrmst or a output 1.516 Vrmst (A-Law) 2. Unity gain input amplifier : GSX is connected to VFXI, Signal input VFXI+; Maximum gain output amplifier: GSR is connected to PWRO, output to PWRO+. 3. Noise free: DX PCM Code stable at 01010101. 9/17 M5913 A.C. CHARACTERISTICS (continued) Symbol Parameter DISTORTION Transmit Signal to Distortion, µ-law SD1X Sinusoidal Input; CCITT G.712-method 2 SD2X Transmit Signal to Distortion, A-law Sinusoidal Input, CCITT G.712-method 2 SD1R Transmit Signal to Distortion, µ-law Sinusoidal Input , CCITT G.712-method 2 Receive Signal to Distortion, A-law SD2R Sinusoidal Input; CCITT G.712-method 2 DP X1 Transmit Single Frequency Distortion Products Receive Single Frequency Distortion DPR1 Products Intermodulation Distortion, IMD1 End to End Measurement Intermodulation Distortion, IMD2 End to End Measurement SOS Spurious Out of Band Signals, End to End Measurement SIS Spurious in Band Signals, End to End Measurement Transmit Absolute Delay DAX DDX Transmit Differential Envelope Delay Relative to DAX DAR Receive Absolute Delay D DR Receive Differential Envelope Delay Relative to DAR 10/17 Test Conditions Max. Unit – 46 dB dB dB dB dB dB dB dB dB dB dB dB dB – 46 dB – 35 dB CCITT G.712 (7.2) – 49 dB CCITT G.712 (6.1) – 30 dBm0 CCITT G.712 (9) – 40 dBm0 0 ≤ VFXI+ ≤ – 30dBm0 – 40dBm0 – 45dBm0 0 ≤ VFXI+ ≤ – 30dBm0 – 40dBm0 – 45dBm0 0 ≤ VFXI+ ≤ – 30dBm0 – 40dBm0 – 45dBm0 0 ≤ VFXI+ ≤ – 30dBm0 – 40dBm0 – 45dBm0 AT & T Adivisory # 64 (3.8) 0dBm0 Input Signal AT & T Adivisory # 64 (3.8) 0dBm0 Input Signal CCITT G.712 (7.1) Fixed Data Rate CLKX = 2.048MHz, 0dBm0, 1.02kHz Signal at VFXI+ Measure at D X f = 500 – 600Hz f = 600 – 1000Hz f = 1000 – 2600Hz f = 2600 – 2800Hz Fixed data rate, CLKR = 2.048MHz; Digital input is DMW codes. Measure at PWRO+ f = 500 – 600Hz f = 600 – 1000Hz f = 1000 – 2600Hz f = 2600 – 2800Hz Min. Typ. 36 30 25 36 30 25 36 30 25 36 30 25 300 µs 170 95 45 80 µs µs µs µs µs 190 10 10 85 110 µs µs µs µs M5913 A.C. CHARACTERISTICS (continued) TRANSMIT CHANNEL TRANSFER CHARACTERISTICS (Input amplifier is set for unity gain, noninverting; maximum gain output.) Symbol GRX Parameter Gain Relative to Gain at 1.02 kHz 16.67Hz 50Hz 60Hz 200Hz 300 to 3000Hz 3300Hz 3400Hz 4000Hz 4600Hz and Above Test Conditions 0 dBm0 Signal Input at VFXI+ Min. – 1.8 – 0.125 – 0.35 – 0.7 Typ. Max. Unit – 30 – 25 – 23 – 0.125 + 0.125 + 0.03 – 0.10 – 14 – 32 dB dB dB dB dB dB dB dB dB Figure 5: Transmit Filter 11/17 M5913 A.C. CHARACTERISTICS (continued) RECEIVE CHANNEL TRANSFER CHARACTERISTICS Symbol GRR Parameter Gain Relative to Gainat 1.02kHz below 200Hz 200Hz 300 to 3000Hz 3300Hz 3400Hz 4000Hz 4600Hz and Above Figure 6: Receive Filter 12/17 Test Conditions 0dBm0 Signal Input at D R Min. – 0.5 – 0.125 – 0.35 – 0.7 Typ. Max. Unit + 0.125 + 0.125 + 0.125 + 0.03 – 0.1 – 14 – 30 dB dB dB dB dB dB dB M5913 AC CHARACTERISTICS - TIMING PARAMETERS Symbol Parameter Test Conditions CLOCK SECTION Clock Period, CLKX, CLKR fCLKX = fCLKR = 2.048MHz tCY tCLK Clock Pulse Width CLKX, CLKR 1 Data Clock Pulse Width 64kHz ≤ fDCLK ≤ 2.048MHz tDCLK Clock Duty Cycle CLKX, CLKR tCDC Clock Rise and Fall Time tr, tf TRANSMIT SECTION, FIXED DATA RATE MODE2 tDZX Data Enabled on TS Entry 0 < CLOAD < 100pF Data Delay from CLKX 0 < CLOAD < 100pF tDDX Data Float on TS Exit C LOAD = 0 tHZX tSON Timeslot X to Enable 0 < CLOAD < 100pF Timeslot X to Disable C LOAD = 0 tSOFF tFSD Frame Sync Delay Signal Setup Time tSS Signal Setup Time tSH RECEIVE SECTION, FIXED DATA RATE MODE Receive Data Setup tDSR tDHR Receive Data Hold Frame Sync Delay tFSD tSIGR SIGR Update TRANSMIT SECTION, FIXED DATA RATE MODE2 tTSDX Timeslot Delay from DCLKX Frame Sync Delay tFSD Data Delay from DCLKX 0 < CLOAD < 100pF tDDX tDON Timeslot to D X Active 0 < CLOAD < 100pF Timeslot to D X Inactive 0 < CLOAD < 100pF tDOFF fDX Data Clock Frequency Data Delay from FSX tTSDX = 80ns tDFSX RECEIVE SECTION, FIXED DATA RATE MODE Timeslot Delay from DCLKR tTSDR tFSD Frame Sync Delay Receive Data Setup Time tDSR Receive Data Hold Time tDHR Data Clock Frequency tDR tSER Timeslot End Receive Time 64KB OPERATION, VARIABLE DATA RATE MODE Transmit Frame Sync Minimum FSX is TTL high for tFSLX Downtime remainder of frame Receive Frame Sync Miniumum FSR is TTL high for tFSLR Downtime remainder of frame Data Clock Pulse Width tDCLK Min. 488 195 195 40 5 0 0 60 0 50 0 0 0 Typ. 50 Max. Unit 60 30 ns ns ns % ns 145 145 190 145 190 120 ns ns ns ns ns ns ns ns 10 60 0 0 120 2 ns ns ns µs -80 0 0 0 0 64 0 80 120 100 50 80 1 2048 140 ns ns ns ns ns KHz ns -80 0 10 60 64 0 80 120 ns ns ns ns kHz ns 20481 488 ns 1952 ns 10 µs Notes: 1. Devices are available wich operate at data rates up to 4.096MHz; the minimum data clock pulse width for these devices is 110ns 2. Timing parameters tDZX, tHZX, and tSOFF are referenced to a high impedance state. 13/17 M5913 WAVEFORMS: Fixed Data Rate Timing - Transmit Timing NOTE: All timing parameters referenced to VIH and VIL except tDZX, tSOFF and tHZX which reference a high impedance state. Receive Timing NOTE: All timing parameters referenced to VIH and VIL 14/17 M5913 VARIABLE DATA RATE TIMING AC Timing Input, Output Waveform 15/17 M5913 DIP20 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.254 B 1.39 TYP. MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L Z 16/17 inch 3.3 0.130 1.34 0.053 M5913 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 17/17