STMICROELECTRONICS M65KG512AB8W9

M65KG512AB
512Mbit (4 banks x 8 Mb x 16)
1.8 V supply, DDR low power SDRAM
Features
■
512Mbit Synchronous Dynamic RAM
– Organized as 4 banks of 8 Mwords, each
16 bits wide
■
Double Data Rate (DDR)
– 2 Data Transfers/Clock cycle
– Data Rate: 332 Mbit/s max. for 6ns speed
class
■
Supply voltage
– VDD = 1.7 to 1.9 V (1.8 V typical in
accordance with JEDEC standard)
– VDDQ = 1.7 to 1.9 V for Inputs/Outputs
■
Synchronous Burst Read and Write
– Fixed Burst Lengths: 2-, 4-, 8-, 16 words
– Burst Types: Sequential and Interleaved.
– Clock Frequency: 133 MHz (7.5 ns speed
class), 166 MHz (6 ns speed class)
– Clock Valid to Output Delay (CAS Latency):
3 at the maximum clock frequency
– Burst Read Control by Burst Read
Terminate And Precharge Commands
■
Automatic Precharge
■
Byte Write controlled by LDQM and UDQM
■
Low-power features
– Partial Array Self Refresh (PASR)
– Automatic Temperature Compensated Self
Refresh (ATCSR)
– Driver Strength (DS)
– Deep Power-Down mode
– Auto Refresh and Self Refresh
■
LVCMOS interface compatible with multiplexed
addressing
■
Operating temperature:
– −30 to 85 °C
– −30 to 105 °C
Wafer
The M65KG512AB is only available as part of a multi-chip package product.
February 2007
Rev 3
1/54
www.st.com
1
Contents
M65KG526AB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
2/54
2.1
Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Clock Inputs (K, K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Lower/Upper Data Input Mask (LDQM, UDQM) . . . . . . . . . . . . . . . . . . . . 10
2.11
Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) . . . . 10
2.12
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13
VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15
VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Mode Register Set command (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Extended Mode Register Set command (EMRS) . . . . . . . . . . . . . . . . . . . 12
3.3
Bank(Row) Activate command (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Read command (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Read with Auto Precharge command (READA) . . . . . . . . . . . . . . . . . . . . 13
3.6
Burst Read Terminate command (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7
Write command (WRIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8
Write with Auto Precharge command (WRITA) . . . . . . . . . . . . . . . . . . . . 14
3.9
Precharge Selected Bank/Precharge All Banks command (PRE/PALL) . 14
3.10
Self Refresh Entry command (SELF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.11
Self Refresh Exit command (SELFX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
M65KG526AB
4
5
Contents
3.12
Auto Refresh command (REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.13
Power-Down Entry command (PDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.14
Power-Down Exit command (PDEX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.15
Deep Power-Down Entry command (DPDEN) . . . . . . . . . . . . . . . . . . . . . 16
3.16
Device Deselect command (DESL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.17
No Operation command (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Extended Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3/54
List of tables
M65KG526AB
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
4/54
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bank selection using BA0-BA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Minimum delay between two commands in concurrent Auto Precharge Mode . . . . . . . . . 18
Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Mode Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Extended Mode Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Self Refresh current (IDD6) in normal operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC characteristics - TJ = -30 to 85 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AC characteristics - TJ = -30 to 105 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics measured in clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
M65KG526AB
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Simplified command state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Definition of command and address inputs timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Definition of Read timings 1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Definition of Read timings 2/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Consecutive Bank(Row) Activate command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Read followed by Read in same bank and row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Read followed by Read in a different bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read followed by Auto Precharge ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Read operation (Burst lengths = 2, 4 and 8, CAS latency = 3) . . . . . . . . . . . . . . . . . . . . . . 37
Burst Terminate during Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Write followed by Write in same bank and row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Write followed by Write in a different bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Write operation with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Write with Auto Precharge ac Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Write operation (Burst lengths = 2, 4 and 8, CAS latency = 1) . . . . . . . . . . . . . . . . . . . . . . 41
AC Write ac waveforms (data masking using LDQM/UDQM). . . . . . . . . . . . . . . . . . . . . . . 42
Mode Register/Extended Mode Register Set commands ac waveforms . . . . . . . . . . . . . . 43
Read followed by Write using the Burst Read Terminate command (BST) . . . . . . . . . . . . 44
Write followed by Read (Write completed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Write followed by Read in the same Bank and Row (Write Interrupted). . . . . . . . . . . . . . . 46
Power-Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Auto Refresh command ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Self Refresh Entry and Exit commands ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Deep Power-Down Entry command ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Deep Power-Down Exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5/54
Description
1
M65KG526AB
Description
The M65KG512AB is a 512Mbit Double Data Rate (DDR) Low Power Synchronous DRAM
(LPSDRAM). The memory array is organized as 4 Banks of 8,388,608 words of 16 bits
each.
The device achieves low power consumption and very high-speed data transfer using the 2bit prefetch pipeline architecture that allows doubling the data input/output rate. Command
and address inputs are synchronized with the rising edge of the clock while data
inputs/outputs are transferred on both edges of the system clock. The M65KG512AB is well
suited for handheld battery powered applications like PDAs, 2.5 and 3G mobile phones and
handheld computers.
The device architecture is illustrated in Figure 2: Functional block diagram. It uses Burst
mode to read and write data. It is capable of two, four, and eight-word, sequential and
interleaved burst.
To minimize current consumption during self refresh operations, the M65KG512AB includes
three mechanisms configured via the Extended Mode Register:
●
Automatic Temperature Compensated Self Refresh (ATCSR) adapts the refresh
frequency according to the operating temperature provided by a built-in temperature
sensor.
●
Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of
bank, one bank, two banks or all banks.
●
The Deep Power-Down (DPD) mode completely halts the refresh operation and
achieves minimum current consumption by cutting off the supply voltage from the
whole memory array.
The device is programmable through two registers, the Mode Register and the Extended
Mode Register:
6/54
●
The Mode Register is used to select the CAS Latency, the Burst Type (sequential,
interleaved) and the Burst Length. For more details, refer to Table 7: Mode Register
definition, and to Section 3.1: Mode Register Set command (MRS).
●
Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of
bank, one bank, two banks or all banks.
●
The Extended Mode Register is used to configure the low-power features (PASR,
ATCSR and Driver Strength) to reduce the current consumption during the Self Refresh
operations. For more details, refer to Table 8: Extended Mode Register definition, and
to Section 3.2: Extended Mode Register Set command (EMRS).
M65KG526AB
Figure 1.
Description
Logic diagram
VDD VDDQ
13
16
A0-A12
DQ0-DQ15
2
BA0-BA1
E
UDQS
RAS
LDQS
CAS
M65KG512AB
K
K
KE
W
UDQM
LDQM
VSS
VSSQ
AI12443
Table 1.
Signal names
A0-A12
Address Inputs
BA0-BA1
Bank Select Inputs
DQ0-DQ15
Data Inputs/Outputs
K, K
Clock Inputs
KE
Clock Enable Input
E
Chip Enable Input
W
Write Enable Input
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
UDQM
Upper Data Input Mask
LDQM
Lower Data Input Mask
UDQS
Upper Data Read/ Write Strobe I/O
LDQS
Lower Data Read/Write Strobe I/O
VDD
Supply Voltage
VDDQ
Input/Output Supply Voltage
VSS
Ground
VSSQ
Input/Output Ground
7/54
Description
Figure 2.
M65KG526AB
Functional block diagram
Clock Generator
K
K
KE
TCSR, PASR
Extended
Mode
Register
Self Refresh
Logic & Timer
Internal Row
Counter
...
Burst Length
Address Buffers
...
...
BA0
DQ15
UDQM/LDQM
UDQS/LDQS
Address
Registers
A0
BA1
DQ0
Column Add
Counter
Bank Select
A12
I/O Buffer & Logic
Column Decoders
...
Memory
Cell
Array
Sense AMP & I/O Gate
Column
PreDecoders
8 Mb x 16 Bank A
...
W
Column
Active
8 Mb x 16 Bank B
Row Decoders
CAS
Refresh
8 Mb x 16 Bank C
Row Decoders
RAS
8 Mb x 16 Bank D
Row Decoders
StateMachine
E
Row
PreDecoders
Row Decoders
Row
Active
Mode
Register
Burst
Counter
CAS Latency
Data Out
Control
ai12450
8/54
M65KG526AB
2
Signal descriptions
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A12)
The A0-A12 Address Inputs are used to select the row or column to be made active. If a row
is selected, all thirteen, A0-A12 Address Inputs are used. If a column is selected, only the
ten least significant Address Inputs, A0-A9, are used. In this latter case, A10 determines
whether Auto Precharge is used:
●
●
During a Read or Write operation:
–
If A10 is High (set to ‘1’), the Read or Write operation includes an Auto Precharge
cycle.
–
If A10 is Low (set to ‘0’), the Read or Write cycle does not include an Auto
Precharge cycle.
When issuing a Precharge command:
–
If A10 is Low, only the bank selected by BA1-BA0 will be precharged.
–
If A10 is High, all the banks will be precharged.
The address inputs are latched at the cross point of K rising edge and K falling edge.
2.2
Bank Select Address Inputs (BA0-BA1)
The Banks Select Address Inputs, BA0 and BA1, are used to select the bank to be made
active (see Table 2: Bank selection using BA0-BA1).
When selecting the addresses, the device must be enabled, the Row Address Strobe, RAS,
must be Low, VIL, the Column Address Strobe, CAS, and W must be High, VIH.
2.3
Data Inputs/Outputs (DQ0-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a Read
operation, or to input the data during a write operation.
2.4
Chip Enable (E)
The Chip Enable input, E, activates the memory state machine, address buffers and
decoders when driven Low, VIL. When E is High, VIH, the device is not selected.
2.5
Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A0-A9 and
BA1-BA0, to select the starting column location prior to a read or write operation.
9/54
Signal descriptions
2.6
M65KG526AB
Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A0-A12 and
BA1-BA0, to select the starting address location prior to a Read or Write.
2.7
Write Enable (W)
The Write Enable input, W, controls writing.
2.8
Clock Inputs (K, K)
The Clock signals, K and K, are the master clock inputs. All input signals except
UDQM/LDQM, UDQS/LDQS and DQ0-DQ15 are referred to the cross point of K rising edge
and K falling edge. During read operations, UDQS/LDQS and DQ0-DQ15 are referred to the
cross point of K rising edge and K falling edge. During write operations, UDQM/LDQM and
DQ0-DQ15 are referred to the cross point of UDQS/LDQS and VREF, and UDQS/LDQS to
the cross point of K rising edge and K falling edge.
2.9
Clock Enable (KE)
When driven Low, VIL, the Clock Enable input, KE, is used to suspend the Clock K, to switch
the device to Self Refresh, Power-Down or Deep Power-Down mode.
The Clock Enable, KE, must be stable for at least one clock cycle. This means that, if KE
level changes on K rising edge and K falling edge with a setup time of tAS, it must be at the
same level by the next K rising edge with a hold time of tAH.
2.10
Lower/Upper Data Input Mask (LDQM, UDQM)
Lower Data Input Mask and Upper Data Input Mask are input signals used to mask the data
input during write operations. UDQM and LDQM are sampled when UDQS/LDQS level
crosses VREF. When LDQM is Low, VIL, DQ0 to DQ7 inputs are selected. When UDQM is
Low, VIL, DQ8 to DQ15 inputs are selected.
2.11
Lower/Upper Data Read/Write Strobe Input/Output (LDQS,
UDQS)
LDQS and UDQS act as write data strobe (as input) and read data strobe (as output)
respectively. LDQS and UDQS are the strobe signals for DQ0 to DQ7 and DQ8 to DQ15,
respectively. During read operations, the device outputs the data strobe through
LDQS/UDQS pins simultaneously with data (see Figure 10). Data is output at both the rising
and falling edge of the data strobe.
During write operations, LDQS/UDQS should be input as the strobe for the input data
together with LDQM/UDQM (see Figure 18). The inputs data should be synchronized with
the high and low pulse of LDQS/UDQS.
10/54
M65KG526AB
2.12
Signal descriptions
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (Read and Write).
2.13
VDDQ supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently of VDD. VDDQ can be tied to VDD or can use a separate supply. It is
recommended to power-up and power-down VDD and VDDQ together to avoid certain
conditions that would result in data corruption.
2.14
VSS ground
Ground, VSS, is the reference for the core power supply. It must be connected to the system
ground.
2.15
VSSQ ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS.
Note:
Each device in a system should have VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package).
Table 2.
Bank selection using BA0-BA1
Selected bank
BA0
BA1
Bank A
VIL
VIL
Bank B
VIH
VIL
Bank C
VIL
VIH
Bank D
VIH
VIH
11/54
Commands
3
M65KG526AB
Commands
The M65KG512AB recognizes a set of commands that are obtained by specific statuses of
Chip Enable, E, Column Address Strobe, CAS, Row Address Strobe, RAS, Write Enable, W,
and address inputs. Refer to Table 3: Commands, in conjunction with the text descriptions
below.
Figure 3: Simplified command state diagram shows the operations that are performed when
each command is issued at each state of the DDR LPSDRAM.
3.1
Mode Register Set command (MRS)
The Mode Register Set command is used to configure the Burst Length, Burst Type and
CAS Latency of the device by programming the Mode Register.
The command is issued with KE held High, with BA0, BA1 and A10 set to ‘0’, and E, RAS,
CAS and W driven Low, VIL. The value of address inputs A0 to A7 determines the Burst
Length, Burst Type and CAS Latency of the device (see Table 7: Mode Register definition
and Figure 22: Mode Register/Extended Mode Register Set commands ac waveforms):
●
The Burst Length (2, 4, 8, 16 words) is programmed using the address inputs A2-A0
●
The Burst Type (sequential or interleaved) is programmed using A3.
●
The CAS Latency (3 Clock cycles) is programmed using A6-A4.
It is required to execute a Mode Register Set command at the end of the Power-up
sequence. Once the command has been issued, it is necessary to wait for at least two clock
cycles before issuing another command.
3.2
Extended Mode Register Set command (EMRS)
The Extended Mode Register Set command is used to configure the low-power features of
the device by programming the Extended Mode Register.
The command is issued with KE held High, BA0 at ‘0’, BA1 at ‘1’, A10 at ‘0’, by driving E,
RAS, CAS and W, Low, VIL. The value of address inputs A0 to A9 determines the Driver
Strength, the part of the array that is refreshed during Self Refresh and the Automatic
Temperature Compensated Self Refresh feature (see Table 8: Extended Mode Register
definition and Figure 22: Mode Register/Extended Mode Register Set commands ac
waveforms):
●
The part of the array to be refreshed (all banks, Bank A and B, Bank A only) during Self
Refresh is set using A2-A0.
●
The Driver Strength (full, 1/2 strength, 1/4 strength, 1/8 strength) is set using bits A6-A5
●
The Automatic temperature Compensated Self Refresh feature is always enabled (A9
set to ‘0’).
It is required to execute an Extended Mode Register Set command at the end of the Powerup sequence. Once the command has been issued, it is necessary to wait for at least two
clock cycles before issuing another command.
12/54
M65KG526AB
3.3
Commands
Bank(Row) Activate command (ACT)
The Bank(Row) Activate command is used to switch a row in a specific bank of the device
from the Idle to the active mode. The bank is selected by BA0 and BA1 and the row by A0 to
A12 (see Table 2: Bank selection using BA0-BA1).
This command is initiated by driving KE High, VIH, with E and RAS Low, VIL, and CAS and W
High.
A minimum delay of tRCD is required after issuing the Bank (Row) Activate command prior to
initiating Read and Write operations from and to the active bank.
A minimum time of tRC is required between two Bank(Row) Activate commands to the same
bank (see Figure 9: Consecutive Bank(Row) Activate command).
3.4
Read command (READ)
The Read command is used to read from the memory array in Burst Read mode. In this
mode, data is output in bursts synchronized with the cross points of the clock signals, K and
K.
The start address of the Burst Read is determined by the column address, A0 to A12, and
the bank address, BA0-BA1, at the beginning of the Burst Read operation. A valid Read
command is initiated by driving E and CAS Low, VIL, and W and RAS High, VIH.
3.5
Read with Auto Precharge command (READA)
This command is identical to the Read command except that a precharge is automatically
performed at the end of the Read operation. The precharge starts tRPD (Burst Length/2
clock periods) after the Read with Auto Precharge command is input.
A tRAS(min) delay elapses between the Bank (Row) Activate and the Auto Precharge
commands. This lock-out mechanism allows a Read with auto Precharge command to be
issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min)
requirement.
The DDR LPSDRAM supports the Concurrent Auto Precharge mode: a Read with autoprecharge can be followed by any command to another active bank, as long as that
command does not interrupt the read data transfer, and that all other related limitations
apply (e.g. contention between read data and written data must be avoided). Table 4:
Minimum delay between two commands in concurrent Auto Precharge Mode shows the
minimum delays between a Read with Auto Precharge command to one bank and a
command to a different bank.
Refer to Figure 13 for a description of Read operation with Auto Precharge.
13/54
Commands
3.6
M65KG526AB
Burst Read Terminate command (BST)
The Burst Read Terminate command is used to terminate a Burst Read operation.
It is issued with KE held High, by driving E and W Low and CAS and RAS High. tBSTZ after
issuing the Burst Read Terminate command, DQ0-DQ15 and LDQS, UDQS revert to the
high impedance state (see Figure 15: Burst Terminate during Read operation).
There is no such command for Burst Write operations.
3.7
Write command (WRIT)
This Write command is used to write to the memory array in Burst Write mode. In this mode,
data is input synchronized with the cross points of the clock signals, K and K.
The start address of the Burst Write is determined by the column address, A0 to A9, and the
address of the selected bank, BA0-BA1, at the beginning of the Burst Read operation. A
valid Write command is initiated by driving E, CAS and W Low, VIL, and RAS High, VIH.
3.8
Write with Auto Precharge command (WRITA)
This command is identical to the Write command except that a precharge is automatically
performed at the end of the Write operation. The precharge starts tWPD (Burst Length/2 +3
clock periods) after the Write with Auto Precharge command is input.
Refer to Figure 19 for a description of Write operation with Auto Precharge.
3.9
Precharge Selected Bank/Precharge All Banks command
(PRE/PALL)
The Precharge Selected Bank and Precharge All Banks are used to place the bank selected
by BA0 and BA1 (see Table 2: Bank selection using BA0-BA1) and all banks in idle mode,
respectively.
The precharge commands are issued by driving E, RAS and W Low, with CAS and KE held
High. The value on A10 determines whether either the selected bank or all the banks will be
precharged:
●
If A10 is High, BA0-BA1 are Don’t Care and all the banks are precharged.
●
If A10 is Low when, only the bank selected by BA0-BA1 is precharged.
The bank(s) is/are placed in the Idle mode tRP after issuing the Precharge command. Once
the bank is in Idle mode, the Bank (Row) Activate command has to be issued to switch the
bank back to active mode.
The precharge commands can be issued during Burst Read or Burst Write in which case the
Burst Read or Write operation is terminated and the selected bank placed in Idle mode.
The device needs to be in Idle mode before entering Self Refresh, Auto Refresh, PowerDown and Deep Power-Down.
14/54
M65KG526AB
3.10
Commands
Self Refresh Entry command (SELF)
The Self Refresh Entry command is used to start a Self Refresh operation. Before starting a
Self Refresh, the device must be idle. The Self Refresh Entry command is issued by driving
KE Low, with E, RAS, and CAS Low, and W High (see Figure 28: Self Refresh Entry and
Exit commands ac waveforms).
During the Self Refresh operation, the internal memory controller generated the addresses
of the row to be refreshed.
The Self Refresh operation goes on as long as the Clock Enable signal, KE, is held Low.
3.11
Self Refresh Exit command (SELFX)
The Self Refresh Exit command is used to exit from Self Refresh mode.
There are two ways to exit from Self Refresh mode:
●
Driving KE Low to High, with E High, RAS, CAS and W Don’t Care,
●
Driving E Low and RAS, CAS and W High.
Non-read commands can be executed 3tCK + tRC after the end of the Self Refresh operation,
where tCK is the Clock period and tRC the RAS Cycle time.
See Figure 28 for a description of Self Refresh Exit ac waveforms.
3.12
Auto Refresh command (REF)
This command performs an Auto Refresh. The device is placed in Auto refresh mode from
Idle by holding KE High, VIH, driving E, RAS and CAS Low and driving W High. The address
bits are “Don’t Care” because the addresses of the bank and row to be refreshed are
internally determined by the internal refresh controller. The output buffer becomes High-Z
after the Auto Refresh has started. Precharge operations are automatically completed after
the Auto Refresh. A Bank(Row) Activate, a Mode Register Set or an Extended Mode
Register Set command can be issued tRFC after the last Auto Refresh command (see
Figure 27: Auto Refresh command ac waveforms).
The average refresh cycle is tREF (see Table 16: AC characteristics - TJ = -30 to 105 °C). To
optimize the operation scheduling, a flexibility in the absolute refresh interval is provided.
A maximum of eight Auto Refresh commands can be issued to the DDR LPSDRAM and the
maximum absolute interval between two Auto Refresh commands 8tREF.
3.13
Power-Down Entry command (PDEN)
The DDR LPSDRAM is caused to enter Power-Down mode from Idle by driving either:
●
KE Low and E High (other signals are Don’t Care),
●
KE Low and RAS, CAS and W High with E Low.
The Power-Down mode continues as long as KE remains Low.
15/54
Commands
3.14
M65KG526AB
Power-Down Exit command (PDEX)
The DDR LPSDRAM exits from Power-Down mode by driving KE High.
3.15
Deep Power-Down Entry command (DPDEN)
The device is placed in Deep Power-Down mode by driving KE Low, with E and W Low and
RAS and CAS High (see Figure 29: Deep Power-Down Entry command ac waveforms). All
banks must be precharged or in idle state before entering the Deep Power-Down mode.
After the command execution, the device remains in Deep Power-Down mode while KE is
low.
Deep Power-Down Exit (DPDEX)
The M65KG512AB exits Deep Power-Down mode by asserting KE High. A special
sequence is then required before the device can take any new command into account:
1.
Maintain No Operation status conditions for a minimum of 200µs,
2.
Issue a Precharge All Banks command (see Section 3.9: Precharge Selected
Bank/Precharge All Banks command (PRE/PALL) for details),
3.
Once all banks are precharged and after the minimum tRP delay is satisfied, issue 2 or
more Auto Refresh commands,
4.
Issue a Mode Register Set command to initialize the Mode Register bits,
5.
Issue an Extended Mode Register Set command to initialize the Extended Mode
Register bits.
The Deep Power-Down mode exit sequence is illustrated in Figure 30: Deep Power-Down
Exit ac waveforms.
3.16
Device Deselect command (DESL)
When the Chip Enable, E, is High at the cross point of the Clock K rising edge with VREF, all
input signals are ignored and the device internal status is held.
3.17
No Operation command (NOP)
The device is placed in the No Operation mode, by driving CAS, RAS and W High, with E
Low and KE High.
As long as this command is input at the cross point of the Clock K rising edge with the VREF
level, address and data input are ignored and the device internal status is held.
16/54
M65KG526AB
Table 3.
Commands
Commands(1)(2)
Command
Mode Register Set
Extended Mode Register
Set
Bank (Row) Activate
Read
Read with Auto Precharge
Symbol KEn-1 KEn
ACT
BA1 BA0
VIH
VIL
VIL
VIL
VIL
A0-A9,
A11-A12
READA
Write with Auto Precharge
WRITA
Precharge Selected Bank
PRE
VIL
VIH
MR/EMR
Data(3)
VIL
VIH
VIH
VIL
VIL
VIH
VIH
V
V
VIH
VIH
VIL
VIH
VIL
VIH
V
V
Column
Address
VIH
VIH
VIL
VIH
VIH
VIL
X
X
X
VIH
VIH
VIL
VIH
VIL
VIL
V
V
Column
V(6)
V(6)
X
VIH
VIH
VIL
VIL
VIH
VIL
VIL(6)
X(7)
X(7)
X
VIH(7)
VIL
VIL
VIL
VIH
X
X
X
X
VIH
X
X
X
VIL
VIH
VIH
VIH
VIL
VIL
VIL
VIH
VIH
X
X
X
VIL
VIH
VIH
VIH
VIH
X
X
X
VIL
VIH
VIH
VIH
Precharge All Banks
PALL
Self-Refresh Entry(8)
SELF
VIH
VIL
SELFX
VIL
VIH
REF
VIH
VIH
PDEN
VIH
VIL
VIL
VIH
PDEX
A10
MR/EMR
Data(3)
READ
WRIT
Power-Down Exit
W
EMRS
Write
Power-Down Entry(8)
CAS
VIL
VIH
BST
Auto Refresh(8)
RAS
MRS
Burst Read Terminate
Self Refresh Exit
E
Row Address
VIL(4)
VIH(5)
VIL(4)
VIH(4)
X
X
X
X
X
X
X
X
X
X
X
X
Deep Power-down Entry(8)
DPDEN
VIH
VIL
VIL
VIH
VIH
VIL
X
X
X
Deep Power-down Exit
DPDEX
VIL
VIH
X
X
X
X
X
X
X
1. X = Don’t Care (VIL or VIH); V = Valid Address Input.
2. Clock Enable KE must be stable at least for one clock cycle.
3. MR and EMR data is the value to be written in the Mode Register and Extended Mode Register, respectively.
4. If A10 is Low, VIL, when issuing the command, the row remains active at the end of the operation.
5. If A10 is High, VIH, when issuing the command, an automatic precharge cycle is performed at the end of the operation and
the row reverts to the Idle mode.
6. If A10 is Low, VIL, when issuing the command, only the bank selected by BA0-BA1 is precharged (BA0-BA1 should be
valid).
7. If A10 is High, VIH, when issuing the command, all the banks are precharged and BA0-BA1 are Don’t Care.
8. All the banks must be idle before executing this command.
17/54
Commands
Table 4.
M65KG526AB
Minimum delay between two commands in concurrent Auto Precharge Mode
From command
READA
WRITEA
To command
Minimum delay between the 2 commands in
concurrent Auto Precharge mode(1)
Unit
READ or READA
BL/2
tCK
WRITE or WRITEA
CAS Latency (rounded up) + BL/2
tCK
PRE or ACT
1
tCK
READ or READA
1 + BL/2 + tWTR
tCK
WRITE or WRITEA
BL/2
tCK
PRE or ACT
1
tCK
1. BL = Burst Length.
Table 5.
Burst Type Definition
Burst length = 2
words
Start
addr. (A0SequenInterA3)
tial
leaved
Burst length = 4
words
Burst length = 8 words
Burst length = 16 words
Sequential
Interleaved
Sequential
Interleaved
Sequential
Interleaved
00h
0-1
0-1
0-1-2-3
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0-1-2-..D-E-F
0-1-2-..D-E-F
01h
1-0
1-0
1-2-3-0
1-0-3-2
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
1-2-3..D-E-F-0
1-0-3-..C-F-E
02h
2-3-0-1
2-3-0-1
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
2-3-4..E-F-0-1
2-3-0- ..F-C-D
03h
3-0-1-2
3-2-1-0
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
3-4-5..F-0-1-2
3-2-1-..E-D-C
04h
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
4-5-6..0-1-2-3
4-5-6-..9-A-B
05h
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
5-6-7..1-2-3-4
5-4-7..8-B-A
06h
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
6-7-8..2-3-4-5
6-7-4-..B-8-9
07h
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
7-8-9..3-4-5-6
7-6-5-..A-9-8
08h
8-9-A..4-5-6-7
8-9-A..5-6-7
09h
9-A-B..5-6-7-8
9-8-A..4-7-6
0Ah
A-B-C..6-7-8-9
A-B-8..7-4-5
0Bh
B-C-D..7-8-9-A
B-A-9..6-5-4
0Ch
C-D-E..8-9-A-B
C-D-E..1-2-3
0Dh
D-E-F..9-A-B-C
D-C-F..0-3-2
0Eh
E-F-0..A-B-C-D
E-F-C..3-0-1
0Fh
F-0-1..B-C-D-E
F-E-D..2-1-0
18/54
M65KG526AB
Simplified command state diagram
Extended
Mode Register
Set
Self
Refresh
LF
Ex
it
SE
LF
S
R
EM
SE
MRS
Mode Register
Set
REF
IDLE
Auto Refresh
EN
PD
EX
Power-Down
ACT
D
Deep
Power-Down
D
PD
EN
ee
Ex p P
it ow
Se e
qu r-D
en ow
ce n
PD
PDEN
Precharge
n)
READ
har
rec
E (P
READA
PR
n)
atio
min
Ter
POWER-ON
Read
ge
ge
har
Ter
rec
min
atio
PRE
E (P
PR
WRITEA
Active
Power-Down
READA
W
Read
T
BS
d
ea
R
ith
d w rge
Rea recha
oP
WRITE
PDEX
aut
Write
rite
Wri
t
e
Aut
o P with
rech
arge
ROW
ACTIVE
WRITEA
Figure 3.
Commands
Precharge
Automatic Sequence
Manual Input
Deep Power-Down Exit Sequence
ai11204b
19/54
Operating modes
4
M65KG526AB
Operating modes
There are 7 operating modes that control the memory. Each of these is composed by a
sequence of commands (see Table 6: Operating modes for a summary).
4.1
Power-Up
The DDR LPSDRAM has to be powered up and initialized in a well determined manner:
1.
After applying power to VDD and VDDQ an initial pause of at least 200µs is required
before the signals can be toggled.
2.
The Precharge command must then be issued to all banks. Until the command is
issued KE and UDQM/LDQM must be held High to make sure that DQ0-DQ15 remain
high impedance.
3.
tRP after precharging all the banks, the Mode Register and the Extended Mode
Register must be set by issuing a Mode Register Set command and an Extended Mode
Register Set command, respectively. A minimum pause of tMRD must be respected
after each register set command.
4.
After the two registers are configured, two or more auto Refresh cycles must be
executed before the device is ready for normal operation.
The third and fourth steps can be swapped.
Refer to Figure 26 for a detailed description of the Power-Up ac waveforms.
4.2
Burst Read
The M65KG512AB is switched in Burst Read mode by issuing a Bank (Row) Activate
command to set the bank and row addresses to be read from, followed by a Read command
(see Section 3.3: Bank(Row) Activate command (ACT) and Section 3.4: Read command
(READ) for details).
Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the
A10 Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the
Burst Read operation will be followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’),
the row will remain active for subsequent accesses.
Burst Read operations are performed at word level only. Different Burst Types (sequential or
interleaved), Burst Lengths (2, 4, 8, and 16 words) can be programmed using the Mode
Register bits. Only a CAS Latency of 3 clock cycles is available. Refer to Section 5.1, and to
Section 3.1: Mode Register Set command (MRS), for details on the Mode Register bits and
how to program them.
The Burst Read starts 2tCK + tAC after the Clock K rising edge where the Read command is
latched, where tCK is the Clock period and tAC is the access time from K or K. Data Strobe,
UDQS/LDQS, are output simultaneously with data. tRPRE prior to the first rising edge of the
data strobe, the UDQS/LDQS signals go from High-Z to Low state. This Low pulse is
referred to as the Read Preamble. The burst data are then output synchronized with the
rising and falling edge of the data strobe. UDQS/LDQS become High-Z on the next clock
cycle after the Burst Read is completed. tRPST from the last falling edge of the data strobe,
the DQS pins become High-Z. This low period of DQS is referred as Read Postamble.
20/54
M65KG526AB
Operating modes
See Table 5, Table 16, Table 17, Figure 12 and Figure 14, for a detailed description of Burst
Read operation and characteristics.
Burst Read can be terminated by issuing a Burst Read Terminate command (see
Section 3.6: Burst Read Terminate command (BST) and Section Figure 15.: Burst
Terminate during Read operation).
The interval between Burst Read to Burst Read and Burst Read to Burst Write commands
are described in Figure 10, Figure 11 and Figure 23.
4.3
Burst Write
The M65KG512AB is switched in Burst Write mode by issuing a Bank (Row) Activate
command to set the bank and row addresses to be written to, followed by a Write command
(see Section 3.3: Bank(Row) Activate command (ACT) and Section 3.7: Write command
(WRIT) for details).
Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the
A10 Address Input. If A10 is High (set to ‘1’) when the Write command is issued, the Write
operation will be followed by an Auto Precharge cycle. If A10 is Low (set to ‘0’), Auto
Precharge is not selected and the row will remain active for subsequent accesses.
Burst Write operations can be performed either at byte or at word level. The CAS Latency for
Burst Write operations is fixed to 1 clock cycle.
UDQS/LDQS input act as the strobe for the input data and UDQM/LDQM select the byte to
be written. UDQS/LDQS must be Low tWPRE prior to their first rising edge; and can be
changed to High-Z tWPST after their last falling edge. These two periods of time are referred
to as Write Preamble and Write Postamble, respectively.
See Table 16, Table 17, Figure 18, Figure 20, and Figure 21, and for a detailed description
of Burst Write ac waveforms and characteristics.
The interval between Burst Write to Burst Write commands are described in Figure 16,
Figure 17, Figure 24 and Figure 25.
4.4
Self Refresh
In the Self Refresh mode, the data contained in the DDR LPSDRAM memory array is
retained and refreshed. The size of the memory array to be refreshed is programmed in the
Extended Mode Register. Only the data contained in the part of the array selected for Self
Refresh will be retained and refreshed. In this respect, this is a power saving feature.
The Self Refresh mode is entered and exited by issuing a Self Refresh Entry and Self
Refresh Exit command, respectively (see Section 3: Commands). When in this mode, the
device is not clocked any more.
When the Automatic Temperature Compensated Self Refresh mode (ATCSR) is enabled,
the internal refresh is adjusted according to die temperature in order to reduce power
consumption.
21/54
Operating modes
4.5
M65KG526AB
Auto Refresh
This command performs the auto refresh of the memory array. The bank and the row
addresses to be refreshed are internally determined by the internal refresh controller.
Issuing an Auto Refresh command, caused the device to execute an auto refresh (see
Section 3: Commands).
4.6
Power-Down
In Power-Down mode, the current is reduced to the active standby current (IDD3P).
The Power-Down mode is initiated by issuing a Power-Down Entry command. tPDEN (1 clock
cycle) after the cycle when this command was issued, the DDR LPSDRAM enters into
Power-Down mode. In Power-Down mode, power consumption is reduced by deactivating
the input initial circuit. There is no internal refresh when the device is in the Power-Down
mode.
The device can exit from Power-Down tPDEX (1 cycle minimum) after issuing a Power-Down
Exit command.
See Section 3: Commands for details on the Power-Down Entry and Exit commands.
4.7
Deep Power-Down
In Deep Power-Down mode, the power consumption is reduced to the standby current
(IDD7).
Before putting the device in the Deep Power-Down mode all the banks must be Idle or have
been precharged.
The Deep Power-Down mode is entered and exited by issuing a Deep Power-Down Entry
and a Deep Power-Down Exit command.
See Section 3: Commands for details on the Power-Down Entry and Exit commands.
Table 6.
Operating modes (1)
KEn-1
KEn
E
RAS
CAS
W
A10
A10,
A11
A0-A9
BA0-BA1
Burst Read
VIH
VIH
VIL
VIH
VIL
VIH
VIL(2)
X
Start Column
Address
Bank
Select
Burst Write
VIH
VIH
VIL
VIH
VIL
VIL
VIL(2)
X
Start Column
Address
Bank
Select
Self Refresh
VIH
VIL
VIL
VIL
VIL
VIH
X
X
Auto Refresh
VIH
VIH
VIL
VIL
VIL
VIH
X
X
Power-Down
VIH
VIL
VIL
VIH
VIH
VIH
X
X
VIH
X
X
X
VIH
VIL
VIL
VIH
VIH
VIL
X
X
Operating mode
Deep Power-Down
1. X = Don’t Care VIL or VIH.
2. If A10 = VIL the Burst Read or Write operation is not followed by an Auto Precharge cycle. If A10 = VIH, the Burst Read or
Write operation is followed by an Auto Precharge cycle to the bank selected by BA0-BA1.
22/54
M65KG526AB
5
Registers description
Registers description
The DDR Mobile RAM has the two mode registers, the Mode Register and the Extended
Mode register.
5.1
Mode Register description
The Mode Register is used to select the CAS Latency, Burst Type, and Burst Length of the
device:
●
The CAS Latency defines the number of clock cycles after which the first data will be
output during a Burst Read operation.
●
The Burst Type specifies the order in which the burst data will be addressed. This order
is programmable either to sequential or interleaved (see Table 5: Burst Type Definition).
●
The Burst Length is the number of words that will be output or input during a Burst
Read or Write operation. It can be configured as 2, 4, 8, or 16 words.
The Mode Register must be programmed at the end of the Power-Up sequence prior to
issuing any command. It is loaded by issuing a Section 3.1: Mode Register Set command
(MRS), with BA0-BA1 are set to ‘00’ to select the Mode Register.
Table 7: Mode Register definition shows the available Mode Register configurations.
Table 7.
Mode Register definition
Address
bits
Mode
Register bit
Register
description
A12-A7
-
-
A6-A4
MR6-MR4
CAS Latency Bits
(Read Operations)
A3
A2-A0
MR3
MR2-MR0
Value
Description
000000
011
3 Clock Cycles
Other configurations reserved
0
Sequential
1
Interleaved
001
2 words
010
4 words
011
8 words
100
16 words
Burst Type Bit
Burst Length Bit
Other configurations reserved
BA1-BA0
-
-
00
23/54
Registers description
5.2
M65KG526AB
Extended Mode Register description
The Extended Mode Register is used to program the low-power Self Refresh operation of
the device:
●
Partial Array Self Refresh
●
Driver Strength
●
Automatic Temperature Compensated Self Refresh.
It is loaded by issuing a Section 3.2: Extended Mode Register Set command (EMRS) with
BA0-BA1 set to ‘01’ to select the Extended Mode Register.
Table 8: Extended Mode Register definition shows the available Extended Mode Register
configurations.
Table 8.
Extended Mode Register definition
Address
bits
Mode
Register bit
Description
A12-A10
-
-
A9
EMR9
A8-A7
A6-A5
A4-A3
A2-A0
-
EMR6-EMR5
-
EMR2-EMR0
Value
000
Automatic Temperature
0
Compensated Self Refresh
1
Bits
-
Description
Enabled
Reserved
00
00
Full Strength
01
1/2 Strength
10
1/4 Strength
11
1/8 Strength
Driver Strength Bits
-
Partial Array Self Refresh
Bits
00
000
All Banks
001
Bank A and Bank B (BA1=0)
010
Bank A (BA0 and BA1 =0)
Other configurations reserved
BA1-BA0
24/54
-
-
10
M65KG526AB
6
Maximum rating
Maximum rating
Stressing the device above the ratings listed in Table 9: Absolute maximum ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 9.
Absolute maximum ratings
Value
Symbol
TJ
Parameter
Unit
Min
Max
Temperature
range option 8(1)
−30
85
°C
Temperature
range option 9(1)
−30
105
°C
Junction Temperature
TSTG
Storage Temperature
−55
125
°C
VIO
Input or Output Voltage
−0.5
2.3
V
VDD, VDDQ
Supply Voltage
−0.5
2.3
V
IOS
Short Circuit Output Current
50
mA
PD
Power Dissipation
1.0
W
1. See Table 18: Ordering Information Scheme.
25/54
DC and ac parameters
7
M65KG526AB
DC and ac parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 10: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 10.
Operating and ac measurement conditions(1)
M65KG512AB
Symbol
VDD
VDDQ(2)
Min
Typ
Max
Supply voltage
1.7
1.8
1.9
V
Input/Output supply voltage
1.7
1.8
1.9
V
CL
Load capacitance
15
pF
VIL
Input pulses voltages
0.2
V
VIH
Input pulses voltages
1.6
V
VDDQ/2
V
1.4
V
VDDQ/2 with VDD=VDDQ
V
1
V/ns
VREF(3)
Input and output timing ref. voltages
VID
Input differential voltage (K and K)
VIX
Input differential cross point voltage (K and K)
tτ or
∆VI/∆ tR
Input signal slew rate
1. All voltages are referenced to VSS.
2. VDDQ must be equal to VDD.
3. Generated internally.
Figure 4.
AC measurement I/O waveform
Clock Timing Reference Voltage
K
VIX
VREF
K
Output Transition Timing Reference Voltage
VDDQ
VREF
0V
Input Transition Timing Voltage
VIH
VIL
∆t
Input Signal Slew Rate = VIH - VIL
∆t
26/54
Units
Parameter
AI10238
M65KG526AB
Figure 5.
DC and ac parameters
AC measurement load circuit
Output
CL
AI12451
Table 11.
Capacitance
M65KG512AB
Symbol
CI1(1)
CI2
CIO(1)(2)
CDI2(1)
Signal
Unit
Min
Max
K, K
2.0
4.5
pF
All other input pins
2.0
4.5
pF
DQ0-DQ15, UDQS/LDQS,
LDQM/UDQM
3.5
6.0
pF
K, K
0.25
pF
All other input pins
0.5
pF
Input capacitance
(1)
CDI1(1)
Parameter
Data I/O capacitance
Delta Input capacitance
1. TJ = 25 °C; VDD and VDDQ = 1.7 to 1.9 V; f = 100 MHz; VOUT = VDDQ/2; ∆VOUT = 0.2 V.
2. Data Output are disabled.
Table 12.
Symbol
DC Characteristics 1
Parameter
M65KG512AB
Test Condition(1)
Unit
Min
Max
ILI
Input leakage current
0V≤ VIN ≤ VDDQ
-2.0
2.0
µA
ILO
Output leakage current
0V≤ VOUT ≤ VDDQ,
DQ0-DQ15 disabled.
-1.5
1.5
µA
VIH(2)
Input High voltage
VIN = 0 V
0.8VDDQ
VDDQ+0.3
V
VIL(3)
Input Low voltage
VIN = 0 V
-0.3
0.2VDDQ
V
VOL
Output Low voltage
IOUT = 100 µA
0.1VDDQ
V
VOH
Output High voltage
IOUT = −100 µA
VIN
Input voltage level for K and K inputs
VIX
Input differential cross point voltage for K
and K inputs
0.4VDDQ 0.5VDDQ
0.6VDDQ
V
VID
Input differential voltage for K and K inputs
0.4VDDQ
VDDQ+0.6
V
0.9VDDQ
-0.3
V
VDDQ+0.3
1. VDD and VDDQ = 1.7 to 1.9 V; VSS and VSSQ = 0 V.
2. VIH maximum value = 2.3 V (pulse width ≤ 5 ns).
3. VIL minimum value = -0.5 V (pulse width ≤ 5 ns).
27/54
DC and ac parameters
Table 13.
M65KG526AB
DC characteristics 2(1)
M65KG512AB
Symbol
Parameter
−30 to 85°C −85 to 105°C Unit
Test Condition
Max
IDD1(2)
Operating current
IDD2P
Precharge Standby
current in Power-Down
mode
IDD2PS
IDD2N
Precharge Standby
current in non PowerDown mode
IDD2NS
IDD3P
Active Standby current
in Power-Down mode
70
KE ≤ VIL(max), tCK = tCK(min)
0.8
1.4
KE ≤ VIL(max), tCK = ∞
0.6
1.2
133 MHz
4.0
4.6
166 MHz
5.0
6.0
2.0
2.6
133 MHz
3.0
3.1
166 MHz
3.0
4.0
1.2
1.8
KE ≥ VIH (min), E ≥ VIH (min),
tCK = tCK(min), Input signals
changed once in 2 clock cycles.
KE ≥ VIH (min), tCK = ∞, Input signals are
stable
KE ≤ VIL(max), tCK = tCK(min)
Active Standby current
in non Power-Down
mode
IDD3NS
75
80
KE ≥ VIH (min), E ≥ VIH (min), tCK = tCK(min),
Input signals are changed once in 2 clock
cycles.
10.0
KE ≥ VIH (min), tCK = ∞, Input signals are
stable
7.0
tCK ≥ tCK (min), IOL = 0 mA
All banks active,
Burst Length = 4
133 MHz
IDD4(2)
Burst Mode current
IDD5(3)
Auto Refresh current
tRRC ≥ tRRC (min)
IDD6
Self Refresh current
KE ≤ 0.2 V
IDD7
Standby current in Deep KE ≤ 0.2 V (see Section 4.7: Deep PowerPower-down mode
Down)
166 MHz
90.0
140
mA
mA
mA
180
mA
90.0
mA
See Table 14
µA
10
µA
2. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
28/54
mA
mA
1. VDD and VDDQ = 1.7 to 1.9V, VSS = VSSQ = 0V.
3. Addresses change only once during tCK.
mA
mA
KE ≤ VIL(max), tCK = ∞
IDD3PS
IDD3N
Burst length = 2, one bank active 133 MHz
tRC ≥ tRC(min), IOL = 0 mA
166 MHz
M65KG526AB
Table 14.
DC and ac parameters
Self Refresh current (IDD6) in normal operating mode
Memory array(1)
Temperature
in °C
All banks
Typ
85 ≤ TJ ≤ 105
2 banks
Max
Typ
2.2
1 banks
Max
1.2
Typ
Unit
Max
0.8
70 ≤ TJ ≤ 85
800
650
490
40 ≤ TJ ≤ 70
550
380
290
–30 ≤ TJ ≤ 40
300
240
210
µA
1. VDD and VDDQ = 1.7 to 1.9 V, VSS = VSSQ = 0V; KE ≤ 0.2 V.
Table 15.
AC characteristics(1) - TJ = −30 to 85 °C
M65KG512AB
Symbol
Alt
tAC(2)
Parameter
Unit
Min
Max
Data Output access time from K and K
2.0
6.0
ns
tAS(3)
tIS
Address and Control Input setup time
1.3
ns
(3)
tIH
Address Control Input hold time
1.3
ns
tCK
Clock Cycle Time
7.5
ns
tDAL
Autoprecharge write recovery and precharge time
tWR+tRP
ns
tAH
tDQSCK(2)
UDQS/LDQS access time from K and K
2.0
6.0
ns
Data Output and LDQM/UDQM inputs pulse width
1.75
tDQSHZ(4)
UDQS/LDQS High-Z Time from K and K
1.5
6.0
ns
tDQSLZ(6)
UDQS/LDQS Low-Z time from K and K
1.5
6.0
ns
tDQSQ(3)
UDQS/LDQS to Data Output skew
0.65
ns
tDIPW
ns
tDS(3)
Data Input and UDQM/LDQM setup time
0.8
ns
tDH(3)
Data Input and UDQM/LDQM hold time
0.8
ns
3
ns
Addresses and control pulse width
tIPW
tOHZ(4)
tHZ
Data Output High-Z time from K and K
1.0
6.0
ns
tOLZ(5)
tLZ
Data Output Low-Z time from K and K
1.0
6.0
ns
tQH
Data and LDQS/UDQS Output hold time from DQS
tHP-tQHS
ns
tQHS
Data hold skew factor
tRAS
RAS Active Time (Bank (Row) Activate to Bank Precharge)
45
tRC
RAS Cycle Time (Bank (Row) Activate to Bank Activate in Auto
Refresh mode)
75
ns
tRFC
RAS Cycle Time (Auto Refresh to Bank Active in Auto Refresh
mode)
108
ns
tRCD
Delay Time, from RAS Active to CAS active
30
ns
tRRD
Delay Time, from RAS Active to RAS Bank active
15
ns
0.75
ns
120000
ns
29/54
DC and ac parameters
M65KG526AB
AC characteristics(1) - TJ = −30 to 85 °C (continued)
Table 15.
M65KG512AB
Symbol
Alt
Parameter
Unit
Min
tRP
RAS Precharge time
tREF
Average Periodic Refresh time
tSRE
tSREX
22.5
ns
7.8
Self Refresh Exit Time
µs
165
ns
0
ns
Write Preamble setup time
tWPRES
Max
1. The above timings are measured according to the test conditions shown in Table 10: Operating and ac measurement
conditions with driver strength set to “Full Strength” (EMR5 to EMR6 = ‘00’).
2. These timings define the signal transition delays from K or K cross point, that is when K or K signal crosses VREF.
3. The timing reference level is VREF.
4. tOHZ and tDQSHZ define the transition time from Low-Z to High-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst
Read operation, respectively. They specify when data outputs stop being driven.
5. tOLZ and tDQSLZ define the transition time from High-Z to Low-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read
operation. They specify when data outputs begin to be driven.
AC characteristics(1) - TJ = −30 to 105 °C
Table 16.
M65KG512AB
Symbol
Alt
tAC(2)
Parameter
133MHz
166MHz
Min
Max
Min
Max
Data Output access time from K and K
1.5
6.0
2.0
5.0
Unit
ns
tAS(3)
tIS
Address and Control Input setup time
1.4
1.4
ns
tAH(3)
tIH
Address Control Input hold time
1.4
1.4
ns
Clock Cycle Time
7.5
6.0
ns
UDQS/LDQS access time from K and K
1.5
Data Output and LDQM/UDQM inputs pulse width
1.8
tDQSHZ(4)
UDQS/LDQS High-Z Time from K and K
1.5
6.0
1.5
4.5
ns
tDQSLZ(6)
UDQS/LDQS Low-Z time from K and K
1.5
6.0
1.5
4.5
ns
tDQSQ(3)
UDQS/LDQS to Data Output skew
0.5
ns
tCK
tDQSCK(2)
tDIPW
6.0
2.0
5.0
1.75
0.65
ns
ns
tDS(3)
Data Input and UDQM/LDQM setup time
0.9
0.9
ns
tDH(3)
Data Input and UDQM/LDQM hold time
0.9
0.9
ns
tDAL
Data Input Valid to Precharge command
2tCK+22.5
tWR+tRP
ns
tIPW
Addresses and control pulse width
2.8
2.7
ns
tOHZ(4)
tHZ
Data Output High-Z from K and K
1.5
6.0
1.0
5.5
ns
tOLZ(5)
tLZ
Data Output Low-Z from K and K
1.5
6.0
1.0
5.5
ns
30/54
tQH
Data and LDQS/UDQS Output hold time from
DQS
tQHS
Data hold skew factor
tRAS
RAS Active Time (Bank (Row) Activate to Bank
Precharge)
tHP-tQHS
tHP-tQHS
0.75
60
120000
54
ns
0.65
ns
120000
ns
M65KG526AB
DC and ac parameters
AC characteristics(1) - TJ = −30 to 105 °C (continued)
Table 16.
M65KG512AB
Symbol
Alt
Parameter
133MHz
Min
166MHz
Max
Min
Unit
Max
tRC
RAS Cycle Time (Bank (Row) Activate to Bank
Activate in Auto Refresh mode)
90
84
ns
tRFC
RAS Cycle Time (Auto Refresh to Bank Active in
Auto Refresh mode)
150
150
ns
tRCD
Delay Time, from RAS Active to CAS active
37.5
36
ns
tRRD
Delay Time, from RAS Active to RAS Bank active
15
18
ns
22.5
24
ns
RAS Precharge time
tRP
tREF
TJ = −30
to 85 °C
7.8
7.8
µs
TJ = 85
to 105 °C
1.95
1.95
µs
Average Periodic Refresh time
tSREX Self Refresh Exit Time
tSRE
tWPRES
Write Preamble setup time
165
165
ns
0
0
ns
1. The above timings are measured according to the test conditions shown in Table 10: Operating and ac measurement
conditions with driver strength set to “Full Strength” (EMR5 to EMR6 = ‘00’).
2. These timings define the signal transition delays from K or K cross point, that is when K or K signal crosses VREF.
3. The timing reference level is VREF.
4. tOHZ and tDQSHZ define the transition time from Low-Z to High-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read
operation, respectively. They specify when data outputs stop being driven.
5. tOLZ and tDQSLZ define the transition time from High-Z to Low-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read
operation. They specify when data outputs begin to be driven.
Table 17.
AC characteristics measured in clock period
M65KG512AB
Symbol
Alt
Parameter
133MHz
Min
Max
166MHz
Min
Unit
Max
tBSTW(1)
Burst Read Terminate Command to Write
Command Delay Time
3
3
tCK
tBSTZ(1)
Burst Read Terminate Command to Data Output
Hi-Z
3
3
tCK
tCHW
tCLW
tHP
Clock High Pulse Width
0.45
0.55
0.45
0.55
tCK
Clock Low Pulse Width
0.45
0.55
0.45
0.55
tCK
tCKE
Clock Enable pulse width
2
2
tCK
tDMD
UDQM/LDQM to Data Input Latency
0
0
tCK
tDSC
LDQS/UDQS cycle time
0.9
1.1
0.9
1.1
tCK
tDQSS
Write Command to First UDQS/LDQS latching
transition
0.75
1.25
0.75
1.25
tCK
31/54
DC and ac parameters
Table 17.
M65KG526AB
AC characteristics measured in clock period (continued)
M65KG512AB
Symbol
Alt
Parameter
133MHz
Min
Max
166MHz
Min
Unit
Max
tDSS(4)
UDQS/LDQS Falling Edge to K Setup Time
0.2
0.2
tCK
tDSH(4)
UDQS/LDQS Falling Edge Hold Time from K
0.2
0.2
tCK
tDQSH
UDQS/LDQS High Pulse Width
0.35
0.35
tCK
tDQSL
UDQS/LDQS Low Pulse Width
0.35
0.35
tCK
tDPE
tPDEN Power-Down Entry Time
2
2
tCK
tDPX
tPDEX Power-Down Exit Time
1
1
tCK
2
2
tCK
3
3
tCK
tCK
tMRD
tPROZ(1)
Mode Register Set Cycle Time
tHZP Precharge Command to Data Output High-Z
tRPD
Delay Time from Read to Precharge Command
(same Bank)
BL/2(2)
BL/2(2)
tRWD
Delay Time from Read to Write Command (all
data output)
3+BL/2
3+BL/2
(2)
(2)
tRPRE
Read Preamble Time
0.9
1.1
0.9
1.1
tCK
tRPST
Read Postamble Time
0.4
0.6
0.4
0.6
tCK
tSRE
tSREX Self Refresh Exit Time
TJ = −30 to 85 °C
16
TJ =−30 to 105 °C
22
27
tCK
tCK
tCK
tWPD
Delay Time from Write to Precharge Command
(same Bank)
3+BL/2
3+BL/2
(2)
(3)
tWRD
Delay Time from Write to Read Command
(all data input)
2+BL/2
2+BL/2
(2)
(2)
tCK
tWCD
Write Command to Data Input Latency
1
1
tCK
tWR
Write Recovery Time
tWTR
Internal Write to Read
command Delay
tWPRE
tWPST(4)
TJ = −30 to 85 °C
tCK
tCK
2
TJ =−30 to 105 °C
3
tCK
TJ = −30 to 85 °C
1
TJ =−30 to 105 °C
2
2
tCK
Write Preamble
0.25
0.25
tCK
Data Strobe Low Pulse Width (Write Postamble)
0.4
tCK
0.6
0.4
0.6
tCK
1. CAS Latency equals 3 clock cycles.
2. BL stands for Burst Length.
3. BL stands for Burst Length.
4. The transition for Low-Z to High-Z occur when the device outputs become floating. No specific reference voltage is given in
this document.
32/54
M65KG526AB
Figure 6.
DC and ac parameters
Definition of command and address inputs timings
K
K
tAS
Command
(RAS, CAS, W, E)
tAH
Addresses
ai12455
Figure 7.
Definition of Read timings 1/2
K
K
Command
READ
tOHZ(min)
tOLZ(max)
tOLZ(min)
tOHZ(max)
Hi-Z
DQ0-DQ15
(output)
tDQSHZ(max)
tDQSLZ(min)
tDQSHZ(min)
Hi-Z
tDQSLZ(max)
Hi-Z
UDQS, LDQS
ai12456b
Figure 8.
Definition of Read timings 2/2
K
K
tAC(max)
tAC(min)
Hi-Z
Hi-Z
DQ0-DQ15
(Output)
tDQSCK
tDQSQ
Hi-Z
Hi-Z
UDQS, LDQS
tDSC
tQH
ai12457
33/54
DC and ac parameters
Figure 9.
M65KG526AB
Consecutive Bank(Row) Activate command
K
K
tRRD
Command
ACT
A CT
Address
Row 0
Row 1
NOP
ACT
NOP
PRE
NOP
Row 0
tRC
BA0-BA1
Bank A
Active
Bank D
Active
Bank A
Active
Precharge
Bank A
ai11210
1. The above figure shows consecutive Bank(Row) Activate commands issued to different banks. A tRRD delay must be
respected between two consecutive Bank(Row) Activate commands (ACT) to different banks. If the destination row is
already active, the bank must be precharged to close the row; the ACT command can then be issued tRP after the PRE
command.
2. Consecutive ACT commands to the same bank must be issued at a tRC interval and separated by a Precharge command
(PRE).
Figure 10. Read followed by Read in same bank and row
t0
t1
t2
ACT
NOP
READ
t3
t4
t5
t6
t7
t8
K
K
Command
Address
Row
NOP
READ
Column A Column B
BA0-BA1
Read from
Column A
Read from
Column B
DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
DQ0-DQ15
UDQS, LDQS
Bank A
Active
Note: 1. Burst Length = 4
2. CAS Latency = 3
3. Bank = Bank A
Data Read from
Column A
Data Read from
Column B
ai11205
1. The consecutive READ command must be issued after a minimum delay of tCK to interrupt the previous Read operation.
2. To issue the consecutive READ to a different row, precharge the bank (PRE) to interrupt the previous Read operation. tRP
after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD after the ACT
command.
34/54
M65KG526AB
DC and ac parameters
Figure 11. Read followed by Read in a different bank
t0
t1
t2
t3
t4
t5
Command
ACT
NOP
ACT
NOP
READ
READ
Address
Row 0
t6
t7
t8
t9
t10
K
K
NOP
Column A Column B
Row 1
BA0-BA1
Read from Read from
Column A Column B
DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
DQ0-DQ15
UDQS/
LDQS
Bank A
Active
Read from Read from
Bank D
Bank A
Bank D
Active
Data Read from
Bank A
Data Read from
Bank D
Note: 1. Burst Length = 4
2. CAS Latency = 3
ai11206
1. If the consecutive Read operation targets an active row, the second READ command must be issued after a minimum
delay of tCK to interrupt the previous Read operation.
2. If the consecutive Read operation targets an idle row, precharge the bank (PRE) without interrupting the previous Read
operation. tRP after the PRE command, issue the ACT command. The consecutive READ command can be issued tRCD
after the ACT command.
Figure 12. Read with Auto Precharge
K
K
tRP (min)
tRAS
tRPD
tRCD
Command
ACT
READA
NOP
ACT
UDQS, LDQS
tAC
tDQSCK
DO0 DO1 DO2 DO3
DQ0-DQ15
Note: Burst Length = 2
Start of
Internal
Auto Precharge cycle
ai10586
35/54
DC and ac parameters
M65KG526AB
Figure 13. Read followed by Auto Precharge ac waveforms
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tCK
K
K
tCHW
tCLW
tRP
KE
tRC
E
tRAS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
tAS
tAH
tAS
tAH
tAS
tAH
tAH
LDQM/
UDQM
tDQSLZ
tRPST
tRPRE
LDQS/
UDQS
tDQSQ
DQ0-DQ15
Hi-Z
DO0 DO1 DO2 DO3
tRCD
tDV
tDQSHZ
tAC,
tDQSCK
Bank(Row) Activate
in Bank A
Read
from Bank A
1. Burst Length = 4 words, CAS Latency = 3 clock cycles.
36/54
Precharge
in Bank A
Bank(Row) Activate
in Bank A
AI11212b
M65KG526AB
DC and ac parameters
Figure 14. Read operation (Burst lengths = 2, 4 and 8, CAS latency = 3)
t0
t1
t2
t3
t4
t5
t6
K
K
tRCD
Command
NOP
ACT
A0-A12
BA0-BA1
NOP
Row
Address
READ
NOP
Column
Address
tRPST
tRPRE
UDQS,
LDQS(1)
tAC
tDQSCK
DO0 DO1
DQ0-DQ15(1)
UDQS,
LDQS(2)
DO0 DO1 DO2 DO3
DQ0-DQ15(2)
UDQS,
LDQS(2)
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7
DQ0-DQ15(2)
Notes: 1. Burst Length = 2
2. Burst Length = 4
3. Burst Length = 8.
4. In all cases, CAS Latency = 3.
ai10552
Figure 15. Burst Terminate during Read operation
t0 t0.5
t1 t1.5
t2 t2.5
t3 t3.5
t4
t4.5
t5
t5.5
K
K
Command
READ
BST
NOP
tBSTZ
UDQS,
LDQS
DQ0-DQ15
DO0 DO1
ai10585
37/54
DC and ac parameters
M65KG526AB
Figure 16. Write followed by Write in same bank and row
t0
t1
t2
ACT
NOP
WRIT
t3
t4
t5
t6
t7
t8
K
K
Command
Address
Row
WRIT
NOP
Column A Column B
BA0-BA1
DIA0 DIA1 DIB0 DIB1 DIB2 DIB3
DQ0-DQ15
UDQS, LDQS
Bank A
Active
Note: 1. Burst Length = 4
2. Bank = Bank A
Data Written to
Column A
Data Written to
Column B
ai11207
1. The consecutive WRIT command must be issued after a minimum delay of tCK to interrupt the previous Write operation.
2. To issue the consecutive WRITE to a different row, precharge the bank (PRE) to interrupt the previous Write operation. tRP
after the PRE command, issue the ACT command. The consecutive WRIT command can be issued tRCD after the ACT
command.
38/54
M65KG526AB
DC and ac parameters
Figure 17. Write followed by Write in a different bank
K
K
Command
ACT
NOP
ACT
NOP
WRIT
NOP
WRIT
tRCD
Address
Row 0
Column A Column B
Row 1
BA0-BA1
DIA0 DIA1
DQ0-DQ15
DIB0 DIB1 DIB2 DIB3
UDQS/
LDQS
Bank A
Active
Data Read from
Bank A
Bank D
Active
Data Read from
Bank D
ai11208b
Note: 1. Burst Length = 4
1. If the consecutive Write operation targets an active row, the second WRIT command must be issued after a minimum delay
of tCK to interrupt the previous Write operation.
2. If the consecutive Write operation targets an idle row, precharge the bank (PRE) without interrupting the previous Write
operation. tRP after the PRE command, issue the ACT command. The consecutive WRIT command can be issued tRCD
after the ACT command.
Figure 18. Write operation with Auto Precharge
K
K
tRAS(min)
tRP
tRCD
Command
ACT
NOP
WRITEA
NOP
ACT
UDQM, LDQM
tWPD
UDQS, LDQS
DQ0-DQ15
Note: Burst Length = 4
DI0
DI1
DI2
DI3
Start of
Internal
Auto Precharge cycle
ai10587c
39/54
DC and ac parameters
M65KG526AB
Figure 19. Write with Auto Precharge ac Waveforms
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tCK
K
K
tCHW
tCLW
tRP
KE
tRC
E
tRAS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
tAS
tAH
tAS
tAH
tDIPW
tAS
tAH
tAH
LDQM/
UDQM
tDQSL
tDQSS
LDQS/
UDQS
tWPRE
tWPST
tDS
DQ0-DQ15
tDSH
Hi-Z
D
IN
tRCD
D
IN+3
tDH
tDIPW
Bank A
Active
D
IN+2
Write
to Bank A
tDQSH
tWR
Precharge
in Bank A
Bank A
Active
AI11213d
1. Burst Length = 4 words, CAS Latency = 1 clock cycle.
40/54
M65KG526AB
DC and ac parameters
Figure 20. Write operation (Burst lengths = 2, 4 and 8, CAS latency = 1)
t0
t1
t2
t3
t4
t5
t6
K
K
tRCD
Command
A0-A12
BA0-BA1
NOP
ACT
NOP
Row
Address
WRITE
NOP
Column
Address
tWPRE
UDQS,
LDQS(1)
tWPRES
DQ0-DQ15(1)
DI0
DI1
tWPST
UDQS,
LDQS(2)
DQ0-DQ15(2)
DI0
DI1
DI2
DI3
DI0
DI1
DI2
DI3
UDQS,
LDQS(2)
DQ0-DQ15(2)
Notes: 1. Burst Length = 2
2. Burst Length = 4
3. Burst Length = 8.
4. In all cases, CAS Latency = 1.
DI4
DI5
DI6
DI7
ai10553
41/54
42/54
1. Burst Length = 4 words.
UDQM
LDQM
Hi-Z
Hi-Z
t2
tCLW
tAH
tAS
t1
Bank/Row Activate
Read
in Bank D
from Bank D
DQ8-DQ15
DQ0-DQ7
t0
High
tAH
tAS
LDQS/
UDQS
tCK
tCHW
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
K
t3
tWPRE
t4
Lower Byte
Read
t5
t6
t7
Upper Byte
Read
tWPST
t8
tAH
t10
tDQSS
tAS
t9
tDQSL
t14
Read from
Bank D
tAH
tAS
t13
Upper Byte
Write
t12
Lower Byte
Write
Upper Byte
Write
t11
t15
t16
t18
Upper Byte
Read
t17
t19
AI11218b
Upper Byte
Read
t20
DC and ac parameters
M65KG526AB
Figure 21. AC Write ac waveforms (data masking using LDQM/UDQM)
M65KG526AB
DC and ac parameters
Figure 22. Mode Register/Extended Mode Register Set commands ac waveforms
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
K
K
High
KE
tMRD
E
RAS
CAS
W
BA0-BA1
A10
MR
Address
Data (2)
LDQM/
UDQM
LDQS/ Hi-Z
UDQS
DQ0-DQ15
(OUT)
Hi-Z
tRP
Precharge
(optionnal)
Mode Register
Set
Bank D
Active
Read to
Bank D
Precharge
Bank D
AI11214b
1. To program the Extended Mode Register, BA0 and BA1 must be set to ‘0’ and ‘1’ respectively, and A0 to A11 to the
Extended Mode Register Data.
2. MR Data is the value to be written to the Mode Register.
43/54
DC and ac parameters
M65KG526AB
Figure 23. Read followed by Write using the Burst Read Terminate command (BST)
t0
t1
READ
BST
t2
t3
t4
t6
t5
t7
t8
K
K
Command
WRIT
NOP
NOP
tBSTW ( ≥tBSTZ)
UDQM,
LDQM
tBSTZ ( = CL)
DQ0-DQ15
DO0 DO1
DI0
DI1
DI2
DI3
UDQS,
LDQS
Data Output
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
Data Input
ai11209b
1. If the Write operation is performed to the same bank and row than the Read operation, the Burst Read Terminate command
(BST) must be issued to terminate the Read operation.The WRIT command can then be issued tBSTW (ŠtBSTW) after the
BST command.
2. If the Write operation is performed to the same bank but to a different row, the bank must be precharged to interrupt the
Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued tRCD
after the ACT command.
3. If the Write operation is performed to a different bank and to an active row, the sequence is identical to the one described in
Note 1
4. If the Write operation is performed to a different bank and to an idle row, the bank must be precharged independently from
the Read operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued
tRCD after the ACT command.
44/54
M65KG526AB
DC and ac parameters
Figure 24. Write followed by Read (Write completed)
t0
t1
t2
t3
t4
t5
t6
t7
t8
K
K
Command
WRIT
READ
NOP
NOP
tWRDmin (3)
UDQM,
LDQM
DQ0-DQ15
DI0
DI1
DI2
DI3
DO0 DO1 DO2 DO3
UDQS,
LDQS
Data Input
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
3. tWRD = BL/2 + 2 clock cycles
Data Output
ai10838b
1. If the Read operation is performed to the same bank and row than the Write operation, the READ command should be
performed tWRD after the WRIT command to complete the Write operation.
2. If the Read operation is performed to the same bank but to a different row, the bank must be precharged tWPD after the
Write operation. tRP after the Precharge command, issue the ACT command. The READ command can then be issued
tRCD after the ACT command.
3. If the Read operation is performed to a different bank and to an active row, the sequence is identical to the one described in
Note 1
4. If the Read operation is performed to a different bank and to an idle row, the bank must be precharged independently from
the Write operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued
tRCD after the ACT command.
45/54
DC and ac parameters
M65KG526AB
Figure 25. Write followed by Read in the same Bank and Row (Write Interrupted)
t0
t1
WRIT
READ
t2
t3
t4
t6
t5
t7
t8
K
K
Command
NOP
UDQM,
LDQM
DQ0-DQ15
DI0
DI1
DI2
DO0 DO1 DO2 DO3
UDQS,
LDQS
Data Input Masked
Data Output
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
ai10839
1. UDQM/LDQM must be input 1 clock cycle prior to the READ command to prevent invalid data from being written. If the
READ command is input on the next cycle after the WRIT command, UDQM/LDQM are not necessary.
2. If the Read operation is issued to a different row in the same bank, or to an idle row in a different bank, a Precharge
command (PRE) must be issued before the READ command. In this case, the Read operation does not interrupt the Write
operation.
3. If the Read operation is issued to a different bank, and to an active row, the sequence is identical to the one described in
Note 1.
46/54
K
High
Precharge
All Banks
High 1 Clock Cycle needed
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
EMR
Data (1)
tMRD
Mode
Extended Mode
CBR
Register Set Register Set Auto Refresh
tRP
MR
Data (1)
tMRD
tRFC
CBR
Auto Refresh
tRFC
2 Refresh Cycles needed
Bank(Row)
Activate
AI11211b
M65KG526AB
DC and ac parameters
Figure 26. Power-Up sequence
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
47/54
DC and ac parameters
M65KG526AB
Figure 27. Auto Refresh command ac waveforms
t0
t1
t2
t3
t4
t5
t6
tm
tm+1
tm+2
tm+3
tm+4
tm+5
tm+6
tm+7
tm+8
tm+9
K
K
High
KE
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM/
UDQM
LDQS/
UDQS
Hi-Z
DQ0-DQ15
(OUT)
Hi-Z
DQ0-DQ15
(IN)
Hi-Z
tRP
Precharge
(optional)
tRFC
Auto Refresh
1. Burst Length = 4 words, CAS Latency = 3 clock cycles.
48/54
Bank A
Active
Read from
Bank A
AI11215b
M65KG526AB
DC and ac parameters
Figure 28. Self Refresh Entry and Exit commands ac waveforms
t0
t1
t2
t3
t4
t5
tn
tn+1
tn+2
tm
tm+1 tm+2
tm+3 tm+4
tm+5
K
K
tAS
tAH
KE
tCKE
E
RAS
CAS
W
BA0
BA1
A10
Address
LDQM/
UDQM
UDQS/
LDQS
DQ0-DQ15
(OUT)
DQ0-DQ15
(IN)
Hi-Z
Hi-Z
Hi-Z
tRP
Precharge
(optional)
tSRE
Self Refresh
Entry
Self Refresh
Exit
Bank A
Active
Read to
Bank A
ai11216c
1. Burst Length = 4 words.
49/54
DC and ac parameters
M65KG526AB
Figure 29. Deep Power-Down Entry command ac waveforms
t0
t1
t2
t3
t4
t5
K
K
KE
E
RAS
CAS
W
A10
UDQM/ Low
LDQM
DQ0-DQ15
Hi-Z
tRP
Precharge
All Banks
Deep Power-Down
Entry
ai10847b
1. BA0, BA1 and address bits A0 to A11 (except A10) are ‘Don’t Care’. Upper and Lower Data Input Mask signals, UDQM and
LDQM are Low, VIL.
50/54
High
t1
t2
Precharge
All Banks
200µs
High Level nedeed
1 Clock Cycle needed
t0
Deep
Power-Down
Exit
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
K
t5
EMR
Data (1)
t6
t7
tMRD
t8
Mode
Extended Mode Auto Refresh
Register Set Register Set
tRP
t4
MR
Data (1)
tMRD
t3
t9
tRFC
t10
t11
t13
Auto Refresh
t12
t14
t15
t17
t18
tRFC
t19
t20
t21
AI11217b
Bank/Row Activate
2 Refresh Cycles needed
t16
M65KG526AB
DC and ac parameters
Figure 30. Deep Power-Down Exit ac waveforms
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
51/54
Part numbering
8
M65KG526AB
Part numbering
Table 18.
Ordering Information Scheme
Example:
M65KG512AB
8
W
8
Device Type
M65 = Low-Power SDRAM
Architecture
K = Bare Die
Operating Voltage
G = VDD = VDDQ = 1.8 V, DDR LPSDRAM, x16
Array Organization
512 = 4 Banks x 8 Mbit x 16
Number of Chip Enable Inputs
A = One Chip Enable
Die Version
B = B-Die
Speed
8 = 7.5ns (Clock frequency 133 MHz)
6 = 6.0ns (Clock frequency 166 MHz)
Delivery Form
W = Wafer form
Temperature Range
8 = −30 to 85 °C(1)
9 = −30 to 105 °C
1. Only available with speed class 133 MHz.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the ST Sales Office nearest to you.
52/54
M65KG526AB
9
Revision history
Revision history
Table 19.
Document revision history
Date
Revision
31-Jan-2006
1.0
04-Sep-2006
01-Feb-2007
Changes
Initial release.
2
Speed class 166MHz added.
Temperature range −25 to 85°C changed to −30 to 85°C, and
associated to speed class 7.5ns (133MHZ). Temperature range
−30 to 105°C added for both 6.0ns (166MHz) and 7.5ns
(133MHz).
Figure 3: Simplified command state diagram updated.
Ambient temperature TA changed to junction temperature TJ.
Table 9: Absolute maximum ratings, Table 13: DC
characteristics 2, Table 14: Self Refresh current (IDD6) in
normal operating mode, Table 15: AC characteristics - TJ = -30
to 85 °C, Table 16: AC characteristics - TJ = -30 to 105 °C, and
Table 17: AC characteristics measured in clock period, updated
accordingly.
Figure 7, Figure 13, Figure 19, Figure 21, Figure 21, Figure 26,
Figure 27, Figure 28, Figure 29, and Figure 30 updated.
New speed classes and temperature range options added in
Table 18: Ordering Information Scheme.
3
Section 2.10: Lower/Upper Data Input Mask (LDQM, UDQM)
and Section 2.11: Lower/Upper Data Read/Write Strobe
Input/Output (LDQS, UDQS) modified.
Section 3.3: Bank(Row) Activate command (ACT) and
Section 3.5: Read with Auto Precharge command (READA)
updated.
Column address updated in Section 3.7: Write command
(WRIT), Section 4.2: Burst Read and Section 4.3: Burst Write.
Interval between Auto Refresh commands modified in
Section 3.12: Auto Refresh command (REF).
Table 4 updated and Note 1 removed.
Section 4.2: Burst Read, Section 4.4: Self Refresh and
Section 4.5: Auto Refresh updated.
tSRE added in Table 15 and Table 16.
Figure 17, Figure 18, Figure 21, Figure 23, and Figure 24
updated.
53/54
M65KG526AB
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