M68AF031A 256 Kbit (32K x 8) 5.0V Asynchronous SRAM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 4.5 to 5.5V 32K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55, 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN PACKAGES – SO28, PDIP28, TSOP28 Standard and Reverse Pinout. – TSOP28 Standard Available in Lead-Free Version Figure 1. Packages SO28 (MS) 28 1 PDIP28 (B) TSOP28 (N) 8 x 13.4mm TSOP28 (NS) 8 x 13.4 mm (Reverse) November 2004 1/22 M68AF031A TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TSOP Connections (Normal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TSOP Connections (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Figure 8. Figure 9. Table 4. Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DC Characteristics (M68AF031A-55 and M68AF031A-70) . . . . . . . . . . . . . . . . . . . . . . . . 9 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10.Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 11.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . 11 Figure 12.Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 14.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 15.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 16.SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Outline . . . . . . . . 16 Table 10. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Mechanical Data . 16 Figure 17.PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . 17 Table 11. PDIP28 - 28 pin Plastic DIP, n600 mils width, Package Mechanical Data . . . . . . . . . . . 17 Figure 18.TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Outline . . . . . . . . . . . 18 Table 12. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data . . . 18 2/22 M68AF031A Figure 19.TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Outline . . . . . . . . . . 19 Table 13. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data. . . 19 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3/22 M68AF031A SUMMARY DESCRIPTION The M68AF031A is a 256 Kbit (262,144 bit) CMOS SRAM, organized as 32,768 bytes. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply. This device has an automatic powerdown feature, reducing the power consumption by over 99% when deselected. The M68AF031A is available in SO28 (28-lead Small Outline), PDIP28 (28-pin Plastic Dual-In- Line) and TSOP28 (28-lead Thin Small Outline, Standard and Reverse Pinout) packages. In addition to the standard version, the TSOP28 Standard package is also available in Lead-free version (standard and Tape & Reel packing), in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. It is also compliant with Lead-free soldering processes. Figure 2. Logic Diagram Table 1. Signal Names VCC 16 8 A0-A14 DQ0-DQ7 W M68AF031A E G VSS AI05920C 4/22 A0-A14 Address Inputs DQ0-DQ7 Data Input/Output E Chip Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground NC Not Connected Internally M68AF031A Figure 3. SO Connections A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 DQ1 DQ2 VSS Figure 5. TSOP Connections (Normal) 1 2 3 4 5 6 7 M68AF031A 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W A4 A3 A2 A1 G A0 E DQ7 DQ6 DQ5 DQ4 DQ3 G A1 A2 A3 A4 W 22 21 VCC A5 A6 A7 A8 A9 A10 A11 28 1 M68AF031A 15 (Normal) 14 7 AI07200C AI05921C Figure 4. DIP Connections A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 DQ1 DQ2 VSS 8 A0 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A14 A13 A12 Figure 6. TSOP Connections (Reverse) 1 2 3 4 5 6 7 M68AF031A 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AI05922C VCC W A4 A3 A2 A1 G A0 E DQ7 DQ6 DQ5 DQ4 DQ3 A11 A10 A9 A8 A7 A6 A5 VCC W A4 A3 A2 A1 G 7 1 28 22 8 M68AF031A (Reverse) 14 15 21 A12 A13 A14 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E A0 AI07201C 5/22 M68AF031A Figure 7. Block Diagram A14 ROW DECODER MEMORY ARRAY A7 DQ7 I/O CIRCUITS COLUMN DECODER DQ0 A0 A6 E W G AI05919 6/22 M68AF031A MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1 sec periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol Value Unit Output Current 20 mA PD Power Dissipation 1 W TA Ambient Operating Temperature –55 to 125 °C (1) °C IO (1) Parameter TLEAD Lead Temperature during Soldering TSTG Storage Temperature –65 to 150 °C VCC Supply Voltage –0.5 to 6.5 V –0.5 to VCC +0.5 V VIO (2) Input or Output Voltage Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 6.0V only. 3. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 7/22 M68AF031A DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M68AF031A VCC Supply Voltage 4.5 to 5.5V Range 1 0 to 70°C Range 6 –40 to 85°C Ambient Operating Temperature Load Capacitance (CL) 100pF Output Circuit Protection Resistance (R1) 3.0kΩ Load Resistance (R2) 3.1kΩ Input and Output Timing Ref. Voltages VCC/2 Input Rise and Fall Times 1ns/V 0 to VCC Input Pulse Voltages VRL = 0.3VCC; VRH = 0.7VCC Output Transition Timing Ref. Voltages Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit VCC I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST OUT CL Output Timing Reference Voltage VCC 0V R2 0.7VCC 0.3VCC AI05831 CL includes probe capacitance AI05932 8/22 M68AF031A Table 4. Capacitance CIN COUT Test Condition Parameter(1,2) Symbol Max Unit VIN = 0V 6 pF VOUT = 0V 8 pF Max Unit VCC = 5.5V, f = 1/tAVAV, IOUT = 0mA 50 mA VCC = 5.5V, f = 1MHz, IOUT = 0mA 5 mA Input Capacitance on all pins (except DQ) Output Capacitance Min Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1 MHz, VCC = 5.0V. Table 5. DC Characteristics (M68AF031A-55 and M68AF031A-70) Symbol Parameter ICC1 (1,2) Operating Supply Current ICC2 (3) Operating Supply Current ISB Standby Supply Current CMOS ILI Input Leakage Current ILO (4) Test Condition Output Leakage Current VCC = 5.5V, f = 0, E ≥ VCC –0.2V Min Typ Range 1 0.1 5 µA Range 6 0.1 10 µA 0V ≤ VIN ≤ VCC –1 1 µA 0V ≤ VOUT ≤ VCC –1 1 µA VIH Input High Voltage 2.2 VCC + 0.3 V VIL Input Low Voltage –0.3 0.8 V VOH Output High Voltage IOH = –1.0mA VOL Output Low Voltage IOL = 2.1mA Note: 1. 2. 3. 4. 2.4 V 0.4 V Average AC current, cycling at tAVAV minimum. E = VIL, VIN = VIL OR VIH. E ≤ 0.2V, VIN ≤ 0.2V OR VIN ≥ VCC –0.2V. Output disabled. 9/22 M68AF031A OPERATION The M68AF031A has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cy- cles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E, as summarized in the Operating Modes table (see Table 6., Operating Modes). Table 6. Operating Modes Operation E W G DQ0-DQ7 Power Deselected VIH X X Hi-Z Standby (ISB) Read VIL VIH VIL Data Output Active (ICC) Write VIL VIL X Data Input Active (ICC) Output Disabled VIL VIH VIH Hi-Z Active (ICC) Note: 1. X = VIH or VIL. Read Mode The M68AF031A is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data of the 262,144 locations in the static memory array, specified by the 15 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX but data lines will always be valid at tAVQV. Figure 10. Address Controlled, Read Mode AC Waveforms tAVAV A0-A14 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI05939 Note: E = Low, G = Low, W = High. 10/22 M68AF031A Figure 11. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV A0-A14 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI05940 Note: Write Enable (W) = High. Figure 12. Chip Enable Controlled, Standby Mode AC Waveforms E ICC ISB tPU tPD 50% AI05956 11/22 M68AF031A Table 7. Read and Standby Mode AC Characteristics M68AF031A Symbol Parameter 55 Min. tAVAV Read Cycle Time tAVQV Address Valid to Output Valid 70 Max. 55 Min. Unit Max. 70 55 ns 70 ns tAXQX (1) Data hold from address change tEHQZ (2,3) Chip Enable High to Output Hi-Z 20 25 ns tELQV Chip Enable Low to Output Valid 55 70 ns tELQX (1) Chip Enable Low to Output Lo-Z 5 5 5 ns 5 ns tGHQZ (2,3) Output Enable High to Output Hi-Z 20 25 ns tGLQV Output Enable Low to Output Valid 25 35 ns tGLQX (1) Output Enable Low to Output Transition tPD (4) Chip Enable High to Power Down tPU (4) Chip Enable Low to Power Up 5 5 55 0 ns 70 0 ns ns Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters. 12/22 M68AF031A Write Mode The M68AF031A is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. When E (W) is Low, write cycle begins on the W (E)'s falling edge. Therefore, address setup time is referenced to Write Enable or Chip Enable as tAVWL and tAVEL respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E or W. If the Output is enabled (E = Low, G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX and tEHDX respectively. Figure 13. Write Enable Controlled, Write AC Waveforms tAVAV A0-A14 VALID tAVWH tELWH tWHAX E tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ7 DATA (1) DATA (1) DATA INPUT tDVWH AI05941 Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied. Figure 14. Chip Enable Controlled, Write AC Waveforms tAVAV A0-A14 VALID tAVEH tAVEL tELEH tEHAX E tWLEH W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI05942 13/22 M68AF031A Table 8. Write Mode AC Characteristics M68AF031A Symbol Parameter 55 Min. 70 Max. Min. Unit Max. tAVAV Write Cycle Time 55 70 ns tAVEH Address Valid to Chip Enable High 45 60 ns tAVEL Address valid to Chip Enable Low 0 0 ns tAVWH Address Valid to Write Enable High 45 60 ns tAVWL Address Valid to Write Enable Low 0 0 ns tDVEH Input Valid to Chip Enable High 25 30 ns tDVWH Input Valid to Write Enable High 25 30 ns tEHAX Chip Enable High to Address Transition 0 0 ns tEHDX Chip enable High to Input Transition 0 0 ns tELEH Chip Enable Low to Chip Enable High 45 60 ns tELWH Chip Enable Low to Write Enable High 45 60 ns tWHAX Write Enable High to Address Transition 0 0 ns tWHDX Write Enable High to Input Transition 0 0 ns tWHQX (1) Write Enable High to Output Transition 5 5 ns tWLEH Write Enable Low to Chip Enable High 45 60 ns tWLQZ (1,2) tWLWH Write Enable Low to Output Hi-Z 20 Write Enable Low to Write Enable High 45 25 50 ns ns Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. Figure 15. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 5.5V VCC 4.5V VDR > 2.0V tCDR tR E ≥ VDR – 0.2V E AI05925 14/22 M68AF031A Table 9. Low VCC Data Retention Characteristics Symbol ICCDR (1) Parameter Supply Current (Data Retention) Test Condition VCC = 2.0V, E ≥ VCC –0.2V, f = 0 (3) Chip Deselected to Data Retention tCDR (1,2) Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention) Min E ≥ VCC –0.2V, f = 0 Typ Max Unit 6 µA 0 ns tAVAV ns 2.0 V Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V. 15/22 M68AF031A PACKAGE MECHANICAL Figure 16. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Outline D 14 h x 45˚ 1 C E 15 H 28 A B ddd A1 e A1 α L SO-E Note: Drawing is not to scale. Table 10. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Mechanical Data millimeters inches Symbol Typ Min Max A 2.38 A1 Min Max 2.79 0.094 0.110 0.05 0.35 0.002 0.014 A2 2.28 2.43 0.090 0.096 B 0.35 0.50 0.014 0.020 C 0.20 0.30 0.008 0.012 D 18.03 18.41 0.710 0.725 ddd 0.10 E 7.39 7.62 – – H 11.68 L 0.004 0.291 0.300 – – 12.19 0.460 0.480 0.79 1.27 0.031 0.050 α 0° 8° 0° 8° N 28 e 16/22 Typ 1.27 0.050 28 M68AF031A Figure 17. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline A2 A1 B1 B A α L e1 eA D2 C eB D S N E1 E 1 PDIP Note: Drawing is not to scale. Table 11. PDIP28 - 28 pin Plastic DIP, n600 mils width, Package Mechanical Data millimeters inches Symbol Typ Min Max A – A1 Min Max 5.08 – 0.200 0.38 – 0.015 – A2 3.56 4.06 0.140 0.160 B 0.38 0.51 0.015 0.020 – – – – C 0.20 0.30 0.008 0.012 D 36.83 37.34 1.450 1.470 B1 1.52 Typ 0.060 D2 33.02 – – 1.300 – – E 15.24 – – 0.600 – – 13.59 13.84 0.535 0.545 E1 e1 2.54 – – 0.100 – – eA 14.99 – – 0.590 – – eB 15.24 17.78 0.600 0.700 L 3.18 3.43 0.125 0.135 S 1.78 2.08 0.070 0.082 α 0° 10° 0° 10° N 28 28 17/22 M68AF031A Figure 18. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Outline A2 22 21 e 28 1 E B 7 8 A D1 CP D DIE C A1 TSOP-C α L Note: Drawing is not to scale. Table 12. TSOP28 - 28 lead Normal Pinout Plastic Small Outline, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.200 Max 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.910 1.050 0.0358 0.0413 0.0039 0.0083 B 0.220 C 0.0087 0.100 CP 0.210 0.100 0.0039 D 13.400 – – 0.5276 – – D1 11.800 – – 0.4646 – – E 8.000 – – 0.3150 – – e 0.550 – – 0.0217 – – L 0.300 0.700 0.0118 0.0276 α 0 5 0 5 N 18/22 Max 28 28 M68AF031A Figure 19. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Outline A2 7 8 e 1 28 E B 22 21 A D1 CP D DIE C A1 TSOP-H α L Note: Drawing is not to scale. Table 13. TSOP28 - 28 lead Reverse Pinout Plastic Small Outline, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 Max 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.910 1.050 0.0358 0.0413 0.0039 0.0083 B 0.220 C 0.0087 0.100 CP 0.210 0.100 0.0039 D 13.400 – – 0.5276 – – D1 11.800 – – 0.4646 – – E 8.000 – – 0.3150 – – e 0.550 – – 0.0217 – – L 0.300 0.700 0.0118 0.0276 α 0 5 0 5 N 28 28 19/22 M68AF031A PART NUMBERING Table 14. Ordering Information Scheme Example: M68AF031 A L 70 MS 6 T Device Type M68 Mode A = Asynchronous Operating Voltage F = 4.5 to 5.5V Array Organization 031 = 256 Kbit (32K x8) Option 1 A = 1 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 55 = 55ns 70 = 70ns Package MS = SO28 B = PDIP28 N = TSOP28 8x13.4mm (Standard Pinout) NS = TSOP28 8x13.4mm (Reverse Pinout) Operative Temperature 1 = 0 to 70°C 6 = –40 to 85 °C Shipping T = Tape & Reel Packing E = Lead-free and RoHS Package, Standard Packing F = Lead-free and RoHS Package, Tape & Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 20/22 M68AF031A REVISION HISTORY Table 15. Document Revision History Date Version Revision Details January 2002 -01 First Issue 07-Feb-2002 -02 ISB clarified 08-Feb-2002 -03 TSOP28 Package removed AC Measurement Load Circuit changed (Figure 9) Operating and AC Measurement Conditions clarified (Table 3) 06-Mar-2002 -04 Document status changed to Data Sheet 19-Apr-2002 -05 Absolute Maximum current value added (Table 2) Operating and AC Measurement Conditions clarified (Table 3) 26-Apr-2002 -06 Absolute Maximum Ratings Table clarified (Table 2) Operating and AC Measurement Conditions Table clarified (Table 3) DC Characteristics Table clarified (Table 5) Write Mode AC Characteristics Table clarified (Table 8) Low VCC Data Retention AC Waveforms clarified (Figure 15) Low VCC Data Retention Characteristics Table clarified ( Table 9) 20-May-2002 -07 DC Characteristics Table clarified (Table 5) Low VCC Data Retention Characteristics Table clarified (Table 9) 29-May-2002 -08 TSOP28 8x13.4mm Standard and Reverse pinout added (Figure 1, 5, 6, Table 12) 02-Oct-2002 8.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 08 equals 8.0). New part number added. 09-Oct-2002 8.2 Datasheet number simplified. 23-Apr-2003 8.3 55ns speed-class added 27-May-2004 9.0 Package outline and package mechanical data added for TSOP28 Reverse package. 05-Nov-2004 10.0 TSOP28 Standard Lead-free version added in FEATURES SUMMARY, SUMMARY DESCRIPTION. TLEAD parameter added in Table 2., Absolute Maximum Ratings. Standard Lead-free option added in Table 14., Ordering Information Scheme. 15-Nov-2004 11.0 TSOP28 Lead-free Tape & Reel version added in FEATURES SUMMARY, SUMMARY DESCRIPTION. Lead-Free Tape & Reel option added in Table 14., Ordering Information Scheme. 21/22 M68AF031A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 22/22