M68Z512 4 Mbit (512Kb x8) Low Power SRAM with Output Enable ■ ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns ■ ■ LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O ■ CMOS for OPTIMUM SPEED/POWER ■ AUTOMATIC POWER-DOWN WHEN DESELECTED ■ INTENDED FOR USE WITH ST ZEROPOWER® AND TIMEKEEPER ® CONTROLLERS DESCRIPTION The M68Z512 is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V ±10% supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z512 is available in a 32 lead TSOP II (10 x 20mm) package. Table 1. Signal Names A0-A18 Address Inputs DQ0-DQ7 Data Input/Output E Chip Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground 32 1 TSOP II 32 (NC) 10 x 20mm Figure 1. Logic Diagram VCC 19 8 A0-A18 W DQ0-DQ7 M68Z512 E G March 2000 VSS AI03030 1/12 M68Z512 Table 2. Absolute Maximum Ratings (1) Symbol Parameter TA Ambient Operating Temperature TSTG Storage Temperature VIO (2) Input or Output Voltage Value Unit 0 to 70 °C –65 to 150 °C –0.3 to VCC + 0.3 V VCC Supply Voltage –0.3 to 7.0 V IO (3) Output Current 20 mA Power Dissipation 1 W PD Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Up to a maximum operating VCC of 5.5V only. 3. One output at a time, not to exceed 1 second duration. Figure 2. TSOP Connections A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 8 9 16 32 M68Z512 25 24 17 AI03031 2/12 VCC A15 A18 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 READ MODE The M68Z512 is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (t ELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV. WRITE MODE The M68Z512 is in the Write mode whenever the W and E pins are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. Write begins with the concurrence of Chip Enable being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E, or W. if the Output is enabled (E = Low and G = Low), then W will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX or tEHDX. M68Z512 Table 3. Operating Modes Operation E W G DQ0-DQ7 Power Read VIL VIH VIH Hi-Z Active Read VIL VIH VIL Data Output Active Write VIL VIL X Data Input Active Deselect VIH X X Hi-Z Standby Note: 1. X = VIH or VIL. Table 4. AC Measurement Conditions Figure 3. AC Testing Load Circuit ≤ 5ns Input Rise and Fall Times Input Pulse Voltages 5.0V 0 to 3V Input and Output Timing Ref. Voltages 1.5V 1838Ω Note: Output Hi-Z is defined as the point where data is no longer driven. OPERATIONAL MODE The M68Z512 has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table. DEVICE UNDER TEST OUT 994Ω CL = 100pF or 5pF CL includes JIG capacitance AI03032 Table 5. Capacitance (1) (TA = 25°C, f = 1 MHz) Symbol CIN COUT (2) Parameter Test Condition Min Max Unit Input Capacitance on all pins (except DQ) TA = 25°C, f = 1MHz, VCC = 5V 6 pF Output Capacitance TA = 25°C, f = 1MHz, VCC = 5V 8 pF Note: 1. Sampled only, not 100% tested. 2. Outputs deselected. 3/12 M68Z512 Figure 4. Block Diagram VCC VSS A ROW DECODER (10) MEMORY ARRAY A CHIP ENABLE. DQ I/O CIRCUITS INPUT DATA CTRL (8) COLUMN DECODER DQ CHIP ENABLE. (9) A A E W G AI03033 Table 6. DC Characteristics (TA = 0 to 70°C; VCC = 5V ±10%) Symbol Parameter Test Condition Max Unit Input Leakage Current Min Typ ±1 µA ±1 µA Output Leakage Current 0V ≤ VIN ≤ VCC 0V ≤ VOUT ≤ VCC ICC1 (1) Supply Current VCC = 5.5V, (-55) 90 mA ICC2 (2) Supply Current (Standby) TTL VCC = 5.5V, E = VIH 15 mA 20 µA –0.3 0.8 V 2.2 VCC + 0.3 V 0.4 V ILI ILO ICC3 (3) Supply Current (Standby) CMOS VIL Input Low Voltage VCC = 5.5V, E ≥ VCC – 0.3V, f=0 VIH Input High Voltage VOL Output Low Voltage IOL = 2.1mA VOH Output High Voltage IOH = –1mA Note: 1. Average AC current, Outputs open, cycling at tAVAV minimum. 2. All other Inputs at V IL ≤ 0.8V or VIH ≥ 2.2V. 3. All other Inputs at V IL ≤ 0.3V or VIH ≥ VCC –0.3V. 4/12 1.6 2.4 V M68Z512 Table 7. Read and Standby Modes AC Characteristics (TA = 0 to 70°C; VCC = 5V ±10%) M68Z512 Symbol Parameter -70 Min tAVAV Read Cycle Time Unit Max 70 ns tAVQV (1) Address Valid to Output Valid 70 ns tELQV (1) Chip Enable Low to Output Valid 70 ns tGLQV (1) Output Enable Low to Output Valid 35 ns tELQX (3) Chip Enable Low to Output Transition 10 ns tGLQX (3) Output Enable Low to Output Transition 5 ns tEHQZ (2,3) Chip Enable High to Output Hi-Z 25 ns tGHQZ (2,3) Output Enable High to Output Hi-Z 25 ns tAXQX (1) Address Transition to Output Transition 10 ns tPU Chip Enable Low to Power Up 0 ns tPD Chip Enable High to Power Down 70 ns Note: 1. CL = 100pF. 2. CL = 5pF. 3. At any given temperature and voltage condition, tEHQZ is less than t ELQX and tGHQZ is less than t GLQX for any given device. Figure 5. Address Controlled, Read Mode AC Waveforms tAVAV A0-A18 VALID tAVQV DQ0-DQ7 tAXQX DATA VALID AI03034 Note: E = Low, G = Low, W = High. 5/12 M68Z512 Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV VALID A0-A18 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI03035 Note: Write Enable (W) = High. Figure 7. Standby Mode AC Waveforms E ICC1 ICC2 tPU tPD 50% AI03036 6/12 M68Z512 Table 8. Write Mode AC Characteristics (TA = 0 to 70°C; VCC = 5V ±10%) M68Z512 Symbol Parameter -70 Min Unit Max tAVAV Write Cycle Time 70 ns tAVWL Address Valid to Write Enable Low 0 ns tAVWH Address Valid to Write Enable High 60 ns tAVEH Address Valid to Chip Enable High 60 ns tWLWH Write Enable Pulse Width 55 ns tWHAX Write Enable High to Address Transition 0 ns tWHDX Write Enable High to Input Transition 0 ns tWHQX (2) Write Enable High to Output Transition 5 ns tWLQZ (1,2) Write Enable Low to Output Hi-Z 25 ns tAVEL Address Valid to Chip Enable Low 0 ns tELEH Chip Enable Low to Chip Enable High 45 ns tEHAX Chip Enable High to Address Transition 0 ns tDVWH Input Valid to Write Enable High 25 ns tDVEH Input Valid to Chip Enable High 25 ns Note: 1. CL = 5pF. 2. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 7/12 M68Z512 Figure 8. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A18 tAVWH tAVEL tWHAX E tWLWH tAVWL W tWHQX tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI03037 Note: Output Enable (G) = Low. Figure 9. Chip Enable Controlled, Write AC Waveforms (1,2) tAVAV A0-A18 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI03038 Note: 1. Output Enable (G) = High. 2. If E goes High with W high, the output remains in a high-impedance state. 8/12 M68Z512 Table 9. Low V CC Data Retention Characteristics (TA = 0 to 70°C) Symbol Parameter Test Condition Supply Current (Data Retention) VCC = 3V, E ≥ VCC – 0.3V VDR Supply Voltage (Data Retention) E ≥ VCC – 0.3V, f = 0 2 V tCDR Chip Disable to Power Down E ≥ VCC – 0.3V, f = 0 0 ns tER (2) Operation Recovery Time tAVAV ns ICCDR (1) Min Typ Max Unit 0.1 10 µA Note: 1. Typical condition: T A = 25°C. 2. See Figure 10 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time. Figure 10. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 5V VCC 3V VDR > 2.0V tCDR tER E ≥ VDR – 0.3V E 2.2V AI03039 9/12 M68Z512 Table 10. Ordering Information Scheme Example: M68Z512 -70 NC 1 T Device Type M68Z Device Function 512 = 4 Mbit (512Kb x8) Operating Voltage blank = 4.5V to 5.5V Speed -70 = 70 ns Package NC = TSOP II 32 (10 x 20mm) Temperature Range 1 = 0 to 70 °C Shipping Method T = Tape & Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. Table 11. Revision History Date Revision Details May 1999 First Issue 03/14/00 TSOP32 II Package Dimension Changed (Table 12) From Preliminary Data to Data Sheet 10/12 M68Z512 Table 12. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Mechanical Data mm inch Symbol Typ Min Max A Typ Min Max 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 b 0.30 0.52 0.012 0.020 C 0.12 0.21 0.005 0.008 CP 0.10 D 20.82 21.08 – – E 11.56 E1 0.004 0.820 0.830 – – 11.96 0.455 0.471 10.03 10.29 0.395 0.405 L 0.40 0.60 0.016 0.024 α 0° 5° 0° 5° N 32 e 1.27 0.050 32 Figure 11. TSOP II 32 - 32 lead Plastic Thin Small Outline II, 10 x 20 mm, Package Outline D 16 1 E1 17 E 32 b e A2 A C A1 CP α L TSOP-d Drawing is not to scale. 11/12 M68Z512 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 12/12