STMICROELECTRONICS M74HC166RM13TR

M74HC166
8 BIT PISO SHIFT REGISTER
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HIGH SPEED :
fMAX = 63 MHz (TYP.) at VCC = 6V
LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 166
DESCRIPTION
The M74HC166 is an high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated with silicon
gate C2MOS technology.
It consists of parallel or serial inputs and a
serial-out 8 bit shift register with gated clock inputs
and an overriding clear input. The parallel-in or
serial-in modes are controlled by the SHIFT/
LOAD input. When the SHIFT/LOAD input is held
high, the serial data input is enabled and the eight
flip-flops perform serial shifting with each clock
pulse; when held low, the parallel data inputs are
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC166B1R
M74HC166M1R
T&R
M74HC166RM13TR
M74HC166TTR
enabled and synchronous loading occurs on the
next clock pulse. Clocking is accomplished on the
low-to-high level edge of the clock pulse. The
CLOCK-INHIBIT input should be changed to the
high only while the clock input is held high. A direct
clear input overrides all other inputs, including the
clock, and sets all flip-flops to zero. Functional
details are shown in the truth table and the timing
chart. All inputs are equipped with protection
circuits against static discharge and transient
excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/12
M74HC166
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1
2, 3, 4, 5, 10,
11, 12, 14
SI
NAME AND FUNCTION
Serial Data Inputs
A to H
Parallel Data Inputs
Clock Enable Input
(Active Low)
Clock Input (LOW to
CLOCK
HIGH, Edge Triggered
Asynchronous Master
CLEAR
Reset Input (Active Low)
Serial Output from the
QH
Last Stage
Parallel Enable Input
SHIFT/LOAD
(Active Low)
GND
Ground (0V)
Vcc
Positive Supply Voltage
6
CLOCK INH
7
9
13
15
8
16
TRUTH TABLE
INPUTS
INTERNAL OUTPUTS OUTPUTS
CLEAR
SHIFT/
LOAD
CLOCK
INH
CLOCK
SERIAL IN
PARALLEL
A..........H
QA
QB
QH
L
X
X
X
X
X
L
L
L
L
X
X
X
X
H
L
L
X
a..............h
a
b
h
H
H
L
H
X
H
QAn
QGn
H
H
L
L
X
L
QAn
QGn
H
X
H
X
X
X
X : Don’t Care
a........h : The level of steady input voltage at inputs a through H respectively
2/12
NO CHANGE
NO CHANGE
M74HC166
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
TIMING CHART
3/12
M74HC166
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Supply Voltage
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
± 50
mA
VI
DC Input Voltage
VO
DC Output Voltage
IIK
ICC or IGND DC VCC or Ground Current
PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
500(*)
mW
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Unit
2 to 6
V
VI
Input Voltage
0 to VCC
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
-55 to 125
°C
Input Rise and Fall Time
tr, tf
4/12
Value
Supply Voltage
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
M74HC166
DC SPECIFICATIONS
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
ICC
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Value
TA = 25°C
VCC
(V)
Min.
2.0
4.5
6.0
2.0
4.5
6.0
Typ.
Max.
1.5
3.15
4.2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
3.15
4.2
0.5
1.35
1.8
Max.
1.5
3.15
4.2
0.5
1.35
1.8
V
0.5
1.35
1.8
2.0
IO=-20 µA
1.9
2.0
1.9
1.9
4.5
IO=-20 µA
4.4
4.5
4.4
4.4
6.0
IO=-20 µA
5.9
6.0
5.9
5.9
4.5
IO=-4.0 mA
4.18
4.31
4.13
4.10
5.68
Unit
V
V
6.0
IO=-5.2 mA
2.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=20 µA
0.0
0.1
0.1
0.1
6.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=4.0 mA
0.17
0.26
0.33
0.40
6.0
IO=5.2 mA
0.18
0.26
0.33
0.40
6.0
VI = VCC or GND
± 0.1
±1
±1
µA
6.0
VI = VCC or GND
4
40
80
µA
5.8
5.63
5.60
V
5/12
M74HC166
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Symbol
Parameter
tTLH tTHL Output Transition
Time
tPLH tPHL Propagation Delay
Time
(CLOCK - QH)
tPHL
Propagation Delay
Time
(CLEAR - QH)
fMAX
Maximum Clock
Frequency
tW(H)
tW(L)
Minimum Pulse
Width (CLOCK)
tW(L)
Minimum Pulse
Width (CLEAR)
ts
ts
Minimum Set-up
Time (SI, PI)
Minimum Set-up
Time (SHIFT/
LOAD)
Value
TA = 25°C
VCC
(V)
Min.
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.2
31
37
6.0
th
tREM
Minimum Hold
Time
Minimum Removal
Time
2.0
4.5
6.0
2.0
4.5
6.0
-40 to 85°C
-55 to 125°C
Min.
Min.
Typ.
Max.
Max.
30
8
7
70
20
16
60
18
14
14
50
63
28
6
5
28
6
5
20
4
3
25
5
75
15
13
150
30
26
135
27
23
75
15
13
75
15
13
75
15
13
75
15
95
19
16
95
19
16
95
19
16
95
19
110
22
19
110
22
19
110
22
19
110
22
3
13
16
19
12
3
3
0
0
0
50
10
9
0
0
0
65
13
11
0
0
0
75
15
13
95
19
16
190
38
32
170
34
29
5.0
25
30
Unit
Max.
110
22
19
225
45
38
205
41
35
4.2
21
25
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
VCC
(V)
Value
TA = 25°C
Min.
Typ.
Max.
10
CIN
Input Capacitance
5.0
5
CPD
Power Dissipation
Capacitance (note
1)
5.0
60
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
6/12
M74HC166
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : MINIMUM PULSE WIDTH (CLEAR), REMOVAL TIME (CLEAR TO CLOCK)
(f=1MHz; 50% duty cycle)
7/12
M74HC166
WAVEFORM 2 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (CLOCK), SETUP AND
HOLD TIME (SI to CLOCK) (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIME, SETUP AND HOLD TIME (PI, S/L to CLOCK)
(f=1MHz; 50% duty cycle)
8/12
M74HC166
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
9/12
M74HC166
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
PO13H
10/12
M74HC166
TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0°
L
0.45
A
0.60
0.0256 BSC
8°
0°
0.75
0.018
8°
0.024
0.030
A2
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
11/12
M74HC166
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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12/12