DA6179.000 22 January, 2007 MAS6179 This is preliminary information on a new product under development. Micro Analog Systems Oy reserves the right to make any changes without notice. AM Receiver IC • Tri Band Receiver IC • High Sensitivity • Very Low Power Consumption • Wide Supply Voltage Range • Power Down Control • Control for AGC On • High Selectivity by Crystal Filter • Fast Startup Feature DESCRIPTION The MAS6179 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiving. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. MAS6179 supports up to three frequency band operation by switching between three crystal filters and two additional antenna tuning capacitors. FEATURES APPLICATIONS • • • • • • • • • • • MAS6179 has differential input and two internal compensation capacitor options for compensating shunt capacitances of different crystals (See ordering information on page 10). Tri Band Receiver IC Highly Sensitive AM Receiver, 0.4 µVRMS typ. Wide Supply Voltage Range from 1.1 V to 3.6 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On Wide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter Differential Input • Multi Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HBG (Switzerland) and BPC (China) BLOCK DIAGRAM VDD QO3 RFIP QO2 QO1 AON QI VDD AGC Amplifier Demodulator & Comparator OUT RFIM RFI2 RFI3 Power Supply/Biasing VDD VSS PDN1 PDN2 AGC DEC 1 (10) DA6179.000 22 January, 2007 PAD LAYOUT VDD VSS QO2 RFI2 QO1 RFIM QO3 RFIP QI RFI3 AGC PDN1 PDN2 AON OUT 1800 µm MAS6179Ax, x=1, 2 DEC 1420 µm DIE size = 1.42 x 1.80 mm; rectangular PAD 80 µm x 80 µm Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Name X-coordinate Y-coordinate Power Supply Voltage Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 Quartz Filter Output for Crystal 3 Quartz Filter Input for Crystals AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 Receiver Input 3 (for Antenna Capacitor 3) Positive Receiver Input Negative Receiver Input Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground VDD QO2 QO1 QO3 QI AGC PDN2 OUT DEC AON PDN1 RFI3 RFIP RFIM RFI2 VSS 154 µm 154 µm 154 µm 154 µm 154 µm 154 µm 154 µm 154 µm 1266 µm 1266 µm 1266 µm 1266 µm 1266 µm 1266 µm 1266 µm 1266 µm 1580 µm 1393 µm 1207 µm 1021 µm 835 µm 648 µm 462 µm 276 µm 276 µm 462 µm 648 µm 835 µm 1021 µm 1207 µm 1393 µm 1580 µm Note 1 2 3 1 4 4 Notes: 1) PDN1 = PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power up 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 4) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD 2 (10) DA6179.000 22 January, 2007 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature VDD-VSS VIN PMAX TOP TST Conditions Min Max Unit -0.3 VSS-0.3 5.5 VDD+0.3 100 +85 +150 V V mW o C o C -40 -55 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 1.5V, Temperature = 25°C unless otherwise noted Parameter Operating Voltage Current Consumption Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Receiver Input Resistance Receiver Input Capacitance RFI2 Switch On Resistance RFI2 Switch Off Capacitance RFI3 Switch On Resistance RFI3 Switch Off Capacitance Input Levels |lIN|<0.5 µA Output Current VOL<0.2 VDD;VOH >0.8 VDD Output Pulse Symbol VDD IDD IDDoff fIN VIN min VIN max RRFI CRFI RON2 COFF2 RON3 COFF3 VIL VIH |IOUT| T100ms T200ms T500ms T800ms Startup Time TStart Output Delay Time TDelay Conditions VDD=1.5 V, Vin=0 µVrms VDD=1.5 V, Vin=20 mVrms VDD=3.6 V, Vin=0 µVrms VDD=3.6 V, Vin=20 mVrms Min 1.10 40 24 Typ 55 40 58 43 40 0.4 Max Unit 3.6 80 65 V 0.1 100 1 20 f=40kHz..77.5 kHz 600 0.5 5 TBD 2.5 TBD VDD=1.4 V VDD=1.4 V 15 15 0.35 VDD-0.35 5 1 µVrms ≤ VIN ≤ 20 mVrms 1 µVrms ≤ VIN ≤ 20 mVrms 1 µVrms ≤ VIN ≤ 20 mVrms 1 µVrms ≤ VIN ≤ 20 mVrms Fast Start-up, Vin=0.4 µVrms Fast Start-up, Vin=20 mVrms µA µA kHz µVrms mVrms kΩ pF Ω pF Ω pF V µA 50 140 ms 150 230 ms 400 500 600 ms 700 800 900 ms 1.3 3.5 50 s 100 ms Note: Stand-by current consumption may increase if V IH and V IL differ from VDD and GND respectively. TBD = To Be Defined 3 (10) DA6179.000 22 January, 2007 FREQUENCY SELECTION The frequency selection and power down control is accomplished via two digital control pins PDN1 and PDN2. The control logic is presented in table 1. Table 1. Frequency selection and power down control PDN1 PDN2 RFI2 Switch RFI3 Switch Selected Crystal Output Description Power down Frequency 1 Frequency 2, RFI2 capacitor connected in parallel with antenna Frequency 3, RFI2 and RFI3 capacitors connected in parallel with antenna High High Low High Low High Open Open Closed Open Open Open QO1 QO2 Low Low Closed Closed QO3 The internal antenna tuning capacitor switches (RFI2, RFI3) and crystal filter output switches (QO1, QO2, QO3) are controlled according table 1. If frequency 1 is selected the RFI2 and RFI3 switches are open and only crystal output QO1 is active. Antenna frequency is determined by antenna inductor LANT (see Typical Application on page 6), antenna capacitor CANT1 and parasitic capacitances related to antenna inputs RFIP, RFIM, RFI2 and RFI3 (see Antenna Tuning Considerations below). Frequency 1 is the highest frequency of the three selected frequencies. If frequency 2 is selected then RFI2 switch is closed to connect CANT2 to pin RFIM in parallel with ferrite antenna and tune it to frequency 2. Then only crystal output QO2 is active. Frequency 2 is the medium frequency frequencies. of the three selected If frequency 3 is selected both RFI2 and RFI3 switches are closed to connect both CANT2 and CANT3 capacitors to RFIM pin in parallel with ferrite antenna and tune it to frequency 3. Then only crystal output QO3 is active. Frequency 3 is the lowest frequency of the three selected frequencies. It is recommended to switch the device to power down for at least 50ms before switching to another frequency. This guarantees fast startup in switching to another frequency. During minimum 50ms power down time the AGC capacitor voltage is completely pulled to VDD and the proper fast startup conditions are met. Without proper fast startup control the startup time can be several minutes. With fast startup it is shortened typically to few seconds. 4 (10) DA6179.000 22 January, 2007 ANTENNA TUNING CONSIDERATIONS The ferrite bar antenna having inductance LANT and parasitic coil capacitance CCOIL is tuned to three reception frequencies f1, f2 and f3 by parallel capacitors CANT1, CANT2 and CANT3. The receiver input stage and internal antenna capacitor switches have capacitances CRFI, COFF2, COFF3 which affect the resonance frequencies. COFF2 and COFF3 are switch capacitances when switches are open. When switches are closed these capacitances are shorted by on resistance of the switches and they are effectively eliminated. Following relationships can be written for the three tuning frequencies. Frequency f1 (highest frequency): CTOT1=CCOIL+CANT1+CRFI+COFF2+COFF3 1 f1 = 2π L ANT ⋅ CTOT 1 Frequency f2 (middle frequency): CTOT2=CCOIL+CANT1+CANT2+CRFI+COFF3 1 f2 = 2π L ANT ⋅ CTOT 2 Frequency f3 (lowest frequency): CTOT3=CCOIL+CANT1+ CANT2+ CANT3+CRFI 1 f3 = 2π L ANT ⋅ CTOT 3 5 (10) DA6179.000 22 January, 2007 TYPICAL APPLICATION X3 X2 Note 1 Note 4 Optional Control for AGC on/hold X1 VDD Note 5 CANT1 LANT QO2 QO1 QO3 CANT3 CANT2 RFIP AON QI Demodulator & Comparator VDD AGC Amplifier OUT Receiver Output RFIM Ferrite Antenna RFI2 Power Supply/Biasing VSS PDN1 PDN2 VDD RFI3 VBATTERY AGC DEC AGC CDEC 47 nF CAGC 10 µF CAGC 10 µF OR DEC + CDEC 47 nF Note 2 Power Down / VDD VDD Fast Startup / Note 2 Frequency Selection Note 3 Figure 1. Application circuit of tri band receiver MAS6179. X3 40.003 kHz X2 60.003 kHz Note 1 X1 77.503 kHz VDD Note 5 LANT 2.74 mH CANT1 1.5 nF Ferrite Antenna CANT3 1.0 nF CANT2 3.3 nF RFIP QO3 QO2 QO1 Note 4 Optional Control for AGC on/hold AON QI VDD AGC Amplifier Demodulator & Comparator OUT Receiver Output RFIM RFI2 RFI3 Power Supply/Biasing VDD VSS PDN1 PDN2 VBATTERY AGC DEC CAGC 10 µF Power Down / VDD VDD Fast Startup / Note 2 Frequency Selection Note 3 AGC CDEC 47 nF OR CAGC 10 µF DEC + CDEC 47 nF Note 2 Figure 2. Example circuit of tri band receiver MAS6179 for DCF77/MSF/WWVB/JJY frequencies. 6 (10) DA6179.000 22 January, 2007 TYPICAL APPLICATION (Continued) Note 1: Crystals The crystals as well as ferrite antenna frequencies are chosen according to the time signal system (Table 2). The reason why the crystal frequency is about 3 Hz higher than the signal frequency is that the crystal is operated without the loading capacitor. Without loading capacitor the actual resonance frequency is about 3 Hz lower thus 77.503 kHz crystal resonates at 77.500 kHz when no loading capacitor is used. Table 2. Time Signal System Frequencies Time Signal System Location Antenna Frequency Recommended Crystal Frequency DCF77 HBG MSF WWVB JJY BPC 77.5 kHz 75 kHz 60 kHz 60 kHz 40 kHz and 60 kHz 68.5 kHz 77.503 kHz 75.003 kHz 60.003 kHz 60.003 kHz 40.003 kHz and 60.003 kHz 68.505 kHz Germany Switzerland United Kingdom USA Japan China The crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance compensation capacitor CC of MAS6179. See Compensation Capacitance Options in table 3. Table 3. Compensation Capacitance Options Device CC Crystal Description MAS6179A1 MAS6179A2 0.75 pF 1.3 pF For low C0 crystal For high C0 crystal It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of floating crystal shunt capacitance. For example crystal with 1pF floating package shunt capacitance can have 0.85pF grounded package shunt capacitance. PCB traces of crystal and external compensation capacitance should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance mismatching. Highest frequency crystal is connected to crystal output pin 1 (QO1). Medium frequency crystal is connected to crystal output pin 2 (QO2). Lowest frequency crystal is connected to crystal output pin 3 (QO3). The other pin of each crystal is connected to common crystal input pin QI. Table 4 below presents some crystal manufacturers having suitable crystals for time signal receiver application. Table 4. Crystal Manufacturers and Crystal Types in Alphabetical Order for Time Signal Receiver Application Manufacturer Crystal Type Dimensions Web Link Citizen Epson KDS Daishinku Microcrystal Seiko Instruments CFV-206 C-2-Type C-4-Type DT-261 MX1V-L2N MX1V-T1K VTC-120 ø 2.0 x 6.0 ø 1.5 x 5.0 ø 2.0 x 6.0 ø 2.0 x 6.0 ø 2.0 x 6.0 ø 2.0 x 8.1 ø 1.2 x 4.7 http://www.citizen.co.jp/tokuhan/quartz/ http://www.epsontoyocom.co.jp/english/ http://www.kds.info/index_en.htm http://www.microcrystal.com/ http://www.sii-crystal.com Note 2: AGC Capacitor The AGC and DEC capacitors must have low leakage currents due to very small signal currents through the capacitors. The insulation resistance of these capacitors should be at minimum 100 MΩ. Also probes with at least 100 MΩ impedance should be used for voltage probing of AGC and DEC pins. Electrolytic AGC capacitor should have voltage rating at least 25 V for low enough leakage. DEC capacitor can be low leakage chip capacitor. 7 (10) DA6179.000 22 January, 2007 TYPICAL APPLICATION (Continued) Both the AGC and DEC capacitors can be connected either to VDD or to VSS. To minimize leakage currents during power down the AGC and DEC capacitors are best to be connected to VDD since in power down the AGC and DEC pins go to VDD voltage potential. In this case the positive polarity pin of electrolyte capacitor should be connected to VDD. If the capacitors are connected to VSS then the negative polarity pin of electrolyte capacitor should be connected to VSS. Note 3: Power Down / Fast Startup Control Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if PDN1 = PDN2 = VDD and in power up with other three PDN1 and PDN2 control bit combinations (see table 1 on page 4). Fast startup is triggered automatically when moving from power down to power up. The VDD must have been high before moving from power down to power up to guarantee proper operation of fast startup circuitry. Additionally the device should have been kept in power down state at least 50ms before power up. This guarantees that the AGC capacitor voltage has been completely pulled to VDD during power down. The startup time without proper fast startup control can be several minutes. With fast startup it is shortened typically to few seconds. Note 4: Optional Control for AGC On/Hold AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected. Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive of analog clock or watch can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal level. This can be avoided by controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC (AON=VDD) when motors are not driven. The AGC should be in hold only during disturbances and kept on other time released since due to leakage the AGC can change slowly when in hold. Note 5: Ferrite Antenna The ferrite antenna converts the transmitted radio wave into a voltage signal. It has an important role in determining receiver performance. Recommended antenna impedance at resonance is around 150 kΩ. Low antenna impedance corresponds to low noise but often also to small signal amplitude. On the other hand high antenna impedance corresponds to high noise but also large signal. The optimum performance where signal-to-noise ratio is at maximum is achieved in between. The antenna should have also some selectivity for rejecting near signal band disturbances. This is determined by the antenna quality factor which should be approximately 100. Much higher quality factor antennas suffer from extensive tuning accuracy requirements and possible tuning drifts by the temperature. Antenna impedance can be calculated using equation 1 where f0, L, Qant and C are resonance frequency, coil inductance, antenna quality factor and antenna tuning capacitor respectively. Antenna quality factor Qant is defined by ratio of resonance frequency f0 and antenna bandwidth B (equation 2). Rantenna = 2π ⋅ f 0 ⋅ L ⋅ Qantenna = Qantenna = Qantenna 1 = 2π ⋅ f 0 ⋅ C 2π ⋅ B ⋅ C f0 B Equation 1. Equation 2. Table 5 below presents some antenna manufacturers for time signal application. Table 5. Antenna Manufacturers and Antenna Types in Alphaphetical Order for Time Signal Application Manufacturer Antenna Type Dimensions Web Link HR Electronic GmbH Sumida 60716 (60kHz) 60708 (77.5kHz) ACL80A (40kHz) ø 10 x 60 mm http://www.hrelectronic.com/ ø 10 x 80 mm www.sumida.co.jp/jeita/XJA021.pdf 8 (10) DA6179.000 22 January, 2007 MAS6179 SAMPLES IN SBDIL 20 PACKAGE 1 20 VSS 19 RFI2 18 RFIM VDD 2 QO2 3 6 QI 7 AGC 8 17 RFIP 6179zz YYWW XXXXX.X QO1 4 QO3 5 16 RFI3 15 14 PDN1 13 AON PDN2 9 12 DEC 11 OUT 10 Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number zz = Sample Version PIN DESCRIPTION Pin Name VDD QO2 QO1 QO3 QI AGC PDN2 OUT DEC AON PDN1 RFI3 RFIP RFIM RFI2 VSS Pin Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC P AO AO AO NC AI AO DI DO NC AO DI DI NC AI AI AI AI G Function Note Positive Power Supply Quartz Filter Output for Crystal 2 Quartz Filter Output for Crystal 1 Quartz Filter Output for Crystal 3 1 Quartz Filter Input for Crystal AGC Capacitor Power Down/Frequency Selection Input 2 Receiver Output 2 3 Demodulator Capacitor AGC On Control Power Down/Frequency Selection Input 1 4 2 Receiver Input 3 (for Antenna Capacitor 3) Positive Receiver Input Negative Receiver Input Receiver Input 2 (for Antenna Capacitor 2) Power Supply Ground 5 5 A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected Notes: 1) Pin 6 between QO3 and QI must be connected to VSS to eliminate DIL package lead frame parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) PDN1 = PDN2 = VDD means receiver off - Fast start-up is triggered when the receiver is after power down controlled to power up 3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD 9 (10) DA6179.000 22 January, 2007 ORDERING INFORMATION Product Code Product Description Capacitance Option MAS6179A1TC00 Tri Band AM-Receiver IC with Differential Input Tri Band AM-Receiver IC with Differential Input EWS-tested wafer, Thickness 400 µm. EWS-tested wafer, Thickness 400 µm. CC = 0.75 pF MAS6179A2TC00 CC = 1.3 pF Contact Micro Analog Systems Oy for other wafer thickness options. LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 10 (10)