19-2623; Rev 0; 1/03 KIT ATION EVALU E L B A AVAIL 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Features ♦ Operates from a 1.6V to 5.5V Supply (MAX1956) The MAX1955/MAX1956 are dual-output, fixed-frequency, voltage-mode, pulse-width modulated (PWM) step-down controllers with 0.5% output accuracy. Each controller switches at a constant 600kHz and is 180° out-of-phase with the other controller, reducing input ripple current and the number of input capacitors. ♦ 0.5% Output Accuracy ♦ 0.8V to 0.9VIN Output Range ♦ Up to 25A per Phase Output Current ♦ On-Chip Boost Regulator Provides 5V Gate Drive An on-chip bias supply generates a 5V gate drive to deliver up to 25A output current per phase with low-cost N-channel MOSFETs at up to 93% efficiency. Lossless adjustable current limit eliminates expensive currentsense resistors and improves efficiency. Foldback current limit reduces power dissipation during short-circuit conditions and handles transient overloads better than controllers using hiccup-mode short-circuit protection. ♦ Up to 93% Efficiency ♦ 180° Out-of-Phase Operation ♦ ±4% Voltage Margining ♦ Lossless, Foldback Current Limit ♦ Selectable Voltage Sequencing ♦ Synchronizable to External Clock Output voltage margining shifts output voltage by ±4% from the nominal value to simplify system test. Outputs also can be powered up and down in selectable sequences to meet core and logic supply-rail requirements. ♦ Digital Soft-Start and Soft-Stop ♦ Small 28-Pin, 5mm ✕ 5mm Thin QFN Package Ordering Information The MAX1955/MAX1956 are available in a 28-lead thin QFN package with exposed pad. PART Applications Base Stations Telecom and Network Equipment Servers DSP, ASIC, µP, and FPGA Supplies TEMP RANGE PIN-PACKAGE MAX1955ETI -40°C to +85°C 28 Thin QFN-EP* MAX1956ETI -40°C to +85°C 28 Thin QFN-EP* *EP = Exposed pad. Pin Configuration appears at end of data sheet. Typical Operating Circuit INPUT 1.6V TO 5.5V VDD IN LXB OUTPUT 1 0.8V TO 0.9VIN UP TO 25A VDD BST2 BST1 DH2 DH1 LX1 LX2 MAX1956 OUTPUT 2 0.8V TO 0.9VIN UP TO 25A DL2 DL1 PGND FB1 COMP1 FB2 COMP2 REF SEQ GND SYNCHRONIZATION CLOCK ON/OFF VOLTAGE MARGINING ILIM1 SYNC EN ILIM2 VDD AVDD ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1955/MAX1956 General Description MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers ABSOLUTE MAXIMUM RATINGS IN, AVDD, SYNC, EN, ILIM_, FB_, SEQ to GND.......-0.3V to +6V COMP_, REF to GND..............................-0.3V to (VAVDD + 0.3V) LXB to GND ..............................................-0.3V to (VVDD + 0.3V) DL_ to GND ...............................(VPGND - 0.3V) to (VVDD + 0.3V) BST_ to GND ..........................................................-0.3V to +12V DH1 to LX1 ...............................................-0.3V to (BST1 + 0.3V) DH2 to LX2 ...............................................-0.3V to (BST2 + 0.3V) LX1 to BST1..............................................................-6V to +0.3V LX2 to BST2..............................................................-6V to +0.3V PGND to GND or VDD to AVDD ............................-0.3V to +0.3V REF Short-Circuit to GND...........................................Continuous IVDD ...................................................................................250mA Continuous Power Dissipation* (TA = +70°C) 28-Lead Thin QFN (derate 20.8mW/°C above +70°C)................................1667mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C *Exposed pad soldered to PC board. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = VEN = 3.3V; VVDD = VAVDD = 5V; VPGND = VGND = 0; CREF = 0.22µF; SEQ = SYNC = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER IN Input Voltage Range IN Input Voltage UVLO CONDITIONS MIN TYP MAX MAX1955 2.25 5.50 MAX1956 (Note 1) 1.6 5.5 MAX1955, hysteresis = 35mV 1.9 2.2 MAX1956, hysteresis = 30mV 1.30 1.58 Rise or fall FB Regulation Voltage UNITS V V 0.796 0.8 0.804 V FB Regulation Voltage with Positive Voltage Margining Percentage change from nominal regulation voltage 3 4 5 % FB Regulation Voltage with Negative Voltage Margining Percentage change from nominal regulation voltage -5 -4 -3 % Line Regulation Error Note 2 Feedback Input Bias 0.1 -0.2 Feedback Transconductance 1 2 COMP Source Current 100 150 COMP Sink Current 100 150 COMP Pulldown Resistance In shutdown % µA 3 mS µA µA 100 Output Soft-Start Time 4.27 Step-Down Switching Frequency SYNC = GND (Note 3) 540 SYNC Frequency Range 2 times step-down switching frequency 1080 Maximum Duty Cycle Measured at DH_ Minimum Duty Cycle Measured at DH_ 2 0.3 +0.2 90 600 Ω ms 660 kHz 1320 kHz 93 97 % 7 10 % _______________________________________________________________________________________ 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers (VIN = VEN = 3.3V; VVDD = VAVDD = 5V; VPGND = VGND = 0; CREF = 0.22µF; SEQ = SYNC = GND; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER VDD No-Load Supply Current CONDITIONS MIN Total of VDD1 + VDD2 + AVDD current, SYNC = GND, no load on DH_ or DL_ IN Supply Current TYP MAX UNITS 20 32 mA 35 100 µA 20 µA 1.28 1.293 V 0.01 V mV IN Shutdown Supply Current REF Voltage 1.267 REF Load Regulation IREF = -50µA to +50µA Default Current-Limit Threshold ILIM_ = VDD, measured from PGND to LX_ 127.5 150 172.5 RILIM_ = 100kΩ 60 75 90 RILIM_ = 400kΩ 240 300 360 Adjustable Current-Limit Threshold Measured from PGND to LX_ Thermal-Shutdown Threshold TJ rising, 15°C hysteresis DH_ Gate-Driver On-Resistance Pulling up or down 1 1.8 Ω DL_ Gate-Driver Pullup On-Resistance DL_ high state 1 1.8 Ω DL_ Gate-Driver Pulldown On-Resistance DL_ low state 0.35 0.65 Ω Dead Time (Adaptive) °C 160 DH_ falling to DL_ rising 23 DL_ falling to DH_ rising 26 SYNC Minimum Pulse Width High or low 200 EN Voltage Range for Nominal Output Voltage Percentage of VIN 80 EN Voltage Range for Positive Voltage Margining Percentage of VIN EN Voltage Range for Negative Voltage Margining mV ns ns 90 100 % 55 70 % Percentage of VIN 30 45 % EN Voltage Range for Shutdown Percentage of VIN 0 20 % EN, SEQ, SYNC Input High Voltage (Note 4) VIN - 0.5 SEQ, SYNC Input Low Voltage V 0.5 V EN, SEQ, SYNC Input Current -1 +1 µA BST_ Leakage Current in Shutdown -20 +20 µA 4.75 5.50 V VDD Output Voltage IVDD = 0 to 150mA _______________________________________________________________________________________ 3 MAX1955/MAX1956 ELECTRICAL CHARACTERISTICS (continued) MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers ELECTRICAL CHARACTERISTICS (VIN = VEN = 3.3V; VVDD = VAVDD = 5V; PGND = GND = 0; CREF = 0.22µF; SYNC = GND; TA = -40°C to +85°C, unless otherwise noted.) (Note 5) PARAMETER IN Input Voltage Range IN Input Voltage UVLO CONDITIONS MIN TYP MAX MAX1955 2.25 5.50 MAX1956 (Note 1) 1.6 5.5 Rise or fall UNITS V MAX1955 1.9 2.2 MAX1956 1.30 1.58 0.794 0.806 V FB Regulation Voltage V FB Regulation Voltage with Positive Voltage Margining Percentage change from nominal regulation voltage +3 +5 % FB Regulation Voltage with Negative Voltage Margining Percentage change from nominal regulation voltage -5 -3 % Line Regulation Error (Note 2) 0.3 % FB_ Input Bias -0.2 +0.2 µA Feedback Transconductance 1.0 3.1 mS COMP_ Source Current 100 COMP_ Sink Current 100 µA µA 100 Ω 540 660 kHz 1080 1320 kHz 97 % Measured at DH_ 10 % Total of VDD1 + VDD2 + AVDD current, SYNC = GND, no load on DH_ or DL_ 32 mA IN Quiescent Supply Current 100 µA IN Shutdown Supply Current 20 µA 1.267 1.293 V 0.01 V 127.5 172.5 mV RILIM_ = 100kΩ 60 90 RILIM_ = 400kΩ 240 360 COMP_ Pulldown Resistance In shutdown Step-Down Switching Frequency SYNC = GND (Note 3) SYNC Frequency Range 2 times step-down switching frequency Maximum Duty Cycle Measured at DH_ 90 Minimum Duty Cycle VDD Quiescent Supply Current REF Voltage REF Load Regulation IREF = -50µA to +50µA Default Current-Limit Threshold ILIM_ = VDD; measured from PGND to LX_ Adjustable Current-Limit Threshold Measured from PGND to LX_ 4 _______________________________________________________________________________________ mV 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers (VIN = VEN = 3.3V; VVDD = VAVDD = 5V; PGND = GND = 0; CREF = 0.22µF; SYNC = GND; TA = -40°C to +85°C, unless otherwise noted.) (Note 5) MAX UNITS DH_ Gate-Driver On-Resistance PARAMETER Pulling up or down CONDITIONS MIN TYP 1.8 Ω DL_ Gate-Driver Pullup On-Resistance DL_ high state 1.8 Ω DL_ Gate-Driver Pulldown On-Resistance DL_ low state 0.65 Ω SYNC Minimum Pulse Width High or low 200 EN Voltage Range for Nominal Output Voltage Percentage of VIN 80 100 % EN Voltage Range for Positive Voltage Margining Percentage of VIN 55 70 % EN Voltage Range for Negative Voltage Margining Percentage of VIN 30 45 % EN Voltage Range for Shutdown Percentage of VIN 0 20 % EN, SEQ, SYNC Input High Voltage (Note 4) ns VIN - 0.5 SEQ, SYNC Input Low Voltage V 0.5 V EN, SEQ, SYNC Input Current -1 +1 µA BST_ Leakage Current in Shutdown -20 +20 µA 4.75 5.50 V VDD Output Voltage Note 1: Note 2: Note 3: Note 4: Note 5: IVDD = 0 to 150mA IN input voltage must not drop below minimum voltage because of ripple or transient conditions. Guaranteed by design. Boost frequency is 2x step-down frequency. For proper startup, EN must exceed VIN - 0.5V. Specifications to -40°C are guaranteed by design but not production tested. _______________________________________________________________________________________ 5 MAX1955/MAX1956 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 5, TA = +25°C, unless otherwise noted.) EFFICIENCY vs. LOAD CURRENT WITH 2.5V INPUT VOUT = 1.2V 70 60 VOUT = 1.2V VOUT = 1V 60 50 1 10 100 50 0.1 1 10 100 0.1 100 STEP-DOWN SWITCHING FREQUENCY vs. INPUT VOLTAGE CHANGE IN OUTPUT VOLTAGE vs. LOAD CURRENT WITH 3.3V INPUT TA = +85°C 610 TA = +25°C 600 590 TA = -40°C 580 570 VOUT = 1.8V 10 20 30 40 50 -4 VOUT = 1.5V VOUT = 1.2V -6 VOUT = 2.5V -8 -10 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT -14 540 -50 -40 -30 -20 -10 0 -2 -12 550 1.270 0 1.6 2.1 2.6 3.1 0 3.6 5 10 15 20 REFERENCE LOAD CURRENT (µA) INPUT VOLTAGE (V) LOAD CURRENT (A) CHANGE IN OUTPUT VOLTAGE vs. LOAD CURRENT WITH 3.3V INPUT OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD -2 VOUT = 1.5V VOUT = 1.2V VOUT = 1.8V -8 2.5 DEVICE IN DROPOUT VOUT = 1.8V 2.0 VOUT = 1.5V 1.5 1.0 VOUT = 1.2V -10 OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT 0.5 5 10 15 LOAD CURRENT (A) 20 25 VOUT = 2.5V 2.5 VOUT = 1.8V DEVICE IN DROPOUT 2.0 VOUT = 1.5V 1.5 1.0 VOUT = 1.2V OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 0.5 0 -14 3.0 OUTPUT VOLTAGE (V) 0 VOUT = 2.5V OUTPUT VOLTAGE (V) VOUT = 2.5V MAX1955/56 toc08 3.0 MAX1955/56 toc07 2 25 MAX1955/56 toc09 FREQUENCY (kHz) 620 2 MAX1955/56 toc06 630 CHANGE IN OUTPUT VOLTAGE (mV) MAX1955/56 toc04 640 560 6 10 REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT 1.275 0 1 LOAD CURRENT (A) 1.280 -12 70 LOAD CURRENT (A) 1.285 -6 VOUT = 1.2V LOAD CURRENT (A) 1.290 -4 80 60 50 0.1 REFERENCE VOLTAGE (V) 80 70 VOUT = 1.5V 90 EFFICIENCY (%) VOUT = 1.5V VOUT = 1.8V 90 MAX1955/56 toc05 EFFICIENCY (%) 80 VOUT = 1.5V EFFICIENCY (%) VOUT = 2.5V 100 MAX1955/56 toc02 VOUT = 1.8V 90 100 MAX1955/56 toc01 100 MAX1956 EFFICIENCY vs. LOAD CURRENT WITH 1.8V INPUT MAX1955/56 toc03 EFFICIENCY vs. LOAD CURRENT WITH 3.3V INPUT CHANGE IN OUTPUT VOLTAGE (mV) MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers 0 2.35 2.60 2.85 3.10 INPUT VOLTAGE (V) 3.35 3.60 2.35 2.60 2.85 3.10 INPUT VOLTAGE (V) _______________________________________________________________________________________ 3.35 3.60 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers DEVICE IN DROPOUT VOUT = 1.8V 2.0 VOUT = 1.5V 1.5 1.0 VOUT = 1.2V VOUT = 1.5V 1.5 1.0 VOUT = 1.2V OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 0.5 0 2.60 2.85 3.10 3.60 3.35 -10 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT -14 2.35 2.60 2.85 3.10 1.6 3.60 3.35 2.1 2.6 3.6 3.1 OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 0 -2 -4 MAX1956 VOUT = 1V ONLY -6 -8 -10 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT -12 -14 VOUT = 0.8V 3.10 3.60 -2 VOUT = 0.8V MAX1956 ONLY -6 -8 -10 2.10 2.35 2.60 3.10 3.60 OTHER OUTPUT SET TO 1.8V WITH 25A LOAD CURRENT 1.60 INPUT VOLTAGE (V) LOAD TRANSIENT WITH 1.5V OUTPUT VOUT = 1V -4 -14 1.60 INPUT VOLTAGE (V) VOUT = 1.2V 0 -12 -14 2.10 2.35 2.60 2 2.10 2.35 2.60 VLX2 3.60 SYNCHRONIZATION WAVEFORMS MAX1955/56 toc17 50mV/div 3.10 INPUT VOLTAGE (V) SWITCHING WAVEFORMS MAX1955/56 toc16 VOUT MAX1955/56 toc15 MAX1955/56 toc14 VOUT = 1.2V CHANGE IN OUTPUT VOLTAGE (mV) VOUT = 0.8V 2 CHANGE IN OUTPUT VOLTAGE (mV) MAX1955/56 toc13 CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD -8 1.60 -8 CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD MAX1956 ONLY -12 -6 CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD VOUT = 1V -10 -4 INPUT VOLTAGE (V) 0 -6 VOUT = 0.8V INPUT VOLTAGE (V) VOUT = 1.2V -4 VOUT = 1V -2 INPUT VOLTAGE (V) 2 -2 VOUT = 1.2V 0 -12 0 2.35 CHANGE IN OUTPUT VOLTAGE (mV) DEVICE IN DROPOUT VOUT = 1.8V 2.0 2 MAX1955/56 toc12 2.5 OTHER OUTPUT SET TO 1.8V WITH 2.5A LOAD CURRENT 0.5 VOUT = 2.5V WITH 20A LOAD OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.5 3.0 CHANGE IN OUTPUT VOLTAGE (mV) VOUT = 2.5V WITH 20A LOAD MAX1955/56 toc10 3.0 MAX1956 CHANGE IN OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH NO LOAD OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD MAX1955/56 toc11 OUTPUT VOLTAGE vs. INPUT VOLTAGE WITH 25A LOAD MAX1955/56 toc18 5V/div IL2 VSYNC 1V/div 5V/div VDH1 5V/div 5A/div VDH2 5V/div 5A/div VLX1 IOUT 10A/div 10µs/div IL1 400ns/div 2µs/div _______________________________________________________________________________________ 7 MAX1955/MAX1956 Typical Operating Characteristics (continued) (Circuit of Figure 5, TA = +25°C, unless otherwise noted.) MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Typical Operating Characteristics (continued) (Circuit of Figure 5, TA = +25°C, unless otherwise noted.) NO LOAD TO SHORT CIRCUIT 20A LOAD TO SHORT CIRCUIT MAX1955/56 toc19 VOUT HIGH OUTPUT MARGINING MAX1955/56 toc20 1V/div VOUT MAX1955/56 toc21 1V/div IL 10A/div VCTL1 5V/div VCTL2 5V/div VOUT1 100mV/div VOUT2 100mV/div 10A/div IL 0A 40µs/div 40µs/div LOW-OUTPUT MARGINING SHUTDOWN/STARTUP WITH SEQ = AVDD SHUTDOWN/STARTUP WITH SEQ = GND MAX1955/56 toc22 MAX1955/56 toc23 VCTL1 5V/div VCTL2 5V/div VOUT1 100mV/div VOUT2 100mV/div 100µs/div 100µs/div MAX1955/56 toc24 VCTL1 5V/div VCTL1 5V/div VCTL2 5V/div VCTL2 5V/div VOUT1 1V/div VOUT1 1V/div VOUT2 1V/div VOUT2 1V/div 4ms/div 4ms/div Pin Description 8 PIN NAME FUNCTION 1 DL1 Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL1 is pulled low in shutdown. 2 LX1 Inductor Connection. Connect to the switched side of the inductor. 3 DH1 High-Side MOSFET Gate-Driver Output. Connect to the high-side MOSFET gate. DH1 is pulled low in shutdown. 4 BST1 High-Side MOSFET Gate-Driver Bootstrap Connection. Connect a capacitor from BST1 to LX1 and a Schottky diode from VDD to BST1. 5 SYNC Frequency Synchronization Input. Connect to GND for normal 600kHz operation, or drive with a clock signal from 1080kHz to 1320kHz. The two step-down regulators are synchronized to alternating clock pulses, resulting in 180° out-of-phase operation at half the synchronization frequency. _______________________________________________________________________________________ 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers PIN NAME FUNCTION 6 EN Enable and Voltage Margining Input. Connect EN to IN for normal operation or connect to GND for shutdown. Set VEN = (1/3)VIN to set the outputs to -4% of nominal. Set VEN = (2/3)VIN to set the outputs to +4% of nominal (see the Shutdown and Output Voltage Margining (EN) section). 7 ILIM1 Current-Limit Adjust. Sets the threshold for current sensing across the low-side MOSFET’s RDS(ON). Connect ILIM1 to AVDD for a 150mV threshold. For adjustable constant current or foldback current-limit setting, see the Current Limit section. 8 FB1 9 COMP1 10 GND1 11 REF 1.28V Reference. Connect a 0.22µF capacitor from REF to GND. 12 GND Ground. Connect to the PC board analog ground plane. Connect the PC board power ground plane and analog ground plane with a single connection. 13 COMP2 14 FB2 15 ILIM2 Current-Limit Adjust. Sets the threshold for current sensing across the low-side MOSFET’s RDS(ON). Connect ILIM2 to AVDD for a 150mV threshold. For adjustable constant current or foldback current-limit setting, see the Current Limit section. 16 AVDD Analog Supply Input. Connect a 10Ω resistor from VDD to AVDD and a 0.47µF capacitor from AVDD to GND. 17 SEQ Power-Sequence Input. Connect SEQ to GND to set OUT1 and OUT2 to power up and power down simultaneously. Connect SEQ to IN to make OUT1 power up first and power down last. 18 BST2 High-Side MOSFET Gate-Driver Bootstrap Connection. Connect a capacitor from BST2 to LX2 and a Schottky diode from VDD to BST2. 19 DH2 High-Side MOSFET Gate-Driver Output. Connect to the high-side MOSFET gate. DH2 is pulled low in shutdown. 20 LX2 Inductor Connection. Connect to the switched side of the inductor. 21 DL2 Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL2 is pulled low in shutdown. 22 PGND2 23 IN 24 VDD2 Internal Boost Regulator Output. Connect to VDD1, and bypass with a 10µF capacitor to GND. 25 LXB Internal Boost Regulator Inductor Connection. Connect a 4.7µH inductor from LXB to IN. Internally shorted to VDD2 in shutdown. 26 PGND Power Ground. Connect to PC board power ground plane. 27 VDD1 Internal Boost Regulator Output. Connect to VDD2. 28 PGND1 Exposed Pad — Feedback Input. Connect to a voltage-divider from the output to GND to set the output voltage (see the Setting the Output Voltage section). Compensation. Internally pulled to ground during shutdown (see the Compensation Design section). Ground. Connect to the PC board analog ground plane. Connect PC board power ground plane and analog ground plane with a single connection. Compensation. Internally pulled to ground during shutdown (see the Compensation Design section). Feedback Input. Connect to a voltage-divider from the output to GND to set the output voltage (see the Setting the Output Voltage section). Power Ground. Connect to the low-side MOSFET source for regulator 2 and PC board power ground plane. Input Supply Power Ground. Connect to the low-side MOSFET source for regulator 1 and PC board power ground plane. Exposed Pad. Solder to the PC board analog ground plane for optimum power dissipation. _______________________________________________________________________________________ 9 MAX1955/MAX1956 Pin Description (continued) MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers REF AVDD IN VDD2 1.28V BIAS UVLO BOOST CONTROL LXB GND GND1 PGND COMP1 FB1 BST1 CONVERTER 1 DH1 CURRENT LIMIT AND SHUTDOWN SOFTSTART DAC EA PWM R Q LX1 S Q VDD1 DL1 VOLTAGE MARGINING AND SHUTDOWN EN PGND1 fSW SYNC (2 x fSW) OSCILLATOR SEQ SEQUENCING x0.15 fSW 5µA 1V ILIM1 4V COMP2 CONVERTER 2 FB2 BST2 DH2 LX2 VDD2 DL2 PGND2 ILIM2 Figure 1. Functional Diagram Detailed Description The MAX1955/MAX1956 are dual-output, fixed-frequency, voltage-mode, PWM step-down controllers with 0.5% output accuracy. Each controller switches at a constant 600kHz and is 180° out-of-phase with the other controller, which reduces input ripple current and the number of input capacitors. Figure 1 is the functional diagram. 10 An on-chip step-up bias supply generates a 5V gate drive to deliver up to 25A output current per phase with low-cost N-channel MOSFETs at up to 93% efficiency. Lossless adjustable current limit eliminates expensive current-sense resistors and improves efficiency. Foldback current limit reduces power dissipation during short-circuit condition and handles transient overloads better than controllers using hiccup-mode short-circuit protection. ______________________________________________________________________________________ 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers The MAX1955/MAX1956 step-down DC-to-DC converters use a PWM voltage-mode control scheme. The controller generates the clock signal by dividing down the internal oscillator (or SYNC signal when using an external clock) so that each controller’s switching frequency equals 1/2 the oscillator frequency. An internal transconductance error amplifier produces an integrated error voltage at the COMP_ pin, providing high DC accuracy. The voltage at COMP sets the duty cycle, using a PWM comparator and a ramp generator. At the rising edge of the clock, Regulator 1’s high-side N-channel MOSFET turns on and remains on until either the appropriate duty cycle or the maximum duty cycle is reached. Regulator 2 operates out of phase, so its high-side MOSFET turns on at the falling edge of the clock. During the on-time of each high-side MOSFET, the associated inductor current ramps up. During the second half of the switching cycle, the highside MOSFET turns off and the low-side N-channel MOSFET (synchronous rectifier) turns on. The inductor releases its stored energy as its current ramps down, providing current to the load. High-Side Gate-Drive Supply (BST) The gate-drive voltage for the high-side N-channel switch is generated by a flying capacitor. This capacitor between BST and LX is alternately charged from the VDD supply and placed in parallel to the high-side MOSFET’s gate and source terminal through the high-side driver. On startup, the low-side MOSFET forces LX to ground and charges the boost capacitors to VDD through the Schottky diodes (D1 and D2 of Figure 5). On the second half cycle, the controller turns on the high-side MOSFET by closing an internal switch between BST and DH. This provides the necessary gate-to-source voltage to turn on the high-side MOSFET, an action that boosts the 5V gate-drive signal above the input voltage. Current Limit The current-limit circuit employs a “valley” currentsensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the Constant-Current Limit The adjustable current limit accommodates MOSFETs with a wide range of on-resistance values. The currentlimit threshold is adjusted with an external resistor connected from ILIM_ to GND (RILIM_). The adjustment range is 75mV to 300mV, measured across the low-side MOSFET. The value of RILIM_ is calculated using the following formula: RILIM _ = IVALLEY × RDS(ON) 0.15 × 5µA where IVALLEY is the valley current limit and RDS(ON) is the on-resistance of the low-side MOSFET. To avoid reaching the current limit at a lower current than expected, use the maximum value for RDS(ON) at an elevated junction temperature. Refer to the MOSFET manufacturer’s data sheet for maximum values. IPEAK ILOAD INDUCTOR CURRENT DC-to-DC PWM Controller current-sense signal (measured from PGND_ to LX_) is above the current-limit threshold, the MAX1955/ MAX1956 do not initiate a new cycle, and COMP_ is pulled to ground. Since valley current sensing is used, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current (Figure 2). The exact current-limit characteristic and maximum load capacity are a function of the lowside MOSFET’s on-resistance, the current-limit threshold, the inductor value, and the input voltage. This provides a robust lossless current sense that does not require current-sense resistors. An added feature is the implementation of Schottky diodes D3 and D4 (as shown in Figure 5), which reduce output short-circuit currents. IVALLEY TIME Figure 2. Inductor Current Waveform ______________________________________________________________________________________ 11 MAX1955/MAX1956 Output voltage margining shifts the output voltage by ±4% from the nominal value to simplify system testing. Outputs also can be powered up and down in selectable sequences to meet core and logic supply rail requirements. MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Foldback Current Limit Foldback current limit is used to reduce power dissipation during overload and short-circuit conditions. This is accomplished by lowering the current-limit threshold as the output voltage drops because of overload. To use foldback current limit, connect one resistor (RFOBK) from ILIM_ to the corresponding output, and connect another resistor (RILIM) from ILIM_ to GND. The values of RILIM and RFOBK are calculated as follows: 1) First, select the percentage of foldback (PFB). This percentage corresponds to the current limit when VOUT equals zero, divided by the current limit when VOUT equals its nominal voltage. Typical values are 15% to 30%. To solve for the resistor values, use the following equations: RFOBK = RILIM = PFB × VOUT 5µA(1 - PFB ) 6.67 × RDS(ON) × IVALLEY × (1- PFB ) × RFOBK ( ) VOUT - 6.67 × RDS(ON) × IVALLEY × (1- PFB ) 2) Select PFB values that provide R ILIM greater than zero. Recovery from Overload and Short Circuit The MAX1955/MAX1956 do not recover to nominal output voltage at heavy load (near full load) after an overload or short-circuit condition, but they might operate at a voltage below the nominal output until the input power or EN pin is cycled through the OFF state. If automatic recovery is mandatory, without cycling EN or input power, add an RC filter of 1Ω and 0.015µF at LX_’s pins, as shown in Figure 6. Doing so decreases the efficiency by 2% to 3%, depending on the input voltage, output voltage, and current. In this event, the main outputs and the internal boost regulator are disabled. The boost regulator starts up again once the voltage at IN rises above the UVLO threshold. Startup and Output Sequencing The MAX1955/MAX1956 use a digital soft-start to reduce input inrush current during startup. In soft-start, the output voltage is ramped up by increasing the FB_ regulation voltage in 80 steps of 10mV. Total soft-start time is typically 4.27ms. Some power supplies exhibit soft regulation during softstart. If the MAX1955/MAX1956 are powered from such a power supply and enabled at or before power-up, the input voltage might dip below the UVLO threshold, and the output might not soft-start properly. To avoid such issues, enable the MAX1955/MAX1956 after the input supply has stabilized or add an RC filter to the IN pin of the IC as shown in Figure 6. The value of R20 is ~510Ω, and the value of capacitor C31 is from 1µF to 10µF, depending on the startup characteristic of the input power supply. The capacitor value is chosen to provide power to the IC (100µA max) and keep it from falling below the UVLO threshold during the input powersupply dip. The outputs can be set to power up at the same time, or output 1 can be set to power up first and power down last. Connect SEQ to GND for simultaneous power up/down. Connect SEQ to IN to make output 1 power up first and power down last. Figure 3 is a timing diagram. If there is a fault condition (such as a short circuit) on output 1 causing its voltage to drop below 90% of its nominal regulation voltage, and SEQ is connected to IN, then output 2 shuts down. Once the fault is cleared, allowing the voltage on output 1 to rise above 90% of its nominal regulation voltage, output 2 soft-starts and powers up again. AVDD Decoupling Due to high switching frequency and tight output tolerance (±0.5%), decoupling between VDD and AVDD is recommended. Connect a 10Ω resistor between VDD and AVDD and a 0.47µF capacitor between AVDD and GND. Place the capacitor as close to AVDD as possible. SEQ = GND SEQ = IN EN OUT1 Undervoltage Lockout (UVLO) When the voltage at IN drops below its undervoltage lockout (UVLO) threshold (see the Electrical Characteristics), the MAX1955/MAX1956 determine that the input supply voltage is too low to power the IC. 12 OUT2 4.27ms 4.27ms 4.27ms Figure 3. Timing Diagram ______________________________________________________________________________________ 4.27ms 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Thermal-Overload Protection An external clock of 1080kHz to 1320kHz at SYNC forces the controller to switch at half of this clock frequency. DH1 and DH2 positive-going edges alternately synchronize to the rising edge of the external clock, thus operating 180° out-of-phase with each other. See the Synchronization and Switching Waveforms in the Typical Operating Characteristics. Thermal-overload protection limits total power dissipation of the MAX1955/MAX1956. When the junction temperature exceeds +160°C, an internal thermal sensor shuts down the device, allowing the IC to cool. The thermal sensor turns the device on after the junction temperature cools by 15°C. In a continuous thermaloverload condition, this results in a pulsed output. Shutdown and Output Voltage Margining (EN) Low-Side MOSFET NegativeCurrent Conduction The MAX1955/MAX1956 feature a low-power shutdown mode that reduces the IC’s current consumption to less than 20µA. For normal operation, connect EN to IN. To place the part in low-current shutdown mode, connect EN to GND. Under most operating conditions, the low-side MOSFET conducts only positive inductor currents that flow from source to drain and 1/2 of the inductor peak-to-peak ripple current (~15% full load current) in the negative direction when output is at no load. If the MAX1955/ MAX1956 are disabled before their soft-start cycle is complete (~4ms), the converter is disabled without a soft-stop, and the output discharges through its load. In this case, if the converter is reenabled before the output capacitor discharges completely, the soft-start cycle resets the reference input to the error amp to zero and ramps up again. When the MAX1955/MAX1956 enter shutdown (EN goes low), soft-stop begins. In soft-stop, the output voltage is ramped down by lowering the FB_ regulation voltage to zero in 80 steps of 10mV. Total soft-stop time is typically 4.27ms. Each controller can be shut down individually by pulling COMP_ to GND with an open collector NPN transistor (Figure 6). This shuts down the controller immediately without going through soft-stop. Once COMP_ is released, the controller powers up without going through soft-start. To protect against inrush current when using this power-up/-down method, use foldback current limit. Also, connect SEQ to GND to prevent output 2 from powering down when the voltage on output 1 drops. In an effort to improve quality, many OEMs are testing their system’s operation over the range of minimum and maximum supply voltage. To facilitate this testing, the MAX1955/MAX1956 have a voltage-margining feature that increases or decreases the output voltages by 4%. The voltage on EN controls voltage margining. To increase the output voltage by 4%, apply (2/3) VIN to EN. To reduce the output voltage by 4%, apply (1/3) VIN to EN. One easy way to use the voltage-margining feature is to make two control logic inputs (CTL1 and CTL2) by connecting two resistors to EN. Connect a 200kΩ resistor from EN to CTL1, and a 100kΩ resistor from EN to CTL2 (Figure 5). The voltage margining is then controlled by connecting CTL1 and CTL2 to IN or GND, as shown in Table 1. Before applying voltage-margining, pull VCTL1 and VCTL2 to > VIN - 0.5V to ensure proper startup. The converter forces DL on until the feedback drops below the reference input. If the output is almost fully charged when the converter turns back on, a large negative current can build up in the inductor. If the negative current is excessive, a high LX voltage spike can occur because of parasitic circuit inductances as DL is released. This high LX voltage spike can shut down and latch off the circuit. To prevent this from happening, add a series resistor between DL and the gate of the low-side MOSFET (Figure 6) to slow down the turn-off di/dt, reducing the voltage spike and preventing the circuit from shutting down. A 1Ω resistor works fine for most applications without noticeable degrading impact on efficiency or Cdv/dt-induced turn-on effect. Table 1. Voltage Margining CTL1 CTL2 EN OUTPUT VIN VIN VIN Nominal 0 VIN (2/3)VIN +4% VIN 0 (1/3)VIN -4% 0 0 0 Shutdown ______________________________________________________________________________________ 13 MAX1955/MAX1956 Synchronization MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Design Procedure VOUT_ Setting the Output Voltage Output voltage is set with a resistor-divider, as shown in Figure 4. The output voltage can be set to as low as 0.8V. The maximum output voltage is limited by maximum duty cycle and external component selection. Select RX (the resistor from FB to GND) between 8kΩ and 10kΩ, and calculate RY from: V RY = RX × OUT - 1 0.8 RY FB_ RC COMP_ CF Cc RX Figure 4. Feedback Divider Network and Compensation Circuitry Inductor Selection Three key inductor parameters must be specified for operation with the MAX1955/MAX1956: inductance value (L), peak inductor current (IPEAK), and DC resistance (RDC). A good compromise between size and efficiency is to set the inductor peak-to-peak ripple current equal to 30% of maximum load current, thus LIR = 0.3. The switching frequency, input voltage, output voltage, and selected LIR determine the inductor value as follows: L= VOUT (VIN - VOUT ) VIN × fSW × IOUT(MAX) × LIR where fSW is the switching frequency (typically 600kHz). The exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, and also improve transient response, but reduce efficiency and increase output voltage ripple because of higher peak currents. Higher inductance increases efficiency by reducing the RMS current. However, resistive losses because of extra wire turns could exceed the benefit gained from lower AC current levels, especially when the inductance is increased without also allowing larger inductor dimensions. Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. The inductor’s saturation current rating must exceed the peak inductor current at the maximum defined load current (ILOAD(MAX)): LIR IPEAK = IOUT(MAX) + ×I 2 OUT(MAX) Input Capacitor Selection The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit’s switching. The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = 1 VIN (IOUT1 )2 × VOUT1 × (VIN - VOUT1) + (IOUT2 )2 × VOUT2 × (VIN - VOUT2 ) Output Capacitor Selection The key selection parameters for the output capacitor are the actual capacitance value, the ESR, the ESL, and the voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. The output ripple has three components: variations in the charge stored in the output capacitor, the voltage drop across the capacitor’s ESR, and the voltage drop across the capacitor’s ESL caused by the current into and out of the capacitor: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL) The output voltage ripple from the ESR is: VRIPPLE(ESR) = IP-P ✕ ESR The output voltage ripple because of the output capacitance is: VRIPPLE(C) = 14 IP-P 8 × COUT × fSW ______________________________________________________________________________________ 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers ESL VRIPPLE (ESL) = VIN ESL + L IP-P is the peak-to-peak inductor current: V -V V IP-P = IN OUT × OUT fSW × L VIN These equations are suitable for initial capacitor selection to meet the ripple requirement, but final values can depend on the relationship between the LC double-pole frequency and the capacitor ESR zero. Generally, the ESR zero is higher than the LC double pole. However, it is preferable to keep the ESR zero as close to the LC double pole as possible to negate the sharp phase shift of the typically high-Q double-LC pole (see the Compensation Design section). Solid polymer electrolytic capacitors are recommended because of their low ESR and ESL at the switching frequency. Higher output-current applications require multiple output capacitors connected in parallel to meet the output ripple voltage requirements. The response to a load transient depends on the output capacitor. After a load transient, the output voltage instantly changes by ESR x ∆ILOAD + ESL x dI/dt. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time (see the Typical Operating Characteristics), the controller responds by regulating the output voltage back to its nominal state. The response time depends on the closed-loop bandwidth. With a higher bandwidth, the response is faster, thus preventing the output voltage from deviating further from its nominal value. Do not exceed the capacitor’s voltage or ripple-current ratings. MOSFET Selection The MAX1955/MAX1956 drive external, logic-level, Nchannel MOSFETs as the circuit-switch elements. The key selection parameters: On-resistance (RDS(ON)): the lower the better. Maximum drain-to-source voltage (VDSS): should be at least 20% higher than input supply rail at the highside MOSFET’s drain. Gate charges (QG, QGD, QGS): the lower the better. Choose the MOSFETs with rated RDS(ON) at V GS = 4.5V. For a good compromise between efficiency and cost, choose the high-side MOSFET that has a conduction loss equal to switching loss at nominal input voltage and maximum output current (see below). For low-side MOSFET, make sure that it does not spuriously turn on because of dV/dt caused by high-side MOSFET turning on, as this would result in shoot-through current degrading the efficiency. MOSFETs with a lower QGDto-QGS ratio have higher immunity to dV/dt. For proper thermal-management design, calculate the power dissipation at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for low-side MOSFET, worst case is at VIN(MAX); for high-side MOSFET, it could be either at VIN(MIN) or VIN(MAX)). High-side MOSFET and low-side MOSFET have different loss components due to the circuit operation. Low-side MOSFET operates as a zero voltage switch; therefore, major losses are: the channel conduction loss (P LSCC), the bodydiode conduction loss (PLSDC), and the gate-drive loss (PLSDR): V 2 PLSCC = 1- OUT × (ILOAD ) × RDS(ON) V IN Use RDS(ON) at TJ(MAX): PLSDC = 2 ILOAD × VF × t DT × fSW where VF is the body-diode forward-voltage drop, tDT is the dead time (~25ns), and fSW is the switching frequency. Because of the zero-voltage switch operation, low-side MOSFET gate-drive loss occurs as a result of charging and discharging the input capacitance, (C ISS). This loss is distributed among the average DL gate driver’s pullup and pulldown resistance, (RDL (0.68Ω typ)), and the internal gate resistance (RGATE) of the MOSFET (~2Ω). The drive power dissipated is given by: RGATE 2 PLSDR = CISS × (VGS ) × fSW × RGATE + RDL High-side MOSFET operates as a duty-cycle control switch and has the following major losses: the channel conduction loss (PHSCC), the VI overlapping switching loss (PHSSW), and the drive loss (PHSDR). High-side MOSFET does not have body-diode conduction loss because the diode never conducts current: V 2 PHSCC = OUT × (ILOAD ) × RDS(ON) VIN ______________________________________________________________________________________ 15 MAX1955/MAX1956 The output voltage ripple due to the ESL of the output capacitor is: 16 SEQ SYNC CTL2 CTL1 OUT1 IN 1.5V 25A C10 680µF R10 100kΩ R9 200kΩ C28 470µF 2.25V TO 3.6V C11 680µF R3 8.06kΩ C29 470µF R14 100kΩ R2 7.15kΩ C2 10µF N2 R5 1Ω C3 10µF C16 4700pF C24 6800pF C8 82pF L1 0.3µH C17 4700pF R1 1Ω C1 10µF R7 15kΩ D3 N1 C25 33pF N4 C20 0.47µF L3 4.7µH N3 D1 17 5 6 9 8 22 28 26 1 2 3 4 PGND2 SEQ SYNC EN COMP1 FB1 U1 21 20 19 AVDD ILIM2 ILIM1 GND1 GND REF 16 15 7 10 12 11 13 FB2 14 DL2 LX2 DH2 COMP2 MAX1955 PGND1 PGND DL1 LX1 DH1 BST1 23 27 24 IN VDD1 VDD2 25 18 LXB BST2 VDD D4 N5 R8 18kΩ C27 0.22µF C26 33pF N7 C9 0.47µF D2 N8 C21 0.47µF R13 10Ω R12 56.2kΩ R11 60.4kΩ C23 6800pF L2 0.3µH N6 C14 4700pF R15 1Ω VDD C22 10µF R19 90.9kΩ R6 8.06kΩ R4 10kΩ C15 4700pF R16 1Ω C7 82pF C4 10µF R18 75kΩ OUT1 C6 10µF C12 680µF C5 10µF C13 680µF 1.8V 25A OUT2 MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Figure 5. Typical Application Circuit ______________________________________________________________________________________ SYNC CTL2 CTL1 OUT1 1.5V 25A R10 100kΩ OFF R2 7.15kΩ C2 10µF N2 R5 1Ω R26 10kΩ R25 10kΩ D3 N1 R7 15kΩ C3 10µF C16 4700pF C24 6800pF C8 82pF L1 0.3µH C17 4700pF R1 1Ω C1 10µF ENABLE1 ON R14 100kΩ R3 8.06kΩ C29 470µF C11 680µF R9 200kΩ C28 470µF C10 680µF 2.25V TO 3.6V R23 1Ω C32 0.015µF R21 1Ω C31 4.7µF N3 Q1 MMBT3904 C25 33pF N4 C20 0.47µF L3 4.7µH R20 510Ω 17 5 6 9 8 22 28 26 1 2 3 4 25 D1 PGND2 ON ENABLE2 OFF SEQ SYNC EN COMP1 FB1 U1 FB2 DL2 LX2 DH2 16 15 7 10 12 11 13 14 21 20 19 C27 0.22µF C26 33pF N7 R22 1Ω C30 0.015µF C9 0.47µF D2 R24 1Ω R28 10kΩ R27 10kΩ AVDD ILIM2 ILIM1 GND1 GND REF COMP2 MAX1955 PGND1 PGND DL1 LX1 DH1 BST1 23 27 24 IN VDD1 VDD2 18 LXB BST2 VDD D4 Q2 MMBT3904 C14 4700pF R15 1Ω C23 6800pF R13 10Ω R12 56.2kΩ R11 60.4kΩ L2 0.3µH N6 C21 0.47µF N8 R8 18kΩ N5 VDD C22 10µF R19 90.9kΩ R6 8.06kΩ R4 10kΩ C15 4700pF R16 1Ω C7 82pF C4 10µF R18 75kΩ C13 680µF C6 10µF OUT1 C12 680µF C5 10µF 1.8V 25A OUT2 MAX1955/MAX1956 IN 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Figure 6. Independent Output On/Off Control ______________________________________________________________________________________ 17 MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Use RDS(ON) at TJ(MAX). QGS + QGd PHSSW = VIN × ILOAD × fSW × IGATE where IGATE is the average DH driver output-current determined by: IGATE(ON) = 2.5 RDH + RGATE where RDH is the high-side MOSFET driver’s on-resistance (1Ω typical) and RGATE is the internal gate resistance of the MOSFET (~2Ω): RGATE PHSDR = QG × VGS × fSW × RGATE + RDH where VGS = VVDD = 5V. In addition to the losses above, allow about 20% more for additional losses because of MOSFET output capacitances and low-side MOSFET body-diode reverse recovery charge dissipated in the high-side MOSFET that is not well defined in the MOSFET data sheet. Refer to the MOSFET data sheet for thermal-resistance specifications to calculate the PC board area needed to maintain the desired maximum operating junction temperature with the above-calculated power dissipations. To reduce EMI caused by switching noise, add a 0.1µF ceramic capacitor from the high-side switch drain to the low-side switch source, or add resistors in series with DH and DL to slow down the switching transitions. Adding series resistors increases the power dissipation of the MOSFET, so ensure that this does not overheat the MOSFET. MOSFET Snubber Circuit Fast switching transitions cause ringing because of resonating circuit parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at LX’s rising and falling transitions and can interfere with circuit performance and generate EMI. To dampen this ringing, a series R-C snubber circuit is added across each switch. Below is the procedure for selecting the value of the series R-C circuit: 1) Connect a scope probe to measure VLX to GND, and observe the ringing frequency, fR. 2) Find the capacitor value (connected from LX to GND) that reduces the ringing frequency by half. The circuit parasitic capacitance (CPAR) at LX is then equal to 1/3 the value of the added capacitance above. The circuit parasitic inductance (LPAR) is calculated by: 18 LPAR = 1 (2πfR ) 2 × CPAR The resistor for critical dampening (RSNUB) is equal to 2π x fR x LPAR. Adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. The capacitor (CSNUB) should be at least 2 to 4 times the value of the C PAR in order to be effective. The power loss of the snubber circuit is dissipated in the resistor (PRSNUB) and can be calculated as: PRSNUB = CSNUB × ( VIN ) 2 × fSW where VIN is the input voltage and fSW is the switching frequency. Choose an RSNUB power rating that meets the specific application’s derating rule for the power dissipation calculated. Boost-Supply Diode and Capacitor A low-current Schottky diode, such as CMSSH-3 from Central Semiconductor, works well for most applications. Do not use large-power diodes, because higher junction capacitance can charge up the BST to LX voltage and can exceed the device rating of 6V. The boost capacitor should be 0.1µF to 4.7µF, depending on the input and output voltages, external components, and PC board layout. The boost capacitance should be as large as possible to prevent it from charging to excessive voltage, but small enough to adequately charge during the minimum low-side MOSFET conduction time, which happens at maximum operating duty cycle (this occurs at minimum input voltage). In addition, ensure that the boost capacitor does not discharge to below the minimum gate-to-source voltage required to keep the high-side MOSFET fully enhanced for lowest on-resistance. This minimum gateto-source voltage VGS(MIN) is determined by: VGS(MIN) = VVDD - QG CBOOST where VVDD is 5V, QG is the total gate charge of the high-side MOSFET, and CBOOST is the boost capacitor value. Compensation Design The MAX1955/MAX1956 use a voltage-mode control scheme that regulates the output voltage by comparing the error amplifier output (COMP) with a fixed internal ramp to produce the required duty cycle. The inductor and output capacitor create a double pole at the resonant frequency, which has a gain drop of 40dB per decade and phase shift of 180°. The error amplifier ______________________________________________________________________________________ 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers The basic regulator loop consists of a power modulator, an output feedback divider, and an error amplifier. The power modulator has DC gain set by VIN/VRAMP, with a double pole set by the inductor and output capacitor and a single zero set by the output capacitor (COUT) and its ESR. Equations that define the power modulator follow: pensation capacitor (CC), the amplifier-output resistance (RO ≅ 5MΩ), and the compensation resistor (RC): fPEA = A zero is set by the compensation resistor and the compensation capacitor: fZEA = The DC gain of the power modulator: GMOD(DC) = VIN VRAMP where V RAMP = 1V. The double-pole frequency because of the inductor and output capacitor is: fPMOD = 1 2π LCOUT The zero frequency because of the output capacitor’s ESR is: fZESR = 1 2π × ESR × COUT The output capacitor is usually composed of several same-value capacitors connected in parallel. With n capacitors in parallel, the output capacitance is: The loop-gain equation at the crossover frequency is: VFB × GEA ( fc) × GMOD( fc) = 1 VOUT where: GEA(fc) = gmEA ✕ RC, and GMOD(fc) = GMOD(DC) ✕ (fPMOD)2 / (fESR ✕ fC) The compensation resistor (RC) is calculated from: RC = ESR = ESREACH n The ESR zero (f ZESR ) for a parallel combination of capacitors is the same as that of an individual capacitor. The feedback divider has a gain of GFB = VFB/VOUT, where VFB is 0.8V. The transconductance error amplifier has DC gain GEA(dc) of 80dB. A dominant pole is set by the com- 1 2π × CC × RC The total closed-loop gain must equal unity at the crossover frequency, where the crossover frequency should be higher than fZESR, so that the -1 slope is used to cross over at unity gain. Also, the crossover frequency should be less than or equal to 1/5 the switching frequency: f fZESR < fC < SW 5 COUT = n × CEACH The total ESR is: 1 2π × CC × (RO + RC ) VOUT gmEA × VFB × GMOD( fc) where gmEA = 2mS. Because of the underdamped (Q > 1) nature of the output LC double pole, the error amplifier compensation zero should be approximately 0.2 fPMOD to provide good phase boost. CC is calculated from: CC = 5 2π × RC × fPMOD A small capacitor (CF) also can be added from COMP to GND to provide high-frequency decoupling. CF adds ______________________________________________________________________________________ 19 MAX1955/MAX1956 must compensate for this gain drop and phase shift in order to achieve a stable high-bandwidth closed-loop system. MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers another high-frequency pole (fPHF) to the error-amplifier response. This pole should be greater than 100 times the error-amplifier zero frequency in order to have negligible impact on the phase margin. This pole also should be less than half the switching frequency for effective decoupling: 100fZEA < fPHF < 0.5fSW Select a value for fPHF in the range given above, and then solve for CF using the following equation: CF = 1 2π × RC × fPHF With two converters in proximity, there is a potential for crosstalk between the converters. Crosstalk can be managed by board layout and high-frequency filtering, which can be inserted by adding a high-frequency pole in the feedback network. To do so and minimize effect on phase margin, add capacitors C7 and C8 (Figure 5) with a pole frequency of: fPFB2 = (R4 + R6) / 2π x R4 x R6 x C7) fPFB1 = (R2 + R3) / (2π x R2 x R3 x C8) Set the poles above ~4 to 5 times the crossover frequency. Below is a numerical example to calculate the compensation values used in the typical application circuit of Figure 5: VIN = 3V (the midpoint of the input voltage range) VRAMP = 1V VOUT = 1.8V VFB = 0.8V IOUT(MAX) = 25A COUT = 2 x 680µF ESR = 0.008Ω / 2 = 0.004Ω L = 0.3µH gmEA = 2mS fSW = 600kHz fPMOD = = 1 1 = 2π × COUT × ESR 2π × 1360 × 10-6 × 0.004 = 29.3kHz fZESR = Pick the crossover frequency (fC) in the range fZESR < fC < fSW/5: 29.3kHz < fC < 120kHz Select fC = 100kHz (this meets the criteria above), and the bandwidth is high enough for good transient response. The power-modulator gain at fC is: GMOD(fc) = = 1 1 2π × 0.3 × 10-6 × 1360 × 10-6 = 7.879kHz VRAMP × (fPMOD )2 fZESR × fC (7.879kHz)2 3 × = 0.0477 1 29.3kHz × 100kHz Pick RX = 8.06kΩ, then RY = 10kΩ (see the Setting the Output Voltage section). VOUT gmEA × GMOD( fc) × VFB 1.8 = = 17.6kΩ 0.002 × 0.8 × .0636 RC = Select RC = 18kΩ (nearest standard resistor value). CC = 5 5 = = 5620pF 2π × RC × fPMOD 2π × 18kΩ × 7.879kHz Select CC = 6800pF (rounded up to the next standard capacitor value). Select fPHF in the range 100fZEA < fPHF < 0.5fSW. Hence: 157.6kHz < fPHF < 300kHz Select fPHF = 250kHz, and then solve for CF: CF = 2π × L × COUT VIN 1 1 = = 33pF 2π × RC × fPHF 2π × 18kΩ × 250kHz A summary of feedback divider and compensation components follows: RX = 8.06kΩ RY = 10kΩ RC = 18kΩ CC = 6800pF CF = 33pF 20 ______________________________________________________________________________________ 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers Pin Configuration Table 2. Typical Application Circuit Components DESIGNATION QTY DESCRIPTION C10–C13 4 680µF, 2.5V POSCAPs Sanyo 2R5TPD680M8 C28, C29 2 470µF, 6.3V POSCAPs Sanyo 6TPB470M D1–D4 4 Schottky diodes (SOT 323) Central CMSSH-3 L1, L2 2 0.3µH, 35A inductors Sumida CDEP125(U)-0R3 L3 1 4.7µH inductor TDK LDR655312T-4R7W N1, N2, N5, N6 4 N-channel MOSFETs Vishay Si7892DP N3, N4, N7, N8 4 N-channel MOSFETs Vishay Si4842DY PGND1 VDD1 PGND LXB VDD2 IN PGND2 27 26 25 24 23 22 1 21 DL2 LX1 2 20 LX2 DH1 3 19 DH2 BST1 4 18 BST2 SYNC 5 17 SEQ EN 6 16 AVDD ILIM1 7 15 ILIM2 10 11 12 13 14 GND1 REF GND COMP2 FB2 9 COMP1 MAX1955 MAX1956 8 4) Ensure all feedback connections are short and direct. Place the feedback resistors as close to the IC as possible. 5) Route high-speed switching nodes (LX_) away from sensitive analog areas (FB_, COMP_). For a sample PC board layout, refer to the MAX1955 evaluation kit. Table 2 lists typical application circuit components. DL1 FB1 3) Connect the drains of the MOSFETs to a large land area to help cooling the devices to further improve efficiency and long-term reliability. TOP VIEW 28 PC Board Layout Guidelines Careful PC board layout is important in any switching regulator. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: 1) Place decoupling capacitors as close as possible to the IC pins. 2) Keep a separate power ground plane (connect to the sources of the low-side MOSFETs, the input and output capacitors, and PGND_ pins). Connect the input decoupling capacitors across the drain of the high-side MOSFETs and the source of the low-side MOSFETs. The signal ground plane (connected to the GND pin) is connected to the power ground plane at a single point. Keep the high-current paths as short as possible. THIN QFN Chip Information TRANSISTOR COUNT: 8694 PROCESS: BiCMOS ______________________________________________________________________________________ 21 MAX1955/MAX1956 Applications Information Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) D2 0.15 C A D b CL 0.10 M C A B D2/2 D/2 PIN # 1 I.D. QFN THIN.EPS MAX1955/MAX1956 1.6V to 5.5V Input, 0.5% Accurate, Dual 180° Out-of-Phase Step-Down Controllers k 0.15 C B PIN # 1 I.D. 0.35x45 E/2 E2/2 CL (NE-1) X e E E2 k L DETAIL A e (ND-1) X e CL CL L L e e 0.10 C A C 0.08 C A1 A3 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm APPROVAL COMMON DIMENSIONS DOCUMENT CONTROL NO. REV. 21-0140 C 1 2 EXPOSED PAD VARIATIONS NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm APPROVAL DOCUMENT CONTROL NO. REV. 21-0140 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.