MAXIM MAX8743

19-3318; Rev 0; 6/04
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
The on-demand PWM controllers are free running, constant on-time with input feed-forward. This configuration
provides ultra-fast transient response, wide input-output
differential range, low supply current, and tight load-regulation characteristics. The MAX8743 is simple and easy
to compensate.
Single-stage buck conversion allows the MAX8743 to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the 5V system supply instead of the battery at a higher switching frequency) allows the minimum
possible physical size.
The MAX8743 is intended for generating chipset, DRAM,
CPU I/O, or other low-voltage supplies down to 1V. The
MAX8743 is available in 28-pin QSOP and 36-pin thin
QFN packages.
Features
♦ Ultra-High Efficiency
♦ Accurate Current-Limit Option
♦ Quick-PWM™ with 100ns Load-Step Response
♦ 1% VOUT Accuracy over Line and Load
♦ High Output Impedance in Shutdown
♦ Dual Mode™ Fixed 1.8V/1.5V/Adj or 2.5V/Adj Outputs
♦ Adjustable 1V to 5.5V Output Range
♦ 2V to 28V Battery Input Range
♦ 200kHz/300kHz/420kHz/540kHz Nominal Switching
Frequency
♦ Adjustable Overvoltage Protection
♦ 1.7ms Digital Soft-Start
♦ Drives Large Synchronous-Rectifier FETs
♦ Power-Good Window Comparator
♦ 2V ±1% Reference Output
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX8743EEI
-40°C to +85°C
28 QSOP
MAX8743ETX
-40°C to +85°C
36 Thin QFN
6mm x 6mm
Minimal Operating Circuit
Applications
Notebook Computers
5V INPUT
CPU Core Supplies
Chipset/RAM Supplies as Low as 1V
1.8V and 2.5V I/O Supplies
OUTPUT1
1.8V
BATTERY
4.5V TO 28V
VDD
V+
VCC
UVP
ILIM1
ILIM2
ON1
ON2
OVP
BST1
BST2
DH1
DH2
LX1
LX2
DL1
DL2
MAX8743EEI
OUTPUT2
2.5V
CS2
TON
CS1
OUT1
PGOOD
OUT2
REF
SKIP
Pin Configurations appear at end of data sheet.
FB2
FB1
GND
Quick-PWM and Dual Mode are trademarks of Maxim Integrated
Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX8743
General Description
The MAX8743 is a dual pulse-width modulation (PWM)
controller configured for step-down (buck) topologies
that provides the high efficiency, excellent transient
response, and high DC output accuracy necessary for
stepping down high-voltage batteries to generate lowvoltage chipset and RAM power supplies in notebook
computers. The CS_ inputs can be used with low-side
sense resistors to provide accurate current limits or can
be connected to LX_, using low-side MOSFETs as current-sense elements. High output impedance in shutdown eliminates negative output voltages, saving the
cost of a Schottky diode at the output.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
ABSOLUTE MAXIMUM RATINGS (Note 1)
LX_ to BST_ ..............................................................-6V to +0.3V
DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C)........860mW
36-Pin 6mm ✕ 6mm Thin QFN
(derate 26.3mW/°C above +70°C) .............................2105mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
V+ to AGND..............................................................-0.3 to +30V
VCC to AGND............................................................-0.3V to +6V
VDD to PGND............................................................-0.3V to +6V
AGND to PGND .....................................................-0.3V to +0.3V
PGOOD, OUT_ to AGND..........................................-0.3V to +6V
OVP, UVP, ILIM_, FB_, REF,
SKIP, TON, ON_ to AGND......................-0.3V to (VCC + 0.3V)
DL_ to PGND ..............................................-0.3V to (VDD + 0.3V)
BST_ to AGND........................................................-0.3V to +36V
CS_ to AGND.............................................................-6V to +30V
DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)
Note 1: For the MAX8743EEI, AGND and PGND refer to a single pin designated GND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = 0°C to +85°C, typical values are at +25°C, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLERS
Input Voltage Range
DC Output Voltage OUT1
(Note 2)
DC Output Voltage OUT2
(Note 2)
V+
VCC/VDD
Battery voltage, V+
VCC, VDD
V+ = 2V to 28V, ILOAD
= 0 to 8A, SKIP = VCC,
+25°C to +85°C
VOUT1
V+ = 2V to 28V, ILOAD
= 0 to 8A, SKIP = VCC,
0°C to +85°C
V+ = 4.5V to 28V,
ILOAD = 0 to 4A,
SKIP = VCC,
+25°C to +85°C
VOUT2
V+ = 4.5V to 28V,
ILOAD = 0 to 4A,
SKIP = VCC,
0°C to +85°C
2
28
4.5
5.5
FB1 to AGND
1.782
1.8
1.818
1.515
FB1 to VCC
1.485
1.5
FB1 to OUT1
0.99
1
1.01
FB1 to AGND
1.773
1.8
1.827
FB1 to VCC
1.477
1.5
1.523
0.985
1
1.015
FB2 to AGND
2.475
2.5
2.525
FB2 to OUT2
0.99
1
1.01
FB2 to AGND
2.463
2.5
2.537
FB2 to OUT2
0.985
1
1.015
5.5
V
0.1
0.15
V
VCC 0.4
V
V
OUT1, OUT2
Dual-Mode Threshold, Low
OVP, FB_
0.05
OVP, ILIM_
VCC 1.5
FB1
OUT_ Input Resistance
FB_ Input-Bias Current
Soft-Start Ramp Time
2
1
1.9
ROUT1
VOUT1 = 1.5V
75
ROUT2
VOUT2 = 2.5V
100
IFB
2.0
2.1
kΩ
-0.1
Zero to full ILIM
V
FB1 to OUT1
Output Voltage Adjust Range
Dual-Mode Threshold, High
V
+0.1
1700
_______________________________________________________________________________________
µA
µs
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = 0°C to +85°C, typical values are at +25°C, unless otherwise
noted.)
PARAMETER
On-Time, Side 1
SYMBOL
tON1
On-Time, Side 2
tON2
On-Time Tracking
CONDITIONS
V+ = 24V,
VOUT1 = 2V
(Note 3)
MIN
TYP
MAX
TON = AGND
120
137
153
TON = REF
153
174
195
TON = float
222
247
272
TON = VCC
316
353
390
TON = AGND
160
182
204
V+ = 24V,
VOUT2 = 2V
(Note 3)
TON = REF
205
234
263
TON = float
301
336
371
TON = VCC
432
483
534
On-time 2 with
respect to ontime 1
(Note 3)
TON = AGND
125
135
145
TON = REF
125
135
145
TON = float
125
135
145
TON = VCC
125
135
145
UNITS
ns
ns
%
Minimum Off-Time
tOFF
(Note 3)
400
500
ns
Quiescent Supply Current (VCC)
ICC
FB_ forced above the regulation point
1100
1500
µA
Quiescent Supply Current (VDD)
IDD
FB_ forced above the regulation point
<1
5
µA
Quiescent Supply Current (V+)
I+
Measured at V+
25
70
µA
Shutdown Supply Current (VCC)
ON1 = ON2 = AGND, OVP = VCC
<1
5
µA
Shutdown Supply Current (VDD)
ON1 = ON2 = AGND
<1
5
µA
Shutdown Supply Current (V+)
ON1 = ON2 = AGND, measured at V+,
VCC = AGND or 5V
<1
5
µA
2
2.02
V
Reference Voltage
VREF
VCC = 4.5V to 5.5V, no external REF load
Reference Load Regulation
IREF = 0 to 50µA
REF Sink Current
REF in regulation
1.98
0.01
10
V
µA
REF Fault Lockout Voltage
Falling edge, hysteresis = 40mV
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
OVP = AGND, with respect to errorcomparator trip threshold
112
114
117
%
1V < VOVP < 1.8V, external feedback,
measured at FB_ with respect to VOVP
-28
0
+28
mV
1V < VOVP < 1.8V, internal feedback,
measured at OUT_ with respect to OUT_
regulation point
-3.5
0
+3.5
%
OVP Input Leakage Current
1V < VOVP < 1.8V
-100
<1
+100
nA
Overvoltage Fault Propagation
Delay
FB_ forced 2% above trip threshold
Output Undervoltage Threshold
UVP = VCC, with respect to error-comparator
trip threshold
65
Output Undervoltage Protection
Blanking Time
From ON_ signal going high
10
Overvoltage Comparator Offset
(Adjustable-Threshold Mode)
1.6
V
1.5
70
µs
75
%
30
ms
_______________________________________________________________________________________
3
MAX8743
ELECTRICAL CHARACTERISTICS (continued)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = 0°C to +85°C, typical values are at +25°C, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
mV
Current-Limit Threshold (Fixed)
AGND - VCS_, ILIM_ = VCC
40
50
60
Current-Limit Threshold
(Adjustable)
AGND - VCS_, ILIM_ = 0.5V
40
50
60
AGND - VCS_, ILIM_ = 1V
85
100
115
ILIM_ Adjustment Range
VILIM_
0.3
Negative Current-Limit Threshold
(Fixed)
VCS_ - AGND, ILIM_ = VCC, TA = +25 oC
Thermal-Shutdown Threshold
Hysteresis = 15oC
VCC Undervoltage-Lockout
Threshold
Rising edge, hysteresis = 20mV, PWMs
disabled below this level
DH Gate-Driver On-Resistance
BST - LX forced to 5V
(Note 4)
DL Gate-Driver On-Resistance
-75
-60
2.5
V
-45
mV
o
+160
4.05
mV
4.40
C
V
MAX8743EEI
1.5
5
Ω
MAX8743ETX
1.5
6
Ω
DL, high state
(Note 4)
MAX8743EEI
1.5
5
Ω
MAX8743ETX
1.5
6
Ω
DL Gate-Driver On-Resistance
DL, low state
(Note 4)
MAX8743EEI
0.5
1.7
Ω
MAX8743ETX
0.5
2.7
Ω
DH_ Gate-Driver Source/Sink
Current
VDH_ = 2.5V, VBST_ = VLX_ = 5V
1
A
DL_ Gate-Driver Sink Current
VDL_ = 2.5V
3
A
DL_ Gate-Driver Source Current
VDL_ = 2.5V
1
A
ON_, SKIP
Logic Input High Voltage
VIH
Logic Input Low Voltage
VIL
TON Input Logic Level
UVP
2.4
V
VCC 0.4
ON_, SKIP
0.8
UVP
0.05
VCC level
VCC 0.4
Float level
3.15
3.85
REF level
1.65
2.35
AGND level
V
V
0.5
Logic Input Current
TON (AGND or VCC)
-3
+3
µA
Logic Input Current
ON_, SKIP, UVP
-1
+1
µA
PGOOD Trip Threshold (Lower)
With respect to error-comparator trip
threshold, falling edge
-12.5
-10
-7.5
%
PGOOD Trip Threshold (Upper)
With respect to error-comparator trip
threshold, rising edge
+7.5
+10
+12.5
%
PGOOD Propagation Delay
Falling edge, FB_ forced 2% below PGOOD
trip threshold
PGOOD Output Low Voltage
ISINK = 1mA
PGOOD Leakage Current
High state, forced to 5.5V
4
1.5
_______________________________________________________________________________________
µs
0.4
V
1
µA
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLERS
Input Voltage Range
DC Output Voltage, OUT1
DC Output Voltage, OUT2
V+
VCC/VDD
VOUT1
VOUT2
Battery voltage, V+
VCC, VDD
2
28
4.5
5.5
1.827
V
V+ = 2V to 28V, SKIP = VCC,
ILOAD = 0 to 8A
(Note 2)
FB1 to AGND
1.773
FB1 to VCC
1.477
1.523
FB1 to OUT1
0.985
1.015
V+ = 2V to 28V, SKIP = VCC,
ILOAD = 0 to 4A (Note 2)
FB2 to AGND
2.463
2.537
FB2 to OUT2
0.985
1.015
1.0
5.5
V
V
V
Output Voltage Adjust Range
OUT1, OUT2
Dual-Mode Threshold, Low
OVP, FB_
0.05
0.15
V
OVP, ILIM_
VCC 1.5
VCC 0.4
V
2.1
Dual-Mode Threshold, High
OUT_ Input Resistance
FB_ Input Bias Current
On-Time, Side 1
FB_
1.9
ROUT1
VOUT1 = 1.5V
75
ROUT2
VOUT2 = 2.5V
100
IFB
tON1
On-Time, Side 2
tON2
V+ = 24V, VOUT1 = 2V
(Note 3)
V+ = 24V, VOUT2 = 2V
(Note 3)
On-time 2, with
respect to on-time 1
(Note 3)
On-Time Tracking
kΩ
-0.1
+0.1
TON = AGND
120
153
TON = REF
153
195
TON = float
217
272
TON = VCC
308
390
TON = AGND
160
204
TON = REF
205
263
TON = float
295
371
TON = VCC
422
534
TON = AGND
125
145
TON = REF
125
145
TON = float
125
145
TON = VCC
125
µA
ns
ns
%
145
Minimum Off-Time
tOFF
(Note 3)
500
Quiescent Supply Current (VCC)
ICC
FB forced above the regulation point
1500
µA
Quiescent Supply Current (VDD)
IDD
FB forced above the regulation point
5
µA
Quiescent Supply Current (V+)
I+
Measured at V+
70
µA
Reference Voltage
VREF
VCC = 4.5V to 5.5V, no external REF load
2.02
V
0.01
V
112
117
%
UVP = VCC, with respect to FB_ regulation
point, no load
65
75
%
AGND - VCS_, ILIM_ = VCC
35
65
mV
Reference Load Regulation
IREF = 0 to 50µA
Overvoltage Trip Threshold
(Fixed-Threshold Mode)
OVP = GND, with respect to FB_ regulation
point, no load
Output Undervoltage Threshold
Current-Limit Threshold (Fixed)
1.98
ns
_______________________________________________________________________________________
5
MAX8743
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VCC = 5V, SKIP = AGND, V+ = 15V, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Current-Limit Threshold
(Adjustable)
AGND - VCS_, ILIM_ = 0.5V
35
65
AGND - VCS_, ILIM_ = 1V
80
120
VCC Undervoltage-Lockout
Threshold
Rising edge, hysteresis = 20mV, PWMs
disabled below this level
4.05
4.40
ON_, SKIP
2.4
Logic Input High Voltage
VIH
Logic Input Low Voltage
VIL
Logic Input Current
mV
V
V
VCC 0.4
UVP
UNITS
ON_, SKIP
0.8
UVP
0.05
TON (AGND or VCC)
-3
+3
ON_, SKIP, UVP
-1
+1
V
µA
Note 2: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the output voltage ripple. In discontinuous conduction (SKIP = AGND, light load), the output voltage
has a DC regulation higher than the error-comparator threshold by approximately 1.5% due to slope compensation.
Note 3: On-time and off-time specifications are measured from the 50% point to the 50% point at DH_ with LX_ = GND, BST_ = 5V,
and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the QFN
package. The MAX8743EEI and MAX8743ETX contain the same die, and the QFN package imposes no additional resistance in-circuit.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA = +25°C, unless otherwise noted.)
FREQUENCY vs. INPUT VOLTAGE
(TON = FLOAT, SKIP = VCC)
FREQUENCY vs. LOAD CURRENT
OUT1, SKIP = VCC
FREQUENCY (kHz)
300
OUT2, SKIP = VCC
250
200
OUT1, SKIP = GND
150
100
OUT2
250
200
150
100
OUT2, SKIP = GND
50
IOUT1 = 8A
IOUT2 = 4A
50
0
0
0.01
0.1
1
LOAD CURRENT (A)
6
OUT1
350
300
MAX8743 toc02
350
400
MAX8743 toc01
400
FREQUENCY (kHz)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
10
4
8
12
16
20
INPUT VOLTAGE (V)
_______________________________________________________________________________________
24
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
VCC = VDD = 5V
6.0
4.5
ICC
3.0
I+ (25µA TYP)
600
500
400
300
IDD (600nA TYP)
30
I+
20
10
20
25
5
30
10
15
20
OUT1 = 1.8V
0.01
30
0.1
1
10
INPUT VOLTAGE V+ (V)
INPUT VOLTAGE V+ (V)
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
(8A COMPONENTS, SKIP = GND)
EFFICIENCY vs. LOAD CURRENT
(4A COMPONENTS, SKIP = VCC)
EFFICIENCY vs. LOAD CURRENT
(4A COMPONENTS, SKIP = GND)
V+ = 7V
85
80
V+ = 20V
V+ = 12V
70
65
70
60
50
V+ = 12V
40
55
0.1
1
10
OUT2 = 2.5V
75
0.01
0.1
LOAD CURRENT (A)
1
0.01
10
NORMALIZED OVERVOLTAGE PROTECTION
THRESHOLD vs. OVP VOLTAGE
CURRENT-LIMIT TRIP POINT
vs. ILIM VOLTAGE
1
10
LOAD-TRANSIENT RESPONSE
(4A COMPONENTS, PWM MODE, VOUT2 = 2.5V)
MAX8743 toc11
MAX8743 toc10
2.0
1.9
NORMALIZED THRESHOLD (V)
MAX8743 toc09
0.1
LOAD CURRENT (A)
LOAD CURRENT (A)
250
230
210
190
170
150
130
110
90
70
50
30
10
V+ = 20V
85
OUT2 = 2.5V
10
0.01
90
80
20
OUT1 = 1.8V
50
V+ = 7V
V+ = 12V
30
60
95
EFFICIENCY (%)
V+ = 20V
80
MAX8743 toc08
90
100
MAX8743 toc07
100
MAX8743 toc06
V+ = 7V
90
75
25
V+ = 12V
40
0
15
MAX8743 toc05
60
50
100
95
EFFICIENCY (%)
700
0
10
V+ = 20V
70
1.5
100
CURRENT-LIMIT TRIP POINT (mV)
80
ICC
800
200
5
V+ = 7V
90
EFFICIENCY (%)
9.0
EFFICIENCY (%)
SUPPLY CURRENT (mA)
10.5
7.5
900
SUPPLY CURRENT (µA)
IDD
VCC = VDD = 5V
1000
100
MAX8743 toc04
13.5
12.0
1100
MAX8743 toc03
15.0
EFFICIENCY vs. LOAD CURRENT
(8A COMPONENTS, SKIP = VCC)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP = GND)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP = VCC)
1.8
1.7
VOUT2
100mV/div
1.6
1.5
1.4
1.3
IOUT2
2A/div
1.2
1.1
1.0
0
0.5
1.0
1.5
ILIM VOLTAGE (V)
2.0
2.5
MAX8743
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA = +25°C, unless otherwise noted.)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
20µs/div
OVP VOLTAGE (V)
_______________________________________________________________________________________
7
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components from Table 1, VIN = 15V, SKIP = GND, TON = unconnected, TA = +25°C, unless otherwise noted.)
LOAD-TRANSIENT RESPONSE
(8A COMPONENTS, PWM MODE, VOUT1 = 1.8V)
STARTUP WAVEFORM (VOUT2)
2.5V
VOUT1
100mV/div
SHUTDOWN WAVEFORM (VOUT2)
MAX8743 toc13
MAX8743 toc12
MAX8743 toc14
VOUT2
1V/div
ROUT2 = 2.5Ω
ROUT2 = 2.5Ω
2.5V
VOUT2
1V/div
0V
ILX2
1A/div
0V
DL2
5V/div
0V
0A
IOUT1
5A/div
ON2
5V/div
PGOOD
5V/div
0V
0V
PGOOD
5V/div
0V
400µs/div
20µs/div
ON2
5V/div
0V
400µs/div
Pin Description
PIN
NAME
FUNCTION
QSOP
TQFN
1
32
OUT1
Output Voltage Connection for the OUT1 PWM. Connect directly to the junction of the external
inductor and output filter capacitors. OUT1 senses the output voltage to determine the on-time
and also serves as the feedback input in fixed-output modes.
2
33
FB1
Feedback Input for OUT1. Connect to GND for 1.8V fixed output or to VCC for 1.5V fixed output, or
connect to a resistor-divider network from OUT1 for an adjustable output between 1V and 5.5V.
3
34
ILIM1
Current-Limit Threshold Adjustment for OUT1. The current-limit threshold at CS1 is 0.1 times the
voltage at ILIM1. Connect a resistor-divider network from REF to set the current-limit threshold
between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to VCC to assert 50mV default
current-limit threshold.
4
35
V+
Battery Voltage-Sense Connection. Connect to input power source. V+ is only used to adjust the
DH_ on-time for pseudofixed-frequency operation.
On-Time Selection Control Input. This four-level input pin sets the DH_ on-time to determine the
operating frequency.
5
6
8
1
2
TON
SKIP
TON
FREQUENCY (OUT1) (kHz)
FREQUENCY (OUT2) (kHz)
AGND
620
460
REF
485
355
Open
345
255
VCC
235
170
Pulse-Skipping Control Input. Connect to VCC for low-noise forced-PWM mode. Connect to AGND
to enable pulse-skipping operation.
_______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
PIN
NAME
QSOP
TQFN
7
3
PGOOD
FUNCTION
Power-Good Open-Drain Output. PGOOD is low when either output voltage is more than 10%
above or below the normal regulation point, and during the 1.7ms soft-start time.
8
4
OVP
Overvoltage Protection Threshold. An overvoltage fault occurs if the voltage on FB1 or FB2 is
greater than the programmed overvoltage trip threshold. Adjustment range is 1V (100%) to 1.8V
(180%). Connect OVP to GND to set the default overvoltage threshold of 114% of nominal.
Connect to VCC to disable OVP and clear the OVP latch.
9
5
UVP
Undervoltage Protection Threshold. An undervoltage fault occurs if the voltage on FB1 or FB2 is less
than the undervoltage trip threshold (70% of nominal). Connect UVP to VCC to enable undervoltage
protection. Connect to GND to disable undervoltage protection and clear the UVP latch.
10
7
REF
+2.0V Reference Voltage Output. Bypass to GND with 0.22µF (min) capacitor. Can supply 50µA
for external loads.
11
8
ON1
OUT1 ON/OFF Control Input. Connect to AGND to turn OUT1 off. Connect to VCC to turn OUT1 on.
12
11
ON2
OUT2 ON/OFF Control Input. Connect to AGND to turn OUT2 off. Connect to VCC to turn OUT2 on.
13
12
ILIM2
Current-Limit Threshold Adjustment for OUT2. The current-limit threshold at CS2 is 0.1 times the
voltage at ILIM2. Connect a resistor-divider network from REF to set the current-limit threshold
between 25mV and 250mV (with 0.25V to 2.5V at ILIM). Connect to VCC to assert 50mV default
current-limit threshold.
14
13
FB2
Feedback Input for OUT2. Connect to GND for 2.5V fixed output, or connect to a resistor-divider
network from OUT2 for an adjustable output between 1V and 5.5V.
15
14
OUT2
16
15
CS2
Current-Sense Input for OUT2. CS2 is the input to the current-limiting circuitry for valley current
limiting. For lowest cost and highest efficiency, connect to LX2. For highest accuracy, use a sense
resistor. See the Current-Limit Circuit (ILIM_) section.
17
16
LX2
External Inductor Connection for OUT2. Connect to the switched side of the inductor. LX2 serves
as the internal lower supply voltage rail for the DH2 high-side gate driver.
18
18
DH2
High-Side Gate-Driver Output for OUT2. Swings from LX2 to BST2.
19
19
BST2
Boost Flying Capacitor Connection for OUT2. Connect to an external capacitor and diode
according to the standard application circuit in Figure 1. See the MOSFET Gate Drivers (DH_,
DL_) section.
20
20
DL2
Low-Side Gate-Driver Output for OUT2. DL2 swings from PGND to VDD.
21
21
VDD
Supply Input for the DL Gate Drivers. Connect to system supply voltage, +4.5V to +5.5V. Bypass
to PGND with a low-ESR 4.7µF capacitor.
22
22
VCC
Analog Supply Input. Connect to system supply voltage, +4.5V to +5.5V, with a 20Ω series
resistor. Bypass to AGND with a 1µF capacitor.
23
—
GND
Ground. Combined analog and power ground. Serves as negative input for CS_ amplifiers.
Output Voltage Connection for the OUT2 PWM. Connect directly to the junction of the external
inductor and output filter capacitors. OUT2 senses the output voltage to determine the on-time
and also serves as the feedback input in fixed-output modes.
_______________________________________________________________________________________
9
MAX8743
Pin Description (continued)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
Pin Description (continued)
PIN
NAME
FUNCTION
QSOP
TQFN
—
23
AGND
Analog Ground. Serves as negative input for CS_ amplifiers. Connect backside pad to AGND.
—
24
PGND
Power Ground
24
26
DL1
Low-Side Gate-Driver Output for OUT1. DL1 swings from PGND to VDD.
25
27
BST1
Boost Flying Capacitor Connection for OUT1. Connect to an external capacitor and diode according
to the standard application circuit in Figure 1. See the MOSFET Gate Drivers (DH_, DL_) section.
26
28
DH1
High-Side Gate-Driver Output for OUT1. Swings from LX1 to BST1.
27
30
LX1
External Inductor Connection for OUT1. Connect to the switched side of the inductor. LX1 serves
as the internal lower supply voltage rail for the DH1 high-side gate driver.
28
31
CS1
Current-Sense Input for OUT1. CS1 is the input to the current-limiting circuitry for valley current
limiting. For lowest cost and highest efficiency, connect to LX1. For highest accuracy, use a sense
resistor. See the Current-Limit Circuit (ILIM_) section.
—
6, 9, 10,
17, 25,
29, 36
N.C.
No Connection
Standard Application Circuit
The standard application circuit (Figure 1) generates a
1.8V and a 2.5V rail for general-purpose use in notebook computers.
See Table 1 for component selections. Table 2 lists
component manufacturers.
Detailed Description
The MAX8743 buck controller is designed for low-voltage power supplies for notebook computers. Maxim’s
proprietary Quick-PWM pulse-width modulator in the
MAX8743 (Figure 2) is specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point
over a wide range of input voltages. The Quick-PWM
architecture circumvents the poor load-transient timing
problems of fixed-frequency current-mode PWMs while
avoiding the problems caused by widely varying
switching frequencies in conventional constant-on-time
and constant-off-time PWM schemes.
5V Bias Supply (VCC and VDD)
The MAX8743 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
10
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator such as the MAX1615.
The power input and 5V bias inputs can be connected
together if the input source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (ON1, ON2) must be
delayed until the battery voltage is present to ensure
startup. The 5V bias supply must provide VCC and
gate-drive power, so the maximum current drawn is:
IBIAS = ICC + f (QG1 + QG2) = 5mA to 30mA (typ)
where ICC is 1mA (typ), f is the switching frequency,
and QG1 and QG2 are the MOSFET data sheet total
gate-charge specification limits at VGS = 5V.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time current-mode type with
voltage feed-forward (Figure 3). This architecture relies
on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, so the
output ripple voltage provides the PWM ramp signal.
The control algorithm is simple: the high-side switch ontime is determined solely by a one-shot whose pulse
width is inversely proportional to input voltage and
directly proportional to output voltage. Another one-shot
sets a minimum off-time (400ns typ). The on-time one-
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
cy “beating” between the two sides, which switch asynchronously for each side. The on-time is given by:
On-time = K (VOUT + 0.075V) / VIN
where K is set by the TON pin-strap connection (Table
4), and 0.075V is an approximation to accommodate
for the expected drop across the low-side MOSFET
switch. One-shot timing error increases for the shorter
on-time settings due to fixed propagation delays; it is
approximately ±12.5% at higher frequencies and ±10%
at lower frequencies. This translates to reduced switching-frequency accuracy at higher frequencies (Table
4). Switching frequency increases as a function of load
current due to the increasing drop across the low-side
MOSFET, which causes a faster inductor-current discharge ramp. The on-times guaranteed in the Electrical
Characteristics tables are influenced by switching
delays in the external high-side power MOSFET.
Two external factors that influence switching-frequency
accuracy are resistive drops in the two conduction
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time for both controllers. This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency
despite the lack of a fixed-frequency clock generator.
The benefits of a constant switching frequency are
twofold: First, the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band;
second, the inductor ripple-current operating point
remains relatively constant, resulting in easy design
methodology and predictable output voltage ripple.
The on-times for side 1 are set 35% higher than the ontimes for side 2. This is done to prevent audio-frequen-
VDD = 5V
BIAS SUPPLY
C9
4.7µF
D3
CMPSH-3A
C8
1µF
VIN
7V TO 24V
4
R3
20Ω
21
V
9 DD
UVP
22
VCC
3
ILIM1
13
ILIM2
C11
1µF
V+
ON1
11
ON/OFF
CONTROLS
12
ON2
8
OVP
C2
2 ✕ 10µF
MAX8743EEI
C1
3 ✕ 10µF
OUTPUT1
1.8V, 8A
C3
3 ✕ 470µF
25
C5
0.1µF
D1
R1
5mΩ
26
Q1
L1
2.2µH
Q2
C7
0.22µF
27
24
BST1
BST2
DH1
DH2
LX1
LX2
DL1
DL2
5 TON
28 CS1
1 OUT1
10
REF
2
23
CS2
19
18
17
L2
4.7µH
Q3
C6
0.1µF
Q4
20
OUTPUT2
2.5V, 4A
C4
470µF
D2
16
OUT2 15
SKIP
FB1
FB2
GND
PGOOD
6
14
7
5V
100kΩ
R2
10mΩ
POWER-GOOD
INDICATOR
Figure 1. Standard Application Circuit
______________________________________________________________________________________
11
MAX8743
shot is triggered if the error comparator is low, the lowside switch current is below the current-limit threshold,
and the minimum off-time one-shot has timed out
(Table 3).
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
Table 1. Component Selection for
Standard Applications
COMPONENT
SIDE 1: 1.8V AT 8A/
SIDE 2: 2.5V AT 4A
Table 2. Component Suppliers
MANUFACTURER
WEBSITE
Central Semiconductor
www.centralsemi.com
Fairchild Semiconductor
www.fairchildsemi.com
Input Range
4.5V to 28V
International Rectifier
www.irf.com
Q1 High-Side MOSFET
Fairchild Semiconductor
FDS6612A
IRC
www.irctt.com
Kemet
www.kemet.com
Q2 Low-Side MOSFET
Fairchild Semiconductor
FDS6670A
NIEC (Nihon)
www.niec.co.jp
Panasonic
www.panasonic.com
Q3, Q4 High/Low-Side
MOSFETs
Fairchild Semiconductor
FDS6982A
Sanyo
www.sanyo.com/components
Sumida
www.sumida.com
D1, D2 Rectifier
Nihon EP10QY03
Taiyo Yuden
www.t-yuden.com
D3 Rectifier
Central Semiconductor
CMPSH-3A
TDK
www.component.tdk.com
Vishay/Dale
www.vishay.com
L1 Inductor
2.2µH
Panasonic ETQP6F2R2SFA
or
Sumida CDRH127-2R4
L2 Inductor
4.7µH
Sumida CDRH124-4R7MC
C1 (3), C2 (2) Input
Capacitor
10µF, 25V
Taiyo Yuden
TMK432BJ106KM or
TDK C4532X5R1E106M
C3 (3), C4 Output Capacitor
470µF, 6V
Kemet T510X477M006AS or
Sanyo 6TPB330M
RSENSE1
5mΩ, ±1%, 1W
IRC LR2512-01-R005-F or
Dale WSL-2512-R005F
RSENSE2
10mΩ, ±1%, 0.5W
IRC LR2010-01-R010-F or
Dale WSL-2010-R010F
loops (including inductor and PC board resistance) and
the dead-time effect. These effects are the largest contributors to the change of frequency with changing load
current. The dead-time effect increases the effective
on-time, reducing the switching frequency as one or
both dead times. It occurs only in PWM mode (SKIP =
high) when the inductor current reverses at light or negative load currents. With reversed inductor current, the
inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the
low-to-high dead time.
12
For loads above the critical conduction point, the actual
switching frequency is:
f=
VOUT + VDROP1
t ON (VIN + VDROP2 )
where VDROP1 is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the resistances in the charging path; and
tON is the on-time calculated by the MAX8743.
Automatic Pulse-Skipping Switchover
In skip mode (SKIP = GND), an inherent automatic
switchover to pulse-frequency modulation (PFM) takes
place at light loads. This switchover is effected by a
comparator that truncates the low-side switch on-time at
the inductor current’s zero crossing. This mechanism
causes the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction
point). For a 7V to 24V battery range, this threshold is relatively constant, with only a minor dependence on battery voltage:
I LOAD(SKIP) ≈
K × VOUT_  VIN - VOUT_ 


2L
VIN


where K is the on-time scale factor (Table 4). The loadcurrent level at which PFM/PWM crossover occurs,
ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 4).
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
ILIM1
MAX8743
V+
2V TO 28V
ILIM2
V+
VDD
5V INPUT
VDD
PGND*
VDD
VCC - 1V
0.5V
VCC - 1V
0.5V
VDD
V+
V+
BST1
BST2
MAX8743
DH1
DH2
LX1
LX2
PWM
CONTROLLER
(FIGURE 3)
CS1
PWM
CONTROLLER
(FIGURE 3)
CS2
VDD
VDD
DL2
DL1
OUT 2
OUT1
VDD
FB2
FB1
VCC
UVP
OVP
TON
SKIP
PGOOD
20Ω
2V
REF
REF
AGND*
FAULT1
ON1
ON2
FAULT2
* IN THE MAX8743EEI, AGND AND PGND ARE INTERNALLY CONNECTED AND CALLED GND.
Figure 2. Functional Diagram
For example, in the standard application circuit with
VOUT1 = 2.5V, VIN = 15V, and K = 2.96µs (Table 4),
switchover to pulse-skipping operation occurs at ILOAD
= 0.7A or about 1/6 full load. The crossover point
occurs at an even lower value if a swinging (soft-saturation) inductor is used.
The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-transient response (especially at low input-voltage levels).
DC output accuracy specifications refer to the threshold
of the error comparator. When the inductor is in continuous conduction, the output voltage has a DC regulation
higher than the trip level by 50% of the ripple. In discontinuous conduction (SKIP = GND, light-load), the output
______________________________________________________________________________________
13
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
V+
TON
TOFF 1-SHOT
TRIG
FROM
OUT
ON-TIME
COMPUTE
Q
TON
S
Q
TRIG
TO DH DRIVER
Q
R
1-SHOT
ERROR
AMP
FROM ILIM
COMPARATOR
REF
FROM
OPPOSITE
PWM
FROM ZERO-CROSSING
COMPARATOR
TO DL DRIVER
S
Q
R
SHUTDOWN
OVP
1.14V
0.1V
OUT_
TO
OPPOSITE
PWM
R
VCC - 1V
FEEDBACK
MUX
(SEE FIGURE 9)
S
Q
x2
FB_
0.7V
1.1V
S
R
0.9V
TIMER
Q
UVP
FAULT
TO PGOOD
OR-GATE
Figure 3. PWM Controller (One Side Only)
voltage has a DC regulation higher than the trip level by
approximately 1.5% due to slope compensation.
Forced-PWM Mode (SKIP = High)
The low-noise, forced-PWM mode (SKIP = high) disables the zero-crossing comparator, which controls the
low-side switch on-time. This causes the low-side gatedrive waveform to become the complement of the highside gate-drive waveform. This in turn causes the
inductor current to reverse at light loads as the PWM
loop strives to maintain a duty ratio of VOUT/VIN. The
benefit of forced-PWM mode is to keep the switching
frequency fairly constant, but it comes at a cost: The
14
no-load battery current can be 10mA to 40mA, depending on the external MOSFETs.
Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response,
providing sink-current capability for dynamic output
voltage adjustment, and improving the cross-regulation
of multiple-output applications that use a flyback transformer or coupled inductor.
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a unique “valley” currentsensing algorithm. If the magnitude of the current-sense
signal at CS_ is above the current-limit threshold, the
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
MAX8743
Table 3. Operating Mode Truth Table
ON1
ON2
SKIP
DL1/DL2
GND
GND
X
Low/Low
Shutdown
MODE
COMMENTS
Low-power shutdown state. ICC < 1µA (typ).
VCC
GND
VCC
Switching/Low
Run (PWM), Low Noise,
Side 1 Only
GND
VCC
VCC
Low/Switching
Run (PWM), Low Noise,
Side 2 Only
VCC
VCC
VCC
Switching/
Switching
Run (PWM), Low Noise,
Both Sides Active
VCC
GND
GND
Switching/Low
Run (PWM/PFM), Skip
Mode, Side 1 Only
GND
VCC
GND
Low/Switching
Run (PWM/PFM), Skip
Mode, Side 2 Only
VCC
VCC
GND
Switching/
Switching
Run (PWM/PFM), Skip
Mode, Both Sides Active
VCC
VCC
X
Low/Low
UV Fault (Either Side),
Thermal Fault, or
VCC Below UVLO
VCC
VCC
X
High/High
OV Fault
(Either Side)
PWM is not allowed to initiate a new cycle (Figure 5). The
actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and
maximum load capability are a function of the sense
resistance, inductor value, and battery voltage.
There is also a negative current limit that prevents
excessive reverse inductor currents when V OUT is
sinking current. The negative current-limit threshold is
set to approximately 120% of the positive current limit
and therefore tracks the positive current limit when
ILIM is adjusted.
The current-limit threshold is adjusted with an internal
5µA current source and an external resistor at ILIM. The
current-limit threshold adjustment range is from 25mV
to 250mV. In the adjustable mode, the current-limit
threshold voltage is precisely 1/10 the voltage seen at
ILIM. The threshold defaults to 50mV when ILIM is connected to VCC. The logic threshold for switchover to the
50mV default value is approximately VCC - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
Low-noise, fixed-frequency PWM at all load conditions.
Low noise, high IQ.
Normal operation with automatic PWM/PFM switchover
for pulse skipping at light loads. Best light-load
efficiency.
Fault latch has been set by undervoltage protection
circuit, thermal shutdown, or VCC below UVLO. The
MAX8743 remains in fault mode until VCC power is
cycled below POR or ON1/ON2 is toggled.
Fault latch has been set by overvoltage protection circuit.
The MAX8743 remains in fault mode until VCC power is
cycled below the 2V (typ) POR level.
rent-sense signal seen by CS_ and GND. Mount or
place the IC close to the low-side MOSFET and sense
resistor with short, direct traces, making a Kelvin sense
connection to the sense resistor. In Figure 1, the
Schottky diodes (D1 and D2) provide current paths
parallel to the Q2/R SENSE and Q4/R SENSE current
paths, respectively. Accurate current sensing requires
D1/D2 to be off while Q2/Q4 conducts. Avoid large current-sense voltages that, combined with the voltage
across Q2/Q4, would allow D1/D2 to conduct. If very
large sense voltages are used, connect D1/D2 in parallel with Q2/Q4 only.
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving moderate-size, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VBATT - VOUT differential exists. An adaptive dead-time
circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time
______________________________________________________________________________________
15
IPEAK
∆i
VBATT - VOUT
=
L
∆t
IPEAK
INDUCTOR CURRENT
ILOAD
ILOAD = IPEAK / 2
0 ON-TIME
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
circuit to work properly. Otherwise, the sense circuitry
in the MAX8743 interprets the MOSFET gate as “off”
while there is actually still charge left on the gate. Use
very short, wide traces measuring 10 to 20 squares (50
to 100 mils wide if the MOSFET is 1in from the
MAX8743).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typ) internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.5Ω typical on-resistance. This helps
prevent DL from being pulled up during the fast rise
time of the inductor node, due to capacitive coupling
from the drain to the gate of the low-side synchronousrectifier MOSFET. However, for high-current applications, some combinations of high- and low-side FETs
might be encountered that will cause excessive gatedrain coupling, which can lead to efficiency-killing,
EMI-producing shoot-through currents. This is often
remedied by adding a resistor in series with BST, which
increases the turn-on time of the high-side FET without
degrading the turn-off time (Figure 6).
16
INDUCTOR CURRENT
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
ILIMIT
0
TIME
Figure 5. ‘‘Valley’’ Current-Limit Threshold Point
+5V
BST
VIN
5Ω
DH
LX
MAX8743
Figure 6. Reducing the Switching-Node Rise Time
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and preparing the PWM for operation. Below 4.05V (min), the VCC
undervoltage-lockout (UVLO) circuitry inhibits switching
by keeping DH and DL low.
Soft-start allows a gradual increase of the internal current-limit level during startup to reduce the input surge
currents. When ON1 or ON2 goes high, the respective
digital soft-start timer begins to ramp up the maximum
allowed current limit in five steps. During the first step,
the controller limits the current limit to only 20% of the full
current limit. The current limit is increased by 20% every
425µs. 100% current limit is available after 1.7ms ±50%.
A continuously adjustable analog soft-start function can
be realized by adding a capacitor in parallel with the
ILIM external resistor-divider network. This soft-start
method requires a minimum interval between powerdown and power-up to discharge the capacitor.
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
Output Overvoltage Protection
The output voltage can be continuously monitored for
overvoltage. When overvoltage protection is enabled, if
the output exceeds the overvoltage threshold, overvoltage protection is triggered and the DL low-side gatedrivers are forced high. This activates the low-side
MOSFET switch, which rapidly discharges the output
capacitor and reduces the input voltage.
Note that DL latching high causes the output voltage to
dip slightly negative when energy has been previously
stored in the LC tank circuit. For loads that cannot tolerate a negative voltage, place a power Schottky diode
across the output to act as a reverse polarity clamp.
Connect OVP to GND to enable the default trip level of
114% of the nominal output. To adjust the overvoltageprotection trip level, apply a voltage from 1V (100%) to
1.8V (180%) at OVP. Disable the overvoltage protection
by connecting OVP to VCC.
The overvoltage trip level depends on the internal or
external output-voltage feedback divider and is restricted by the output-voltage adjustment range (1V to 5.5V)
and by the absolute maximum rating of OUT_. Setting
the overvoltage threshold higher than the output-voltage adjustment range is not recommended.
Output Undervoltage Protection
The output voltage can be continuously monitored for
undervoltage. When undervoltage protection is
enabled (UVP = VCC), if the output is less than 70% of
the error-amplifier trip voltage, undervoltage protection
is triggered. If an undervoltage protection threshold is
set, the DL low-side gate driver is forced low and the
outputs float. Connect UVP to GND to disable undervoltage protection.
Note the nonstandard logic levels if actively driving
UVP (see the Electrical Characteristics).
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good
switching frequency and inductor operating point, and
the following four factors dictate the rest of the design:
1) Input Voltage Range. The maximum value
(VIN(MAX)) must accommodate the worst-case high
AC adapter voltage. The minimum value (VIN(MIN))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selector
switches. Lower input voltages result in better efficiency.
2) Maximum Load Current. There are two values to
consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and
filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the
design of the current-limit circuit. The continuous
load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing components.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
are proportional to frequency and VIN2.
4) Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output
noise. The minimum practical inductor value is one
that causes the circuit to operate at the edge of critical conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further sizereduction benefit.
The MAX8743’s pulse-skipping algorithm initiates
skip mode at the critical conduction point.
Therefore, the inductor operating point also determines the load-current value at which PFM/PWM
switchover occurs. The optimum point is usually
found between 20% and 50% of ripple current.
______________________________________________________________________________________
17
MAX8743
Power-Good Output (PGOOD)
The PGOOD window comparator continuously monitors
the output voltage for both overvoltage and undervoltage conditions. In shutdown, standby, and soft-start,
PGOOD is actively held low. After a digital soft-start
has terminated, PGOOD is released when the output is
within 10% of the error-comparator threshold. The
PGOOD output is a true open-drain type with no parasitic ESD diodes. Note that the PGOOD window detector is independent of the output overvoltage and
undervoltage protection (UVP) thresholds.
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
Inductor Selection
Determining the Current Limit
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as follows:
For most applications, set the MAX8743 current limit by
the following procedure:
L =
VOUT (VIN - VOUT )
VIN × f × LIR × I LOAD(MAX)
Example: ILOAD(MAX) = 8A, VIN = 15V, VOUT = 1.8V,
f = 300kHz, 25% ripple current or LIR = 0.25:
L =
1.8V (15V - 1.8V)
= 2.3µH
15V × 345kHz × 0.25 × 8A
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
IPEAK = ILOAD(MAX) + [(LIR / 2) ✕ ILOAD(MAX)]
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time:
VSAG =
1) Determine the minimum (valley) inductor current
(IL(MIN)) under conditions when VIN is small, VOUT is
large, and load current is maximum. The minimum
inductor current is ILOAD minus half the ripple current (Figure 4).
2) The sense resistor determines the achievable current-limit accuracy. There is a trade-off between current-limit accuracy and sense-resistor power
dissipation. Most applications employ a currentsense voltage of 50mV to 100mV. Choose a sense
resistor such that:
RSENSE = Current-Limit Threshold Voltage / IL(MIN)
Extremely cost-sensitive applications that do not
require high-accuracy current sensing can use the onresistance of the low-side MOSFET switch in place of
the sense resistor by connecting CS_ to LX_ (Figure
7a). Use the worst-case value for RDS(ON) from the
MOSFET data sheet, and add a margin of 0.5%/°C for
the rise in RDS(ON) with temperature. Use the calculated RDS(ON) and IL(MIN) from step 1 above to determine
the current-limit threshold voltage. If the default 50mV
threshold is unacceptable, set the threshold value as in
step 2 above.
In all cases, ensure an acceptable current limit considering current-sense and resistor accuracies.
(∆I LOAD(MAX) )2 × L
2 × CF × DUTY (VIN(MIN) - VOUT )
MAX8743
where:
DUTY =
K (VOUT + 0.075V) VIN
K (VOUT + 0.075V) VOUT + min off - time
MAX8743
LX
LX
DL
DL
CS
CS
where minimum off-time = 400ns typ (Table 4).
The amount of overshoot during a full-load to no-load
transient due to stored inductor energy can be calculated as:
VSOAR = L ✕ IPEAK2 / (2 x COUT x VOUT)
a)
Figure 7. Current-Sense Configurations
where IPEAK is the peak inductor current.
18
______________________________________________________________________________________
b)
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
TON SETTING
SIDE 1
FREQUENCY
(kHz)
SIDE 1
K-FACTOR
(µs)
SIDE 2
FREQUENCY
(kHz)
SIDE 2
K-FACTOR
(µs)
APPROXIMATE
K-FACTOR
ERROR (%)
±10
VCC
235
4.24
170
5.81
FLOAT
345
2.96
255
4.03
±10
REF
485
2.08
355
2.81
±12.5
AGND
620
1.63
460
2.18
±12.5
Output Capacitor Selection
The output filter capacitor must have low enough ESR to
meet output ripple and load-transient requirements, yet
have high enough ESR to satisfy stability requirements.
Also, the capacitance value must be high enough to
absorb the inductor energy going from a full-load to noload condition without tripping the OVP circuit.
For CPU core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how
much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag
due to finite capacitance:
RESR ≤
VDIP
I LOAD(MAX)
In non-CPU applications, the output capacitor’s size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
RESR ≤
VP−P
LIR × I LOAD(MAX)
The actual microfarad capacitance value required
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true
of tantalums, OS-CONs®, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent VSAG
and VSOAR from causing problems during load transients. Also, the capacitance must be great enough to
prevent the inductor’s stored energy from launching the
output above the overvoltage protection threshold.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising
load edge is no longer a problem (see the VSAG and
VSOAR equations in the Transient Response section).
Output Capacitor Stability
Considerations
Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability
is given by the following equation:
f
f ESR ≤ SW
π
where:
f ESR =
1
2 × π × RESR × CF
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero frequencies of 15kHz. In the design example used for
inductor selection, the ESR needed to support 20mVP-P
ripple is 20mV/2A = 10mΩ. Three 470µF/6V Kemet
T510 low-ESR tantalum capacitors in parallel provide
10mΩ (max) ESR. Their typical combined ESR results in
a zero at 11.3kHz, well within the bounds of stability.
Do not put high-value ceramic capacitors directly
across the outputs without taking precautions to ensure
stability. Large ceramic capacitors can have a highESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series
resistance by placing the capacitors a couple of inches
downstream from the inductor and connecting OUT_ or
the FB_ divider close to the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedbackloop instability.
OS-CON is a registered trademark of Sanyo Electric Co., Ltd.
______________________________________________________________________________________
19
MAX8743
Table 4. Frequency Selection Guidelines
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
Double-pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the
error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it may indicate the possible presence of loop
instability, which is caused by insufficient ESR.
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall
below the tolerance limit.
Switching losses are not an issue for the low-side
MOSFET since it is a zero-voltage switched device
when used in the buck topology.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (refer to the
MAX8743 EV kit manual) and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It
helps to simultaneously monitor the inductor current with
an AC current probe. Do not allow more than one cycle of
ringing after the initial step-response under- or overshoot.
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation limits often limits how small the
MOSFET can be. Again, the optimum occurs when the
switching (AC) losses equal the conduction (RDS(ON))
losses. High-side switching losses do not usually
become an issue until the input is greater than approximately 15V.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up
surge currents:
 V

OUT (VIN - VOUT )

I RMS = ILOAD 
VIN




Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>5A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Ensure
that the conduction losses at the minimum input voltage do not exceed the package thermal limits or violate
the overall thermal budget. Ensure that conduction
losses plus switching losses at the maximum input
voltage do not exceed the package ratings or violate
the overall thermal budget.
Choose a low-side MOSFET (Q2) that has the lowest
possible RDS(ON), comes in a moderate to small package (i.e., SO-8), and is reasonably priced. Ensure that
the MAX8743 DL gate driver can drive Q2; in other
words, check that the gate is not pulled up by the highside switch turning on due to parasitic drain-to-gate
capacitance, causing cross-conduction problems.
20
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty cycle
extremes. For the high-side MOSFET, the worst-casepower dissipation (PD) due to resistance occurs at minimum battery voltage:
 V

PD(Q1 resistance) =  OUT  ILOAD2 × RDS(ON)
 VIN(MIN) 


Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2f switching-loss equation. If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when subjected to
VIN(MAX), reconsider the choice of MOSFET.
Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for bench evaluation, preferably including a verification using a thermocouple mounted on Q1:
PD(Q1 switching) =
CRSS × VIN(MAX)2 × f × ILOAD
IGATE
where CRSS is the reverse transfer capacitance of Q1,
and IGATE is the peak gate-drive source/sink current
(1A typ).
For the low-side MOSFET, Q2, the worst-case power
dissipation always occurs at maximum battery voltage:

VOUT 
PD(Q2) = 1 ILOAD2 × RDS(ON)
VIN(MAX ) 



______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
where I LIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. If short-circuit
protection without overload protection is adequate,
enable overvoltage protection, and use ILOAD(MAX) to
calculate component stresses.
Choose a Schottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency is not critical.
Applications Information
Dropout Performance
The output voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns
(max) minimum off-time one-shot. For best dropout performance, use the slower on-time settings. When working with low input voltages, the duty-cycle limit must be
calculated using the worst-case values for on- and offtimes. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This
error is greater at higher frequencies (Table 4). Also,
keep in mind that transient-response performance of
buck regulators operating close to dropout is poor, and
bulk output capacitance must often be added (see the
VSAG equation in the Design Procedure section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP / ∆IDOWN is an indicator of ability to slew
the inductor current higher in response to increased
load and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the
inductor current is less able to increase during each
switching cycle, and V SAG greatly increases unless
additional output capacitance is used.
A reasonable minimum value for h is 1.5, but this may
be adjusted up or down to allow trade-offs between
V SAG , output capacitance, and minimum operating
voltage. For a given value of h, calculate the minimum
operating voltage as follows:
VIN(MIN) = [(VOUT + VDROP1) / {1 - (tOFF(MIN) ✕ h / K)}]
+ VDROP2 - VDROP1
where VDROP1 and VDROP2 are the parasitic voltage
drops in the discharge and charge paths (see the OnTime One-Shot (TON) section), tOFF(MIN) is from the
Electrical Characteristics, and K is taken from Table 4.
The absolute minimum input voltage is calculated with
h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, reduce the operating frequency
or add output capacitance to obtain an acceptable
VSAG. If operation near dropout is anticipated, calculate VSAG to ensure adequate transient response.
Dropout Design Example:
VOUT = 1.8V
fSW = 600kHz
K = 1.63µs, worst-case K = 1.4175µs
tOFF(MIN) = 500ns
VDROP1 = VDROP2 = 100mV
h = 1.5
VIN(MIN) = (1.8V + 0.1V) / [1 - (0.5µs ✕ 1.5) / 1.4175µs]
+ 0.1V - 0.1V = 3.8V
Calculating again with h = 1 gives an absolute limit of
dropout:
VIN(MIN) = (1.8V + 0.1V) / [1 - (0.5µs ✕ 1) / 1.4175µs]
+ 0.1V - 0.1V = 2.8V
Therefore, VIN must be greater than 2.8V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 3.8V.
Fixed Output Voltages
The MAX8743’s Dual-Mode operation allows the selection of common voltages without requiring external
components (Figure 8). Connect FB1 to GND for a fixed
1.8V output or to VCC for a 1.5V output, or connect FB1
directly to OUT1 for a fixed 1V output.
Connect FB2 to GND for a fixed 2.5V output or to OUT2
for a fixed 1V output.
______________________________________________________________________________________
21
MAX8743
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
ILOAD(MAX) but are not high enough to exceed the current limit. To protect against this possibility, “overdesign” the circuit to tolerate:
ILOAD = ILIMIT(HIGH) + (LIR / 2) ✕ ILOAD(MAX)
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
OUT1
VBATT
OUT2
FIXED
1.5V
TO ERROR
AMP1
DH_
TO ERROR FIXED
AMP2
2.5V
VOUT
FIXED
1.8V
MAX8743
DL_
CS_
FB1
FB2
FB_
0.1V
2V
R1
OUT_
R2
GND
MAX8743
0.1V
Figure 8. Feedback MUX
Setting VOUT_ with a Resistor-Divider
The output voltage can be adjusted from 1V to 5.5V
with a resistor-divider network (Figure 9). The equation
for adjusting the output voltage is:
R1 

VOUT_ = VFB_ 1 +


R2 
Figure 9. Setting VOUT with a Resistor-Divider
USE AGND PLANE TO:
- BYPASS VCC AND REF
- TERMINATE EXTERNAL FB, ILIM,
OVP DIVIDERS, IF USED
- PIN-STRAP CONTROL
INPUTS
AGND PLANE
where VFB_ is 1.0V and R2 is approximately 10kΩ.
USE PGND PLANE TO:
- BYPASS VDD
- CONNECT IC GROUND
TO TOP-SIDE STAR GROUND
PGND PLANE
VIA TO TOP-SIDE
GROUND
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. This is especially true for dual converters, where one channel can
affect the other. The switching power stages require
particular attention (Figure 10). Refer to the MAX1845
evaluation kit data sheet for a specific layout example.
Use a four-layer board. Use the top side for power components and the bottom side for the IC and the sensitive
ground components. Use the two middle layers as
ground planes, with interconnections between the top
and bottom layers as needed. If possible, mount all of
the power components on the top side of the board,
with connecting terminals flush against one another.
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. Short power traces and load connections are essential for high efficiency. Using thick
copper PC boards (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PC board
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable
efficiency penalty.
22
AGND PLANE
VIN
Q1
Q3
Q4
Q2
CIN CIN CIN
L1
VIA TO OUT1
D1
D2
C1
C2
NOTCH
VIA TO CS1
L2
VIA TO PGND PLANE AND IC GND
TOP-SIDE GROUND PLANE
Figure 10. PC Board Layout Example
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
• Minimize the resistance in the high-side path. This
path starts at VIN, goes through the high-side FET,
through the inductor, through the input capacitor,
and back to the input.
• When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF,
ILIM_, FB_).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (sense resistor, C IN -, C OUT -, D1
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the synchronousrectifier MOSFETs, preferably on the back side to keep
CS_, GND, and the DL_ gate-drive line short and wide.
The DL_ gate trace must be short and wide, measuring 10 squares to 20 squares (50mils to 100mils wide if
the MOSFET is 1in from the controller IC).
3) Group the gate-drive components (BST_ diode and
capacitor, VDD bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
follows: Create a small analog ground plane (AGND)
near the IC. Connect this plane directly to GND
under the IC, and use this plane for the ground connection for the REF and VCC bypass capacitors,
FB_, OVP, and ILIM_ dividers (if any). Do not connect the AGND plane to any ground other than the
GND pin. Create another small ground island
(PGND), and use it for the VDD bypass capacitor,
placed very close to the IC. Connect the PGND
plane directly to GND from the outside of the IC.
5) On the board’s top side (power planes), make a star
ground to minimize crosstalk between the two sides.
The top-side star ground is a star connection of the
input capacitors, side 1 low-side MOSFET, and side
2 low-side MOSFET. Keep the resistance low
between the star ground and the source of the lowside MOSFETs for accurate current limit. Connect
the top-side star ground (used for MOSFET, input,
and output capacitors) to the small PGND island with
a short, wide connection (preferably just a via).
Minimize crosstalk between side 1 and side 2 by
directing their switching ground currents into the star
ground with a notch as shown in Figure 10. If multiple layers are available (highly recommended), create PGND1 and PGND2 islands on the layer just
below the top-side layer (refer to the MAX1845 EV kit
for an example) to act as an EMI shield. Connect
each of these individually to the star-ground via,
which connects the top side to the PGND plane. Add
one more solid ground plane under the IC to act as
an additional shield, and also connect that to the
star-ground via.
6) Connect the output power planes directly to the output filter-capacitor positive and negative terminals
with multiple vias.
______________________________________________________________________________________
23
MAX8743
Place the current-sense resistors close to the top-side
star-ground point (where the IC ground connects to the
top-side ground plane) to minimize current-sensing
errors. Avoid additional current-sensing errors by using a
Kelvin connection from CS_ pins to the sense resistors.
The following guidelines are in order of importance:
• Keep the space between the ground connection of
the current-sense resistors short and near the via to
the IC ground pin.
• Minimize the resistance on the low-side path. The
low-side path starts at the ground of the low-side
FET, goes through the low-side FET, through the
inductor, through the output capacitor, and returns
to the ground of the low-side FET. Minimize the resistance by keeping the components close together
and the traces short and wide.
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
MAX8743
Pin Configurations
SKIP 6
PGOOD 7
28
29
30
31
FB1
OUT1
CS1
LX1
N.C.
DH1
32
1
27
2
26
PGOOD
OVP
3
25
23 GND
4
24
22 VCC
UVP
N.C.
5
REF
ON1
N.C.
7
21
8
20
AGND
VCC
VDD
DL2
9
19
BST2
24 DL1
MAX8743EEI
16
17
18
ON2 12
17 LX2
N.C.
DH2
ILIM2 13
16 CS2
15 OUT2
15
18 DH2
14
ON1 11
13
19 BST2
12
REF 10
11
20 DL2
10
UVP 9
22
ON2
ILIM2
FB2
OUT2
CS2
LX2
21 VDD
23
MAX8743ETX
6
N.C.
OVP 8
FB2 14
BST1
DL1
TON
SKIP
25 BST1
V+ 4
TON 5
33
26 DH1
V+
ILIM1
ILIM1 3
34
27 LX1
N.C.
28 CS1
FB1 2
35
OUT1 1
36
TOP VIEW
N.C.
PGND
THIN QFN
QSOP
Chip Information
TRANSISTOR COUNT: 4795
PROCESS: BiCMOS
24
______________________________________________________________________________________
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1
1
Note: The MAX8743EEI does not have a heat slug.
______________________________________________________________________________________
25
MAX8743
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN 6x6x0.8.EPS
MAX8743
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
D2
D
CL
D/2
b
D2/2
k
E/2
E2/2
(NE-1) X e
E
CL
E2
k
e
L
(ND-1) X e
e
L
CL
CL
L1
L
L
e
A1
A2
e
A
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
26
______________________________________________________________________________________
E
1
2
Dual, High-Efficiency, Step-Down
Controller with High Impedance in Shutdown
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
21-0141
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
27 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX8743
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)