19-4781; Rev 0; 11/98 NUAL KIT MA ATION EET H S A EVALU T WS DA O L L O F High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs The MAX1710/MAX1711 step-down controllers are intended for core CPU DC-DC converters in notebook computers. They feature a triple-threat combination of ultra-fast transient response, high DC accuracy, and high efficiency needed for leading-edge CPU core power supplies. Maxim’s proprietary QUICK-PWM™ quick-response, constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. High DC precision is ensured by a 2-wire remote-sensing scheme that compensates for voltage drops in both ground bus and the supply rail. An on-board, digital-toanalog converter (DAC) sets the output voltage in compliance with Mobile Pentium II® CPU specifications. The MAX1710 achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by an ability to drive very large synchronousrectifier MOSFETs. Single-stage buck conversion allows these devices to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at a higher switching frequency allows the minimum possible physical size. The MAX1710 and MAX1711 are identical except that the MAX1711 has a 5-bit DAC rather than a 4-bit DAC. Also, the MAX1711 has a fixed overvoltage protection threshold at VOUT = 2.25V and undervoltage protection at VOUT = 0.8V, whereas the MAX1710 has variable thresholds that track VOUT. The MAX1711 is intended for applications where the DAC code may change dynamically. Features ♦ Ultra-High Efficiency ♦ No Current-Sense Resistor (Lossless ILIMIT) ♦ QUICK-PWM with 100ns Load-Step Response ♦ ±1% VOUT Accuracy over Line and Load ♦ 4-Bit On-Board DAC (MAX1710) ♦ 5-Bit On-Board DAC (MAX1711) ♦ 0.925V to 2V Output Adjust Range (MAX1711) ♦ 2V to 28V Battery Input Range ♦ 200/300/400/550kHz Switching Frequency ♦ Remote GND and VOUT Sensing ♦ Over/Undervoltage Protection ♦ 1.7ms Digital Soft-Start ♦ Drives Large Synchronous-Rectifier FETs ♦ 2V ±1% Reference Output ♦ Power-Good Indicator ♦ Small 24-Pin QSOP Package Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX1710EEG -40°C to +85°C 24 QSOP MAX1711EEG -40°C to +85°C 24 QSOP Minimal Operating Circuit BATTERY 4.5V TO 28V +5V INPUT VCC Applications OVP* VDD V+ SHDN FBS Notebook Computers ILIM Docking Stations GNDS BST DH OUTPUT 0.925V TO 2V (MAX1711) MAX1710 MAX1711 CPU Core DC-DC Converters Single-Stage (BATT to VCORE) Converters REF LX Two-Stage (+5V to VCORE) Converters CC DL D0 QUICK-PWM is a trademark of Maxim Integrated Products. Mobile Pentium II is a registered trademark of Intel Corp. Pin Configuration appears at end of data sheet. D/A INPUTS *MAX1710 ONLY **MAX1711 ONLY D1 PGND D2 FB D3 SKIP D4** GND ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 1-800-835-8769. MAX1710/MAX1711 General Description MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs ABSOLUTE MAXIMUM RATINGS LX to BST..................................................................-6V to +0.3V V+ to GND ..............................................................-0.3V to +30V REF Short Circuit to GND ...........................................Continuous VCC, VDD to GND .....................................................-0.3V to +6V PGND to GND.....................................................................±0.3V Continuous Power Dissipation (TA = +70°C) SHDN, PGOOD to GND ...........................................-0.3V to +6V 24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW OVP, ILIM, FB, FBS, CC, REF, D0–D4, Operating Temperature Range ...........................-40°C to +85°C GNDS, TON to GND ..............................-0.3V to (VCC + 0.3V) Junction Temperature ......................................................+150°C SKIP to GND (Note 1).................................-0.3V to (VCC + 0.3V) Storage Temperature Range .............................-65°C to +165°C DL to PGND................................................-0.3V to (VDD + 0.3V) Lead Temperature (soldering, 10sec) .............................+300°C BST to GND ............................................................-0.3V to +36V DH to LX .....................................................-0.3V to (BST + 0.3V) Note 1: SKIP may be forced below -0.3V, temporarily exceeding the absolute maximum rating, for the purpose of debugging prototype breadboards using the no-fault test mode. Limit the current drawn to -5mA maximum. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VBATT = 15V, VCC = VDD = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN MAX UNIT 28 VCC, VDD 4.5 5.5 DAC codes from 1.3V to 2V VBATT = 4.5V to 28V, includes DAC codes from 0.925V load regulation error to 1.275V -1 1 DC Output Voltage Accuracy -1.2 1.2 Load Regulation Error ILOAD = 0 to 7A 9 mV Remote Sense Voltage Error FB-FBS or GNDS-GND = 0 to 25mV 3 mV Line Regulation Error VCC = 4.5V to 5.5V, VBATT = 4.5V to 28V 5 FB Input Bias Current FB (MAX1710 only) or FBS FB Input Resistance (MAX1711) -0.2 130 GNDS Input Bias Current 180 -1 Soft-Start Ramp Time Rising edge of SHDN to full ILIM On-Time TON = GND (550kHz) VBATT = 24V, TON = REF (400kHz) FB = 2V TON = open (300kHz) (Note 2) TON = VCC (200kHz) Minimum Off-Time (Note 2) Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) V % mV 0.2 µA 240 kΩ 1 1.7 µA ms 140 160 180 175 200 225 260 290 320 380 425 470 400 500 ns Measured at VCC, FB forced above the regulation point 600 950 µA Measured at VDD, FB forced above the regulation point <1 5 µA 25 40 µA Quiescent Battery Supply Current Measured at V+ 2 TYP 2 Input Voltage Range Battery voltage, V+ ns Shutdown Supply Current (VCC) SHDN = 0 <1 5 µA Shutdown Supply Current (VDD) SHDN = 0 <1 5 µA Shutdown Battery Supply Current SHDN = 0, measured at V+ = 28V, VCC = VDD = 0 or 5V <1 5 µA Reference Voltage VCC = 4.5V to 5.5V, no external REF load 2 2.02 V Reference Load Regulation IREF = 0 to 50µA REF Sink Current REF in regulation REF Fault Lockout Voltage Falling edge, hysteresis = 40mV 1.98 0.01 10 V µA 1.6 _______________________________________________________________________________________ V High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs MAX1710/MAX1711 ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VBATT = 15V, VCC = VDD = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER Overvoltage Trip Threshold MIN TYP MAX UNIT With respect to unloaded output voltage (MAX1710) CONDITIONS 10.5 12.5 14.5 % (MAX1711) 2.21 2.25 2.29 V Overvoltage Fault Propagation Delay FB forced 2% above trip threshold Output Undervoltage Protection Threshold With respect to unloaded output voltage (MAX1710) (MAX1711) Output Undervoltage Protection Time From SHDN signal going high 10 Current-Limit Threshold (Positive Direction, Fixed) LX to PGND, ILIM tied to VCC 90 Current-Limit Threshold (Positive Direction, Adjustable) LX to PGND Current-Limit Threshold (Negative Direction) LX to PGND, TA = +25°C Current-Limit Threshold (Zero Crossing) LX to PGND PGOOD Propagation Delay FB forced 2% below PGOOD trip threshold, falling edge PGOOD Output Low Voltage ISINK = 1mA PGOOD Leakage Current High state, forced to 5.5V Thermal Shutdown Threshold Hysteresis = 10°C VCC Undervoltage Lockout Threshold Rising edge, hysteresis = 20mV, PWM disabled below this level DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance (Pull-Up) DL Gate-Driver On-Resistance (Pull-Down) DL, low state DH Gate-Driver Source/Sink Current DH forced to 2.5V, BST-LX forced to 5V 1 A DL Gate-Driver Sink Current DL forced to 2.5V 3 A DL Gate-Driver Source Current DL forced to 2.5V 1 A DL rising 35 DH rising 26 Dead Time 1.5 65 0.76 70 0.8 100 µs 75 0.84 % V 30 ms 110 mV RLIM = 100kΩ 40 50 60 RLIM = 400kΩ 170 200 230 -150 -120 -80 3 mV mV 1.5 µs 0.4 V 1 µA 150 4.1 mV °C 4.4 V BST-LX forced to 5V 5 Ω DL, high state 5 Ω 1.7 Ω 0.5 SKIP Input Current Logic Threshold To enable no-fault mode, TA = +25°C PGOOD Trip Threshold Measured at FB with respect to unloaded output voltage, falling edge, hysteresis = 1% -8 Logic Input High Voltage D0–D4, SHDN, SKIP, OVP 2.4 Logic Input Low Voltage D0–D4, SHDN, SKIP, OVP Logic Input Current SHDN, SKIP, OVP -1 Logic Input Pull-Up Current D0–D4, each forced to GND 3 -1.5 -5 ns -0.1 mA -3 % V 5 0.8 V 1 µA 10 µA _______________________________________________________________________________________ 3 MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VBATT = 15V, VCC = VDD = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX VCC - 0.4 UNIT TON VCC Level TON logic input high level TON Float Voltage TON logic input upper-mid-range level 3.15 3.85 V V TON Reference Level TON logic input lower-mid-range level 1.65 2.35 V TON GND Level TON logic input low level TON Logic Input Current TON only, forced to GND or VCC -3 0.5 V 3 µA ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VBATT=15V, VCC = VDD = 5V, SKIP = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER Input Voltage Range CONDITIONS Battery voltage, V+ MIN TYP MAX UNIT 2 28 4.5 5.5 DAC codes from 1.32V to 2V -1.5 1.5 % DAC codes from 0.925V to 1.275V -1.7 1.7 % 140 180 175 225 260 320 380 470 VCC, VDD DC Output Voltage Accuracy VBATT = 4.5V to 28V, for all D/A codes, includes load regulation error On-Time TON = GND (550kHz) VBATT = 24V, TON = REF (400kHz) FB = 2V TON = open (300kHz) (Note 2) TON = VCC (200kHz) V ns Minimum Off-Time (Note 2) 500 ns Quiescent Supply Current (VCC) Measured at VCC, FB forced above the regulation point 950 µA Reference Voltage VCC = 4.5V to 5.5V, no external REF load 2.02 V % Overvoltage Trip Threshold Output Undervoltage Protection Threshold With respect to unloaded output voltage (MAX1710) 1.98 10 15 2.20 2.30 V 65 75 % 0.75 0.85 V 85 115 mV RLIM = 100kΩ 35 65 RLIM = 400kΩ 160 240 4.4 (MAX1711) With respect to unloaded output voltage (MAX1710) (MAX1711) Current-Limit Threshold (Positive Direction, Fixed) LX to PGND, ILIM tied to VCC Current-Limit Threshold (Positive Direction, Adjustable) LX to PGND VCC Undervoltage Lockout Threshold Rising edge, hysteresis = 20mV, PWM disabled below this level 4.1 Logic Input High Voltage D0–D4, SHDN, SKIP, OVP 2.4 Logic Input Low Voltage D0–D4, SHDN, SKIP, OVP Logic Input Current SHDN, SKIP, OVP Logic Input Pull-Up Current D0–D4, each forced to GND 4 mV V V 0.8 V -1 1 µA 3 10 µA _______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs (Circuit of Figure 1, VBATT=15V, VCC = VDD = 5V, SKIP = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN PGOOD Trip Threshold Measured at FB with respect to unloaded output voltage, falling edge, hysteresis = 1% -8.5 PGOOD Output Low Voltage ISINK = 1mA PGOOD Leakage Current High state, forced to 5.5V TYP MAX UNIT -2.5 % 0.4 V 1 µA Note 2: On-Time and Off-Time specifications are measured from 50% point to 50% point at the DH pin with LX forced to 0V, BST forced to 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds. Note 3: Specifications from -40°C to 0°C are guaranteed but not production tested. __________________________________________Typical Operating Characteristics (7A CPU supply circuit of Figure 1, TA = +25°C, unless otherwise noted.) VIN = 4.5V 90 VIN = 4.5V VIN = 7V 90 EFFICIENCY vs. LOAD CURRENT (VO = 1.3V, f = 300kHz) 100 MAX1710-02 100 MAX1710-01 100 EFFICIENCY vs. LOAD CURRENT (VO = 1.6V, f = 300kHz) MAX1710-03 EFFICIENCY vs. LOAD CURRENT (VO = 2.0V, f = 300kHz) VIN = 4.5V 90 VIN = 7V 70 VIN = 15V 60 VIN = 24V 80 EFFICIENCY (%) 80 EFFICIENCY (%) EFFICIENCY (%) VIN = 7V VIN = 15V 70 VIN = 24V 60 80 70 VIN = 15V 60 VIN = 24V 50 50 40 40 0.1 1 0.1 10 0.1 1 10 EFFICIENCY vs. LOAD CURRENT (VO = 1.6V, f = 550kHz) FREQUENCY vs. LOAD CURRENT (VO = 1.6V) FREQUENCY vs. INPUT VOLTAGE (IO = 7A) 300 VIN = 15V 316 250 200 VIN = 4.5V, SKIP MODE 150 VIN = 15V, SKIP MODE 100 VIN = 24V 1 10 VO = 2.0V 310 VO = 1.6V 308 302 0 0.1 312 304 TON = OPEN LOAD CURRENT (A) 314 306 50 40 318 VIN = 15V, PWM MODE FREQUENCY (kHz) FREQUENCY (kHz) 70 320 MAX1710-06 350 MAX1710-04 80 0.01 0.01 LOAD CURRENT (A) VIN = 7V 50 1 LOAD CURRENT (A) VIN = 4.5V 60 40 0.01 LOAD CURRENT (A) 100 90 10 MAX1710-05 0.01 EFFICIENCY (%) 50 0.01 0.1 1 LOAD CURRENT (A) 10 TON = OPEN 300 0 5 10 15 20 25 30 INPUT VOLTAGE (V) _______________________________________________________________________________________ 5 MAX1710/MAX1711 ELECTRICAL CHARACTERISTICS (continued) _____________________________Typical Operating Characteristics (continued) (7A CPU supply circuit of Figure 1, TA = +25°C, unless otherwise noted.) FREQUENCY vs. TEMPERATURE (VIN = 15V, VO = 2.0V) IO = 4A 295 25 CURRENT TRIP POINT (A) 305 468 466 464 462 20 15 ILIM = VCC 10 5 TON = OPEN 0 456 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 -60 100 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) CONTINUOUS TO DISCONTINUOUS INDUCTOR CURRENT POINT vs. INPUT VOLTAGE INDUCTOR CURRENT PEAKS AND VALLEYS vs. INPUT VOLTAGE (AT CURRENT-LIMIT POINT) NO-LOAD SUPPLY CURRENTS vs. INPUT VOLTAGE (SKIP MODE, f = 300kHz) 0.7 0.6 VO = 1.3V 0.5 0.4 0.3 0.2 13.0 12.5 12.0 11.5 IVALLEY 11.0 0 5 10 15 20 25 5 10 15 20 25 30 20 18 IBATT 0.2 IDD 14 12 IDD 10 8 IBAT 6 25 30 25 20 IDD 18 30 14 12 10 IBAT 8 6 2 ICC 0 20 20 4 2 0 15 16 4 15 10 NO-LOAD SUPPLY CURRENTS vs. INPUT VOLTAGE (PWM MODE, f = 550kHz) SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 0.4 10 5 INPUT VOLTAGE (V) 16 0.5 INPUT VOLTAGE (V) IDD 0 MAX1710-14 ICC 5 0.2 NO-LOAD SUPPLY CURRENTS vs. INPUT VOLTAGE (PWM MODE, f = 300kHz) MAX1710-13 0.7 0.1 IBATT 0.3 INPUT VOLTAGE (V) NO-LOAD SUPPLY CURRENTS vs. INPUT VOLTAGE (SKIP MODE, f = 550kHz) 0.3 0.4 0 0 30 INPUT VOLTAGE (V) 0.6 0.5 0.1 10.0 0 ICC 0.6 10.5 0.1 MAX1710-12 IPEAK INDUCTOR CURRENT (A) VO = 1.6V 13.5 MAX1710-15 VO = 2.0V 100 0.7 SUPPLY CURRENT (mA) 0.8 14.0 MAX1710-10 0.9 0 -40 TEMPERATURE (°C) MAX1710-11 -60 ILIM = 100kΩ 458 IO = 1A 285 6 ILIM = 400kΩ IO = 4A OR 7A 460 290 LOAD CURRENT (A) IO = 1A MAX1710-09 472 470 30 MAX1710-08 MAX1710-07 IO = 7A 300 474 ON TIME (ns) FREQUENCY (kHz) 310 CURRENT-LIMIT TRIP POINT vs. TEMPERATURE ON-TIME vs. TEMPERATURE 315 SUPPLY CURRENT (mA) MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs ICC 0 0 5 10 15 20 INPUT VOLTAGE (V) 25 30 0 5 10 15 20 INPUT VOLTAGE (V) _______________________________________________________________________________________ 25 30 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs (7A CPU supply circuit of Figure 1, TA = +25°C, unless otherwise noted.) LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR) MAX1710-18 LOAD-TRANSIENT RESPONSE (WITHOUT INTEGRATOR) MAX1710-17 MAX1710-16 LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR) A A A B B B 10µs/div 10µs/div VIN = 15V, VO = 1.6V, IO = 0A TO 7A A = VOUT, AC COUPLED, 50mV/div B = INDUCTOR CURRENT, 5A/div LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR) VIN = 15V, VO = 1.6V, IO = 30mA TO 7A A = VOUT, AC COUPLED, 50mV/div B = INDUCTOR CURRENT, 5A/div LOAD-TRANSIENT RESPONSE (WITH INTEGRATOR) MAX1710-21 START-UP WAVEFORM MAX1710-20 MAX1710-19 A 10µs/div VIN = 15V, VO = 1.6V, IO = 30mA, TO 7A A = VOUT, AC COUPLED, 50mV/div B = INDUCTOR CURRENT, 5A/div A A B B B C C 20µs/div VIN = 4.5V, VO = 2V, IO = 30mA TO 7A A = VOUT, AC COUPLED, 50mV/div B = INDUCTOR CURRENT, 5A/div C = DL, 10V/div C 20µs/div VIN = 4.5V, VO = 1.3V, IO = 30mA TO 7A A = VOUT, AC COUPLED, 50mV/div B = INDUCTOR CURRENT, 5A/div C = DL, 10V/div 500µs/div A = SHDN B = VOUT, 0.5V/div C = INDUCTOR CURRENT, 5A/div _______________________________________________________________________________________ 7 MAX1710/MAX1711 _____________________________Typical Operating Characteristics (continued) _____________________________Typical Operating Characteristics (continued) (7A CPU supply circuit of Figure 1, TA = +25°C, unless otherwise noted.) B MAX1710-24 MAX1710-23 A SHUTDOWN WAVEFORM LOAD-TRANSIENT RESPONSE OUTPUT OVERLOAD WAVEFORM MAX1710-22 MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs CERAMIC COUT A A B C B D C C 50µs/div VOUT = 1.6V A = VIN, AC COUPLED, 2V/div B = VOUT, 0.5V/div C = INDUCTOR CURRENT, 5A/div 5µs/div 5µs/div L = 0.7µH, VOUT = 1.6V, VIN = 15V, COUT = 47µF (x4), f = 550kHz A = VOUT, AC COUPLED, 100mV/div B = INDUCTOR CURRENT, 5A/div C = DL, 5V/div VIN = 15V, V0 = 1.6V, I0 = 7A A = VOUT, 0.5V/div B = INDUCTOR CURRENT, 5A/div C = SHDN, 2V/div D = DL, 5V/div Pin Description 8 PIN NAME FUNCTION 1 CC Battery Voltage Sense Connection. V+ is used only for PWM one-shot timing. DH on-time is inversely proportional to V+ input voltage over a range of 2V to 28V. 2 SHDN 3 FB Fast Feedback Input, normally connected to VOUT. FB is connected to the bulk output filter capacitors locally at the power supply. An external resistor-divider can optionally set the output voltage. 4 FBS Feedback Remote-Sense Input, normally connected to VOUT directly at the load. FBS internally connects to the integrator that fine-tunes the DC output voltage. Tie FBS to VCC to disable all three integrator amplifiers. Tie FBS to FB (or disable the integrators) when externally adjusting the output voltage with a resistor-divider. 5 CC Integrator Capacitor Connection. Connect a 100pF to 1000pF (470pF typical) capacitor to GND to set the integration time constant. 6 ILIM Current-Limit Threshold Adjustment. Connects to an external resistor to GND. The LX-PGND current-limit threshold defaults to +100mV if ILIM is tied to VCC. The current-limit threshold is 1/10 of the voltage forced at ILIM. In adjustable mode the threshold is VTH = RLIM · 5µA/10. 7 VCC Analog Supply Voltage Input for PWM Core, 4.5V to 5.5V. Bypass VCC to GND with a 0.1µF minimum capacitor. 8 TON On-Time Selection Control Input. This is a four-level input that sets the K factor to determine DH on-time. GND = 550kHz, REF = 400kHz, open = 300kHz, VCC = 200kHz. 9 REF 2.0V Reference Output. Bypass REF to GND with a 0.22µF minimum capacitor. REF can source 50µA for external loads. Loading REF degrades FB accuracy according to the REF load-regulation error (see Electrical Characteristics). Shutdown Control Input, active low. SHDN cannot withstand the battery voltage. In shutdown mode, DL is forced to VDD in order to enforce overvoltage protection, even when powered down (unless OVP is high). _______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs PIN NAME 10 GND 11 GNDS 12 PGOOD FUNCTION Analog Ground Ground Remote-Sense Input, normally connected to ground directly at the load. GNDS internally connects to the integrator that fine-tunes the ground offset voltage. Open-Drain Power-Good Output. 13 DL 14 PGND Low-Side Gate-Driver Output, swings 0 to VDD. 15 VDD Supply Voltage Input for the DL gate driver, 4.5V to 5.5V 16 (MAX1710) OVP Overvoltage-Protection Disable Control Input (Table 3). GND = normal operation and overvoltage protection active, VCC = overvoltage protection disabled. 16 (MAX1711) D4 DAC Code Input, MSB, 5µA internal pull-up to VCC (Tables 1 and 2). 17 D3 DAC Code Input. 5µA internal pull-up to VCC. 18 D2 DAC Code Input. 5µA internal pull-up. 19 D1 DAC Code Input. 5µA internal pull-up. 20 D0 DAC Code Input LSB. 5µA internal pull-up. Power Ground. Also used as the inverting input for the current-limit comparator. 21 SKIP Low-Noise-Mode Selection Control Input. Low-noise forced-PWM mode causes inductor current recirculation at light loads and suppresses pulse-skipping operation. Normal operation prevents current recirculation. SKIP can also be used to disable both overvoltage and undervoltage protection circuits and clear the fault latch (Figure 6). GND = normal operation, VCC = low-noise mode. Do not leave SKIP floating. 22 BST Boost Flying-Capacitor Connection. An optional resistor in series with BST allows the DH pull-up current to be adjusted (Figure 5). This technique of slowing the LX rise time can be used to prevent accidental turn-on of the low-side MOSFET due to excessive gate-drain capacitance. 23 LX Inductor Connection. LX serves as the lower supply rail for the DH high-side gate driver. Also used for the noninverting input to the current-limit comparator as well as the skip-mode zero-crossing comparator. 24 DH High-Side Gate-Driver Output. Swings LX to BST. Standard Application Circuit The standard application circuit (Figure 1) generates a low-voltage, high-power rail for supplying up to 7A to the core CPU VCC in a notebook computer. This DC-DC converter steps down a battery or AC adapter voltage to sub-2V levels with high efficiency and accuracy, and represents a good compromise between size, efficiency, and cost. See the MAX1710 EV kit manual for a list of components and suppliers. Detailed Description The MAX1710/MAX1711 buck controllers are targeted for low-voltage, high-current CPU power supplies for notebook computers. CPU cores typically exhibit 0 to 10A or greater load steps when the clock is throttled. The proprietary QUICK-PWM pulse-width modulator in the MAX1710/MAX1711 is specifically designed for handling these fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The QUICKPWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs _______________________________________________________________________________________ 9 MAX1710/MAX1711 Pin Description (continued) MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs VBATT 4.5V TO 28V +5V BIAS SUPPLY C5 1µF C6 1µF R1 20Ω C1 3 x 10µF/30V 15 7 1 ON/OFF CONTROL LOW-NOISE CONTROL 2 21 20 19 DAC INPUTS V+ BST SHDN D0 D1 D2 17 D3 16 D4** LX DL PGND 8 TON 9 REF C3 470pF 5 CC FB FBS GNDS Q1 PANASONIC ETQP6F2R0HFA L1 2µH C2 3 x 470µF KEMET T510 23 13 D1 Q2 3 4 11 +5V R4 1k R2 100k OVP* PGOOD 12 POWER-GOOD INDICATOR 16 6 VOUT 1.25V TO 2V AT 7A (MAX1710) 0.925V TO 2V AT 7A (MAX1711) D3 (OPTIONAL OVP REVERSE-POLARITY CLAMP) 14 GND ILIM * MAX1710 ONLY ** MAX1711 ONLY 24 C7 0.1µF MAX1710 MAX1711 C4 1µF TO VCC DH 22 SKIP 18 10 D2 CMPSH-3 VDD VCC Q1 = IRF7807 Q2 = IRF7805 D1, D3 = MBRS130T3 (OPTIONAL) C1 = Sanyo OS-CON (30SC10M) R3 (OPTIONAL) Figure 1. Standard Application Circuit while also avoiding the problems caused by widely varying switching frequencies in conventional constant-ontime and constant-off-time PWM schemes. +5V Bias Supply (VCC and VDD) The MAX1710/MAX1711 requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook’s 95% efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone 10 capability is needed, the +5V supply can be generated with an external linear regulator such as the MAX1615. The battery and +5V bias inputs can be tied together if the input source is a fixed 4.5V to 5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN) must be delayed until the battery voltage is present in order to ensure start-up. The +5V bias supply must provide VCC and gate-drive power, so the maximum current drawn is: IBIAS = ICC + f · (QG1 + QG2) = 15mA to 30mA (typ) ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs RLIM V+ ILIM TOFF TON FROM D/A ON-TIME COMPUTE TON S Q TRIG VCC 1-SHOT TRIG Q BST Q R DH CURRENT LIMIT 1-SHOT Σ OVP +5V MAX1710 5µA LX ERROR AMP SKIP REF ZERO CROSSING VDD 10k SHDN OUTPUT +5V 70k CC DL REF S Q gm gm PGND R gm FB GNDS FBS FB REF -5% REF +12% REF -30% PGOOD R-2R D/A CONVERTER S1 S2 CHIP SUPPLY VCC 2V REF REF +5V TIMER Q GND OVP/UVLO LATCH D0 D1 D2 D3 Figure 2. MAX1710 Functional Diagram where ICC is 600µA typical, f is the switching frequency, and QG1 and QG2 are the MOSFET data sheet total gate-charge specification limits at VGS = 5V. Free-Running, Constant-On-Time PWM Controller with Input Feed-Forward The QUICK-PWM control architecture is an almost fixedfrequency, constant-on-time current-mode type with voltage feed-forward (Figure 2). This architecture relies on the filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the highside switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage and directly proportional to output voltage. Another oneshot sets a minimum off-time (400ns typical). The on-time one-shot is triggered if the error comparator is low, the ______________________________________________________________________________________ 11 MAX1710/MAX1711 VBATT 2V TO 28V MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs Table 1. MAX1710 FB Output Voltage DAC Codes Table 2. MAX1711 FB Output Voltage DAC Codes D3 D2 D1 D0 OUTPUT VOLTAGE (V) D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 0 0 0 0 2.00 0 0 0 0 0 2.00 0 0 0 1 1.95 0 0 0 0 1 1.95 0 0 1 0 1.90 0 0 0 1 0 1.90 0 0 1 1 1.85 0 0 0 1 1 1.85 0 1 0 0 1.80 0 0 1 0 0 1.80 0 1 0 1 1.75 0 0 1 0 1 1.75 0 1 1 0 1.70 0 0 1 1 0 1.70 0 1 1 1 1.65 0 0 1 1 1 1.65 1 0 0 0 1.60 0 1 0 0 0 1.60 1 0 0 1 1.55 0 1 0 0 1 1.55 1 0 1 0 1.50 1 0 1 0 1.50 0 1 0 1 1 1.45 0 1 0 1 1 1.45 1 1 0 0 1.40 0 1 1 0 0 1.40 1 1 0 1 1.35 1 1 0 1 1.35 0 1 1 1 0 1.30 0 1 1 1 0 1.30 1 1 1 1 1.25 0 1 1 1 1 Shutdown 3* 1 0 0 0 0 1.275 1 0 0 0 1 1.250 low-side switch current is below the current-limit threshold, and the minimum off-time one-shot has timed out. 1 0 0 1 0 1.225 1 0 0 1 1 1.200 On-Time One-Shot (TON) 1 0 1 0 0 1.175 The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input, and directly proportional to the output voltage as set by the DAC code. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. 1 0 1 0 1 1.150 1 0 1 1 0 1.125 1 0 1 1 1 1.100 1 1 0 0 0 1.075 1 1 0 0 1 1.050 1 1 0 1 0 1.025 1 1 0 1 1 1.000 1 1 1 0 0 0.975 1 1 1 0 1 0.950 1 1 1 1 0 0.925 1 1 * See Table 3 1 1 1 Shutdown 3* On-Time = K (VOUT + 0.075V) / VIN where K is set by the TON pin-strap connection and 0.075V is an approximation to accommodate for the expected drop across the low-side MOSFET switch. One-shot timing error increases for the shorter on-time 12 settings due to fixed propagation delays and is approximately ±12.5% at 550kHz and 400kHz, and ±10% at the two slower settings. This translates to reduced switching-frequency accuracy at higher frequencies. (see Table 5). Switching frequency increases as a function of load current due to the increasing drop across the low- ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path, and tON is the on-time calculated by the MAX1710/MAX1711. Integrator Amplifiers (CC) There are three integrator amplifiers that provide a fine adjustment to the output regulation point. One amplifier monitors the difference between GNDS and GND, while another monitors the difference between FBS and FB. The third amplifier integrates the difference between REF and the DAC output. These three transconductance amplifiers’ outputs are directly summed inside the chip, so the integration time constant can be set easily with a capacitor. The gm of each amplifier is 160µmho (typical). The integrator block has an ability to move and correct the output voltage by about -2%, +4%. For each amplifier, the differential input voltage range is about ±50mV total, including DC offset and AC ripple. The voltage gain of each integrator is about 80V/V. The FBS amplifier corrects for DC voltage drops in PC board traces and connectors in the output bus path between the DC-DC converter and the load. The GNDS amplifier performs a similar DC correction task for the output ground bus. The third amplifier provides an averaging function that forces VOUT to be regulated at the average value of the output ripple waveform. If the integrator amplifiers are disabled, VOUT is regulated at the valleys of the output ripple waveform. This creates a slight load-regulation characteristic in which the output voltage rises approximately 1% (up to 1/2 the peak amplitude of the ripple waveform as a limit) when under light loads. Integrators have both beneficial and detrimental characteristics. While they do correct for drops due to DC bus resistance and tighten the DC output voltage tolerance limits by averaging the peak-to-peak output ripple, they can interfere with achieving the fastest possible load-transient response. The fastest transient response is achieved when all three integrators are disabled. This works very well when the MAX1710/ MAX1711 circuit can be placed very close to the CPU. There is often a connector, or at least many milliohms of PC board trace resistance, between the DC-DC converter and the CPU. In these cases, the best strategy is to place most of the bulk bypass capacitors close to the CPU, with just one capacitor on the other side of the connector near the MAX1710/MAX1711 to control ripple if the CPU card is unplugged. In this situation, the remote-sense lines and integrators provide a real benefit. When both GNDS and FBS are tied to VCC so that all three integrators are disabled, CC can be left unconnected, which eliminates a component. Automatic Pulse-Skipping Switchover At light loads, an inherent automatic switchover to PFM takes place. This switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. This mechanism causes the threshold between pulse-skipping PFM and non-skipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the “critical conduction” point; see Continuous to Discontinuous Inductor Current Point vs. Input Voltage graphs in the Typical Operating Characteristics). For a battery range of 7V to 24V this threshold is relatively constant, with only a minor dependence on battery voltage. I LOAD(SKIP) ≈ K 2L where K is the On-Time Scale factor (see Table 5). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 3). For example, in the standard application circuit with tON = 300ns at 24V, VOUT = 2V, and L = 2µH, switchover to pulse-skipping operation occurs at ILOAD = 1.65A or ______________________________________________________________________________________ 13 MAX1710/MAX1711 side MOSFET, which causes a faster inductor-current discharge ramp. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in the external high-side power MOSFET. The exact switching frequency will depend on gate charge, internal gate resistance, source inductance, and DH output drive characteristics. Two external factors that can influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and PC board resistance) and the dead-time effect. These effects are the largest contributors to the change of frequency with changing load current. The dead-time effect is a notable discontinuity in the switching frequency as the load current is varied (see Typical Operating Characteristics). It occurs whenever the inductor current reverses, most commonly at light loads with SKIP high. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the low-to-high dead time. For loads above the critical conduction point, the actual switching frequency is: VOUT + VDROP1 f= t ON (VIN + VDROP2 ) ∆i VBATT -VOUT = L ∆t -IPEAK -IPEAK ILOAD = IPEAK/2 0 ON-TIME TIME INDUCTOR CURRENT ILOAD INDUCTOR CURRENT MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs ILIMIT LX-PGND ILIMIT THRESHOLD = 100mV (NOMINAL, DEFAULT) VOLTAGE DROP ACROSS Q2 0 TIME Figure 3. Pulse-Skipping/Discontinuous Crossover Point Figure 4. ‘‘Valley’’ Current-Limit Threshold Point about 1/4 full load. The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency can be made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 4). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore the exact current-limit characteristic and maximum load capability are a function of the MOSFET on-resistance, inductor value, and battery voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the UVP protection circuit, this current-limit method is effective in almost every circumstance. Forced-PWM Mode (SKIP = High) The low-noise, forced-PWM mode (SKIP driven high) disables the zero-crossing comparator, which controls the low-side switch on-time. This causes the low-side gatedrive waveform to become the complement of the highside gate-drive waveform. This in turn causes the inductor current to reverse at light loads, as the PWM loop strives to maintain a duty ratio of VOUT/VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: the noload battery current can be as high as 40mA or more. Forced-PWM mode is most useful for reducing audio-frequency noise, improving load-transient response, providing sink-current capability for dynamic output voltage adjustment, and improving the cross-regulation of multiple-output applications that use a flyback transformer or coupled inductor. Current-Limit Circuit (ILIM) The current-limit circuit employs a unique “valley” current-sensing algorithm that uses the on-state resistance of the low-side MOSFET as a current-sensing element. If 14 There is also a negative current limit that prevents excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. The current-limit threshold can be adjusted with an external resistor (RLIM) at ILIM. A precision 5µA pull-up current source at ILIM sets a voltage drop on this resistor, adjusting the current-limit threshold from 50mV to 200mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM. Therefore, choose RLIM equal to 2kΩ/mV of the currentlimit threshold. The threshold defaults to 100mV when ILIM is tied to VCC. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. The adjustable current limit can accommodate MOSFETs with atypical on-resistance characteristics (see Design Procedure). A capacitor in parallel with RLIM can provide a variable soft-start function. Carefully observe the PC board layout guidelines to ensure that noise and DC errors don’t corrupt the current-sense signals seen by LX and PGND. The IC must be mounted close to the low-side MOSFET with short, ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs MOSFET Gate Drivers (DH, DL) The DH and DL drivers are optimized for driving moderate-size, high-side and larger, low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VBATT - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the high-side FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate in order for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1710/MAX1711 will interpret the MOSFET gate as “off” while there is actually still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the MOSFET is 1 inch from the MAX1710/MAX1711). The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typical) internal delay. The internal pull-down transistor that drives DL low is robust, with a 0.5Ω typical on-resistance. This helps prevent DL from being pulled up during the fast rise-time of the inductor node, due to capacitive coupling from the drain to the gate of the massive low-side synchronousrectifier MOSFET. However, you might still encounter some combinations of high- and low-side FETs that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents. This can often be remedied by adding a resistor in series with BST, which increases the turn-on time of the highside FET without degrading the turn-off time. DAC Converter (D0–D4) The digital-to-analog converter (DAC) programs the output voltage. It receives a digital code from pins on the CPU module that are either hard-wired to GND or left open-circuit. Note that the codes don’t match any desktop VRM codes. The MAX1710/MAX1711 contain weak internal pull-ups on each input in order to eliminate external resistors. When changing MAX1710 DAC codes while powered up, the over/undervoltage protection features can be activated if the code is changed more than 1LSB at a time. For applications needing the capability of changing DAC codes “on-the-fly,” use the MAX1711. POR, UVLO, and Soft-Start Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start counter, and preparing the PWM for operation. VCC undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high (in order to enforce output overvoltage protection) until V CC rises above 4.2V, whereupon an internal digital soft-start timer begins to ramp up the maximum allowed current limit. The ramp occurs in five steps: 20%, 40%, 60%, 80%, and 100%, with 100% current available after 1.7ms ±50%. A continuously adjustable, analog soft-start function can be realized by adding a capacitor in parallel with RLIM at ILIM. This soft-start method requires a minimum interval between power-down and power-up to allow RLIM to discharge the capacitor. Power-Good Output (PGOOD) The output (FB) is continuously monitored for undervoltage by the PGOOD comparator, except in shutdown or standby mode. The -5% undervoltage trip threshold is measured with respect to the nominal unloaded output voltage, as set by the DAC. If the DAC code increases in steps greater than 1LSB, it is likely that PGOOD will momentarily go low. In shutdown and standby modes, PGOOD is actively held low. The PGOOD output is a true open-drain type with no parasitic ESD diodes. Note that the PGOOD undervoltage detector is completely independent of the output UVP fault detector. Output Overvoltage Protection (OVP) The overvoltage protection circuit is designed to protect against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The FB node is continuously monitored for overvoltage. The overvoltage trip threshold tracks the DAC code setting. If the output is more than 12.5% above the nominal regulation point for the MAX1710 (2.25V absolute for the MAX1711), overvoltage protection (OVP) is triggered and the circuit shuts down. The DL low-side gate-driver output is then latched high until SHDN is toggled or VCC power is cycled below 1V. This action turns on the synchronousrectifier MOSFET with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse will blow. Note that DL going high can have the effect of causing output polarity reversal, due to energy stored in the output LC at the instant OVP activates. If the load can’t tolerate being forced to a negative voltage, it may be desirable to place a power Schottky diode across the output to act as a reverse-polarity clamp (Figure 1). The MAX1710/MAX1711 itself can be affected by the FB pin going below ground, with the negative voltage coupling into SHDN. It may be necessary to add 1kΩ resistors in series with FB and FBS (Figure 7). ______________________________________________________________________________________ 15 MAX1710/MAX1711 direct traces making a Kelvin sense connection to the source and drain terminals. MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs Table 3. Operating Mode Truth Table SHDN SKIP OVP DL MODE 0 X 0 High Shutdown1 Low-power shutdown state. DL is forced to VDD, enforcing OVP. ICC < 1µA typ. 0 X 1 Low Shutdown2 Low-power shutdown state. DL is forced to GND, disabling OVP. ICC < 1µA typ. Exiting shutdown triggers a soft-start cycle. 1 X X Low Shutdown3 (MAX1711 only) DAC code = X1111 (see Table 2) DL is forced to PGND, DH is forced to LX. The MAX1711 eventually goes into UVP fault mode as the load current discharges the output. 1 Below GND X Switching No Fault Test mode with OVP, UVP, and thermal faults disabled and latches cleared. Otherwise normal operation, with automatic PWM/PFM switchover for pulse skipping at light loads (Figure 6). 1 X 1 Switching No OVP OVP faults disabled and OVP latch cleared. Otherwise normal operation, with SKIP controlling PWM/PFM switchover. 1 VCC X Switching Run (PWM), Low Noise Low-noise operation with no automatic switchover. Fixed-frequency PWM action is forced regardless of load. Inductor current reverses at light load levels. ICC draw = 750µA typ. IDD draw = 15mA typ. 1 GND X Switching Run (PFM/PWM) Normal operation with automatic PWM/PFM switchover for pulse skipping at light loads. ICC = 600µA typ. IDD draw = load dependent. 1 X X High Fault Fault latch has been set by OVP, output UVLO, or thermal shutdown. Device will remain in FAULT mode until VCC power is cycled, SKIP is forced below ground, or SHDN is toggled. COMMENTS Table 4. Frequency Selection Guidelines FREQUENCY (kHz) 200 TYPICAL COMMENT APPLICATION 4-cell Li+ notebook Use for absolute best CPU core efficiency. 300 4-cell Li+ notebook Considered mainstream CPU core by current standards. 400 Useful in 4-cell systems 3-cell Li+ notebook for lighter loads than the CPU core CPU or where size is key. 550 Good operating point for +5V-input notebook compound buck designs CPU core or desktop circuits. DL is also kept high continuously when VCC UVLO is active as well as in Shutdown1 mode (Table 3). Overvoltage protection can be defeated via the OVP input (MAX1710 only) or via a SKIP test mode (see Pin Description). Output Undervoltage Protection (UVP) The output undervoltage protection function is similar to foldback current limiting, but employs a timer rather than 16 a variable current limit. If the MAX1710 output (FB) is under 70% of the nominal value 20ms after coming out of shutdown, the PWM is latched off and won’t restart until V CC power is cycled or SHDN is toggled. For the MAX1711, the nominal UVP trip threshold is fixed at 0.8V. No-Fault Test Mode The over/undervoltage protection features can complicate the process of debugging prototype breadboards, since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a test mode is provided to totally disable the OVP, UVP, and thermal shutdown features, and clear to the fault latch if it has been previously set. The PWM operates as if SKIP were grounded (PFM/PWM mode). The no-fault test mode is entered by sinking 1.5mA from SKIP via an external negative voltage source in series with a resistor (Figure 6). SKIP is clamped to GND with a silicon diode, so choose the resistor value equal to (VFORCE - 0.65V) / 1.5mA. Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple current ratio). The prima- ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs VBATT BST APPROXIMATELY -0.65V MAX1710 MAX1711 5Ω SKIP DH 1.5mA MAX1710 MAX1711 VFORCE LX GND Figure 5. Reducing the Switching-Node Rise Time ry design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) Input voltage range. The maximum value (VBATT(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VBATT(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. 2) Maximum load current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) · 80%. 3) Switching frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and VBATT2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical (Table 4). 4) Inductor operating point. This choice provides trade-offs between size vs. efficiency. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touch- Figure 6. Disabling Over/Undervoltage Protection (Test Mode) es zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The MAX1710/MAX1711’s pulse-skipping algorithm initiates skip mode at the critical-conduction point. So, the inductor operating point also determines the loadcurrent value at which PFM/PWM switchover occurs. The optimum point is usually found between 20% and 50% ripple current. The inductor ripple current also impacts transientresponse performance, especially at low VBATT - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: (∆I LOAD(MAX) )2 ⋅ L VSAG = 2 ⋅ CF ⋅ DUTY (VBATT(MIN) − VOUT ) Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows: L= VOUT f ⋅ LIR ⋅ I LOAD(MAX) Example: ILOAD(MAX) = 7A, VOUT = 2V, f = 300kHz, 50% ripple current or LIR = 0.5. L= 2V = 1.9µH (2µH) 300kHz ⋅ 0.5 ⋅ 7A Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron ______________________________________________________________________________________ 17 MAX1710/MAX1711 +5V MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs is cheap and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK). IPEAK = ILOAD(MAX) + (LIR / 2) · ILOAD(MAX) Setting the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current, therefore: ILIMIT(LOW) > ILOAD(MAX) - (LIR / 2) · ILOAD(MAX) where ILIMIT(LOW) = minimum current-limit threshold voltage divided by the RDS(ON) of Q2. For the MAX1710, the minimum current-limit threshold (100mV default setting) is 90mV. Use the worst-case maximum value for RDS(ON) from the MOSFET Q2 data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each °C of temperature rise. Examining the 7A notebook CPU circuit example with a maximum RDS(ON) = 15mΩ at high temperature reveals the following: ILIMIT(LOW) = 90mV / 15mΩ = 6A 6A is greater than the valley current of 5.25A, so the circuit can easily deliver the full rated 7A using the default 100mV nominal ILIM threshold. When adjusting the current limit, use a 1% tolerance RLIM resistor to prevent a significant increase of errors in the current-limit tolerance. Output Capacitor Selection The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and loadtransient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the overvoltage protection circuit. In CPU VCORE converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: VDIP RESR ≤ I LOAD(MAX) In non-CPU applications, the output capacitor’s size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple: 18 RESR ≤ Vp - p LIR ⋅ I LOAD(MAX) The actual microfarad capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, and other electrolytics). When using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent the overvoltage protection circuit from being tripped when transitioning from a full-load to a no-load condition. The capacitor must be large enough to prevent the inductor’s stored energy from launching the output above the overvoltage protection threshold. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see also VSAG equation under Design Procedure). With integrators disabled, the amount of overshoot due to stored inductor energy can be calculated as: 2 2 C + L ⋅ IPEAK ⋅V ∆V = OUT OUT − VOUT COUT where IPEAK is the peak inductor current. To absolutely minimize the overshoot, disable the integrator first, since the inherent delay of the integrator can cause extra “runon” switching cycles to occur after the load change. Output Capacitor Stability Considerations Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation: f f ESR = π 1 where f ESR = 2 ⋅ π ⋅ RESR ⋅ CF For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 15kHz. In the design example used for inductor selection, the ESR needed to support 50mVp-p ripple is 50mV/3.5A = 14.2mΩ. Three 470µF/4V Kemet T510 lowESR tantalum capacitors in parallel provide 15mΩ max ESR. Their typical combined ESR results in a zero at 14.1kHz, well within the bounds of stability. ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient (see MAX1710 Evaluation Kit manual) and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Don’t allow more than one cycle of ringing after the initial step-response under- or overshoot. Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Non-tantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents. V (V − VOUT ) I RMS = I LOAD OUT BATT VBATT Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability (>5A) when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. For maximum efficiency, choose a high-side MOSFET (Q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15V). Check to ensure that the conduction losses at minimum input voltage don’t exceed the package thermal limits or violate the overall thermal budget. Check to ensure that conduction losses plus switching losses at the maximum input voltage don’t exceed the package ratings or violate the overall thermal budget. Choose a low-side MOSFET (Q2) that has the lowest possible RDS(ON), comes in a moderate to small package (i.e., SO-8), and is reasonably priced. Ensure that the MAX1710/MAX1711 DL gate driver can drive Q2; in other words, check that the gate isn’t pulled up by the high-side switch turning on due to parasitic drain-to-gate capacitance, causing cross-conduction problems. Switching losses aren’t an issue for the low-side MOSFET, since it’s a zero-voltage switched device when used in the buck topology. MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case power dissipation due to resistance occurs at minimum battery voltage: PD(Q1) = (VOUT / VBATT(MIN)) · ILOAD2 · RDS(ON) Generally, a small high-side MOSFET is desired in order to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. Again, the optimum occurs when the switching (AC) losses equal the conduction (RDS(ON)) losses. High-side switching losses don’t usually become an issue until the input is greater than approximately 15V. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2F switching loss equation. If the high-side MOSFET you’ve chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to VBATT(MAX), you must reconsider your choice of MOSFET. Calculating the power dissipation in Q1 due to switching losses is difficult, since it must allow for difficult to quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a sanity check using a thermocouple mounted on Q1. ______________________________________________________________________________________ 19 MAX1710/MAX1711 Don’t put high-value ceramic capacitors directly across the fast feedback inputs (FB to GND) without taking precautions to ensure stability. Large ceramic capacitors can have a high ESR zero frequency and cause erratic, unstable operation. However, it’s easy to add enough series resistance simply by placing the capacitors a couple of inches downstream from the junction of the inductor and FB pin (see the All-Ceramic-Capacitor Application section). Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on FB or because the ESR is so low that there isn’t enough voltage ramp in the output voltage (FB) signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum off-time period has expired. Doublepulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability, which is caused by insufficient ESR. MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs +5V VIN = 7V TO 24V* 0.1µF 20Ω V+ ON/OFF VDD VCC SHDN BST SKIP DH C1 1µF 5Ω Q1 0.5µH R1 1.6V AT 7A 0.1µF MAX1711 LX D0 D1 D2 D3 D4 DAC INPUTS PGND REF FB CC FBS CPU R2 GND 0.22µF C2 Q2 DL 1k 1k 1k 470pF GNDS TON 1nF * FOR HIGHER MINIMUM INPUT VOLTAGE, * LESS OUTPUT CAPACITANCE IS REQUIRED. C1 = 4 x 4.7µF/25V TAIYO YUDEN (TMK325BJ475K) C2 = 6 x 47µF/10V TAIYO YUDEN (LMK550BJ476KM) R1 + R2 = 5mΩ MINIMUM OF PCB TRACE RESISTANCE (TOTAL) Figure 7. All-Ceramic-Capacitor Application Table 5. Approximate K-Factors Errors TON K SETTING FACTOR (kHz) (µs-V) APPROXIMATE K-FACTOR ERROR (%) MIN VBATT AT VOUT = 2V (V) 200 5 ±10 2.6 300 3.3 ±10 2.9 400 2.5 ±12.5 3.2 550 1.8 ±12.5 3.6 2 PD(switching) = CRSS ⋅ VBATT(MAX) ⋅ f ⋅ ILOAD IGATE where CRSS is the reverse transfer capacitance of Q1 and IGATE is the peak gate-drive source/sink current (1A typical). For the low-side MOSFET, Q2, the worst-case power dissipation always occurs at maximum battery voltage: PD(Q2) = (1 - VOUT / VBATT(MAX)) · ILOAD2 · RDS(ON) The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the 20 current limit and cause the fault latch to trip. To protect against this possibility, you must “overdesign” the circuit to tolerate ILOAD = ILIMIT(HIGH) + (LIR / 2) · ILOAD(MAX), where ILIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. This means that the MOSFETs must be very well heatsinked. If short-circuit protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses. Choose a Schottky diode D1 having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional, and if efficiency isn’t critical it can be removed. Application Issues Dropout Performance The output voltage adjust range for continuous-conduction operation is restricted by the non-adjustable 500ns (max) minimum off-time one-shot. For best dropout performance, use the slowest (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off-times. Manufacturing tolerances and internal ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs DH VOUT MAX1710 DL R1 FB R2 FBS 1k GNDS Figure 8. Setting VOUT with a Resistor-Divider propagation delays introduce an error to the TON K-factor. This error is higher at higher frequencies (Table 5). Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see VSAG equation in the Design Procedure). Dropout Design Example: VBATT = 3V min, VOUT = 2V, f = 300kHz. The required duty is (VOUT + VSW) / (VBATT - VSW) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The worst-case on-time is (V OUT + 0.075) / V BATT · K = 2.075V / 3V · 3.35µs-V · 90% = 2.08µs. The IC duty-factor limitation is: DUTY = t ON(MIN) t ON(MIN) + t OFF(MAX) = 2.08µs + 500ns = 80.6% which meets the required duty. Remember to include inductor resistance and MOSFET on-state voltage drops (VSW) when doing worst-case dropout duty-factor calculations. All-Ceramic-Capacitor Application Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR, are non-combustible, are relatively small, and are nonpolarized. On the other hand, they’re expensive and brittle, and their ultra-low ESR characteristic can result in excessively high ESR zero frequencies (affecting stability). In addition, they can cause output overshoot when going abruptly from full-load to no-load conditions, unless there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the induc- tor. In some cases, there may be no room for electrolytics, creating a need for a DC-DC design that uses nothing but ceramics. The all-ceramic-capacitor application of Figure 7 has the same basic performance as the 7A Standard Application Circuit, but replaces the tantalum output capacitors with ceramics. This design relies on having a minimum of 5mΩ parasitic PC board trace resistance in series with the capacitor in order to reduce the ESR zero frequency. This small amount of resistance is easily obtained by locating the MAX1710/MAX1711 circuit two or three inches away from the CPU, and placing all the ceramic capacitors close to the CPU. Resistance values higher than 5mΩ just improve the stability (which can be observed by examining the load-transient response characteristic as shown in the Typical Operating Characteristics). Avoid adding excess PC board trace resistance, as there’s an efficiency penalty. 5mΩ is sufficient for the 7A circuit. Output overshoot determines the minimum output capacitance requirement. In this example, the switching frequency has been increased to 550kHz and the inductor value has been reduced to 0.5µH (compared to 300kHz and 2µH for the standard 7A circuit) in order to minimize the energy transferred from inductor to capacitor during load-step recovery. Even so, the amount of overshoot is high enough (80mV) that for the MAX1710, it’s wise to disable OVP or use the MAX1711 with its fixed 2.25V overvoltage protection threshold to avoid tripping the fault latch (see the overshoot equation in the Output Capacitor Selection section). The efficiency penalty for operating at 550kHz is about 2% to 3%, depending on the input voltage. Two optional 1kΩ resistors are placed in series with FB and FBS. These resistors prevent the negative output voltage spike (that results from tripping OVP) from pulling SHDN low via its internal ESD diode, which tends to clear the fault latch, causing “hiccup” restarts. Setting VOUT with a Resistor-Divider The output voltage can be adjusted with a resistordivider rather than the DAC if desired (Figure 8). The drawback of this practice is that the on-time doesn’t automatically receive correct compensation for changing output voltage levels. This can result in variable switching frequency as the resistor ratio is changed and/or excessive switching frequency. The equation for adjusting the output voltage is: R1 VOUT = VFB − 1% 1+ R2 ( ) ______________________________________________________________________________________ 21 MAX1710/MAX1711 VBATT MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs VIN 4.5V TO 5.5V 1µF 20Ω C1 4 x 10µF/25V 1µF V+ VDD ILIM VCC SHDN ON/OFF BST D0 DH D1 D/A INPUTS IRF7805 D2 0.1µF D3 D4** 0.22µF MAX1710 MAX1711 L1 0.5µH LX REF DL CC PGND IRF7805 VOUT 1.6V AT 7A C2 3 x 470µF KEMET T510 470pF FB VCC 1k GND 100k GNDS FBS PGOOD TON SKIP 1k TO REMOTE LOAD OVP* * MAX1710 ONLY ** MAX1711 ONLY Figure 9. 5V-Powered, 7A CPU Buck Regulator where VFB is the currently selected DAC value. When using external resistors, FBS remote sensing is not recommended, but GNDS remote sensing is still possible. Connect FBS to FB and GNDS to remote ground location. In resistor-adjusted circuits, the DAC code should be set as close as possible to the actual output voltage so that the switching frequency doesn’t become excessive. For highest accuracy, use the MAX1710 when adjusting VOUT with external resistors. The MAX1710 FB node has very high impedance, while the MAX1711 has a 180kΩ ±35% FB impedance, which degrades VOUT accuracy. Adjusting VOUT Above 2V The feed-forward circuit that makes the on-time dependent on battery voltage maintains a nearly constant switching frequency as VIN, ILOAD, and the DAC code are changed. This works extremely well as long as FB is connected directly to the output. When the output is adjusted higher than 2V with a resistor-divider, the switching frequency can be increased to relatively unreasonable levels as the actual off-time 22 decreases and isn’t compensated for by a change in ontime. 3.3V is about the maximum limit to the practical adjustment range; even at the slowest TON setting and with the DAC set to 2V, the switching rate will exceed 600kHz. The trip threshold for output overvoltage protection scales with the nominal output voltage setting. 2-Stage (5V-Powered) Notebook CPU Buck Regulator The most efficient and overall cost-effective solution for stepping down a high-voltage battery to very low output voltage is to use a single-stage buck regulator that’s powered directly from the battery. However, there may be situations where the battery bus can’t be routed near the CPU, or where space constraints dictate the smallest possible local DC-DC converter. In such cases, the 5Vpowered circuit of Figure 9 may be appropriate. The reduced input voltage allows a higher switching frequency and a much smaller inductor value. ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs High-Power, Dynamically Adjustable CPU Application Changing the output voltage dynamically by switching DAC codes “on-the-fly” can be used to help make power-savings/performance trade-offs in the host system. Several important design issues arise from this practice. First, know that attempting to slew the output upward quickly causes large current surges at the battery as the IC goes into output current limiting during the transition. Surge currents can be controlled either by counting the DAC code slowly (50kHz or slower rate suggested), or by modulating the ILIM current-limit threshold. The DAC inputs must be driven quickly to the new value so the device doesn’t wrongly interpret a disallowed DAC code from the transitory value. Use 100ns maximum rise and fall times. The MAX1711 VCORE regulator of Figure 10 is designed to have its output voltage switched between 1.3V and 1.45V in less than 100µs, while causing a minimum level of input surge current. To this end, the output capacitors were selected for having the correct value to a) support the needed ESR, b) prevent excess load-recovery overshoot, and c) minimize input surge currents. The optional 74HC86 exclusive-OR gate detects code transitions on each of the four most-significant DAC inputs. The transition detector output goes to a precision pulse stretcher, a timer which extends the pulse for 75µs (nominal). This signal then feeds three circuits: the power-good detector, the SKIP input, and the ILIM current-limit control input, thus reducing the current-limit threshold during the transition interval (in order to reduce battery current surges). Likewise, SKIP going high asserts forced PWM mode in order to drag the output voltage down to the new value. Forced PWM mode is incompatible with good light-load efficiency due to inductor-current recirculation losses and gate-drive losses. Therefore, SKIP is driven high only during the 100µs max transition interval. The power-good output signal is the logical OR of the 75µs timer signal and the MAX1711 PGOOD signal. The internal PGOOD detector circuit monitors only output undervoltage; PGOOD will probably go low during upward transitions, but not downward. The final powergood output will always go low for at least 75µs due to the timer signal. Selecting the output capacitors in dynamically adjusted V CORE applications can be tricky due to trade-offs between capacitor capacity and ESR. In other words, if the capacitor has sufficiently low ESR to meet the loadtransient response specification, its large capacity may cause excessive input surge currents. On the other hand, a purely ceramic capacitor may not have enough capacity to prevent overvoltage during the transition from full- to no-load condition (see the overshoot equation under Output Capacitor Selection). It may be necessary to mix capacitor types or use specialized capacitors such as those shown in Figure 7 in order to achieve the required ESR while staying within the min/max capacitance value window. If the minimum load is very light, it may be necessary to assert forced PWM mode (via SKIP) during the transition period to guarantee some output sink current capability. Otherwise, the output voltage won’t ramp downwards until pulled down by external load current. Load current capability is 15A peak and 12A continuous over a 10V to 22V input range. All three MOSFETs require good heatsinking. See the MAX1711 EV Kit Manual for a complete bill of materials. Using forced PWM mode repeatedly to ensure sink current capability can have side effects, however. The energy taken from the output by the synchronous rectifier isn’t lost, but is instead returned to the input. If the frequency of the high-to-low output voltage transition is high enough, efficiency will be degraded by the resistive “friction” losses associated with shuttling energy between input and output capacitors. Also, if the output is being overdriven by an external source (such as an external docking-station power supply), forced PWM mode may cause the battery voltage to become pumped up, possibly overvoltaging the battery. Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. PC Board Layout Guidelines • Tie GND and PGND together close to the IC. Carefully follow the grounding instructions under step 4 of the Layout Procedure. ______________________________________________________________________________________ 23 MAX1710/MAX1711 Dynamic DAC Code Changes (MAX1711) MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs +5V INPUT VBATT 10V TO 22V 6 x 10µF/25V CERAMIC 0.1µF 1µF 20Ω 7 15 1 VDD VCC V+ BST 0.22µF 9 DH REF 22 2Ω CMPSH3 24 IRF7805 470pF 5 10 ON/OFF LSB 2 20 19 18 DAC INPUTS 17 MSB 16 CC 0.1µF MAX1711 LX GND DL SHDN D0 PGND 23 1µH/20A OUTPUT +1.5V AT 15A 13 10X 220µF 4V OS-CON 14 2 x IRF7805 20µF CERAMIC D1 D2 FB 3 FBS 4 11 GNDS 12 PGOOD 21 SKIP ILIM D3 D4 8 TON N.C. 1k 6 40k 1% 2N7002 POWERGOOD 200k 1% 2N7002 +3.3V 0.1µF TRANSITION DETECTOR 12 1k 13 A4 VCC B4 Y4 A3 B3 4 5 A2 74HC86 10 1000pF B2 Y3 1N4148 820pF 5% +3.3V 2N7002 Y2 6 30k 30k 1N4148 1 1000pF MAX986 8 1000pF 1k 100k 1% 1N4148 9 1k 49.9k 1% 11 1000pF 1k 100k 1% 3M 14 2 A1 B1 GND 7 Y1 3 100k 1N4148 100k 2N7002 TIMER BLOCK Figure 10. 15A Dynamically Adjustable Notebook CPU Supply with Battery-Surge Current Limiting 24 ______________________________________________________________________________________ 2N7002 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs MAX1710/MAX1711 VBATT GND IN ALL ANALOG GROUNDS CONNECT TO GND ONLY VIA TO PGND NEAR Q2 SOURCE MAX1710 MAX1711 VIA TO GNDS VCC CIN GND OUT CC REF ILIM GND , , Q1 D1 VDD COUT Q2 VOUT VIA TO SOURCE OF Q2 CONNECT GND TO PGND BENEATH IC, 1 POINT ONLY. SPLIT ANALOG GND PLANE AS SHOWN. VIA TO FBS L1 VIA TO FB NEAR COUT+ VIA TO LX NOTES: "STAR" GROUND IS USED. D1 IS DIRECTLY ACROSS Q2. INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE Figure 11. Power-Stage PC Board Layout Example • Keep the power traces and load connections short. This practice is essential for high efficiency. The use of thick copper PC boards (2 oz. vs. 1 oz.) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. • LX and PGND connections to Q2 for current limiting must be made using Kelvin sense connections in order to guarantee the current-limit accuracy. With SO-8 MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while tying in PGND and LX inside (underneath) the SO-8 package. • When trade-offs in trace lengths must be made, it’s preferable to allow the inductor charging path to be made longer than the discharge path. For example, it’s better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor. • Ensure that the FB connection to COUT is short and direct. However, in some cases it may be desirable to deliberately introduce some trace length between the FB inductor node and the output filter capacitor (see the All-Ceramic-Capacitor Application section). • Route high-speed switching nodes away from sensitive analog areas (CC, REF, ILIM). • Make all pin-strap control input connections (SKIP, ILIM, etc.) to GND or VCC rather than PGND or VDD. ______________________________________________________________________________________ 25 MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs Layout Procedure 1) Place the power components first, with ground terminals adjacent (Q2 source, CIN-, COUT-, D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to MOSFET Q2, preferably on the back side opposite Q2 in order to keep LX-PGND current-sense lines and the DL gatedrive line short and wide. The DL gate trace must be short and wide, measuring 10 to 20 squares (50 to 100 mils wide if the MOSFET is 1 inch from the controller IC). 3) Group the gate-drive components (BST diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figure 11. This diagram can be viewed as having three separate ground planes: output ground, where all the high-power components go; the PGND plane, where the PGND pin and VDD bypass capacitor go; and an analog GND plane, where sensitive analog components go. The analog ground plane and PGND plane must meet only at a single point directly beneath the IC. These two planes are then connected to the high-power output ground with a short connection from VDD cap/PGND to the source of the low-side MOSFET, Q2 (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical. Pin Configurations TOP VIEW TOP VIEW V+ 1 24 DH V+ 1 24 DH SHDN 2 23 LX SHDN 2 23 LX FB 3 FBS 4 MAX1710 FB 3 21 SKIP FBS 4 22 BST 21 SKIP MAX1711 20 D0 CC 5 ILIM 6 19 D1 ILIM 6 19 D1 VCC 7 18 D2 VCC 7 18 D2 TON 8 17 D3 TON 8 17 D3 REF 9 16 OVP REF 9 16 D4 GND 10 15 VDD GND 10 15 VDD CC 5 GNDS 11 14 PGND PGOOD 12 13 DL QSOP 26 22 BST GNDS 11 20 D0 14 PGND PGOOD 12 13 DL QSOP ______________________________________________________________________________________ High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs QSOP.EPS ______________________________________________________________________________________ 27 MAX1710/MAX1711 Package Information MAX1710/MAX1711 High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs NOTES 28 ______________________________________________________________________________________