SLLS047L − FEBRUARY 1989 − REVISED MARCH 2004 D Meets or Exceeds TIA/EIA-232-F and ITU D D D D D D D D MAX232 . . . D, DW, N, OR NS PACKAGE MAX232I . . . D, DW, OR N PACKAGE (TOP VIEW) Recommendation V.28 Operates From a Single 5-V Power Supply With 1.0-mF Charge-Pump Capacitors Operates Up To 120 kbit/s Two Drivers and Two Receivers ±30-V Input Levels Low Supply Current . . . 8 mA Typical ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) Upgrade With Improved ESD (15-kV HBM) and 0.1-mF Charge-Pump Capacitors is Available With the MAX202 Applications − TIA/EIA-232-F, Battery-Powered Systems, Terminals, Modems, and Computers C1+ VS+ C1− C2+ C2− VS− T2OUT R2IN 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC GND T1OUT R1IN R1OUT T1IN T2IN R2OUT description/ordering information The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. The driver, receiver, and voltage-generator functions are available as cells in the Texas Instruments LinASIC library. ORDERING INFORMATION PDIP (N) TOP-SIDE MARKING Tube of 25 MAX232N Tube of 40 MAX232D Reel of 2500 MAX232DR Tube of 40 MAX232DW Reel of 2000 MAX232DWR SOP (NS) Reel of 2000 MAX232NSR MAX232 PDIP (N) Tube of 25 MAX232IN MAX232IN Tube of 40 MAX232ID Reel of 2500 MAX232IDR Tube of 40 MAX232IDW Reel of 2000 MAX232IDWR SOIC (D) 0°C to 70°C SOIC (DW) −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA SOIC (D) SOIC (DW) MAX232N MAX232 MAX232 MAX232I MAX232I † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinASIC is a trademark of Texas Instruments. Copyright 2004, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLLS047L − FEBRUARY 1989 − REVISED MARCH 2004 Function Tables EACH DRIVER INPUT TIN OUTPUT TOUT L H H L H = high level, L = low level EACH RECEIVER INPUT RIN OUTPUT ROUT L H H L H = high level, L = low level logic diagram (positive logic) 11 14 T1IN T1OUT 10 7 T2IN T2OUT 12 13 R1OUT R1IN 9 R2OUT 2 POST OFFICE BOX 655303 8 R2IN • DALLAS, TEXAS 75265 SLLS047L − FEBRUARY 1989 − REVISED MARCH 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Positive output supply voltage range, VS+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC − 0.3 V to 15 V Negative output supply voltage range, VS− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to −15 V Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V Output voltage range, VO: T1OUT, T2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS− − 0.3 V to VS+ + 0.3 V R1OUT, R2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Short-circuit duration: T1OUT, T2OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to network GND. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions VCC VIH Supply voltage VIL R1IN, R2IN Low-level input voltage (T1IN, T2IN) TA High-level input voltage (T1IN,T2IN) MIN NOM MAX 4.5 5 5.5 2 V V Receiver input voltage Operating free-air temperature UNIT 0.8 V ±30 V MAX232 0 70 MAX232I −40 85 °C electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 4) PARAMETER ICC TEST CONDITIONS VCC = 5.5 V, TA = 25°C Supply current All outputs open, MIN TYP‡ MAX 8 10 UNIT mA ‡ All typical values are at VCC = 5 V and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 1 µF at VCC = 5 V ± 0.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLLS047L − FEBRUARY 1989 − REVISED MARCH 2004 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature range (see Note 4) PARAMETER TEST CONDITIONS VOH High-level output voltage T1OUT, T2OUT RL = 3 kΩ to GND VOL Low-level output voltage‡ T1OUT, T2OUT RL = 3 kΩ to GND MIN 5 TYP† MAX 7 −7 UNIT V −5 V Output resistance T1OUT, T2OUT VS+ = VS− = 0, VO = ±2 V 300 Ω IOS§ Short-circuit output current T1OUT, T2OUT VCC = 5.5 V, VO = 0 ±10 mA IIS Short-circuit input current T1IN, T2IN VI = 0 200 µA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels only. § Not more than one output should be shorted at a time. NOTE 4: Test conditions are C1−C4 = 1 µF at VCC = 5 V ± 0.5 V. ro switching characteristics, VCC = 5 V, TA = 25°C (see Note 4) PARAMETER TEST CONDITIONS SR Driver slew rate RL = 3 kΩ to 7 kΩ, See Figure 2 SR(t) Driver transition region slew rate See Figure 3 Data rate One TOUT switching MIN TYP MAX UNIT 30 V/µs 3 V/µs 120 kbit/s NOTE 4: Test conditions are C1−C4 = 1 µF at VCC = 5 V ± 0.5 V. RECEIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature range (see Note 4) PARAMETER TEST CONDITIONS VOH High-level output voltage R1OUT, R2OUT IOH = −1 mA VOL Low-level output voltage‡ R1OUT, R2OUT IOL = 3.2 mA VIT+ Receiver positive-going input threshold voltage R1IN, R2IN VCC = 5 V, TA = 25°C VIT− Receiver negative-going input threshold voltage R1IN, R2IN VCC = 5 V, TA = 25°C MIN TYP† MAX 3.5 V 1.7 0.8 UNIT 0.4 V 2.4 V 1.2 V Vhys Input hysteresis voltage R1IN, R2IN VCC = 5 V 0.2 0.5 1 V ri Receiver input resistance R1IN, R2IN VCC = 5, TA = 25°C 3 5 7 kΩ † All typical values are at VCC = 5 V, TA = 25°C. ‡ The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels only. NOTE 4: Test conditions are C1−C4 = 1 µF at VCC = 5 V ± 0.5 V. switching characteristics, VCC = 5 V, TA = 25°C (see Note 4 and Figure 1) PARAMETER tPLH(R) tPHL(R) TYP UNIT Receiver propagation delay time, low- to high-level output 500 ns Receiver propagation delay time, high- to low-level output 500 ns NOTE 4: Test conditions are C1−C4 = 1 µF at VCC = 5 V ± 0.5 V. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS047L − FEBRUARY 1989 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION VCC Pulse Generator (see Note A) RL = 1.3 kΩ R1OUT or R2OUT R1IN or R2IN See Note C CL = 50 pF (see Note B) TEST CIRCUIT ≤10 ns ≤10 ns Input 10% 90% 50% 90% 50% 3V 10% 0V 500 ns tPLH tPHL VOH Output 1.5 V 1.5 V VOL WAVEFORMS NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%. B. CL includes probe and jig capacitance. C. All diodes are 1N3064 or equivalent. Figure 1. Receiver Test Circuit and Waveforms for tPHL and tPLH Measurements POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLLS047L − FEBRUARY 1989 − REVISED MARCH 2004 PARAMETER MEASUREMENT INFORMATION T1IN or T2IN Pulse Generator (see Note A) T1OUT or T2OUT EIA-232 Output CL = 10 pF (see Note B) RL TEST CIRCUIT ≤10 ns ≤10 ns 90% 50% Input 10% 3V 90% 50% 10% 0V 5 µs tPLH tPHL 90% Output VOH 90% 10% 10% VOL tTLH tTHL 0.8 (V SR + –V ) 0.8 (V –V ) OH OL OL OH or t t TLH THL WAVEFORMS NOTES: A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%. B. CL includes probe and jig capacitance. Figure 2. Driver Test Circuit and Waveforms for tPHL and tPLH Measurements (5-µs Input) Pulse Generator (see Note A) EIA-232 Output 3 kΩ CL = 2.5 nF TEST CIRCUIT ≤10 ns ≤10 ns Input 90% 1.5 V 10% 90% 1.5 V 10% 20 µs tTLH tTHL Output 3V 3V −3 V −3 V SR + t THL 6V or t VOH VOL TLH WAVEFORMS NOTE A: The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%. Figure 3. Test Circuit and Waveforms for tTHL and tTLH Measurements (20-µs Input) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLLS047L − FEBRUARY 1989 − REVISED MARCH 2004 APPLICATION INFORMATION 5V CBYPASS =1µF + − 16 C1 C1+ 1 µF 3 From CMOS or TTL To CMOS or TTL 8.5 V 1 µF 5 6 VS− C2+ 1 µF 2 VS+ C1− 4 C2 C3† VCC 1 −8.5 V C4 + C2− 11 14 10 7 12 13 8 9 0V 1 µF EIA-232 Output EIA-232 Output EIA-232 Input EIA-232 Input 15 GND † C3 can be connected to VCC or GND. NOTES: A. Resistor values shown are nominal. B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as shown. In addition to the 1-µF capacitors shown, the MAX202 can operate with 0.1-µF capacitors. Figure 4. Typical Operating Circuit POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MAX232D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232IN ACTIVE PDIP N 16 CU NIPDAU N / A for Pkg Type 25 Addendum-Page 1 Pb-Free (RoHS) Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MAX232INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type MAX232N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type MAX232NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type MAX232NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MAX232NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MAX232DR D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 MAX232DR D 16 SITE 41 330 16 6.5 10.3 2.1 8 16 Q1 MAX232DWR DW 16 SITE 60 330 16 10.75 10.7 2.7 12 16 Q1 MAX232IDR D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 MAX232IDWR DW 16 SITE 60 330 16 10.75 10.7 2.7 12 16 Q1 MAX232NSR NS 16 SITE 41 330 16 8.2 10.5 2.5 12 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) MAX232DR D 16 SITE 27 342.9 336.6 28.58 MAX232DR D 16 SITE 41 346.0 346.0 33.0 MAX232DWR DW 16 SITE 60 346.0 346.0 33.0 MAX232IDR D 16 SITE 27 342.9 336.6 28.58 MAX232IDWR DW 16 SITE 60 346.0 346.0 33.0 MAX232NSR NS 16 SITE 41 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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