19-4626; Rev 0; 5/09 KIT ATION EVALU E L B A AVAIL Low-Jitter, Precision Clock Generator with Three Outputs Features ♦ Crystal Oscillator Interface: 24.8MHz to 27MHz The MAX3625A is a low-jitter, precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, 10G Fibre Channel, and other networking applications. Maxim’s proprietary PLL design features ultra-low jitter and excellent power-supply noise rejection, minimizing design risk for network equipment. The MAX3625A has three LVPECL outputs. Selectable output dividers and a selectable feedback divider allow a range of output frequencies. ♦ CMOS Input: Up to 320MHz ♦ Output Frequencies Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz 10G Fibre Channel: 159.375MHz, 318.75MHz ♦ Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.36psRMS (12kHz to 20MHz) ♦ Excellent Power-Supply Noise Rejection ♦ No External Loop Filter Capacitor Required Applications Ordering Information Ethernet Networking Equipment PART Fibre Channel Storage Area Network TEMP RANGE PIN-PACKAGE 0°C to +70°C 24 TSSOP MAX3625ACUG+ +Denotes a lead(Pb)-free/RoHS-compliant package. Pin Configuration and Typical Application Circuit appear at end of data sheet. Block Diagram MR IN_SEL BYPASS SELA[1:0] QA_OE SELA[1:0] SELB[1:0] FB_SEL BYPASS RESET LOGIC/POR RESET DIVIDER NA LVPECL BUFFER QA QA RESET 0 LVCMOS 0 REF_IN 620MHz TO 648MHz PFD 27pF 1 X_IN FILTER VCO 1 RESET RESET CRYSTAL OSCILLATOR DIVIDER M X_OUT LVPECL BUFFER DIVIDER NB QB1 QB1 QB_OE 33pF DIVIDERS: M = 24, 25 NA = 10, 2, 4, 5 NB = 10, 2, 4, 5 LVPECL BUFFER MAX3625A FB_SEL QB0 QB0 SELB[1:0] ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3625A General Description MAX3625A Low-Jitter, Precision Clock Generator with Three Outputs ABSOLUTE MAXIMUM RATINGS Supply Voltage Range VCC, VCCA, VCCO_A, VCCO_B ..............................................-0.3V to +4.0V Voltage Range at REF_IN, IN_SEL, FB_SEL, SELA[1:0], SELB[1:0], QA_OE, QB_OE, MR, BYPASS ..............-0.3V to (VCC + 0.3V) Voltage Range at X_IN Pin ...................................-0.3V to +1.2V Voltage Range at X_OUT Pin ......................-0.3V to (VCC - 0.6V) Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA Continuous Power Dissipation (TA = +70°C) 24-Pin TSSOP (derate 13.9mW/°C above +70°C) .....1111mW Operating Junction Temperature Range ...........-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER Power-Supply Current (Note 4) SYMBOL ICC TYP MAX IN_SEL = high CONDITIONS MIN 72 98 IN_SEL = low 74 UNITS mA CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR, BYPASS Pins) Input Capacitance Input Pulldown Resistor Input Logic Bias Resistor Input Pullup Resistor CIN 2 pF 75 k Pins SELA[1:0], SELB[1:0] 50 k Pins QA_OE, QB_OE, IN_SEL, BYPASS 75 k RPULLDOWN Pins MR, FB_SEL RBIAS RPULLUP LVPECL OUTPUTS (QA, QA, QB0, QB0, QB1, QB1 Pins) Output High Voltage VOH VCC 1.13 VCC 0.98 VCC 0.83 V Output Low Voltage VOL VCC 1.85 VCC 1.7 VCC 1.55 V Peak-to-Peak Output-Voltage Swing (Single-Ended) (Note 2) 0.6 0.72 0.9 VP-P Clock Output Rise/Fall Time 20% to 80% (Note 2) 200 350 600 ps PLL enabled 48 50 52 PLL bypassed (Note 5) 45 50 55 Output Duty-Cycle Distortion % LVCMOS/LVTTL INPUTS (SELA[1:0], SELB[1:0], FB_SEL, IN_SEL, QA_OE, QB_OE, MR, BYPASS Pins) Input-Voltage High VIH Input-Voltage Low VIL Input High Current I IH VIN = VCC Input Low Current I IL VIN = 0V 2 2.0 -80 _______________________________________________________________________________________ V 0.8 V 80 μA μA Low-Jitter, Precision Clock Generator with Three Outputs (VCC = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Notes 1, 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REF_IN SPECIFICATIONS (Input DC- or AC-Coupled) PLL enabled Reference Clock Frequency 24.8 27.0 PLL bypassed Input-Voltage High VIH Input-Voltage Low VIL Input High Current I IH Input Low Current I IL Reference Clock Duty Cycle 320 2.0 V VIN = VCC VIN = 0V PLL enabled 0.8 V 240 μA -240 μA 30 Input Capacitance MHz 70 2.5 % pF CLOCK OUTPUT AC SPECIFICATIONS VCO Frequency Range 620 648 0.36 1.875MHz to 20MHz 0.14 Deterministic Jitter Induced by Power-Supply Noise (Notes 6, 7, and 8) 5.6 psP-P Spurs Induced by Power-Supply Noise (Notes 6, 8, and 9) -54 dBc -70 dBc 5 ps Random Jitter (Note 6) RJRMS Nonharmonic and Subharmonic Spurs Output Skew Between any output pair Clock Output SSB Phase Noise at 125MHz (Note 10) f = 1kHz -124 f = 10kHz -127 f = 100kHz -131 f = 1MHz -145 f > 10MHz -153 1.0 MHz 12kHz to 20MHz psRMS dBc/Hz A series resistor of up to 10.5Ω is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V ±5%. See Figure 1. Note 2: LVPECL outputs guaranteed up to 320MHz. Note 3: Measured using setup shown in Figure 1. Note 4: All outputs enabled and unloaded. Note 5: Measured with a crystal (see Table 4) or an AC-coupled, 50% duty-cycle signal on REF_IN. Note 6: Measured with crystal source, see Table 4. Note 7: Measured with Agilent DSO81304A 40GS/s real-time oscilloscope. Note 8: Measured with 40mVP-P, 100kHz sinusoidal signal on the supply. Note 9: Measured at 156.25MHz output. Note 10: Measured with 25MHz crystal or 25MHz reference clock at REF_IN with a slew rate of 0.5V/ns or greater. Note 1: _______________________________________________________________________________________ 3 MAX3625A ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Typical values are at VCC = +3.3V, TA = +25°C, crystal frequency = 25MHz.) SUPPLY CURRENT vs. TEMPERATURE MAX3625A toc02 ALL OUTPUTS ACTIVE AND TERMINATED 175 150 125 100 NOISE POWER DENSITY (dBc/Hz) AMPLITUDE (200mv/div) 200 ALL OUTPUTS ACTIVE AND UNTERMINATED 75 50 -90 -100 -110 -120 -130 -140 25 -150 0 -160 0 10 20 30 40 50 60 70 0.1 1ns/div PHASE NOISE AT 156.25MHz CLOCK FREQUENCY PHASE NOISE AT 125MHz CLOCK FREQUENCY 10 100 -100 -110 -120 -130 -140 JITTER HISTOGRAM (312.5MHz OUTPUT, 40mVP-P SUPPLY NOISE AT 100kHz) MAX3625A toc05 -90 -100 DJ = 5.6psP-P -110 -120 -130 -140 -150 -150 DJ + RJ = 14psP-P -160 -160 0.1 1 10 100 1000 10,000 100,000 0.1 OFFSET FREQUENCY (kHz) 1 10 100 1000 10,000 100,000 5ps/div OFFSET FREQUENCY (kHz) 0 fC = 312.5MHz NOISE AMPLITUDE = 40mVP-P -10 SPUR POWER (dBc) -20 MAX3625A toc07 SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY -30 -40 -50 -60 -70 -80 -90 10 100 1000 10,000 NOISE FREQUENCY (kHz) 4 1000 10,000 100,000 MAX3625A toc06 -80 NOISE POWER DENSITY (dBc/Hz) MAX3625A toc04 -90 1 OFFSET FREQUENCY (kHz) AMBIENT TEMPERATURE (°C) -80 MAX3625A toc03 -80 MAX3625A toc01 225 SUPPLY CURRENT (mA) PHASE NOISE AT 312.5MHz CLOCK FREQUENCY DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz 250 NOISE POWER DENSITY (dBc/Hz) MAX3625A Low-Jitter, Precision Clock Generator with Three Outputs _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Three Outputs PIN NAME 1, 24 SELB0, SELB1 LVCMOS/LVTTL Inputs. Control NB divider setting. Has 50k input impedance. See Table 2 for more information. FUNCTION 2 BYPASS LVCMOS/LVTTL Input (Active Low). Connect low to bypass the internal PLL. Connect high or leave open for normal operation. When in bypass mode the output dividers are set to divide by 1. Has internal 75k pullup to VCC. 3 MR 4 VCCO_A 5 QA Noninverting Clock Output, LVPECL 6 QA Inverting Clock Output, LVPECL 7 QB_OE LVCMOS/LVTTL Input. Enables/disables QB clock outputs. Connect pin high or leave open to enable LVPECL clock outputs QB0 and QB1. Connect low to set QB0 and QB1 to a logic 0. Has internal 75k pullup to VCC. 8 QA_OE LVCMOS/LVTTL Input. Enables/disables the QA clock output. Connect this pin high or leave open to enable the LVPECL clock output QA. Connect low to set QA to a logic 0. Has internal 75k pullup to VCC. 9 FB_SEL LVCMOS/LVTTL Input. Controls M divider setting. See Table 3 for more information. Has internal 75k pulldown to GND. 10 VCCA 11 VCC 12, 13 SELA0, SELA1 LVCMOS/LVTTL Input. Master reset input. Pulse high for > 1μs to reset all dividers. Has internal 75k pulldown to GND. Not required for normal operation. Power Supply for QA Clock Output. Connect to +3.3V. Analog Power Supply for the VCO. Connect to +3.3V. For additional power-supply noise filtering, this pin can connect to VCC through 10.5 as shown in Figure 1 (requires VCC = 3.3V ±5%). Core Power Supply. Connect to +3.3V. 14 GND 15 X_OUT LVCMOS/LVTTL Inputs. Control NA divider setting. See Table 2 for more information. 50k input impedance. Supply Ground Crystal Oscillator Output 16 X_IN 17 REF_IN Crystal Oscillator Input LVCMOS Reference Clock Input. Self-biased to allow AC- or DC-coupling. 18 IN_SEL LVCMOS/LVTTL Input. Connect high or leave open to use a crystal. Connect low to use REF_IN. Has internal 75k pullup to VCC. 19 QB1 LVPECL, Inverting Clock Output 20 QB1 LVPECL, Noninverting Clock Output 21 QB0 LVPECL, Inverting Clock Output 22 QB0 23 VCCO_B LVPECL, Noninverting Clock Output Power Supply for QB0 and QB1 Clock Output. Connect to +3.3V. _______________________________________________________________________________________ 5 MAX3625A Pin Description MAX3625A Low-Jitter, Precision Clock Generator with Three Outputs Detailed Description The MAX3625A is a low-jitter clock generator designed to operate at Ethernet and Fibre Channel frequencies. It consists of an on-chip crystal oscillator, PLL, programmable dividers, and LVPECL output buffers. Using a low-frequency clock (crystal or CMOS input) as a reference, the internal PLL generates a high-frequency output clock with excellent jitter performance. Crystal Oscillator An integrated oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between X_IN and X_OUT. The crystal frequency is 24.8MHz to 27MHz. Applications Information Power-Supply Filtering The MAX3625A is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. In addition to excellent on-chip power-supply noise rejection, the MAX3625A provides a separate powersupply pin, VCCA, for the VCO circuitry. Figure 1 illustrates the recommended power-supply filter network for V CCA . The purpose of this design technique is to ensure a clean power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is +3.3V ±5%. Decoupling capacitors should be used on all supply pins for best performance. REF_IN Buffer An LVCMOS-compatible clock source can be connected to REF_IN to serve as the reference clock. The LVCMOS REF_IN buffer is internally biased to the threshold voltage (1.4V typ) to allow AC- or DC-coupling, and is designed to operate up to 320MHz. PLL The PLL takes the signal from the crystal oscillator or reference clock input and synthesizes a low-jitter, highfrequency clock. The PLL contains a phase-frequency detector (PFD), a lowpass filter, and a voltage-controlled oscillator (VCO) with a 620MHz to 648MHz operating range. The VCO is connected to the PFD input through a feedback divider. See Table 3 for divider values. The PFD compares the reference frequency to the divided-down VCO output (fVCO/M) and generates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO output clock is sent to the output dividers. To minimize noise-induced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies. Output Dividers The output dividers are programmable to allow a range of output frequencies. See Table 2 for the divider input settings. The output dividers are automatically set to divide by 1 when the MAX3625A is in bypass mode (BYPASS = 0). Output Divider Configuration Table 2 shows the input settings required to set the output dividers. Note that when the MAX3625A is in bypass mode (BYPASS set low), the output dividers are automatically set to divide by 1. PLL Divider Configuration Table 3 shows the input settings required to set the PLL feedback divider. Crystal Selection The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 4 for recommended crystal specifications. See Figure 3 for external capacitance connection. Crystal Input Layout The crystal, trace, and two external capacitors should be placed on the board as close as possible to the MAX3625A’s X_IN and X_OUT pins to reduce crosstalk of active signals into the oscillator. The example layout shown in Figure 2 gives approximately 3pF of trace plus footprint capacitance per side of the crystal. The dielectric material is FR-4 and dielectric thickness of the reference board is 15 mils. Using a 25MHz crystal and the capacitor values of C10 = 27pF and C9 = 33pF, the measured output frequency accuracy is -14ppm at +25°C ambient temperature. LVPECL Drivers The high-frequency outputs—QA, QB0, and QB1—are differential PECL buffers designed to drive transmission lines terminated with 50Ω to VCC - 2.0V. The maximum operating frequency is specified up to 320MHz. The outputs can be disabled, if not used. The outputs go to a logic 0 when disabled. +3.3V ±5% VCC 0.01μF 10.5Ω VCCA Reset Logic/POR During power-on, a power-on reset (POR) signal is generated to synchronize all dividers. An external master reset (MR) signal is not required. 6 0.01μF Figure 1. Analog Supply Filtering _______________________________________________________________________________________ 10μF Low-Jitter, Precision Clock Generator with Three Outputs MAX3625A Table 1. Output Frequency Determination CRYSTAL OR CMOS INPUT FREQUENCY (MHz) VCO FREQUENCY (MHz) FEEDBACK DIVIDER, M 25 25 625 25.78125 25 644.53125 26.04166 24 26.5625 625 24 637.5 OUTPUT DIVIDER, NA AND NB OUTPUT FREQUENCY (MHz) 2 312.5 4 156.25 5 125 Ethernet 10 62.5 4 161.132812 2 312.5 4 156.25 5 125 10 62.5 2 318.75 4 159.375 APPLICATIONS 10Gbps Ethernet Ethernet 10G Fibre Channel Table 2. Output Divider Configuration INPUT NA/NB DIVIDER SELA1/SELB1 SELA0/SELB0 0 0 /10 0 1 /2 1 0 /4 1 1 /5 Table 3. PLL Divider Configuration FB_SEL INPUT M DIVIDER 0 /25 1 /24 Figure 2. Crystal Layout Table 4. Crystal Selection Parameters PARAMETER SYMBOL MIN Crystal Oscillation Frequency f OSC 24.8 Shunt Capacitance CO 2.0 Load Capacitance CL 18 Equivalent Series Resistance (ESR) RS Maximum Crystal Drive Level TYP MAX UNITS 27 MHz 7.0 pF 27pF X_IN CRYSTAL (CL = 18pF) X_OUT pF 50 300 μW 33pF Figure 3. Crystal, Capacitors Connection _______________________________________________________________________________________ 7 MAX3625A Low-Jitter, Precision Clock Generator with Three Outputs +3.3V VCC VB = 1.4V 130Ω 130Ω VCC MAX3625A Qx Z0 = 50Ω Qx Z0 = 50Ω HIGH IMPEDANCE 82Ω 82Ω VB 14.5kΩ VB REF_IN Figure 4. Thevenin Equivalent of Standard PECL Termination ESD STRUCTURES 0.1μF Z0 = 50Ω Qx 100Ω MAX3625A 0.1μF Figure 6. Simplified REF_IN Pin Circuit Schematic HIGH IMPEDANCE Z0 = 50Ω Qx 150Ω VCC 150Ω NOTE: AC-COUPLING IS OPTIONAL. Qx Figure 5. AC-Coupled PECL Termination Qx Interfacing with LVPECL Outputs The equivalent LVPECL output circuit is given in Figure 7. These outputs are designed to drive a pair of 50Ω transmission lines terminated with 50Ω to VTT = VCC - 2V. If a separate termination voltage (VTT) is not available, other terminations methods can be used such as shown in Figures 4 and 5. Unused outputs should be disabled and may be left open. For more information on LVPECL terminations and how to interface with other logic families, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML. ESD STRUCTURES Figure 7. Simplified LVPECL Output Circuit Schematic Interface Models Figures 6 and 7 show examples of interface models. 8 _______________________________________________________________________________________ Low-Jitter, Precision Clock Generator with Three Outputs Pin Configuration TOP VIEW SELB0 1 24 SELB1 BYPASS 2 23 VCCO_B MR 3 22 QB0 VCCO_A 4 21 QB0 QA 5 20 QB1 19 QB1 QA 6 QB_OE 7 MAX3625A 18 IN_SEL QA_OE 8 17 REF_IN FB_SEL 9 16 X_IN VCCA 10 15 X_OUT VCC 11 14 GND SELA0 12 13 SELA1 TSSOP Chip Information TRANSISTOR COUNT: 10,840 PROCESS: BiCMOS _______________________________________________________________________________________ 9 MAX3625A Layout Considerations The inputs and outputs are critical paths for the MAX3625A, and care should be taken to minimize discontinuities on these transmission lines. Here are some suggestions for maximizing the MAX3625A’s performance: • An uninterrupted ground plane should be positioned beneath the clock I/Os. • Supply and ground pin vias should be placed close to the IC and the input/output interfaces to allow a return current path to the MAX3625A and the receive devices. • Supply decoupling capacitors should be placed close to the MAX3625A supply pins. • Maintain 100Ω differential (or 50Ω single-ended) transmission line impedance out of the MAX3625A. • Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3625A Evaluation Kit for more information. MAX3625A Low-Jitter, Precision Clock Generator with Three Outputs Typical Application Circuit +3.3V ±5% 0.01μF 10.5Ω VCC 10μF VCCO_A 0.1μF VCCO_B 0.1μF VCCA QA Z0 = 50Ω REF_IN QA Z0 = 50Ω ASIC 0.01μF 312.5MHz 150Ω IN_SEL 0.1μF FB_SEL QA_OE VCC 0.1μF 150Ω Z0 = 50Ω QB0 Z0 = 50Ω ASIC MAX3625A QB_OE QB0 156.25MHz 150Ω BYPASS 0.1μF 150Ω SELA0 SELB1 0.1μF SELB0 SELA1 QB1 Z0 = 50Ω QB1 Z0 = 50Ω ASIC MR X_OUT X_IN 156.25MHz GND 150Ω 0.1μF 150Ω 26.0416MHz (CL = 18pF) 33pF 27pF Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 24 TSSOP U24-1 21-0066 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.