19-1314; Rev 3; 9/04 KIT ATION EVALU E L B A AVAIL +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector Features The MAX3969 is a recommended upgrade for the MAX3964, MAX3965, and MAX3968. The MAX3964A limiting amplifier, with 2mVP-P input sensitivity and PECL data outputs, is ideal for low-cost ATM, FDDI, and Fast Ethernet fiber optic applications. The MAX3964A features an integrated power detector that senses the input-signal power. It provides a received-signal-strength indicator (RSSI), which is an analog indication of the power level and complementary PECL loss-of-signal (LOS) outputs, which indicate when the power level drops below a programmable threshold. The threshold can be adjusted to detect signal amplitudes as low as 2.7mVP-P. An optional squelch function disables switching of the data outputs by holding them at a known state during an LOS condition. The MAX3965 provides the same functionality, but offers TTL-compatible LOS outputs. The MAX3968 provides the same functionality as the MAX3964A, but has data-output edge speed suitable for ESCON and 266Mbps fibre channel applications. The MAX3964A/MAX3965/MAX3968 are available in die form, as tested wafers, and in 20-pin QSOP packages. The MAX3964AETP is available in a 20-pin thin QFN package. ♦ Single Supply: +3.0V to +5.5V ♦ 2mVP-P Input Sensitivity ♦ 1.2ns Output Edge Speed ♦ Loss-of-Signal Detector with Programmable Threshold ♦ Analog Received-Signal-Strength Indicator ♦ Output Squelch Function ♦ Choice of TTL or PECL LOS Outputs ♦ Compatible with 4B/5B Data Coding Ordering Information PART TEMP RANGE 0oC to +70oC 20 QSOP MAX3964C/D 0oC to +70oC Dice* MAX3964C/DW 0oC to +70oC Wafers* MAX3964AETP -40oC to +85oC o MAX3964AC/D Applications 125Mbps FDDI Receivers 155Mbps LAN ATM Receivers Fast Ethernet Receivers ESCON Receivers 155Mbps FTTx Receivers PIN-PACKAGE MAX3964CEP 20 Thin QFN** o -40 C to +85 C Dice* MAX3965CEP 0oC to +70oC 20 QSOP MAX3965C/D 0oC to +70oC Dice* o o MAX3965C/DW 0 C to +70 C Wafers* MAX3968CEP 0oC to +70oC 20 QSOP MAX3968C/D 0oC to +70oC Dice* o MAX3968C/DW o 0 C to +70 C Wafers* *Dice and wafers are designed to operate over a 0°C to +100°C junction temperature (Tj) range, but are tested and guaranteed only at TA = +25°C. Pin Configurations appear at end of data sheet. Selector Guide appears at end of data sheet. **Package Code: T2044-1 Typical Operating Circuit CAZ 27nF VCC 10nF FILTER 10nF VCC CZP VCC LOS TERMINATIONS ARE USED ONLY FOR THE MAX3964 AND MAX3968 CZN RSSI FILTER SQUELCH VCC0 VCC VCC CIN 10nF PHOTODIODE 155Mbps TIA OUTOUT+ LOS+ IN- MAX3964A LOSMAX3965 MAX3968 OUT- IN+ OUT+ CIN 10nF IN GND (MAX3965 ONLY) R1 ≥100k SUB* GND VTH GNDO INV R2 50Ω 50Ω 50Ω 50Ω VCC - 2V *PIN NOT AVAILABLE ON MAX3964AETP. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3964A/MAX3965/MAX3968 General Description MAX3964A/MAX3965/MAX3968 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector ABSOLUTE MAXIMUM RATINGS (SUB, GND, GNDO tied to ground) VCC, VCCO.............................................................-0.5V to +7.0V FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH, LOS+, LOS-, INV, VTH, OUT+, OUT- ......-0.5V to (VCC + 0.5V) PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA Differential Voltage Between CZP and CZN..........-1.5V to +1.5V Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V Continuous Power Dissipation (TA = +70°C) 20-Lead Thin QFN (derate 16.9mW/°C above +70°C) ..........................1349mW 20-Pin QSOP (derate 6.7mW/°C above +70°C)...........500mW Operating Temperature Range ...........................-40°C to +85°C Operating Junction Temperature Range (die) .....-40°C to +150°C Processing Temperature (die) ........................................+400°C Storage Temperature Range .......................... -65°C to +160°C Lead Temperature (soldering, 10s) ................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX3964ACEP/MAX3965CEP/MAX3968CEP (VCC = +3.0V to +5.5V, PECL outputs terminated with 50Ω to (VCC - 2V), TA = 0°C to +70°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25°C.) (Note 1) PARAMETER Supply Current SYMBOL ICC LOS Hysteresis CONDITIONS MIN PECL outputs open Input = 3.3mVP-P to 90mVP-P (Note 2) 3.8 TYP MAX UNITS 22 40 mA 5 8.0 dB SQUELCH Input Current VSQUELCH = VCC, TA = +25°C 100 µA PECL Output Voltage High (Note 3) -1025 27 -880 mV PECL Output Voltage Low (Note 3) -1810 -1620 mV PECL LOS Output Voltage High (Note 3) -1035 -880 mV PECL LOS Output Voltage Low (Note 3) -1810 -1620 mV LOS Assert Accuracy Input = 7mVP-P or 90mVP-P -2.5 +2.5 dB 2.7 mVP-P Minimum LOS Assert Input Maximum LOS Deassert Input 143 Input Sensitivity Input Overload Output Transition Time mVP-P 2.0 3.3 1.5 tr, tf mVP-P VP-P 20% to 80% transition time, MAX3964A/MAX3965 0.92 1.2 MAX3968 0.4 0.8 1.2 50 200 ps 2.20 ns Pulse-Width Distortion (Note 4) TTL Output High IOH = -200µA 2.4 3.1 VCC V TTL Output Low IOL = 200µA 0 0.3 0.4 V 2 _______________________________________________________________________________________ +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964A/MAX3965/MAX3968 ELECTRICAL CHARACTERISTICS—MAX3964AETP (VCC = +3.0V to +5.5V, PECL outputs terminated with 50Ω to (VCC - 2V), TA = -40°C to +85°C. Typical values measured at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Supply Current ICC CONDITIONS MIN PECL outputs open LOS Hysteresis Input = 4.0mVP-P (Note 2) TYP MAX UNITS 22 45 mA 5 8.0 dB 3.0 SQUELCH Input Current 100 µA PECL Output Voltage High (Note 3) -1.085 27 -0.880 V PECL Output Voltage Low (Note 3) -1.830 -1.550 V LOS Assert Accuracy Input = 7mVP-P or 90mVP-P, 0°C to +85°C -3 +3 Input = 7mVP-P or 90mVP-P, -40°C to 0°C -3.6 +3.6 Minimum LOS Assert Input 2.7 Maximum LOS Deassert Input mVP-P 143 mVP-P Input Sensitivity 2 4 20% to 80% 1.6 2.4 ns (Note 4) 50 250 psP-P Input Overload mVP-P 1.5 Output Transition Time tr, tf Pulse-Width Distortion Note 1: Note 2: Note 3: Note 4: dB VP-P Dice are tested and guaranteed at TA = +25°C only. LOS hysteresis = 20log(VLOS-DEASSERT / VLOS-ASSERT). Voltage measurements are relative to supply voltage (VCC). PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern. Typical Operating Characteristics (MAX3964A EV kit, VCC = +3.3V, decibels (dB) calculated as 20 log ∆V, PECL outputs terminated with 50Ω to (VCC - 2V), TA = +25°C, unless otherwise noted.) RSSI VOLTAGE vs. INPUT AMPLITUDE 2.2 2.00 80 2.0 1.9 1.50 1.7 1.00 50 INPUT = 5mV 40 30 1.5 100 INPUT AMPLITUDE (mV) 60 INPUT = 10mV 1.6 10 70 1.8 LOS ASSERTED 1 90 PWD (ps) VRSSI (V) VRSSI (V) INPUT = 100mV 2.1 LOS DEASSERTED 100 MAX3964/65toc03 2.50 2.3 MAX3964/65toc02 INPUT PATTERN IS 223 - 1 PRBS MAX3964/65toc01 3.00 PULSE-WIDTH DISTORTION vs. INPUT AMPLITUDE RSSI VOLTAGE vs. TEMPERATURE 1k -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 1 10 100 1k 10k INPUT AMPLITUDE (mVP-P) _______________________________________________________________________________________ 3 Typical Operating Characteristics (continued) (MAX3964A EV kit, VCC = +3.3V, decibels (dB) calculated as 20 log ∆V, PECL outputs terminated with 50Ω to (VCC - 2V), TA = +25°C, unless otherwise noted.) OUTPUT AMPLITUDE vs. INPUT VOLTAGE (DIFFERENTIAL SIGNAL LEVELS) DATA OUTPUT EDGE SPEED (20% to 80%) vs. TEMPERATURE OUTPUT AMPLITUDE (mV) 2.4 MAX3964A/MAX3965 1.8 1.2 MAX3968 MAX3964/65toc05 1600 MAX3964/65toc04 3.0 EDGE SPEED (ns) 1400 1200 1000 800 0.6 0 600 -50 -25 0 25 50 75 100 0.1 TEMPERATURE (°C) 1 10 100 MAX3964 toc07 200mV/div DATA OUTPUT LOS+ 10µs/div 4 10k MAX3964A/MAX3965 EYE DIAGRAM (INPUT = 3.3mV) LOS OPERATION WITH SQUELCH DATA INPUT 1k INPUT VOLTAGE (mV) MAX3964 toc06 MAX3964A/MAX3965/MAX3968 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector 1ns/div _______________________________________________________________________________________ +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector PIN THIN QFN NAME QSOP 1 19 SQUELCH 2 20 VTH Output of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a resistor from VTH to INV and from INV to ground (minimum resistance 100kΩ) to program the desired threshold voltage. 3 1 INV Inverting Input of Internal Op Amp that Sets Loss-of-Signal Threshold Voltage (Figure 1). Connect a resistor from VTH to INV and from INV to ground (minimum resistance 100kΩ) to program the desired threshold voltage. 4 2 FILTER 5 3 RSSI 6 4 IN- Inverting Data Input 7 5 IN+ Noninverting Data Input 8 — SUB Substrate. Connect to ground. 9, 10 6, 7, 8 GND Ground 11 9 CZP Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offsetcorrection-loop bandwidth. 12 10 CZN Auto-Zero Capacitor Input. Connect a capacitor between CZP and CZN to determine the offsetcorrection-loop bandwidth. 13 11 VCCO Output Buffer Supply Voltage. Connect to the same potential as VCC, but filter VCCO and VCC separately. 14 12 OUT+ Noninverting PECL Data Output. Terminate with 50Ω to (VCC - 2V). 15 13 OUT- Inverting PECL Data Output. Terminate with 50Ω to (VCC - 2V). LOS- Inverting Loss-of-Signal Output. LOS- is asserted low when input power drops below the LOS threshold. For the MAX3964A/MAX3968, this pin is PECL compatible and should be terminated with 50Ω to (VCC - 2V). For the MAX3965, this output is TTL compatible and does not require termination. LOS+ Noninverting Loss-of-Signal Output. LOS+ is asserted high when input power drops below the LOS threshold. For the MAX3964A/MAX3968, this pin is PECL compatible and should be terminated with 50Ω to (VCC - 2V). For the MAX3965, this output is TTL compatible and does not require termination. VCCO MAX3964A/MAX3968: This pin can be left open or connected to the positive supply. GNDO MAX3965: This pin must be connected to ground. 16 14 17 15 18 16 19, 20 — 17, 18 VCC EP Exposed Pad FUNCTION Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high during a loss-of-signal condition. Connect to GND or leave unconnected to disable. Connect to VCC to enable squelching. Filter Output of Full-Wave Logarithmic Detectors (FWDs). The FWD outputs are summed together at FILTER to generate the received-signal-strength indicator (RSSI). Connect a capacitor from FILTER to VCC for proper operation. Received-Signal-Strength Indicator Output. The analog DC voltage at RSSI indicates the input signal power. The RSSI output is reduced approximately 120mV when LOS+ is asserted. +3.0V to +5.5V Supply Voltage Connect the exposed pad to board ground for optional electrical and thermal performance. _______________________________________________________________________________________ 5 MAX3964A/MAX3965/MAX3968 Pin Description MAX3964A/MAX3965/MAX3968 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector CAZ VCC CZP VCCO CZN OFFSET CORRECTION LIMITER LIMITER LIMITER I LIMITER I OUT+/OUT- O IN+/IN- SQUELCH LOS+ FWD FWD FWD FWD RSSI FILTER LOS+/LOSCFILTER MAX3964A MAX3965 MAX3968 VCC 1.2V REFERENCE LOS COMPARATOR VTR INV SUB R1 R2 GND GNDO (MAX3965 ONLY) FWD = FULL-WAVE DETECTOR Figure 1. Functional Diagram Detailed Description The MAX3964A contains a series of limiting amplifiers and power detectors, offset correction, data-squelch circuitry, and PECL output buffers for data and loss-ofsignal (LOS) outputs. The MAX3965 is functionally the same, but it provides TTL buffers on the LOS outputs. The MAX3968 provides PECL LOS outputs with data outputs suitable for 266Mbps. Figure 1 shows a functional diagram of the MAX3964A/MAX3965/MAX3968. This relation translates to a 25mV increase in VRSSI for every 1dB increase in VIN (25mV/dB). The RSSI output is reduced approximately 120mV when LOS+ is asserted. PECL Outputs The data outputs (OUT+, OUT-) and the MAX3964A/ MAX3968 loss-of-signal outputs (LOS+, LOS-) are supply-referenced PECL outputs. Standard PECL termination at each output of 50Ω to (VCC - 2V) is recommended for best performance. Limiting Amplifiers TTL Outputs A series of four limiting amplifiers provides gain of approximately 65dB. The MAX3965 LOS outputs (LOS+, LOS-) are implemented with open-collector Schottky-clamped TTLcompatible outputs. The LOS outputs are pulled to VCC internally with 2kΩ resistors and do not require external pullup resistors. Power Detector Each amplifier stage contains a full-wave logarithmic detector (FWD), which indicates the RMS input signal power. The FWD outputs are summed together at the FILTER pin where the signal is filtered by an external capacitor (CFILTER) connected between FILTER and VCC. The FILTER signal generates the RSSI output voltage, which is proportional to the input power in decibels. When LOS+ is low, VRSSI is approximated by the following equation: VRSSI (V) = 1.2V + 0.5log (VIN) where VIN is measured in mVP-P. 6 Input Offset Correction A low-frequency feedback loop around the limiting amplifier improves receiver sensitivity and powerdetector accuracy. The offset-correction loop’s bandwidth is determined by an external capacitor (CAZ) connected between the CZP and CZN pins. The offset correction is optimized for data streams with a 50% duty cycle. A different average duty cycle results in increased pulse-width distortion and loss of _______________________________________________________________________________________ +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector Loss-of-Signal Comparator The LOS comparator indicates when the input signal power is below the programmed LOS threshold. To ensure supply and temperature independence, VTH is generated by a 1.2V bandgap reference. The op amp’s external gain-setting resistors (R1 and R2) can be chosen to set VTH between 1.2V and 2.4V. To ensure chatter-free operation, the LOS comparator is designed with approximately 5dB of hysteresis. Squelch The squelch function disables the data outputs by forcing OUT- low and OUT+ high during a LOS condition. This function ensures that when there is a loss of signal, the limiting amplifier (and all downstream devices) does not respond to input noise or corrupt data. Connect SQUELCH to GND or leave it unconnected to disable squelch. Connect SQUELCH to VCC to enable data squelching. Applications Information Program the LOS Threshold Figure 2 provides information for selecting the LOS threshold voltage (V TH ). If R1 is 100kΩ and if the responsivities of the photodiode and preamplifier are known, then the value of R2 can be selected from Figure 2 to provide LOS assert at the desired input power. Select Capacitors A typical MAX3964A/MAX3965/MAX3968 implementation requires four external capacitors (CAZ, CFILTER, and two input coupling capacitors). For all applications up to 266Mbps, Maxim recommends the following: CAZ = 27nF CFILTER = 10nF CIN = 10nF Wire Bonding For high-current density and reliable operation, the MAX3964A series uses gold metalization. Diepad size is 4mils square with a 6mil pitch. Die thickness is 15mils. Selector Guide 120 PART 200kV/W VALUE OF R2 (kΩ) 100 80 LOS OUTPUTS 125 to 155 PECL MAX3965 125 to 155 MAX3968 125 to 266 TTL PECL *The MAX3964A is functionally equivalent to MAX3964, but offers slightly improved ESD tolerance. The MAX3969 is a recommended upgrade for the MAX3964, MAX3964A, MAX3965, and MAX3968. 100kV/W 60 DATA RATE (Mbps) MAX3964A* 30kV/W 20kV/W 40 15kV/W 20 10kV/W 0 -40 -38 -36 -34 -32 -30 -28 -26 OPTICAL INPUT POWER AT LOS ASSERT (dBm) Figure 2. LOS Assert Programming Resistor vs. LOS Assert Power (for Various PIN-TIA Gains ) _______________________________________________________________________________________ 7 MAX3964A/MAX3965/MAX3968 sensitivity. The offset-correction circuitry is less sensitive to variations of input duty cycle (for example, the 40% to 60% duty cycle encountered in 4B/5B coding) when the input is less than 30mVP-P. +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964A/MAX3965/MAX3968 Pin Configurations TOP VIEW SQUELCH 1 20 VCC SQUELCH 1 20 VCC 2 19 VCC VTH 2 19 VCC VTH INV 3 FILTER 4 RSSI 5 MAX3964A MAX3968 IN- 6 18 VCCO INV 3 18 GNDO 17 LOS+ FILTER 4 17 LOS+ 16 LOS- RSSI 5 MAX3965 16 LOS- 15 OUT- IN- 6 15 OUT14 OUT+ IN+ 7 14 OUT+ IN+ 7 SUB 8 13 VCCO SUB 8 13 VCCO GND 9 12 CZN GND 9 12 CZN 11 CZP GND 10 11 CZP GND 10 QSOP VTH SQUELCH VCC VCC VCCO 19 18 17 16 TOP VIEW 20 QSOP INV 1 15 LOS+ FILTER 2 14 LOS- RSSI 3 13 OUT- IN- 4 12 OUT+ IN+ 5 11 VCCO 7 8 9 10 GND GND CZP CZN GND 6 MAX3964AETP THIN QFN 8 _______________________________________________________________________________________ +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector MAX3964A MAX3968 SQUELCH VTH VCC VCC MAX3965 VCC0 VTH LOS+ INV FILTER LOS- RSSI OUT- IN- OUT+ IN+ SQUELCH VCC V CC GNDO LOS+ INV 0.047" (1.19mm) FILTER LOS- RSSI OUTINOUT+ IN+ VCCO VCCO SUB GND GND CZP CZN 0.057" (1.45mm) 0.047" (1.19mm) SUB GND GND CZP CZN 0.057" (1.45mm) TRANSISTOR COUNT: 915 SUBSTRATE CONNECTED TO SUB SUB CONNECTED TO GND ON MAX3964AETP _______________________________________________________________________________________ 9 MAX3964A/MAX3965/MAX3968 Chip Topographies Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QSOP.EPS MAX3964A/MAX3965/MAX3968 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH 21-0055 10 ______________________________________________________________________________________ E 1 1 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector 24L QFN THIN.EPS PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 1 2 ______________________________________________________________________________________ 11 MAX3964A/MAX3965/MAX3968 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3964A/MAX3965/MAX3968 +3.0V to +5.5V, 125Mbps to 266Mbps Limiting Amplifiers with Loss-of-Signal Detector Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm 21-0139 C 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.