19-1560; Rev 0; 10/99 +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs Features ♦ +2.7V to +5.5V Single-Supply Operation ♦ Ultra-Low Supply Current 0.3mA while Operating 1µA in Software Shutdown Mode ♦ Ultra-Small 16-Pin TSSOP Package ♦ Output Buffer Amplifiers Swing Rail-to-Rail ♦ Power-On Reset Sets All Registers to Zero Applications Ordering Information Digital Gain and Offset Adjustment PART TEMP. RANGE PINPACKAGE INL (LSB) Portable Instruments MAX5101AEUE -40°C to +85°C 16 TSSOP ±1 Power-Amp Bias Control MAX5101BEUE -40°C to +85°C 16 TSSOP ±2 Programmable Attenuators Pin Configuration Functional Diagram TOP VIEW INPUT LATCH A INPUT LATCH B D0–D7 OUTA DAC A OUTB 1 16 OUTC OUTA 2 15 GND OUTB DAC B VDD 3 WR 4 INPUT LATCH C A0 A1 CONTROL LOGIC OUTC DAC C 14 A0 MAX5101 13 A1 D7 5 12 D0 D6 6 11 D1 D5 7 10 D2 D4 8 9 D3 MAX5101 TSSOP WR Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5101 General Description The MAX5101 parallel-input, voltage-output, triple 8-bit digital-to-analog converter (DAC) operates from a single +2.7V to +5.5V supply and comes in a space-saving 16-pin TSSOP package. Internal precision buffers swing Rail-to-Rail®. For all three DACs, the internal reference voltage is tied to VDD. The MAX5101 has separate input latches for each of its three DACs. Data is transferred to the input latches from a common 8-bit input port. The DACs are individually selected through address inputs A0 and A1 and are updated by bringing WR low. The MAX5101 features a 1µA software shutdown mode, as well as a power-on reset mode that resets all registers to code 00 hex on power-up. MAX5101 +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V D_, A_, WR to GND ..................................................-0.3V to +6V OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 5.7mW/°C above +70°C) ..........457mW Operating Temperature Range MAX5101_EUE .................................................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 8 Bits STATIC ACCURACY Resolution MAX5101A ±1 MAX5101B ±2 Integral Nonlinearity (Note 1) INL Differential Nonlinearity (Note 1) DNL Guaranteed monotonic ±1 LSB Zero-Code Error ZCE Code = 00 hex ±20 mV 10 mV Zero-Code-Error Supply Rejection Code = 00 hex, VDD = 2.7V to 5.5V Zero-Code Temperature Coefficient Code = 00 hex Gain Error (Note 2) Code = F0 hex Gain-Error Temperature Coefficient Code = F0 hex ±10 LSB µV/°C ±1 ±0.001 % LSB/°C DAC OUTPUTS Output Voltage Range RL = ∞ 0 VDD = 2.7V to 3.6V 2 VDD = 3.6V to 5.5V 3 VDD V DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Current IIN Input Capacitance DYNAMIC PERFORMANCE CIN V VIN = VDD or GND 0.8 V ±1.0 µA 10 pF 0.6 V/µs 6 µs Output Voltage Slew Rate From code 00 to code F0 hex Output Settling Time (Note 3) To 1/2LSB, from code 10 to code F0 hex Channel-to-Channel Isolation (Note 4) Code 00 to code FF hex 500 nVs Digital Feedthrough (Note 5) Code 00 to code FF hex 0.5 nVs 2 _______________________________________________________________________________________ +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs (VDD = +2.7V to +5.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and TA = +25°C.) PARAMETER SYMBOL Digital-to-Analog Glitch Impulse CONDITIONS MIN Code 80 hex to code 7F hex Wideband Amplifier Noise TYP MAX UNITS 90 nVs 60 µVRMS Shutdown Recovery Time tSDR To ±1/2LSB of final value of VOUT 13 µs Time to Shutdown tSDN IDD < 5µA 20 µs POWER SUPPLIES Power-Supply Voltage VDD Supply Current (Note 6) IDD 2.7 Shutdown Current 5.5 V 280 520 µA 1 3 µA DIGITAL TIMING (Figure 1) (Note 7) Address to WR Setup tAS 5 ns Address to WR Hold tAH 0 ns Data to WR Setup tDS 25 ns Data to WR Hold tDH 0 ns WR Pulse Width tWR 20 ns Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded. Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VDD]. Where VF0,meas is the DAC output voltage with input code F0 hex, and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VDD · 240 / 256). Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value. Note 4: Channel-to-Channel Isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any other DAC output. The measured channel has a fixed code of 80 hex. Note 5: Digital Feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight data inputs with WR at VDD. Note 6: RL = ∞ , digital inputs at GND or VDD. Note 7: Timing measurement reference level is (VIH + VIL) / 2. _______________________________________________________________________________________ 3 MAX5101 ELECTRICAL CHARACTERISTICS (continued) MAX5101 +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs ADDRESS ADDRESS VALID tWR tAS tAH- WR tDSDATA tDHDATA VALID SEE NOTE 7, ELECTRICAL CHARACTERISTICS Figure 1. Timing Diagram __________________________________________Typical Operating Characteristics (VDD = +3V, RL = 10kΩ, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT (µA) VDD = 3V VOUT (V) VOUT (V) 0.8 0.6 6 VDD = 5V 4 0.4 VDD = 5V VDD = 3V 2 0.2 0 2 4 6 8 10 220 VDD = 3V; CODE = F0 HEX 200 VDD = 5V; CODE = 00 HEX 180 VDD = 3V; CODE = 00 HEX 160 0 0 VDD = 5V; CODE = F0 HEX 240 8 1 DAC AT CODE 00 OR F0 2 DACs AT CODE 00 (RL = ∞) 140 0 SINK CURRENT (mA) 2 4 6 8 10 -40 -20 0 SOURCE CURRENT (mA) DAC CODE FROM 80 TO 7F HEX WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE) MAX5101-04 WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE) 20 DAC CODE FROM 7F TO 80 HEX CH1 CH1 CH2 CH2 2µs/div CH1 = WR, 2V/div CH2 = VOUTA, 50mV/div, AC-COUPLED 4 40 60 TEMPERATURE (°C) MAX5101-05 1.0 SUPPLY CURRENT vs. TEMPERATURE 260 MAX5101-02 10 MAX5101-01 1.2 DAC FULL-SCALE OUTPUT VOLTAGE vs. SOURCE CURRENT MAX5101-03 DAC ZERO-CODE OUTPUT VOLTAGE vs. SINK CURRENT 2µs/div CH1 = WR, 2V/div CH2 = VOUTA, 50mV/div, AC-COUPLED _______________________________________________________________________________________ 80 100 +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs DIGITAL FEEDTHROUGH GLITCH IMPULSE (1 TO 0 DIGITAL TRANSMISSION) CH1 CH1 CH2 CH2 DAC CODE FROM 10 TO F0 HEX MAX5101-08 POSITIVE SETTLING TIME MAX5101-07 MAX5101-06 DIGITAL FEEDTHROUGH GLITCH IMPULSE (0 TO 1 DIGITAL TRANSMISSION) CH1 CH2 0 TO 1 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) 1 TO 0 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) 200ns/div 1µs/div 200ns/div CH1 = D7, 2V/div CH2 = VOUTA, 1mV/div, AC-COUPLED CH1 = WR, 2V/div CH2 = VOUTA, 2V/div CH1 = D7, 2V/div CH2 = VOUTB, 1mV/div, AC-COUPLED 0.5 MAX5101-09 DAC CODE FROM F0 TO 10 HEX MAX5101-10 INTEGRAL AND DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE NEGATIVE SETTLING TIME RL = ∞ 0.4 0.3 INL/DNL (LSB) 0.2 CH1 DNL 0.1 0 -0.1 -0.2 CH2 -0.3 INL -0.4 -0.5 1µs/div CH1 = WR, 2V/div CH2 = VOUTA, 2V/div 0 32 64 96 128 160 192 224 256 DIGITAL CODE _______________________________________________________________________________________ 5 MAX5101 Typical Operating Characteristics (continued) (VDD = +3V, RL = 10kΩ, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.) +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5101 Pin Description PIN NAME FUNCTION 1 OUTB DAC B Voltage Output 2 OUTA DAC A Voltage Output 3 VDD Positive Supply Voltage. Bypass VDD to GND using a 0.1µF capacitor. 4 WR Write Input (active low). Use WR to load data into the DAC input latch selected by A0 and A1. 5–12 D7–D0 13 A1 DAC Address Select Bit (MSB) 14 A0 DAC Address Select Bit (LSB) 15 GND Ground 16 OUTC DAC C Voltage Output Data Inputs 7–0 Detailed Description Digital-to-Analog Section The MAX5101 uses a matrix decoding architecture for the digital-to-analog converters (DACs). The internal reference voltage is connected to VDD and divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor network converts the 8-bit digital input into an equivalent analog output voltage in proportion to the supply voltage (VDD). The resistor string presents a code-independent input impedance to the supply and guarantees a monotonic output. The voltages are buffered by rail-to-rail op amps connected in a follower configuration to provide a rail-to-rail output (see Functional Diagram). Output Buffer Amplifiers The DAC outputs are internally buffered by a precision amplifier with a typical slew rate of 0.6V/µs. The typical settling time to ±1/2LSB at the output is 6µs when loaded with 10kΩ in parallel with 100pF. Digital Inputs and Interface Logic In the MAX5101, address lines A0 and A1 select the DAC that receives data from D0–D7, as shown in Table 1. When WR is low, the addressed DAC’s input latch is transparent. Data is latched when WR is high. The DAC outputs (OUTA, OUTB) represent the data held in the three 8-bit input latches. To avoid output glitches in the MAX5101, ensure that data is valid before WR goes low. Low-Power Shutdown Mode The MAX5101 features a software shutdown mode. A write performed to address A1 = H and A0 = H causes the device to shut down. A subsequent write to any of the other three addresses disables shutdown and turns the analog circuitry on. As the MAX5101 comes out of shutdown, all registers retain their digital values prior to shutdown. However, when the device powers up (i.e., VDD ramps up), all latches are internally preset with code 00 hex. In shutdown, the output amplifiers enter a high-impedance state. When bringing the device out of shutdown, allow 13µs for the output to stabilize. Power-Supply Bypassing and Ground Management The MAX5101’s reference is internally tied to VDD. The output voltage (VOUT) for any DAC is represented by a digitally programmable voltage source as follows: Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1µF capacitor, located as close to VDD and GND as possible. VOUT = (NB · VDD) / 256 Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs. DAC Reference Voltage where NB is the numeric value of the DAC binary input code. 6 _______________________________________________________________________________________ +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs WR A1 A0 H X X Input data latched L L L DAC A input latch transparent L L H DAC A input latch transparent L H L DAC A input latch transparent L H H Enter shutdown mode OPERATION Chip Information TRANSISTOR COUNT: 6848 H = high state, L = low state, X = don’t care _______________________________________________________________________________________ 7 MAX5101 Table 1. MAX5101 Addressing Table (partial) +2.7V to +5.5V, Low-Power, Triple, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs TSSOP.EPS MAX5101 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.