19-1565; Rev 0; 10/99 +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs The MAX5102 has separate input latches for each of its DACs. Data is transferred to the input latches from a common 8-bit input port. The DACs are individually selected through address input A0 and are updated by bringing WR low. Features ♦ +2.7V to +5.5V Single-Supply Operation ♦ Ultra-Low Supply Current 0.2mA while Operating 1nA in Shutdown Mode ♦ Ultra-Small 16-Pin TSSOP Package ♦ Ground to VDD Reference Input Range ♦ Output Buffer Amplifiers Swing Rail-to-Rail ♦ Power-On Reset Sets All Registers to Zero The MAX5102 features a shutdown mode that reduces current to 1nA, as well as a power-on reset mode that resets all registers to code 00 hex on power-up. Ordering Information INL (LSB) PART TEMP. RANGE PIN-PACKAGE Digital Gain and Offset Adjustment MAX5102AEUE -40°C to +85°C 16 TSSOP ±1 Programmable Attenuators MAX5102BEUE -40°C to +85°C 16 TSSOP ±2 Applications Portable Instruments Power-Amp Bias Control Functional Diagram Pin Configuration TOP VIEW INPUT LATCH A OUTA DAC A VDD 1 16 OUTA REF 2 15 OUTB SHDN 3 D0–D7 INPUT LATCH B A0 WR 4 OUTB DAC B CONTROL LOGIC 14 GND MAX5102 13 A0 D7 5 12 D0 D6 6 11 D1 D5 7 10 D2 D4 8 9 D3 MAX5102 TSSOP WR REF SHDN Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5102 General Description The MAX5102 parallel-input, voltage-output, dual 8-bit digital-to-analog converter (DAC) operates from a single +2.7V to +5.5V supply and comes in a space-saving 16-pin TSSOP package. Internal precision buffers swing Rail-to-Rail ® , and the reference input range includes both ground and the positive rail. Both DACs share a common reference input. MAX5102 +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V D_, A0, WR, SHDN to GND ......................................-0.3V to +6V REF to GND ................................................-0.3V to (VDD + 0.3V) OUT_ to GND ...........................................................-0.3V to VDD Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 5.7mW/°C above +70°C) .......457mW Operating Temperature Range MAX5102_EUE ..............................................-40°C to +85°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = VREF = +2.7V to +5.5V, GND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF = +3V and TA = +25°C.) PARAMETER STATIC ACCURACY SYMBOL CONDITIONS MIN TYP Resolution MAX UNITS 8 Bits MAX5102A ±1 MAX5102B ±2 Integral Nonlinearity (Note 1) INL Differential Nonlinearity (Note 1) DNL Guaranteed monotonic ±1 LSB Zero-Code Error ZCE Code = 00 hex ±20 mV 10 mV Zero-Code-Error Supply Rejection Code = 00 hex, VDD = 2.7V to 5.5V Zero-Code Temperature Coefficient Code = 00 hex Gain Error (Note 2) Code = F0 hex Gain-Error Temperature Coefficient Code = F0 hex Power-Supply Rejection Code = FF hex Code = FF hex ±10 LSB µV/°C ±1 ±0.001 % LSB/°C VDD = 2.7V to 3.6V, VREF = 2.5V 1 VDD = 4.5V to 5.5V, VREF = 4.096V 1 LSB REFERENCE INPUT 0 Input Voltage Range 320 Input Resistance V 600 kΩ 15 Input Capacitance DAC OUTPUTS Output Voltage Range DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Current IIN Input Capacitance CIN 2 460 VDD RL = ∞ 0 VDD = 2.7V to 3.6V 2 VDD = 3.6V to 5.5V 3 pF VREF V V VIN = VDD or GND 10 _______________________________________________________________________________________ 0.8 V ±1.0 µA pF +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs (VDD = VREF = +2.7V to +5.5V, GND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF = +3V and TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE 0.6 V/µs 6 µs Code 00 to code FF hex 500 nVs Digital Feedthrough (Note 5) Code 00 to code FF hex 0.5 nVs Digital-to-Analog Glitch Impulse Code 80 hex to code 7F hex 90 nVs REF = 2.5Vp-p at 1kHz, VREF(DC) = 1.5V, VDD = 3V, code FF hex 70 REF = 2.5Vp-p at 10kHz, VREF(DC) = 1.5V, VDD = 3V, code FF hex 60 REF = 0.5Vp-p, VREF(DC) = 1.5V, VDD = 3V, -3dB bandwidth 650 kHz 60 µVRMS Output Voltage Slew Rate From code 00 to code F0 hex Output Settling Time (Note 3) To 1/2LSB, from code 00 to code F0 hex Channel-to-Channel Isolation (Note 4) Signal-to-Noise plus Distortion Ratio SINAD Multiplying Bandwidth dB Wideband Amplifier Noise Shutdown Recovery Time tSDR To ±1/2LSB of final value of VOUT 13 µs Time to Shutdown POWER SUPPLIES tSDN IDD < 5µA 20 µs Power-Supply Voltage VDD Supply Current (Note 6) IDD 2.7 Shutdown Current DIGITAL TIMING (Figure 1) (Note 7) 5.5 V 190 360 µA 0.001 1 µA Address to WR Setup tAS 5 ns Address to WR Hold tAH 0 ns Data to WR Setup tDS 25 ns Data to WR Hold tDH 0 ns WR Pulse Width tWR 20 ns Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded. Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex, and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF · 240 / 256). Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value. Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any other DAC output. The measured channel has a fixed code of 80 hex. Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight data inputs with WR at VDD. Note 6: RL = ∞, digital inputs at GND or VDD. Note 7: Timing measurement reference level is (VIH + VIL) / 2. _______________________________________________________________________________________ 3 MAX5102 ELECTRICAL CHARACTERISTICS (continued) MAX5102 +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs ADDRESS ADDRESS VALID tWR tAS tAH- WR tDSDATA tDHDATA VALID Figure 1. Timing Diagram Typical Operating Characteristics (VDD = VREF = +3V, RL = 10kΩ, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.) DAC FULL-SCALE OUTPUT VOLTAGE vs. SOURCE CURRENT 4 VOUT (V) 0.6 VDD = VREF = 5V 0.4 VDD = VREF = 3V 3 2 1 DAC AT CODE 00 OR F0 1 DAC AT CODE 00 (RL = ∞) 190 180 1 0.2 VDD = 5V; CODE = F0 HEX 170 160 VDD = 3V; CODE = F0 HEX 150 140 130 VDD = 5V; CODE = 00 120 VDD = 3V; CODE = 00 110 0 0 2 4 6 8 180 80 60 CODE = F0 HEX 160 -20 0 20 40 60 80 120 CODE = 00 HEX 80 60 40 VDD = 5.0V 1 DAC AT CODE 00 OR F0 1 DAC AT CODE 00. (RL = ∞) 20 VDD = 3.0V 0 1.0 1.5 2.0 REFERENCE VOLTAGE (V) 2.5 3.0 0 DAC CODE = FF HEX VREF = SINE WAVE CENTERED AT 1.5V 80kHz FILTER -20 140 100 0 -10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5. 5.0 REFERENCE VOLTAGE (V) THD + NOISE (dB) MAX5102 toc04 200 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 100 40 4 -40 TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE AMPLITUDE CODE = 00 HEX 0.5 10 SUPPLY CURRENT vs. REFERENCE VOLTAGE 120 0 8 SUPPLY CURRENT vs. REFERENCE VOLTAGE CODE = F0 HEX 0 6 TEMPERATURE (°C) 160 20 4 SOURCE CURRENT (mA) 1 DAC AT CODE 00 OR F0 1 DAC AT CODE 00 (RL = ∞) 140 2 SINK CURRENT (mA) 200 180 VDD = 3.0V 100 0 10 MAX5102 toc05 0 MAX5102 toc03 5 0.8 VOUT (V) VDD = VREF = 5V SUPPLY CURRENT (µA) VDD = VREF = 3V SUPPLY CURRENT vs. TEMPERATURE 200 MAX5102 toc02 1.0 6 MAX5102 toc01 1.2 100 MAX5102 toc06 DAC ZERO-CODE OUTPUT VOLTAGE vs. SINK CURRENT -30 20kHz REF SIGNAL -40 10kHz REF SIGNAL -50 -60 -70 -80 1kHz REF SIGNAL -90 0 0.5 1.0 1.5 2.0 REFERENCE AMPLITUDE (Vp-p) _______________________________________________________________________________________ 2.5 +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs -20 -30 -40 REF = 0.5Vp-p -50 REF = 1Vp-p -10 DAC CODE FROM 80 TO 7F HEX -20 -30 1 -40 -50 -60 2 -70 -60 -80 REF = 2Vp-p -70 MAX55102 toc09 MAX5100 toc08 0 OUTPUT AMPLITUDE (dB) DAC CODE = FF HEX VREF = SINE WAVE CENTERED AT 1.5V 1kHz FREQUENCY 500kHz FILTER -10 CODE = FF HEX REF IS IVp-p SIGNAL VREF = 1.5V -90 10 100 0.1 1 2µs/div 10 FREQUENCY (MHz) CH1 = WR, 1V/div, CH2 = VOUTA, 50mV/div, AC-COUPLED FREQUENCY (kHz) 0 TO 1 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) MAX55102 toc11 DAC CODE FROM 7F TO 80 HEX DIGITAL FEEDTHROUGH GLITCH IMPULSE (1 TO 0 DIGITAL TRANSITION) DIGITAL FEEDTHROUGH GLITCH IMPULSE (0 TO 1 DIGITAL TRANSITION) MAX55102 toc10 WORST-CASE 1LSB DIGITAL STEP CHANGE (POSITIVE) 1 TO 0 DIGITAL TRANSITION ON ALL DATA BITS (WITH WR HIGH) 1 1 1 2 2 2 POSITIVE SETTLING TIME DAC CODE FROM 10 TO F0 HEX 20ns/div 20ns/div CH1 = D7, 2V/div, CH2 = VOUTA, 1mV/div CH1 = D7, 2V/div, CH2 = VOUTA, 1mV/div NEGATIVE SETTLING TIME INTEGRAL AND DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE DAC CODE FROM F0 TO 10 HEX 0.5 MAX55102 toc14 1µs/div CH1 = WR, 1V/div, CH2 = VOUTA, 50mV/div, AC-COUPLED 0.4 MAX55102 toc12 1 MAX5102 toc15 0.01 -80 MAX55102 toc13 RL = ∞ 0.3 0.2 1 INL/DNL (LSB) THD + NOISE (dB) 10 MAX5102 toc07 0 WORST-CASE 1LSB DIGITAL STEP CHANGE (NEGATIVE) REFERENCE INPUT FREQUENCY RESPONSE TOTAL HARMONIC DISTORTION PLUS NOISE AT DAC OUTPUT vs. REFERENCE FREQUENCY 1 0 -0.1 -0.2 2 2 DNL 0.1 INL -0.3 -0.4 -0.5 1µs/div CH1 = WR = 2V/div, CH2 = VOUTA = 2V/div 1µs/div CH1 = WR, 2V/div, CH2 = VOUTA, 2V/div 0 32 64 96 128 160 192 224 256 DIGITAL CODE _______________________________________________________________________________________ 5 MAX5102 Typical Operating Characteristics (continued) (VDD = VREF = +3V, RL = 10kΩ, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.) +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs MAX5102 Pin Description PIN NAME FUNCTION 1 VDD Positive Supply Voltage. Bypass VDD to GND using a 0.1µF capacitor. 2 REF Reference Voltage Input 3 SHDN 4 WR 5–12 D7–D0 13 A0 14 GND Ground 15 OUTB DAC B Voltage Output 16 OUTA DAC A Voltage Output Shutdown. Connect SHDN to GND for normal operation. Write Input (active low). Use WR to load data into the DAC input latch selected by A0. Data Inputs DAC Address Select Bit Detailed Description Digital-to-Analog Section The MAX5102 uses a matrix decoding architecture for the DACs. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. The resistor network converts the 8-bit digital input into an equivalent analog output voltage in proportion to the applied reference voltage input. The resistor string presents a codeindependent input impedance to the reference and guarantees a monotonic output. These devices can be used in multiplying applications. Their voltages are buffered by rail-to-rail op amps connected in a follower configuration to provide a rail-to-rail output (see Functional Diagram). Low-Power Shutdown Mode The MAX5102 features a shutdown mode that reduces current consumption to 1nA. A high voltage on the SHDN pin shuts down the DACs and the output amplifiers. In shutdown mode, the output amplifiers enter a high-impedance state. When bringing the device out of shutdown, allow 13µs for the output to stabilize. Output Buffer Amplifiers The DAC outputs are internally buffered by precision amplifiers with a typical slew rate of 0.6V/µs. The typical settling time to ±1/2LSB at the output is 6µs when loaded with 10kΩ in parallel with 100pF. Reference Input The MAX5102 provides a code-independent input impedance on the REF input. Input impedance is typically 460kΩ in parallel with 15pF, and the reference input voltage range is 0 to VDD. The reference input accepts positive DC signals, as well as AC signals with peak values between 0 and VDD. The voltage at REF sets the full-scale output voltage for the DAC. The output voltage (VOUT) for any DAC is represented by a digitally programmable voltage source as follows: VOUT = (NB · VREF) / 256 where NB is the numeric value of the DAC binary input code. Digital Inputs and Interface Logic In the MAX5102, address line A0 selects the DAC that receives data from D0–D7, as shown in Table 1. When WR is low, the addressed DAC’s input latch is transparent. Data is latched when WR is high. The DAC outputs (OUTA, OUTB) represent the data held in the two 8-bit Table 1. MAX5102 Addressing Table (partial list) WR A0 H X Input data latched L L DAC A input latch transparent L H DAC B input latch transparent LATCH STATE H = High state, L = Low state, X = Don’t care 6 _______________________________________________________________________________________ +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs connect an external Schottky diode between REF and VDD to ensure compliance with the absolute maximum ratings. Do not apply signals to the digital inputs before the device is fully powered up. Applications Information Power-Supply Bypassing and Ground Management External Reference The reference source resistance must be considerably less than the reference input resistance. To keep within 1LSB error in an 8-bit system, RS must be less than R REF /256. Hence, maintain a value of R S < 1kΩ to ensure 8-bit accuracy. If VREF is DC only, bypass REF to GND with a 0.1µF capacitor. Values greater than this improve noise rejection. Digital or AC transient signals on GND can create noise at the analog output. Return GND to the highest-quality ground available. Bypass VDD with a 0.1µF capacitor, located as close to VDD and GND as possible. Careful PC board ground layout minimizes crosstalk between the DAC outputs and digital inputs. Chip Information Power Sequencing The voltage applied to REF should not exceed VDD at any time. If proper power sequencing is not possible, TRANSISTOR COUNT: 6848 _______________________________________________________________________________________ 7 MAX5102 input latches. To avoid output glitches in the MAX5102, ensure that data is valid before WR goes low. When the device powers up (i.e., VDD ramps up), all latches are internally preset with code 00 hex. +2.7V to +5.5V, Low-Power, Dual, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs TSSOP.EPS MAX5102 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.