MAXIM MAX5100AEUP

19-1557; Rev 0; 10/99
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
The MAX5100 provides double-buffered logic inputs:
four 8-bit buffer registers followed by four 8-bit DAC
registers. This keeps the DAC outputs from changing
during the write operation. An asynchronous control
pin, LDAC, allows for simultaneous updating of the
DAC registers.
The MAX5100 features a shutdown mode that reduces
current to 1nA, as well as a power-on reset mode that
resets all registers to code 00 hex on power-up.
Features
♦ +2.7V to +5.5V Single-Supply Operation
♦ Ultra-Low Supply Current
0.4mA while Operating
1nA in Shutdown Mode
♦ Ultra-Small 20-Pin TSSOP Package
♦ Ground to VDD Reference Input Range
♦ Output Buffer Amplifiers Swing Rail-to-Rail
♦ Double-Buffered Registers for Synchronous
Updating
♦ Power-On Reset Sets All Registers to Zero
Ordering Information
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
MAX5100AEUP
-40°C to +85°C
20 TSSOP
±1
MAX5100BEUP
-40°C to +85°C
20 TSSOP
±2
Applications
Digital Gain and Offset Adjustments
Pin Configuration
Programmable Attenuators
Portable Instruments
Power-Amp Bias Control
TOP VIEW
OUTB 1
20 OUTC
OUTA 2
19 OUTD
VDD 3
18 GND
REF 4
SHDN 5
17 A0
MAX5100
16 A1
WR 6
15 LDAC
D7 7
14 D0
D6 8
13 D1
D5 9
12 D2
D4 10
11 D3
TSSOP
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
________________________________________________________________ Maxim Integrated Products
1
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MAX5100
General Description
The MAX5100 parallel-input, voltage-output, quad 8-bit
digital-to-analog converter (DAC) operates from a single +2.7V to +5.5V supply and comes in a space-saving 20-pin TSSOP package. Internal precision buffers
swing Rail-to-Rail ® , and the reference input range
includes both ground and the positive rail. All four
DACs share a common reference input.
MAX5100
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
D_, A_, WR, SHDN, LDAC to GND...........................-0.3V to +6V
REF to GND ................................................-0.3V to (VDD + 0.3V)
OUT_ to GND ...........................................................-0.3V to VDD
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (TA = +70°C)
20-Pin TSSOP (derate 7.0mW/°C above +70°C) .......559mW
Operating Temperature Range
MAX5100_EUP ..............................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VREF = +2.7V to +5.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF
= +3V and TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8
Bits
STATIC ACCURACY
Resolution
MAX5100A
±1
MAX5100B
±2
Integral Nonlinearity (Note 1)
INL
Differential Nonlinearity (Note 1)
DNL
Guaranteed monotonic
±1
LSB
Zero-Code Error
ZCE
Code = 00 hex
±20
mV
10
mV
Zero-Code-Error Supply
Rejection
Code = 00 hex, VDD = 2.7V to 5.5V
Zero-Code Temperature
Coefficient
Code = 00 hex
Gain Error (Note 2)
Code = F0 hex
Gain-Error Temperature
Coefficient
Code = F0 hex
Power-Supply Rejection
Code = FF hex
±10
LSB
µV/°C
±1
±0.001
%
LSB/°C
VDD = 2.7V to 3.6V,
VREF = 2.5V
1
VDD = 4.5V to 5.5V,
VREF = 4.096V
1
LSB
REFERENCE INPUT
0
Input Voltage Range
320
Input Resistance
V
600
kΩ
15
Input Capacitance
DAC OUTPUTS
Output Voltage Range
DIGITAL INPUTS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
IIN
Input Capacitance
CIN
2
460
VDD
RL = ∞
0
VDD = 2.7V to 3.6V
2
VDD = 3.6V to 5.5V
3
pF
VREF
V
V
VIN = VDD or GND
10
_______________________________________________________________________________________
0.8
V
±1.0
µA
pF
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
(VDD = VREF = +2.7V to +5.5V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = VREF
= +3V and TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
0.6
V/µs
6
µs
Code 00 to code FF hex
500
nVs
Digital Feedthrough (Note 5)
Code 00 to code FF hex
0.5
nVs
Digital-to-Analog Glitch Impulse
Code 80 hex to code 7F hex
90
nVs
Signal-to-Noise plus Distortion
Ratio
VREF(DC) = 1.5V,
VDD = 3V,
code = FF hex
Output Voltage Slew Rate
From code 00 to code F0 hex
Output Settling Time (Note 3)
To 1/2LSB, from code 10 to code F0 hex
Channel-to-Channel Isolation
(Note 4)
SINAD
REF = 2.5Vp-p at
1kHz
70
dB
REF = 2.5Vp-p at
10kHz
60
REF = 0.5Vp-p, VREF(DC) = 1.5V,
VDD = 3V, -3dB bandwidth
Multiplying Bandwidth
Wideband Amplifier Noise
650
kHz
60
µVRMS
Shutdown Recovery Time
tSDR
To ±1/2LSB of final value of VOUT
13
µs
Time to Shutdown
POWER SUPPLIES
tSDN
IDD < 5µA
20
µs
Power-Supply Voltage
VDD
Supply Current (Note 6)
IDD
2.7
Shutdown Current
DIGITAL TIMING (Figure 1) (Note 7)
5.5
V
370
700
µA
0.001
1
µA
Address to WR Setup
tAS
5
ns
Address to WR Hold
tAH
0
ns
Data to WR Setup
tDS
25
ns
Data to WR Hold
tDH
0
ns
WR Pulse Width
tWR
20
ns
LDAC Pulse Width (Note 8)
tLD
20
ns
Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.
Note 2: Gain error is: [100 (VF0,meas - ZCE - VF0,ideal) / VREF]. Where VF0,meas is the DAC output voltage with input code F0 hex,
and VF0,ideal is the ideal DAC output voltage with input code F0 hex (i.e., VREF · 240 / 256).
Note 3: Output settling time is measured from the 50% point of the falling edge of WR to ±1/2LSB of VOUT’s final value.
Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any
other DAC output. The measured channel has a fixed code of 80 hex.
Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight
data inputs with WR at VDD.
Note 6: RL = ∞, digital inputs at GND or VDD.
Note 7: Timing measurement reference level is (VIH + VIL) / 2.
Note 8: If LDAC is activated prior to WR’s rising edge, it must stay low for tLD (or longer) after WR goes high.
_______________________________________________________________________________________
3
MAX5100
ELECTRICAL CHARACTERISTICS (continued)
MAX5100
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
ADDRESS
ADDRESS VALID
tWR
tAS
tAH-
WR
tLD
LDAC (NOTE 8)
tDS-
tDH-
DATA
DATA VALID
Figure 1. Timing Diagram
Typical Operating Characteristics
(VDD = VREF = +3V, RL = 10kΩ, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.)
5
4
VDD = VREF = 3V
VOUT (V)
0.6
VDD = VREF = 5V
0.4
VDD = VREF = 5V
3
VDD = VREF = 3V
2
300
VDD = 5V; CODE = 00 HEX
280
260
VDD = 3V; CODE = F0 HEX
240
220
0.2
1
0
0
0
2
4
6
8
180
0
2
4
6
8
10
-20
0
20
40
60
80
100
SOURCE CURRENT (mA)
TEMPERATURE (°C)
SUPPLY CURRENT vs. REFERENCE VOLTAGE
(VDD = 3V)
SUPPLY CURRENT vs. REFERENCE VOLTAGE
(VDD = 5V)
TOTAL HARMONIC DISTORTION PLUS NOISE
AT DAC OUTPUT vs. REFERENCE AMPLITUDE
220
CODE = 00
CODE = F0
0
VDD = +3V
DAC CODE = FF HEX
VREF = SINE WAVE CENTERED AT 1.5V
80kHz FILTER
-10
-20
280
260
240
CODE = 00
180
THD + NOISE (dB)
240
200
300
SUPPLY CURRENT (µA)
260
1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (RL = ∞)
MAX5100 toc05
CODE = F0
320
MAX5100 toc04
1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (RL = ∞)
280
-30
-40
20kHz REF SIGNAL
10kHz REF SIGNAL
-50
-60
220
160
-70
1kHz REF SIGNAL
200
140
0
0.5
1.0
1.5
2.0
REFERENCE VOLTAGE (V)
4
-40
SINK CURRENT (mA)
300
SUPPLY CURRENT (µA)
10
VDD = 3V; CODE = 00 HEX
200
MAX5100 toc06
VOUT (V)
0.8
1 DAC AT CODE 00 OR F0,
3 DACS AT 00 (RL = ∞)
VDD = 5V; CODE = F0 HEX
320
SUPPLY CURRENT (µA)
1.0
SUPPLY CURRENT vs. TEMPERATURE
340
MAX5100 toc02
6
MAX5100 toc01
1.2
DAC FULL-SCALE OUTPUT VOLTAGE
vs. SOURCE CURRENT
MAX5100 toc03
DAC ZERO-CODE OUTPUT VOLTAGE
vs. SINK CURRENT
2.5
3.0
-80
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
REFERENCE AMPLITUDE (Vp-p)
_______________________________________________________________________________________
2.5
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
REFERENCE INPUT
FREQUENCY RESPONSE
-30
REF = 0.5Vp-p
-50
REF = 1Vp-p
-60
MAX5100 toc08
CH1 = LDAC, 2V/div
CH2 = VOUTA, 50mV/div,
AC-COUPLED
DAC CODE FROM
80 TO 7F HEX
-20
1
-30
-40
-50
2
-60
-70
CODE = FF HEX, REF IS 1Vp-p SIGNAL
VREF = 1.5V
-80
-90
-80
10
0.01
100
0.1
1
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(0 TO 1 DIGITAL TRANSITION)
CH1 = D7, 2V/div
CH2 = VOUTA, 2mV/div,
AC-COUPLED
0 TO 1 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH,
LDAC LOW)
1
2
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(1 TO 0 DIGITAL TRANSITION)
MAX55100 toc11
WORST-CASE 1LSB DIGITAL STEP CHANGE
(POSITIVE)
MAX55100 toc10
FREQUENCY (MHz)
CH1 = LDAC, 2V/div
CH2 = VOUTA, 50mV/div,
AC-COUPLED
DAC CODE FROM
7F TO 80 HEX
1µs/div
10
FREQUENCY (kHz)
CH1 = D7, 2V/div
CH2 = VOUTA, 2mV/div,
AC-COUPLED
1 TO 0 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH,
LDAC LOW)
1
1
2
2
1µs/div
20ns/div
20ns/div
POSITIVE SETTLING TIME
NEGATIVE SETTLING TIME
INTEGRAL AND DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
CH1 = WR, 2V/div
CH2 = VOUTA, 2V/div
DAC CODE FROM
10 TO F0 HEX
1
1
2
2
0.5
0.4
RL = ∞
0.3
0.2
INL/DNL (LSB)
CH1 = WR, 2V/div
CH2 = VOUTA, 2V/div
DAC CODE FROM
10 TO F0 HEX
MAX5100 toc15
1
MAX55100 toc12
REF = 2Vp-p
-70
MAX55100 toc14
-40
-10
MAX55100 toc13
THD + NOISE (dB)
-20
0
OUTPUT AMPLITUDE (dB)
VDD = +3V
DAC CODE = FF HEX
VREF = SINE WAVE CENTERED AT 1.5V
1kHz FREQUENCY
500kHz FILTER
-10
10
MAX5100 toc07
0
WORST-CASE 1LSB DIGITAL STEP CHANGE
(NEGATIVE)
MAX55100 toc09
TOTAL HARMONIC DISTORTION PLUS NOISE
AT DAC OUTPUT vs. REFERENCE FREQUENCY
DNL
0.1
0
-0.1
-0.2
INL
-0.3
-0.4
-0.5
1µs/div
1µs/div
0
32
64
96
128 160 192 224 256
DIGITAL CODE
_______________________________________________________________________________________
5
MAX5100
Typical Operating Characteristics (continued)
(VDD = VREF = +3V, RL = 10kΩ, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.)
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
MAX5100
Pin Description
PIN
NAME
FUNCTION
1
OUTB
DAC B Voltage Output
2
OUTA
DAC A Voltage Output
3
VDD
Positive Supply Voltage. Bypass VDD to GND using a 0.1µF capacitor.
4
REF
Reference Voltage Input
5
SHDN
6
WR
7–14
D7–D0
Data Inputs 7–0
15
LDAC
Load DAC Input (active low). Drive the asynchronous LDAC input low to transfer the contents of all input
latches to their respective DAC latch.
16
A1
DAC Address Select Bit (MSB)
17
A0
DAC Address Select Bit (LSB)
18
GND
Ground
19
OUTD
DAC D Voltage Output
20
OUTC
DAC C Voltage Output
Shutdown. Connect SHDN to GND for normal operation.
Write Input (active low). Use WR to load data into the DAC input latch selected by A0 and A1.
Detailed Description
Digital-to-Analog Section
The MAX5100 uses a matrix decoding architecture for
the DACs. The external reference voltage is divided
down by a resistor string placed in a matrix fashion.
Row and column decoders select the appropriate tab
from the resistor string to provide the needed analog
voltages. The resistor network converts the 8-bit digital
input into an equivalent analog output voltage in proportion to the applied reference voltage input. The
resistor string presents a code-independent input
impedance to the reference and guarantees a monotonic output.
The device can be used in multiplying applications.
The voltages are buffered by rail-to-rail op amps connected in a follower configuration to provide a rail-to-rail
output. The functional block diagram for the MAX5100
is shown in Figure 2.
Low-Power Shutdown Mode
The MAX5100 features a shutdown mode that reduces
current consumption to 1nA. A high voltage on the
shutdown pin shuts down the DACs and the output
amplifiers. In shutdown mode, the output amplifiers
enter a high-impedance state. When bringing the
6
device out of shutdown, allow 13µs for the output to
stabilize.
Output Buffer Amplifiers
The DAC outputs are internally buffered by precision
amplifiers with a typical slew rate of 0.6V/µs. The typical
settling time to ±1/2LSB at the output is 6µs when
loaded with 10kΩ in parallel with 100pF.
Reference Input
The MAX5100 provides a code-independent input
impedance on the REF input. The input impedance is
typically 460kΩ in parallel with 15pF, and the reference
input voltage range is 0 to VDD. The reference input
accepts positive DC signals as well as AC signals with
peak values between 0 and VDD. The voltage at REF
sets the full-scale output voltage for the DAC. The output voltage (VOUT) for any DAC is represented by a
digitally programmable voltage source as follows:
VOUT = (NB · VREF) / 256
where NB is the numeric value of the DAC binary input
code.
Digital Inputs and Interface Logic
In the MAX5100, address lines A0 and A1 select the
DAC that receives data from D0–D7, as shown in Table 1.
_______________________________________________________________________________________
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
DAC A
LATCH
DAC A
OUTA
INPUT
LATCH B
DAC B
LATCH
DAC B
OUTB
INPUT
LATCH C
DAC C
LATCH
DAC C
OUTC
INPUT
LATCH D
DAC D
LATCH
DAC D
OUTD
MAX5100
INPUT
LATCH A
D0–D7
AO
A1
CONTROL
LOGIC
WR
MAX5100
LDAC
REF SHDN
Figure 2. Functional Diagram
Table 1. MAX5100 Address Table (Partial)
LDAC
WR
A1
A0
H
H
X
X
Input and DAC data latched
H
L
L
L
DAC A input latch transparent
L
H
X
X
All 4 DACs’ DAC latches
transparent
L
L
L
L
DAC A input registers transparent and all 4 DACs’ DAC
latches transparent
LATCH STATE
H
L
L
H
DAC B input latch transparent
H
L
H
L
DAC C input latch transparent
H
L
H
H
DAC D input latch transparent
H = High state, L = Low state, X = Don’t care
When WR is low, the addressed DAC’s input latch is
transparent. Data is latched when WR is high.
The MAX5100 LDAC feature allows simultaneous
updating of all four DACs. LDAC low latches the data in
the data registers to the DAC registers. If simultaneous
updating is not required, tie LDAC low to keep the DAC
latches transparent. If WR and LDAC are low simultaneously, avoid output glitches by ensuring that data is
valid before the two signals go low. When the device
powers up (i.e., VDD ramps up), all latches are internally preset with code 00 hex.
Applications Information
External Reference
The reference source resistance must be considerably
less than the reference input resistance. To keep within
1LSB error in an 8-bit system, RS must be less than
RREF / 256. Hence, maintain a value of RS <1kΩ to
ensure 8-bit accuracy. If VREF is DC only, bypass REF
to GND with a 0.1µF capacitor. Values greater than this
improve noise rejection.
Power Sequencing
The voltage applied to REF should not exceed VDD at
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
VDD to ensure compliance with the absolute maximum
ratings.
Power-Supply Bypassing and
Ground Management
Digital or AC transient signals on GND can create noise
at the analog output. Return GND to the highest-quality
ground available. Bypass VDD with a 0.1µF capacitor,
located as close to VDD and GND as possible.
Careful PC board ground layout minimizes crosstalk
between the DAC outputs and digital inputs.
Chip Information
TRANSISTOR COUNT: 6848
_______________________________________________________________________________________
7
+2.7V to +5.5V, Low-Power, Quad, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
TSSOP.EPS
MAX5100
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.