19-1603; Rev 0; 1/00 Octal, 13-Bit Voltage-Output DAC with Parallel Interface Minimum Component Count Analog Systems Digital Offset/Gain Adjustment SONET Applications Automatic Test Equipment (ATE) ♦ 8 DACs in a Single Package ♦ Buffered Voltage Outputs ♦ Unipolar or Bipolar Voltage Swing to +9V and -4V ♦ 22µs Output Settling Time ♦ Drives up to 10,000pF Capacitive Load ♦ Low Output Glitch: 30mV ♦ Low Power Consumption: 10mA (typ) ♦ Small Package: 44-Pin MQFP ♦ Double-Buffered Digital Inputs ♦ Asynchronous Load Updates All DACs Simultaneously ♦ Asynchronous CLR Forces All DACs to DUTGND Potential Ordering Information PART TEMP. RANGE PINPACKAGE INL (LSB) MAX5839ACMH 0°C to +70°C 44 MQFP ±2 MAX5839BCMH 0°C to +70°C 44 MQFP ±4 MAX5839AEMH -40°C to +85°C 44 MQFP ±2 MAX5839BEMH -40°C to +85°C 44 MQFP ±4 34 35 OUTE DUTGNDEF OUTF OUTG 36 37 38 39 40 41 42 TOP VIEW OUTB OUTC DUTGNDCD OUTD REFCDEFREFCDEF+ VDD Pin Configuration 43 Industrial Process Controls Arbitrary Function Generators Avionics Equipment ♦ Full 13-Bit Performance Without Adjustments 44 Applications Features DUTGNDAB OUTA REFABREFAB+ VDD 1 33 2 32 3 31 4 30 VSS LD A2 A1 A0 6 CS 11 23 5 29 28 MAX5839 7 27 8 26 9 25 10 24 DUTGNDGH OUTH REFGHREFGH+ VSS CLR D12 D11 D10 D9 D8 22 21 20 19 18 17 16 15 14 13 WR VCC GND D0 D1 D2 D3 D4 D5 D6 D7 12 Functional Diagram appears at end of data sheet. MQFP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5839 General Description The MAX5839 contains eight 13-bit, voltage-output digital-to-analog converters (DACs). On-chip precision output amplifiers provide the voltage outputs. The device operates from +14V/-9V supplies. Its bipolar output voltage swing ranges from +9V to -4V and is achieved with no external components. The MAX5839 has three pairs of differential reference inputs; two of these pairs are connected to two DACs each, and a third pair is connected to four DACs. The references are independently controlled, providing different full-scale output voltages to the respective DACs. The MAX5839 operates within the following voltage ranges: VDD = +7V to +14V, VSS = -5V to -9V, and VCC = +4.75V to +5.25V. The MAX5839 features double-buffered interface logic with a 13-bit parallel data bus. Each DAC has an input latch and a DAC latch. Data in the DAC latch sets the output voltage. The eight input latches are addressed with three address lines. Data is loaded to the input latch with a single write instruction. An asynchronous load input (LD) transfers data from the input latch to the DAC latch. The LD input controls all DACs; therefore, all DACs can be updated simultaneously by asserting the LD pin. An asynchronous CLR input sets the output of all eight DACs to the respective DUTGND input of the op amp. Note that CLR is a CMOS input, which is powered by VDD. All other logic inputs are TTL/CMOS compatible. The “A” grade of the MAX5839 has a maximum INL of ±2LSBs, while the “B” grade has a maximum INL of ±4LSBs. Both grades are available in 44-pin MQFP packages. MAX5839 Octal, 13-Bit Voltage-Output DAC with Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +17V VSS to GND ........................................................... -11V to +0.3V VCC to GND ............................................................ -0.3V to +6V A_, D_, WR, CS, LD, CLR to GND.............+0.3V to (VCC + 0.3V) REF_ _ _ _+, REF_ _ _ _-, DUTGND_ _ ..................................(VSS - 0.3V) to (VDD + 0.3V) OUT_ ..........................................................................VDD to VSS Maximum Current into REF_ _ _ _ _, DUTGND_ _ ...........±10mA Maximum Current into Any Signal Pin ............................. ±50mA OUT_ Short-Circuit Duration to VDD, VSS, and GND .......... 1sec Continuous Power Dissipation (TA = +70°C) 44-Pin MQFP (derate 11.1mW/°C above +70°C)......... 870mW Operating Temperature Ranges MAX5839_CMH ................................................... 0°C to +70°C MAX5839_EMH................................................. -40°C to +85°C Junction Temperature ..................................................... +150°C Storage Temperature Range ............................ -65°C to +150°C Lead Temperature (soldering, 10s) ................................ +300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, RL = 10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (ANALOG SECTION) Resolution N Relative Accuracy INL Differential Nonlinearity DNL Zero-Scale Error ZSE Full-Scale Error FSE 13 Bits MAX5839A ±2 MAX5839B ±4 Guaranteed monotonic ±1 LSB ±2 ±4 LSB ±4 ±8 LSB ±2 ±5 LSB Gain Error LSB Gain Temperature Coefficient (Note 1) 0.15 20 ppm FSR/°C DC Crosstalk (Note 1) 14 75 µV ±1 ±10 µA REFERENCE INPUTS Input Resistance 1 Input Current MΩ REF_ _ _ _+ Input Range 0.5 4.5 V REF_ _ _ _- Input Range -2.0 -0.5 V 2 6.5 V (REF_ _ _ _+) - (REF_ _ _ _-) Range ANALOG OUTPUTS Maximum Output Voltage 9 Minimum Output Voltage VDD - 2 VSS + 2 Resistive Load to GND V -4 5 V kΩ Capacitive Load to GND (Note 2) 10,000 pF DC Output Impedance (Note 1) 0.5 Ω 2 _______________________________________________________________________________________ Octal, 13-Bit Voltage-Output DAC with Parallel Interface (VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, RL = 10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP 40 84 MAX UNITS DUTGND_ _ CHARACTERISTICS Input Impedance per DAC Input Current per DAC (Note 1) Input Range kΩ -165 100 µA -2 2 V DIGITAL INPUTS Input Voltage High VIH Input Voltage Low VIL 2.4 Input Capacitance CIN (Note 1) Input Current IIN VIN = 0 or VCC V 0.8 V 10 pF -1 1 µA POWER SUPPLIES VDD Analog Power-Supply Range VDD 7 14 V VSS Analog Power-Supply Range VSS -9 -5 V Digital Power Supply VCC 5 5.25 V Positive Supply Current IDD RL = ∞ 10 13 mA Negative Supply Current ISS RL = ∞ 9 12 mA Digital Supply Current ICC 4.75 (Note 3) 0.5 (Note 4) 5 mA PSRR, ∆VOUT / ∆VDD VDD = 14V ±5% 94 dB PSRR, ∆VOUT / ∆VSS VSS = -9V ±5% 98 dB INTERFACE TIMING CHARACTERISTICS (VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, Figure 2, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS Pulse Width Low t1 50 ns WR Pulse Width Low t2 50 ns LD Pulse Width Low t3 50 ns CS Low to WR Low t4 0 ns CS High to WR High t5 0 ns Data Valid to WR Setup t6 50 ns Data Valid to WR Hold t7 0 ns Address Valid to WR Setup t8 15 ns Address Valid to WR Hold t9 0 ns _______________________________________________________________________________________ 3 MAX5839 ELECTRICAL CHARACTERISTICS (continued) DYNAMIC CHARACTERISTICS (VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, RL = 10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Output Settling Time CONDITIONS MIN TYP To ±1/2LSB of full scale Output Slew Rate Digital Feedthrough (Note 5) Digital Crosstalk (Note 6) Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Channel-to-Channel Isolation Output Noise Spectral Density At ƒ = 1kHz MAX UNITS 22 µs 1 V/µs 3 nVs 3 nVs 120 nVs 3 nVs 100 dB 120 nV/√Hz Guaranteed by design. Not production tested. Guaranteed by design when 220Ω resistor is in series with CL = 10,000pF. All digital inputs (D_, A_, WR, CS, LD, and CLR) at GND or VCC potential. All digital inputs (D_, A_, WR, CS, LD, and CLR) at +0.8V or +2.4V. All data inputs (D0 to D12) transition from GND to VCC, with WR = VCC. All digital inputs (D_, A_, WR, CS, LD, and CLR) at +0.8V or +2.4V. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Typical Operating Characteristics (VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, TA = +25°C, unless otherwise noted.) 0.3 0.1 0.1 0 0 -0.1 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 2048 4096 DIGITAL CODE 6144 8192 0.2 DNL 0.1 -0.4 0 INL 0.3 ERROR (LSB) 0.2 DNL (LSB) 0.2 INL AND DNL ERROR vs. TEMPERATURE 0.4 MAX5260-02 0.3 4 0.4 MAX5260-01 0.4 DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE MAX5260-03 INTEGRAL NONLINEARITY vs. DIGITAL CODE INL (LSB) MAX5839 Octal, 13-Bit Voltage-Output DAC with Parallel Interface 0 0 2048 4096 DIGITAL CODE 6144 8192 0 10 20 30 40 50 TEMPERATURE (°C) _______________________________________________________________________________________ 60 70 Octal, 13-Bit Voltage-Output DAC with Parallel Interface IDD AND ISS vs. TEMPERATURE (UNLOADED) 10.2 0.05 9.6 FULL SCALE -0.05 ZERO SCALE -0.10 23 SUPPLY CURRENT (µA) 9.8 IDD, ISS (mA) 0.10 0 IDD 10.0 9.4 9.2 ISS 9.0 25 MAX5260-05 0.15 8.8 8.4 8.2 0 10 20 30 40 50 60 15 0 70 25 REFERENCE INPUT FREQUENCY RESPONSE -20 -25 30 40 50 60 LARGE-SIGNAL STEP RESPONSE MAX5260-08 D12 5V/div 80 SETTLING TIME (µs) -15 20 SETTLING TIME vs. CAPACITIVE LOAD 90 -5 -10 10 TEMPERATURE (°C) 100 MAX5260-07 REF_ _ _ _ _ = 200mVp-p 0 0 TEMPERATURE (°C) TEMPERATURE (°C) 5 70 70 MAX5260-09 -0.20 70 60 50 40 OUT 1V/div 30 -30 20 -35 10 0 -40 10k 100k 1M 10 10M 100 1000 10k CAPACITIVE LOAD (pF) POSITIVE SETTLING TIME NEGATIVE SETTLING TIME LD OUT 1mV/div 100k LD OUT 1mV/div 5µs/div NOISE VOLTAGE DENSITY vs. FREQUENCY MAX5260-11 FREQUENCY (Hz) MAX5260-10 1k 1000 NOISE VOLTAGE DENSITY (nV/√Hz) AMPLITUDE (dB) 19 17 8.6 -0.15 21 MAX5260-12 ERROR (LSB) 10.4 MAX5260-04 0.20 DIGITAL SUPPLY CURRENT vs. TEMPERATURE MAX5260-06 ZERO-SCALE AND FULL-SCALE ERROR vs. TEMPERATURE 100 5µs/div 5µs/div 10 100 1k 10k FREQUENCY (Hz) _______________________________________________________________________________________ 5 MAX5839 Typical Operating Characteristics (continued) (VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +14V, VSS = -9V, VCC = +5V, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +4.500V, VREF_ _ _ _- = -2.000V, TA = +25°C, unless otherwise noted.) MAJOR CARRY GLITCH IMPULSE (0x1000–0xFFF) LD 5V/div MAX5260-15 LD 5V/div GAIN ERROR vs. VREF (VREF+ - VREF-) 0.4 MAX5260-14 MAX5260-13 MAJOR CARRY GLITCH IMPULSE (0xFFFF–0x10000) 0.3 OUT GAIN ERROR (LSB) 0.2 OUT 5mV/div 5mV/div 0.1 0 -0.1 -0.2 -0.3 2µs/div 2µs/div 0 2 4 6 VREF (V) INTEGRAL NONLINEARITY (MAX, MIN) vs. VREF (VREF+ - VREF-) DIFFERENTIAL NONLINEARITY (MAX, MIN) vs. VREF (VREF+ - VREF-) 0.20 0.4 0.15 0.3 0.10 INL (MAX, MIN) (LSB) DNL (MAX, MIN) (LSB) MAX5260-19 0.5 MAX5260-16 0.25 0.05 0 -0.05 -0.10 0.2 0.1 0 -0.1 -0.15 -0.2 -0.20 -0.3 -0.25 2 4 6 8 0 10 2 4 6 8 VREF (V) VREF (V) FULL-SCALE ERROR vs. VREF (VREF+ - VREF-) ZERO-SCALE ERROR vs. VREF (VREF+ - VREF-) 0 MAX5260-18 0 -0.2 10 MAX5260-17 0 -0.2 -0.4 ZSE (LSB) -0.4 FSE (LSB) MAX5839 Octal, 13-Bit Voltage-Output DAC with Parallel Interface -0.6 -0.6 -0.8 -1.0 -0.8 -1.2 -1.0 -1.4 -1.6 -1.2 0 2 4 6 VREF (V) 6 8 10 0 2 4 6 8 10 VREF (V) _______________________________________________________________________________________ 8 10 Octal, 13-Bit Voltage-Output DAC with Parallel Interface PIN NAME FUNCTION 1 DUTGNDAB Device Sense Ground Input for OUTA and OUTB. In normal operation, OUTA and OUTB are referenced to DUTGNDAB. When CLR is low, OUTA and OUTB are forced to the potential on DUTGNDAB. 2 OUTA 3 REFAB- Negative Reference Input for DACs A and B 4 REFAB+ Positive Reference Input for DACs A and B 5, 38 VDD Positive Analog Power Supply. Normally set to +14V. Connect both pins to the supply voltage. See Grounding and Bypassing section for bypass requirements. 6, 29 VSS Negative Analog Power Supply. Normally set to -9V. Connect both pins to the supply voltage. See Grounding and Bypassing section for bypass requirements. 7 LD Load Input. Drive this asynchronous input low to transfer the contents of the input latches to their respective DAC latches. DAC latches are transparent when LD is low and latched when LD is high. 8 A2 Address Bit 2 (MSB) 9 A1 Address Bit 1 10 A0 Address Bit 0 (LSB) 11 CS Chip Select. Active-low input. 12 WR Write Input. Active-low strobe for conventional memory write sequence. Input data latches are transparent when WR and CS are both low. WR latches data into the DAC input latch selected by A2–A0 on the rising edge of CS. 13 VCC Digital Power Supply. Normally set to +5V. See Grounding and Bypassing section for bypass requirements. 14 GND Ground 15–27 D0–D12 28 CLR 30 REFGH+ Positive Reference Input for DACs G and H 31 REFGH- Negative Reference Input for DACs G and H DAC A Buffered Output Voltage Data Bits 0–12. Offset binary coding. Clear Input. Drive CLR low to force all DAC outputs to the voltage on their respective DUTGND _ _. Does not affect the status of internal registers. All DACs return to their previous levels when CLR goes high. _______________________________________________________________________________________ 7 MAX5839 Pin Description Octal, 13-Bit Voltage-Output DAC with Parallel Interface MAX5839 Pin Description (continued) 8 PIN NAME FUNCTION 32 OUTH 33 DUTGNDGH 34 OUTG DAC G Buffered Output Voltage 35 OUTF DAC F Buffered Output Voltage 36 DUTGNDEF 37 OUTE 39 REFCDEF+ Positive Reference Input for DACs C, D, E, and F 40 REFCDEF- Negative Reference Input for DACs C, D, E, and F 41 OUTD 42 DUTGNDCD 43 OUTC DAC C Buffered Output Voltage 44 OUTB DAC B Buffered Output Voltage DAC H Buffered Output Voltage Device Sense Ground Input for OUTG and OUTH. In normal operation, OUTG and OUTH are referenced to DUTGNDGH. When CLR is low, OUTG and OUTH are forced to the potential on DUTGNDGH. Device Sense Ground Input for OUTE and OUTF. In normal operation, OUTE and OUTF are referenced to DUTGNDEF. When CLR is low, OUTE and OUTF are forced to the potential on DUTGNDEF. DAC E Buffered Output Voltage DAC D Buffered Output Voltage Device Sense Ground Input for OUTC and OUTD. In normal operation, OUTC and OUTD are referenced to DUTGNDCD. When CLR is low, OUTC and OUTD are forced to the potential on DUTGNDCD. _______________________________________________________________________________________ Octal, 13-Bit Voltage-Output DAC with Parallel Interface CLR R Analog Section R OUT 2R 2R 2R 2R D11 D12 D0 2R 2R DUTGND REF- The MAX5839 contains eight 13-bit voltage-output DACs. These DACs are “inverted” R-2R ladder networks that convert 13-bit digital inputs into equivalent analog output voltages, in proportion to the applied reference voltages (Figure 1). The MAX5839 has three positive reference inputs (REF_ _ _ _+) and three negative reference inputs (REF_ _ _ _-). The difference from REF_ _ _ _+ to REF_ _ _ _- , multiplied by two, sets the DAC output span. In addition to the differential reference inputs, the MAX5839 has four analog-ground input pins (DUTGND_ _). When CLR is high (unasserted), the voltage on DUTGND_ _ offsets the DAC output voltage range. If CLR is asserted, the output amplifier is forced to the voltage present on DUTGND_ _. REF+ Figure 1. DAC Simplified Circuit Reference and DUTGND Inputs All of the MAX5839’s reference inputs are buffered with precision amplifiers. This allows the flexibility of using resistive dividers to set the reference voltages. Because of the relatively high multiplying bandwidth of the reference input (188kHz), any signal present on the reference pin within this bandwidth is replicated on the DAC output. t1 CS t4 t5 t2 WR The DUTGND pins of the MAX5839 are connected to the negative source resistor (nominally 84kΩ) of the output amplifier. The DUTGND pins are typically connected directly to analog ground. Each of these pins has an input current that varies with the DAC digital code. If the DUTGND pins are driven by external circuitry, budget ±200µA per DAC for load current. t8 t9 A0–A2 t6 Output Buffer Amplifiers t7 D0–D12 t3 t3 (NOTE 3) LD The MAX5839’s voltage outputs are internally buffered by precision gain-of-two amplifiers with a typical slew rate of 1V/µs. With a full-scale transition at its output, the typical settling time to ±1/2LSB is 22µs. This settling time does not significantly vary with capacitive loads less than 10,000pF. Output Deglitching Circuit NOTES: 1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. tr = tf = 5ns. 2. MEASUREMENT REFERENCE LEVEL IS (VINH + VINL) / 2. 3. IF LD– IS ACTIVATED WHILE WR IS LOW, THEN LD– MUST STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH. The MAX5839’s internal connection from the DAC ladder to the output amplifier contains special deglitch circuitry. This glitch/deglitch circuitry is enabled on the falling edge of LD to remove the glitch from the R-2R DAC. This enables the MAX5839 to exhibit a fraction of the glitch impulse energy of parts without the deglitching circuit. Figure 2. Digital Timing Diagram _______________________________________________________________________________________ 9 MAX5839 _______________Detailed Description MAX5839 Octal, 13-Bit Voltage-Output DAC with Parallel Interface Digital Inputs and Interface Logic All digital inputs are compatible with both TTL and CMOS logic. The MAX5839 interfaces with microprocessors using a data bus at least 13 bits wide. The interface is double buffered, allowing simultaneous updating of all DACs. There are two latches for each DAC (see Functional Diagram): an input latch that receives data from the data bus, and a DAC latch that receives data from the input latch. Address lines A0, A1, and A2 select which DAC’s input latch receives data from the data bus, as shown in Table 1. Both the input latches and the DAC latches are transparent when CS, WR, and LD are all low. Any change of D0–D12 during this condition appears at the output instantly. Transfer data from the input latches to the DAC latches by asserting the asynchronous LD signal. Each DAC’s analog output reflects the data held in its DAC latch. All control inputs are level triggered. Table 2 is an interface truth table. Table 1. MAX5839 DAC Addressing FUNCTION Loading the DACs Taking LD high latches data into the DAC latches. If LD is brought low when WR and CS are low, the DAC addressed by A0, A1, and A2 is directly controlled by the data on D0–D12. This allows the maximum digital update rate; however, it is sensitive to any glitches or skew in the input data stream. Asynchronous Clear The MAX5839 has an asynchronous clear pin (CLR) that, when asserted, sets all DAC outputs to the voltage present on their respective DUTGND pins. Deassert CLR to return the DAC output to its previous voltage. Note that CLR does not clear any of the internal digital registers. A2 A1 A0 0 0 0 DAC A input latch 0 0 1 DAC B input latch 0 1 0 DAC C input latch 0 1 1 DAC D input latch 1 0 0 DAC E input latch Multiplying Operation The MAX5839 can be used for multiplying applications. Its reference accepts both DC and AC signals. Since the reference inputs are unipolar, multiplying operation is limited to two quadrants. See the graphs in the Typical Operating Characteristics for dynamic performance of the DACs and output buffers. 1 0 1 DAC F input latch 1 1 0 DAC G input latch 1 1 1 DAC H input latch Table 2. Interface Truth Table CLR LD WR CS X X 0 0 Input register transparent X X X 1 Input register latched X X 1 X Input register latched X 0 X X DAC register transparent X 1 X X DAC register latched 0 X X X Outputs of DACs at DUTGND_ _ X Outputs of DACs set to voltage defined by the DAC register, the references, and the corresponding DUTGND_ _ 1 1 X = Don’t care 10 Input Write Cycle Data can be latched or transferred directly to the DAC. CS and WR control the input latch, and LD transfers information from the input latch to the DAC latch. The input latch is transparent when CS and WR are low, and the DAC latch is transparent when LD is low. The address lines (A0, A1, A2) must be valid for the duration that CS and WR are low (Figure 1), to prevent data from being inadvertently written to the wrong DAC. Data is latched within the input latch when either CS or WR is high. X FUNCTION Applications Information Digital Code and Analog Output Voltage The MAX5839 uses offset binary coding. A 13-bit two’s complement code is converted to a 13-bit offset binary code by adding 212 = 4096. Output Voltage Range For typical operation, connect DUTGND to signal ground, VREF+ to +4.5V, and VREF- to -2.0V. Table 3 shows the relationship between digital code and output voltage. The DAC digital code controls each leg of the 13-bit R-2R ladder. A code of 0x0 connects all legs of the ladder to REF-, corresponding to a DAC output voltage (VDAC) equal to REF-. A code of 0x1FFF connects all legs of the ladder to REF+, corresponding to a VDAC approximately equal to REF+. ______________________________________________________________________________________ Octal, 13-Bit Voltage-Output DAC with Parallel Interface INPUT CODE OUTPUT VOLTAGE (V) 1 1111 1111 1111 +8.998413 1 0000 0000 0000 +4.500 0 1001 1101 1001 +600µ 0 0000 0000 0001 -3.998586 0 0000 0000 0000 -4.000 Note: Output voltage is based on REF+ = +4.5V, REF- = -2.0V, and DUTGND = 0. The output amplifier multiplies VDAC by 2, yielding an output voltage range of 2 · REF- to 2 · REF+ (Figure 1). Further manipulation of the output voltage span is accomplished by offsetting DUTGND. The output voltage of the MAX5839 is described by the following equation: DATA VOUT = 2 VREF+ − VREF− + VREF− 13 2 − VOUTGND ( ) where DATA is the numeric value of the DAC’s binary input code, and DATA ranges from 0 (2 0 ) to 8191 (213 - 1). The resolution of the MAX5839, defined as 1LSB, is described by the following equation: LSB = ( 2 REF+ − REF − ) For optimum performance, use a multilayer PC board with an unbroken analog ground. For normal operation, connect the four DUTGND pins directly to the ground plane. Avoid sharing the connections of these sensitive pins with other ground traces. As with any sensitive data acquisition system, connect the digital and analog ground planes together at a single point, preferably directly underneath the MAX5839. Avoid routing digital signals underneath the MAX5839 to minimize their coupling into the IC. For normal operation, bypass VDD and VSS with 0.1µF ceramic chip capacitors to the analog ground plane. To enhance transient response and capacitive drive capability, add 10µF tantalum capacitors in parallel with the ceramic capacitors. Note, however, that the MAX5839 does not require the additional capacitance for stability. Bypass VCC with a 0.1µF ceramic chip capacitor to the digital ground plane. Power-Supply Sequencing To guarantee proper operation of the MAX5839, ensure that power is applied to VDD before VSS and VCC. Also ensure that V SS is never more than 300mV above ground. To prevent this situation, connect a Schottky diode between VSS and the analog ground plane, as shown in Figure 3. Do not power up the logic input pins before establishing the supply voltages. If this is not possible and the digital lines can drive more than 10mA, place current-limiting resistors (e.g., 470Ω) in series with the logic pins. 13 2 Reference Selection Because the MAX5839 has precision buffers on its reference inputs, the requirements for interfacing to these inputs are minimal. Select a low-drift, low-noise reference within the recommended REF+ and REF- voltage ranges. The MAX5839 does not require bypass capacitors on its reference inputs. Add capacitors only if the reference voltage source requires them to meet system specifications. VSS VSS VSS MAX5839 1N5817 Minimizing Output Glitch The MAX5839’s internal deglitch circuitry is enabled on the falling edge of LD. Therefore, to achieve optimum performance, drive LD low after the inputs are either latched or steady state. This is best accomplished by having the falling edge of LD occur at least 50ns after the rising edge of CS. GND SYSTEM GND Figure 3. Schottky Diode Between VSS and GND ______________________________________________________________________________________ 11 MAX5839 Power Supplies, Grounding, and Bypassing Table 3. Analog Voltage vs. Digital Code MAX5839 Octal, 13-Bit Voltage-Output DAC with Parallel Interface Driving Capacitive Loads The MAX5839 typically drives capacitive loads up to 0.01µF without a series output resistor. However, whenever driving high capacitive loads, it is prudent to use a 220Ω series resistor between the MAX5839 output and the capacitive load. 12 Chip Information TRANSISTOR COUNT: 10,973 ______________________________________________________________________________________ LD WR CS A0 A1 A2 GND VCC D0– D12 ADDRESS DECODE LOGIC DIGITAL POWER SUPPLY DATA REG H 13 DATA REG F 13 DATA REG G 13 DATA REG E 13 13 13 DATA REG D 13 13 13 13 13 DATA REG C 13 13 13 DATA REG B DATA R REG A 13 13 13 13 MAX5839 DAC REG H DAC REG G 13 DAC H DAC G DAC F DAC E 13 DAC REG E DAC REG F DAC D DAC C DAC B DAC A 13 13 13 13 DAC REG D DAC REG C DAC REG B DAC REG A ANALOG POWER SUPPLY VDD DUTGNDGH OUTH OUTG DUTGNDEF OUTF OUTE DUTGNDCD OUTD OUTC DUTGNDAB OUTB OUTA VSS Functional Diagram REFAB- REFAB+ REFCDEF- REFCDEF+ REFGH- REFGH+ ______________________________________________________________________________________ 13 MAX5839 CLR Octal, 13-Bit Voltage-Output DAC with Parallel Interface Octal, 13-Bit Voltage-Output DAC with Parallel Interface MQFP44.EPS MAX5839 Package Information 14 ______________________________________________________________________________________ Octal, 13-Bit Voltage-Output DAC with Parallel Interface MAX5839 NOTES ______________________________________________________________________________________ 15 MAX5839 Octal, 13-Bit Voltage-Output DAC with Parallel Interface NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.