19-1316; Rev 1; 12/97 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface ____________________________Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ______________Ordering Information ________________________Applications Industrial Process Control Digital Offset and Gain Adjustment Motion Control Remote Industrial Controls MicroprocessorControlled Systems Automatic Test Equipment (ATE) 12-Bit Dual DAC with Internal Gain of +2V/V Rail-to-Rail Output Swing 12µs Settling Time Single-Supply Operation: +5V (MAX5154) +3V (MAX5155) Low Quiescent Current: 500µA (normal operation) 2µA (shutdown mode) SPI/QSPI and Microwire Compatible Available in Space-Saving 16-Pin QSOP Package Power-On Reset Clears Registers and DACs to Zero Adjustable Output Offset PART TEMP. RANGE MAX5154ACPE MAX5154BCPE MAX5154ACEE MAX5154BCEE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP INL (LSB) ±1/2 ±1 ±1/2 ±1 Ordering Information continued at end of data sheet. Pin Configuration appears at end of data sheet. _________________________________________________________Functional Diagram DOUT CL PDL DGND AGND VDD REFA OSA DECODE CONTROL R R INPUT REG A 16-BIT SHIFT REGISTER DIN OUTA OSB DAC A R MAX5154 MAX5155 SR CONTROL CS DAC REG A LOGIC OUTPUT SCLK INPUT REG B UPO Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. DAC REG B R OUTB DAC B REFB SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 408-737-7600 ext. 3468. MAX5154/MAX5155 _______________General Description The MAX5154/MAX5155 low-power, serial, voltage-output, dual 12-bit digital-to-analog converters (DACs) consume only 500µA from a single +5V (MAX5154) or +3V (MAX5155) supply. These devices feature Rail-toRail® output swing and are available in a space-saving 16-pin QSOP package. To maximize the dynamic range, the DAC output amplifiers are configured with an internal gain of +2V/V. The 3-wire serial interface is SPI™/QSPI™ and Microwire™ compatible. Each DAC has a doublebuffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include programmable shutdown (2µA), hardware-shutdown lockout (PDL), a separate reference voltage input for each DAC that accepts AC and DC signals, and an active-low clear input (CL) that resets all registers and DACs to zero. These devices provide a programmable logic pin for added functionality, and a serial-data output pin for daisy chaining. MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 10.5mW/°C above +70°C) ...........842mW QSOP (derate 8.30mW/°C above +70°C) ...................667mW CERDIP (derate 10.00mW/°C above +70°C) ..............800mW Operating Temperature Ranges MAX515_ _C_ E .................................................0°C to +70°C MAX515_ _E_ E ..............................................-40C° to +85°C MAX515_ _MJE.............................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................±0.3V OSA, OSB to AGND........................(AGND - 4V) to (VDD + 0.3V) REF_, OUT_ to AGND.................................-0.3V to (VDD + 0.3V) Digital Inputs (SCLK, DIN, CS, CL, PDL) to DGND............................................................(-0.3V to +6V) Digital Outputs (DOUT, UPO) to DGND ................................................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................±20mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—MAX5154 (VDD = +5V ±10%, VREFA = VREFB = 2.048V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C (OS_ tied to AGND for a gain of +2V/V).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 Bits MAX5154A ±1/2 MAX5154B ±1 Integral Nonlinearity INL (Note 1) Differential Nonlinearity DNL Guaranteed monotonic ±1 Code = 6 ±6 Offset Error Offset Tempco Vos TCVos Normalized to 2.048V 4 Gain Error -0.2 Gain-Error Tempco VDD Power-Supply Rejection Ratio PSRR Normalized to 2.048V 4 4.5V ≤ VDD ≤ 5.5V 20 LSB LSB mV ppm/°C ±3 LSB ppm/°C 260 µV/V REFERENCE INPUT Reference Input Range REF Reference Input Resistance RREF 0 Minimum with code 1554 hex 14 VDD - 1.4 V 20 kΩ MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Input code = 1FFE hex, VREF_ = 0.67Vp-p at 2.5VDC 300 kHz Reference Feedthrough Input code = 0000 hex, VREF_ = (VDD - 1.4Vp-p) at 1kHz -82 dB Input code = 1FFE hex, VREF_ = 1Vp-p at 1.25VDC, f = 25kHz 75 dB Signal-to-Noise plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage VIH CL, PDL, CS, DIN, SCLK Input Low Voltage VIL CL, PDL, CS, DIN, SCLK Input Hysteresis VHYS Input Leakage Current IIN Input Capacitance CIN 2 3 V 0.8 200 VIN = 0V to VDD 0.001 8 _______________________________________________________________________________________ V mV ±1 µA pF Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface (VDD = +5V ±10%, VREFA = VREFB = 2.048V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C (OS_ tied to AGND for a gain of +2V/V).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.13 0.40 UNITS DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA VDD - 0.5 V V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 1/2LSB of full-scale, VSTEP = 4V Output Voltage Swing Rail-to-rail (Note 2) OSA or OSB Input Resistance ROS_ 24 Time Required to Exit Shutdown CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p Digital Feedthrough Digital Crosstalk 0.75 V/µs 15 µs 0 to VDD V 34 kΩ 25 µs 5 nV-s 5 nV-s POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current IDD Power-Supply Current in Shutdown 4.5 (Note 3) IDD(SHDN) (Note 3) Reference Current in Shutdown 5.5 V 0.5 0.65 mA 2 10 µA 0 ±1 µA TIMING CHARACTERISTICS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH (Note 4) 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SDI Setup Time tDS 40 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 80 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 80 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold tCS1 40 ns CS Pulse Width High tCSW 100 ns Note 1: Accuracy is specified from code 6 to code 4095. Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞. Note 4: SCLK minimum clock period includes the rise and fall times. _______________________________________________________________________________________ 3 MAX5154/MAX5155 ELECTRICAL CHARACTERISTICS—MAX5154 (continued) MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX5155 (VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C (OS_ pins tied to AGND for a gain of +2V/V).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 12 Bits MAX5155A ±1 MAX5155B ±2 Integral Nonlinearity INL (Note 5) Differential Nonlinearity DNL Guaranteed monotonic ±1 Offset Error Vos Code = 10 ±6 Offset Tempco TCVos Normalized to 1.25V 6.5 Gain Error VDD Power-Supply Rejection Ratio PSRR Normalized to 1.25V 6.5 2.7V ≤ VDD ≤ 3.6V 40 LSB mV ppm/°C -0.2 Gain-Error Tempco LSB ±4 LSB ppm/°C 320 µV/V REFERENCE INPUT (VREF) Reference Input Range REF Reference Input Resistance RREF 0 Minimum with code 1554 hex 14 VDD - 1.4 V 20 kΩ MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Input code = 1FFE hex, VREF_ = 0.67Vp-p at 0.75VDC 300 kHz Reference Feedthrough Input code = 0000 hex, VREF_ = (VDD - 1.4)Vp-p at 1kHz -82 dB Input code = 1FFE hex, VREF_ = 1Vp-p at 1VDC, f = 15kHz 73 dB Signal-to-Noise plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage VIH CL, PDL, CS, DIN, SCLK Input Low Voltage VIL CL, PDL, CS, DIN, SCLK Input Hysteresis Input Leakage Current Input Capacitance VHYS IIN 2.2 V 0.8 200 VIN = 0V to VDD 0 CIN V mV ±1 8 µA pF DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA VDD - 0.5 V 0.13 0.4 V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 1/2LSB of full-scale, VSTEP = 2.5V Output Voltage Swing Rail-to-rail (Note 6) OSA or OSB Input Resistance ROS_ 24 Time Required for Valid Operation after Shutdown Digital Feedthrough Digital Crosstalk 4 CS = VDD, fDIN = 100kHz, VSCLK = 3Vp-p 0.75 V/µs 15 µs 0 to VDD V 34 kΩ 25 µs 5 nV-s 5 nV-s _______________________________________________________________________________________ Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface (VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C (OS_ pins tied to AGND for a gain of +2V/V).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current IDD Power-Supply Current in Shutdown 2.7 (Note 7) IDD (SHDN) (Note 7) Reference Current in Shutdown 3.6 V 0.45 0.6 mA 1 8 µA 0 ±1 µA TIMING CHARACTERISTICS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH (Note 4) 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SDI Setup Time tDS 50 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 120 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 120 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold tCS1 40 ns CS Pulse Width High tCSW 100 ns Note 5: Accuracy is specified from code 10 to code 4095. Note 6: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 80mV. Guaranteed by PSRR test at the end points. Note 7: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞. _______________________________________________________________________________________ 5 MAX5154/MAX5155 ELECTRICAL CHARACTERISTICS—MAX5155 (continued) __________________________________________Typical Operating Characteristics (VDD = +5V, RL = 10kΩ, CL = 100pF, OS_ pins tied to AGND, TA = +25°C, unless otherwise noted.) MAX5154 -8 -10 -12 -14 -16 370 740 1110 1480 -40 CODE = 0000 (HEX) -60 -70 VREF = 2.048V RL = ∞ -55 -35 -15 1850 -50 5 25 45 65 -80 1 85 105 125 10 100 FREQUENCY (kHz) TEMPERATURE (°C) FREQUENCY (kHz) FULL-SCALE ERROR vs. RESISTIVE LOAD REFERENCE FEEDTHROUGH AT 1kHz SHUTDOWN CURRENT vs. TEMPERATURE 0 -0.25 -0.50 -0.75 -1.00 VREF = 3.6Vp-p @ 1.88VDC CODE = 0000 (HEX) -60 -70 -80 -90 -100 -110 -120 6 VREF = 1V 5 -130 -1.25 MAX5154/5155 toc06 0.25 -50 SHUTDOWN CURRENT (µA) VREF = 2.048V RELATIVE OUTPUT (dB) MAX5154/5155 toc04 0.50 FULL-SCALE ERROR (LSB) 550 400 -20 1 VREF = 1Vp-p @ 2.5VDC CODE = 1FFE (HEX) 450 VREF = 0.67Vp-p @ 2.5VDC CODE = 1FFE (HEX) -18 600 500 -30 THD + NOISE (dB) -6 CODE = 1FFE (HEX) 650 MAX5154/5155 toc05 RELATIVE OUTPUT (dB) -4 700 MAX5154/5155 toc02 -2 SUPPLY CURRENT (µA) MAX5154/5155toc01 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE MAX5154/5155 toc03 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE 4 3 2 1 -140 -1.50 -150 0.1 1 10 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 RL (kΩ) FREQUENCY (kHz) OUTPUT FFT PLOT DYNAMIC RESPONSE RISE TIME -55 -35 -15 MAX5154/5155 toc07 VREF = 2.45Vp-p @ 1.225VDC f = 1kHz CODE = 1FFE (HEX) -10 -20 -30 5 25 45 65 DYNAMIC RESPONSE FALL TIME MAX5154/5155 toc09 CS 5V/div CS 5V/div OUT_ 1V/div OUT_ 1V/div NOTE: RELATIVE TO FULL-SCALE -40 -50 -60 -70 -80 -90 -100 0.5 1.6 2.7 3.8 FREQUENCY (kHz) 6 85 105 125 TEMPERATURE (°C) MAX5154/5155 toc08 0 RELATIVE OUTPUT (dB) MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface 4.9 6.0 2µs/div VREF = 2.048V 2µs/div VREF = 2.048V _______________________________________________________________________________________ Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface MAX5154/MAX5155 _____________________________Typical Operating Characteristics (continued) (VDD = +3V, RL = 10kΩ, CL = 100pF, OS_pins tied to AGND, TA = +25°C, unless otherwise noted.) MAX5155 -8 -10 -12 -14 CODE = 1FFE (HEX) 520 -30 VREF = 1Vp-p @ 1VDC CODE = 1FFE (HEX) -40 THD + NOISE (dB) -6 540 VREF = 1V RL = ∞ MAX5154/5155 toc11 -4 560 SUPPLY CURRENT (µA) MAX5154/5155 toc10 0 -2 500 480 460 440 VREF = 0.67Vp-p @ 0.75VDC CODE = 1FFE -70 420 400 -20 1 320 640 960 1280 5 25 45 65 1 85 105 125 10 100 TEMPERATURE (°C) FREQUENCY (kHz) FULL-SCALE ERROR vs. RESISTIVE LOAD REFERENCE FEEDTHROUGH AT 1kHz SHUTDOWN CURRENT vs. TEMPERATURE -0.50 -0.75 -1.00 -70 -80 -90 -100 -110 -120 3.0 2.8 SHUTDOWN CURRENT (µA) -0.25 VREF = 1.6Vp-p @ 0.88VDC CODE = 0000 (HEX) -60 RELATIVE OUTPUT (dB) MAX5154/5155 toc13 0 -50 MAX5154/5155 toc14 FREQUENCY (kHz) VREF = 1.25V FULL-SCALE ERROR (LSB) -80 -55 -35 -15 1600 0.25 1 10 100 2.0 1.8 1.6 1.2 1.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT FFT PLOT DYNAMIC RESPONSE RISE TIME VREF = 1.4Vp-p @ 0.75VDC f = 1kHz CODE = 1FFE (HEX) 5 25 45 65 85 105 125 DYNAMIC RESPONSE FALL TIME MAX5154/5155 toc17 0 -55 -35 -15 TEMPERATURE (°C) FREQUENCY (kHz) -20 2.2 1.4 RL (kΩ) -10 2.4 -140 MAX5154/5155toc16 0.1 VREF = 1V RL = ∞ 2.6 -130 -150 -1.25 RELATIVE OUTPUT (dB) -60 CODE = 0000 (HEX) -16 -18 -50 MAX5154/5155 toc15 RELATIVE OUTPUT (dB) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE MAX5154/5155 toc12 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE MAX5154/5155 toc18 CS 2V/div CS 2V/div OUT_ 500mV/div OUT_ 500mV/div -30 -40 -50 -60 -70 -80 -90 -100 0.5 1.6 2.7 3.8 FREQUENCY (kHz) 4.9 2µs/div 6.0 VREF = 1.25V 2µs/div VREF = 1.25V _______________________________________________________________________________________ 7 _____________________________Typical Operating Characteristics (continued) (VDD = +5V (MAX5154), VDD = +3V (MAX5155), RL = 10kΩ, CL = 100pF, OS_ pins tied to AGND, unless otherwise noted.) MAX5154/MAX5155 0.60 MAX5154/5155toc19 0.60 MAX5155 SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.55 CODE = 1FFE (HEX) SUPPLY CURRENT (mA) CODE = 1FFE (HEX) 0.50 CODE = OOOO (HEX) 0.45 0.55 MAX5154/5155toc20 MAX5154 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT (mA) 0.50 CODE = OOOO (HEX) 0.45 0.40 0.40 4.50 4.75 5.00 5.25 5.50 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 SUPPLY VOLTAGE (V) MAX5154/5155 toc21 MAX5154 MAJOR-CARRY TRANSITION CS 2V/div OUT_ 50mV/div AC COUPLED 5µs/div TRANSITION FROM 1000 (HEX) TO 0FFE (HEX) MAX5154 ANALOG CROSSTALK MAX5154/5155 toc23 MAX5154 DIGITAL FEEDTHROUGH MAX5154/5155 toc22 MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface OUTA 5V/div OUTA 500µV/div AC COUPLED OUTB 200µV/div AC COUPLED 250µs/div 2.5µs/div VREF = 2.048V, GAIN = +2V/V, CODE = 1FFE HEX 8 SCLK 5V/div _______________________________________________________________________________________ Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface MAX5154/MAX5155 _____________________Pin Description OS_ R PIN NAME FUNCTION 1 AGND Analog Ground 2 OUTA DAC A Output Voltage 3 OSA DAC A Offset Adjustment 4 REFA Reference for DAC A 5 CL Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V. 6 CS Chip-Select Input 7 DIN Serial-Data Input 8 SCLK Serial Clock Input 9 DGND Digital Ground Figure 1. Simplified DAC Circuit Diagram 10 DOUT Serial-Data Output 11 UPO User-Programmable Output 12 PDL Power-Down Lockout. The device cannot be powered down when PDL is low. 13 REFB Reference for DAC B 14 OSB DAC B Offset Adjustment 15 OUTB DAC B Output Voltage VOUT = (VREF x NB / 4096) x 2 where NB is the numeric value of the DAC’s binary input code (0 to 4095) and VREF is the reference voltage. The reference input impedance ranges from 14kΩ (1554 hex) to several giga ohms (with an input code of 0000 hex). The reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 50pF with a full-scale input code. 16 VDD Positive Power Supply R R 2R 2R D0 _______________Detailed Description The MAX5154/MAX5155 dual, 12-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition, trimmed internal resistors produce an internal gain of +2V/V that maximizes output voltage swing. The amplifier’s offset-adjust pin allows for a DC shift in the DAC’s output. Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent full-scale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs. Reference Inputs The reference inputs accept both AC and DC values with a voltage range extending from 0V to (VDD - 1.4V). Determine the output voltage using the following equation (OS_ = AGND): R 2R D9 OUT_ R 2R 2R D10 D11 REF_ AGND SHOWN FOR ALL 1s ON DAC Output Amplifier The output amplifiers on the MAX5154/MAX5155 have internal resistors that provide for a gain of +2V/V when OS_ is connected to AGND. These resistors are trimmed to minimize gain error. The output amplifiers have a typical slew rate of 0.75V/µs and settle to 1/2LSB within 15µs, with a load of 10kΩ in parallel with 100pF. Loads less than 2kΩ degrade performance. The OS_ pin can be used to produce an adjustable offset voltage at the output. For instance, to achieve a 1V offset, apply -1V to the OS_ pin to produce an output range from 1V to (1V + VREF x 2). Note that the DAC’s output range is still limited by the maximum output voltage specification. Power-Down Mode The MAX5154/MAX5155 feature a software-programmable shutdown mode that reduces the typical supply current to 2µA. The two DACs can be shutdown independently, or simultaneously using the appropriate programming command. Enter shutdown mode by writing the appropriate input-control word (Table 1). In shutdown mode, the reference inputs and amplifier out- puts become high impedance, and the serial interface remains active. Data in the input registers is _______________________________________________________________________________________ 9 MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD D11.......................D0 (MSB) (LSB) FUNCTION A0 C1 C0 S0 0 0 1 12-bit DAC data 0 Load input register A; DAC registers are unchanged. 1 0 1 12-bit DAC data 0 Load input register B; DAC registers are unchanged. 0 1 0 12-bit DAC data 0 Load input register A; all DAC registers are updated. 1 1 0 12-bit DAC data 0 Load input register B; all DAC registers are updated. 0 1 1 12-bit DAC data 0 Load all DAC registers from the shift register (start up both DACs with new data.). 1 0 0 xxxxxxxxxxxx 0 Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). 1 1 1 xxxxxxxxxxxx 0 Shut down both DACs (provided PDL = 1). 0 0 0 0 0 1 x xxxxxxxx 0 Update DAC register A from input register A (start up DAC A with data previously stored in input register A). 0 0 0 1 0 1 x xxxxxxxx 0 Update DAC register B from input register B (start up DAC B with data previously stored in input register B). 0 0 0 1 1 0 x xxxxxxxx 0 Shut down DAC A (provided PDL = 1). 0 0 0 1 1 1 x xxxxxxxx 0 Shut down DAC B (provided PDL = 1). 0 0 0 0 1 0 x xxxxxxxx 0 UPO goes low (default). 0 0 0 0 1 1 x xxxxxxxx 0 UPO goes high. 0 0 0 1 0 0 1 xxxxxxxx 0 Mode 1, DOUT clocked out on SCLK’s rising edge. 0 0 0 1 0 0 0 xxxxxxxx 0 Mode 0, DOUT clocked out on SCLK’s falling edge (default). 0 0 0 0 0 0 x xxxxxxxx 0 No operation (NOP). x = Don’t care Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub bit, always zero. MAX5154 MAX5155 SCLK SK DIN SO CS Figure 2. Connections for Microwire 10 I/O MICROWIRE PORT saved, allowing the MAX5154/MAX5155 to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting shutdown), wait 20µs for output stabilization. Serial Interface The MAX5154/MAX5155 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word consists of an address bit, two control bits, 12 bits of data (MSB to LSB), and one sub bit as shown in Figure 4. The address and control bits determine the MAX5154/ MAX5155’s response, as outlined in Table 1. ______________________________________________________________________________________ Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface SS DIN MAX5154 MAX5155 MOSI SCLK SCK CS SPI/QSPI PORT I/O CPOL = 0, CPHA = 0 Figure 3. Connections for SPI/QSPI The general timing diagram of Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 10MHz. Figure 6 depicts a more detailed timing diagram of the serial interface. MSB...................................................................................LSB 16 Bits of Serial Data Address Bits Control Bits MSB...DataBits...LSB SUB BIT A0 C1, C0 D11.......................D0 S0 12 Data Bits 0 1 Address/2 Control Bits Figure 4. Serial-Data Format CS COMMAND EXECUTED SCLK 1 DIN A0 8 C1 C0 D11 D10 D9 D8 D7 9 D6 16 D5 D4 D3 D2 D1 D0 S0 Figure 5. Serial-Interface Timing Diagram ______________________________________________________________________________________ 11 MAX5154/MAX5155 The MAX5154/MAX5155’s digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow the DACs to act independently. Send the 16-bit data as one 16-bit word (QSPI) or two 8-bit packets (SPI, Microwire), with CS low during this period. The address and control bits determine which register will be updated, and the state of the registers when exiting shutdown. The 3-bit address/control determines the following: • registers to be updated • clock edge on which data is to be clocked out via the serial-data output (DOUT) • state of the user-programmable logic output • configuration of the device after shutdown. +5V MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface tCSW CS tCSS tCSO tCL tCP tCH tCSH tCS1 SCLK tDS tDH DIN Figure 6. Detailed Serial-Interface Timing Diagram SCLK SCLK MAX5154 MAX5155 DIN SCLK MAX5154 MAX5155 DOUT CS DIN MAX5154 MAX5155 DOUT CS DIN DOUT CS TO OTHER SERIAL DEVICES Figure 7. Daisy Chaining MAX5154/MAX5155s DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS MAX5154 MAX5155 CS MAX5154 MAX5155 MAX5154 MAX5155 SCLK SCLK SCLK DIN DIN DIN Figure 8. Multiple MAX5154/MAX5155s Sharing a Common DIN Line 12 ______________________________________________________________________________________ Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface User-Programmable Logic Output (UPO) UPO allows an external device to be controlled through the serial interface (Table 1), thereby reducing the number of microcontroller I/O pins required. On powerup, UPO is low. PDL) Power-Down Lockout Input (P The power-down lockout pin (PDL) disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to asynchronously wake up the device. Daisy Chaining Devices Any number of MAX5154/MAX5155s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). Since the MAX5154/MAX5155’s DOUT pin has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the digital output VOH and VOL specifications in the Electrical Characteristics. Figure 8 shows an alternate method of connecting several MAX5154/MAX5155s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC. __________Applications Information OS_ +5V/+3V REF_ VDD R MAX5154 MAX5155 R DAC_ OUT_ AGND DGND GAIN = +2V/V Figure 9. Unipolar Output Circuit (Rail-to-Rail) OS_ +5V/+3V REF_ VOS VDD R MAX5154 MAX5155 R DAC _ OUT_ AGND DGND Figure 10. Setting OS_ for Output Offset Table 2. Unipolar Code Table (Gain = +2) DAC CONTENTS MSB LSB ANALOG OUTPUT 1 1 1 1 1 1 1 1 11 1 1 ( 0 ) +V 4095 x 2 1 0 0 0 0 0 0 0 00 0 1 ( 0 ) +V 2049 x 2 REF 4096 REF 4096 Unipolar Output Figure 9 shows the MAX5154/MAX5155 configured for unipolar, rail-to-rail operation with a gain of +2V/V. The MAX5154 can produce a 0V to 4.096V output with 2.048V reference (Figure 9), while the MAX5155 can produce a range of 0V to 2.5V with a 1.25V reference. Table 2 lists the unipolar output codes. An offset to the output can be achieved by connecting a voltage to OS_, as shown in Figure 10. By applying VOS_ = -1V, the output values will range between 1V and (1V + VREF x 2). MAX5154/MAX5155 Serial-Data Output The serial-data output, DOUT, is the internal shift register’s output. DOUT allows for daisy chaining of devices and data readback. The MAX5154/MAX5155 can be programmed to shift data out of DOUT on SCLK’s falling edge (Mode 0) or on the rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which maintains compatibility with SPI/QSPI and Microwire interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0. 1 0 0 0 0 0 0 0 00 0 0 ( 0 ) +V 2048 x 2 = V REF 4096 REF 0 1 1 1 1 1 1 1 11 1 1 ( 0 ) +V 2047 x 2 0000 0000 0001 (0) +V 0 0 0 0 0 0 0 0 00 0 0 ( 0 ) REF 4096 1 x 2 REF 4096 0V Note: ( ) are for the sub bit. ______________________________________________________________________________________ 13 MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface Table 3. Bipolar Code Table DAC CONTENTS MSB LSB +5V/ +3V +5V/+3V ANALOG OUTPUT 26k AC REFERENCE INPUT 1111 1111 1 111 (0) 2047 +VREF 2048 1000 0000 0 001 (0) 1 +VREF 2048 1000 0000 0 000 (0) 0V 0111 1111 1 111 (0) 1 -VREF 2048 0000 0000 0 001 (0) 2047 -VREF 2048 0000 0000 0 000 (0) 2048 -VREF = - VREF 2048 500mVp-p MAX495 10k VDD REF R OS_ R OUT_ DAC_ MAX5154 MAX5155 AGND DGND Figure 12. AC Reference Input Circuit Note: ( ) are for the sub bit. V+ +5V/+3V REF_ 10k REF_ 10k PHOTODIODE +5V/+3V OS_ VDD OS_ VDD R R MAX5154 MAX5155 V+ MAX5154 MAX5155 R VOUT 10k DAC _ OUT_ DGND AGND R 10k V- VOUT OUT_ µP DAC _ V- DIN AGND DGND RPULLDOWN Figure 13. Digital Calibration Figure 11. Bipolar Output Circuit Bipolar Output The MAX5154/MAX5155 can be configured for a bipolar output, as shown in Figure 11. The output voltage is given by the equation (OS_ = AGND): VOUT = VREF [((2 x NB) / 4096) - 1] where NB represents the numeric value of the DAC’s binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11’s circuit. Using an AC Reference In applications where the reference has an AC signal component, the MAX5154/MAX5155 have multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for apply14 V+ ing a sinusoidal input to REF_, where the AC signal is offset before being applied to the reference input. Harmonic Distortion and Noise The total harmonic distortion plus noise (THD+N) is typically less than -78dB at full scale with a 1Vp-p input swing at 5kHz. The typical -3dB frequency is 300kHz for both devices, as shown in the Typical Operating Characteristics. Digital Calibration and Threshold Selection Figure 13 shows the MAX5154/MAX5155 in a digital calibration application. With a bright light value applied to the photodiode (on), the DAC is digitally ramped until ______________________________________________________________________________________ Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface MAX5154/MAX5155 VDD OSA VIN REFA R OUTA CS SCLK DIN VREF R MAX5154 MAX5155 SHIFT REGISTER INPUT REG A DAC REG A DACA INPUT REG B DAC REG B DACB R1 R2 OUTB REFB VOUT R3 R4 R R [ ] [ ] = (V 2NA )( R2 )(1+ R4 ) (V [ 4096 R1+R2 R3 ] [ VOUT = GAIN – OFFSET OSB IN AGND DGND REF 2NB 4096 )( R4R3 )] NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB. Figure 14. Digital Control of Gain and Offset it trips the comparator. The microprocessor (µP) stores this “high” calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The µP then programs the DAC to set an output voltage at the midpoint of the two calibrated values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis. Digital Control of Gain and Offset The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14). Power-Supply Considerations On power-up, the input and DAC registers clear (set to zero code). For rated performance, VREF_ should be at least 1.4V below VDD. Bypass the power supply with a 4.7µF capacitor in parallel with a 0.1µF capacitor to AGND. Minimize lead lengths to reduce lead inductance. Grounding and Layout Considerations Digital and AC transient signals on AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. ______________________________________________________________________________________ 15 __________________Pin Configuration TOP VIEW AGND 1 16 VDD OUTA 2 15 OUTB OSA 3 14 OSB REFA 4 CL 5 MAX5154 MAX5155 13 REFB 12 PDL CS 6 11 UPO DIN 7 10 DOUT 9 SCLK 8 DGND DIP/QSOP ___________________Chip Information TRANSISTOR COUNT: 3053 _Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX5154AEPE MAX5154BEPE MAX5154AEEE MAX5154BEEE MAX5154BMJE MAX5155ACPE MAX5155BCPE MAX5155ACEE MAX5155BCEE MAX5155AEPE MAX5155BEPE MAX5155AEEE MAX5155BEEE MAX5155BMJE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP* 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP* INL (LSB) ±1/2 ±1 ±1/2 ±1 ±1 ±1 ±2 ±1 ±2 ±1 ±2 ±1 ±2 ±2 *Contact factory for availability. SUBSTRATE CONNECTED TO AGND ________________________________________________________Package Information QSOP.EPS MAX5154/MAX5155 Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.