FUJITSU MB82DBS08164D-70L

FUJITSU MICROELECTRONICS
DATA SHEET
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MEMORY Mobile FCRAMTM
CMOS
128 M Bit (8 M word×16 bit)
Mobile Phone Application Specific Memory
MB82DBS08164D-70L
■ DESCRIPTION
The FUJITSU MICROELECTRONICS MB82DBS08164D is a CMOS Fast Cycle Random Access Memory
(FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 134,217,728 storages
accessible in a 16-bit format.
The MB82DBS08164D adopts asynchronous mode and synchronous burst mode for fast memory access as user
configurable options.
The MB82DBS08164D is suited for mobile applications such as Cellular Handset and PDA.
* : FCRAM is a trademark of Fujitsu Microelectronics Limited, Japan
■ FEATURES
• Asynchronous SRAM Interface
• COSMORAM Revision 3 Compliance
(COSMORAM : Common Specifications of Mobile RAM)
• Fast Access Time : tCE = 70 ns Max
• Burst Read/Write Access Capability :
tCK = 13 ns Min /77 MHz Max
tAC = 6 ns Max
• Low Voltage Operating Condition : VDD = 1.7 V to 1.95 V
• Wide Operating Temperature : TA = 0 °C to + 70 °C
• Byte Control by LB and UB
• Low-Power Consumption : IDDA1 = 35 mA Max
IDDS1 = 200 μA Max (TA ≤ + 40 °C)
• Various Power Down mode : Sleep
16 M-bit Partial
32 M-bit Partial
64 M-bit Partial
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.10
MB82DBS08164D-70L
■ PIN ASSIGNMENT
(TOP VIEW)
A
B
8
NC
NC
7
NC
NC
D
E
F
G
H
J
A15
A21
A22
A16
NC
VSS
A11
A12
A13
A14
NC
DQ15
DQ7
6
A8
A19
A9
A10
DQ6
DQ13 DQ12
DQ5
5
WE
CE2
A20
DQ4
VDD
NC
4
CLK
ADV WAIT
DQ3
VDD
DQ11
3
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
A3
A2
A1
A0
NC
CE1
2
NC
1
NC
NC
C
K
DQ14
L
M
NC
NC
NC
NC
NC
NC
NC
NC
(BGA-71P-M03)
■ PIN DESCRIPTION
Pin Name
A22 to A0
2
Description
Address Input
CE1
Chip Enable 1 (Low Active)
CE2
Chip Enable 2(High Active)
WE
Write Enable (Low Active)
OE
Output Enable (Low Active)
LB
Lower Byte Control (Low Active)
UB
Upper Byte Control (Low Active)
CLK
Clock Input
ADV
Address Valid Input (Low Active)
WAIT
Wait Output
DQ7 to DQ0
Lower Byte Data Input/Output
DQ15 to DQ8
Upper Byte Data Input/Output
VDD
Power Supply Voltage
VSS
Ground
NC
No Connection
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MB82DBS08164D-70L
■ BLOCK DIAGRAM
VDD
VSS
A22 to A0
CLK
WAIT
DQ15 to DQ8
COMMAND
DECODER
BURST
ADDRESS
COUNTER
MEMORY
CELL
ARRAY
134,217,728 bits
ADDRESS
CONTROLLER
MEMORY
CORE
CONTROLLER
BURST
CONTROLLER
X CONTROLLER
MODE
CONTROLLER
CE2
CE1
ADV
WE
OE
LB
UB
Y CONTROLLER
ADDRESS
LATCH &
BUFFER
READ
AMP
WRITE
AMP
BUS
CONTROLLER
I/O
BUFFER
DQ7 to DQ0
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MB82DBS08164D-70L
■ FUNCTION TRUTH TABLE
1. Asynchronous Operation
Mode
Standby
(Deselect)
CE2 CE1 CLK ADV
H
H
WE
OE
LB
UB A22 to A0 DQ7 to DQ0 DQ15 to DQ8
WAIT
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
Output Disable*1
X
*3
H
H
X
X
*5
High-Z
High-Z
High-Z
Output Disable
(No Read)
X
*3
H
H
Valid
High-Z
High-Z
High-Z
Read (Upper Byte)
X
*3
H
L
Valid
High-Z
Output
Valid
High-Z
H
L
X
*3
L
H
Valid
Output
Valid
High-Z
High-Z
X
*3
L
L
Valid
Output
Valid
Output
Valid
High-Z
No Write
X
*3
H
H
Valid
Invalid
Invalid
High-Z
Write (Upper Byte)
X
*3
H
L
Valid
Invalid
Write (Lower Byte)
X
*3
L
H
Valid
Input
Valid
Write (Word)
X
*3
L
L
Valid
Input
Valid
X
X
X
X
X
High-Z
Read (Lower Byte)
Read (Word)
Power Down*2
H
L
L
X
L
X
H*4
X
Input Valid High-Z
Invalid
High-Z
Input Valid High-Z
High-Z
High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
*1 : Should not be kept this logic condition longer than 1 μs.
*2 : Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in
"■FUNCTIONAL DESCRIPTION" for the details.
*3 : "L" for address pass through and "H" for address latch on the rising edge of ADV.
*4 : OE can be VIL during write operation if the following conditions are satisfied;
(1) Write pulse is initiated by CE1. Refer to "(12) Asynchronous Read/Write Timing 1-1 (CE1 Control)" in
"■TIMING DIAGRAMS".
(2) OE stays VIL during Write cycle.
*5 : Can be either VIL or VIH but must be valid before Read or Write.
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MB82DBS08164D-70L
2. Synchronous Operation (Burst Mode)
Mode
CE2 CE1
Standby(Deselect)
CLK
ADV
WE
OE
LB
X
X
X
X
X
L
X*4
X*6
H
Start Address Latch*1
*3
Advance Burst Read to
Next Address*1
*3
Burst Read
Suspend*1
X
L
*3
High-Z
High-Z
Valid*8
High-Z*9
Output
Invalid
L
Output
Valid*10
Output
Valid
H
High-Z
High*12
Input
Valid*11
High*13
Input
Invalid
High*12
X*7
Advance Burst Write to
Next Address*1
*3
H
X*7
L*5
X
H
1
3
5
*
WAIT
X
H
H
Burst Write Suspend*
UB A22 to A0 DQ15 to DQ0
H*
Terminate Burst Read
X
H
X
High-Z
High-Z
Terminate Burst Write
X
X
H
High-Z
High-Z
X
X
High-Z
High-Z
Power Down*
2
L
X
X
Note : L = VIL, H = VIH, X can be either VIL or VIH,
X
X
X
X
= valid edge, High-Z = High impedance
*1
: Should not be kept this logic condition longer than 8 μs.
*2
: Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program.
Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details.
*3
: CLK must be started and stable prior to memory access.
*4
: Can be VIH for the burst write operation in "WE Level Control" mode but must be VIL for the burst write
operation in "WE Single Clock Pulse Control" mode. WE must be VIH for the burst read operation.
*5
: When device is operating in "WE Single Clock Pulse Control" mode, WE is a “don't care” once write operation
is determined by WE Low Pulse at the beginning of write access together with address latching. Burst write
suspend feature is not supported in "WE Single Clock Pulse Control" mode.
*6
: Can be VIL for the burst read operation but must be VIH for the burst write operation.
*7
: Can be either VIL or VIH. During burst write operation, byte write control by LB and UB can be performed at
each clock cycle. During read operation, LB and UB must be valid before read operation is initiated. And once
LB and UB input levels are determined, they must not be changed until the end of burst read.
*8
: Once a valid address is determined, the input address must not be changed during ADV = L.
*9
: If OE = L, data output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L,
data input is Invalid. If OE = WE = H, data output is High-Z.
*10 : Data output is either Valid or High-Z depending on the level of LB and UB input.
*11 : Data input is either Valid or Invalid depending on the level of LB and UB input.
*12 : Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in
"■FUNCTIONAL DESCRIPTION" for the details.
*13 : WAIT output is driven in High level during burst write operation.
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MB82DBS08164D-70L
■ STATE DIAGRAM
• Initial/Standby State
Asynchronous Operation
CR Verify
Power Up
@M = 1
CE2 = H
CE2 = L
Common State
CR Set
Pause Time
Power
Down
Synchronous Operation
(Burst Mode)
Power
Down
CE2 = H
@M = 0
Standby
Standby
CE2 Low Pulse
@RA = 0
CE2 = L
@RA = 1
• Asynchronous Operation
Standby
CE1 = L
CE1 = L &
WE = L
Output
Disable
CE1 = H
Byte
Control
CE1 = L &
OE = L
CE1 = H
CE1 = H
WE = H
Address Change
or Byte Control
OE = L
WE = L
OE = H
Write
Read
Byte Control @OE = L
• Synchronous Operation
Standby
CE1 = H
CE1 = H
CE1 = H
Write
Suspend
CE1 = H
CE1 = L &
ADV = L &
CLK =
WE = H
WE = L
WE = L
Write
Address
Latch
Read
Suspend
OE = H
OE = L
OE = L
Read
* : Assuming WE Level Control
Note : Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the "■ FUNCTION
TRUTH TABLE", "■ FUNCTIONAL DESCRIPTION", "2. AC Characteristics" in "■ ELECTRICAL CHARACTERISTICS", and "■TIMING DIAGRAMS" for details.
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MB82DBS08164D-70L
■ FUNCTIONAL DESCRIPTION
This device supports asynchronous read & write operation and synchronous burst read and burst write operations
for faster memory access and features four kinds of power down modes for power saving as user configurable
option.
• Power-up
It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing".
After Power-up, the device defaults to asynchronous read & write operation mode with sleep power down feature.
• Configuration Register
The Configuration Register(CR) is used to configure the type of device function among optional features. Each
selection of features is set through CR Set sequence after power-up. If CR Set sequence is not performed after
power-up, the device is configured for asynchronous operations with sleep power down feature as default
configuration. The content of CR can be confirmed using CR Verify sequence.
• CR Set & Verify Sequence
The CR Set and CR Verify requires total 6 read/write operations with unique address and data. The device
should be in standby mode in the interval between each read/write operation. The following table shows the
detail sequence of CR Set and CR Verify.
Cycle #
Address
1st
CR Set
CR Verify
Operation
Data
Operation
Data
7FFFFFh (MSB)
Read
Read Data (RDa)
Read
Read Data (RDa)
2nd
7FFFFFh
Write
RDa
Write
RDa
3rd
7FFFFFh
Write
RDa
Write
RDa
4th
7FFFFFh
Write
CR Key 0
Write
CR Key 0
5th
7FFFFFh
Write
CR Key 1
Read
CR Key 1
6th
7FFFFFh
Write
CR Key 2
Read
CR Key 2
The 1st cycle is to read from most significant address(MSB).
The 2nd and 3rd cycles are to write to MSB. If the 2nd or 3rd cycle is written into the different address, the CR
Set is cancelled and the data written by the 2nd or 3rd cycle is valid as a normal write operation. It is recommended
to write back the data(RDa) read by 1st cycle to MSB in order to secure the data.
The 4th cycle is to write the appropriate “CR Key 0” to select the CR Set or CR Verify.
The 5th and 6th cycles are to access into MSB to set the “CR Keys” or to verify the “CR Keys”. Refer to the "CR
Key Table". If the 4th to 6th cycles are not access into MSB , the CR Set or CR Verify are cancelled and CR
input or output data will be invalid.
Once this CR Set sequence is performed from an initial CR Set to the other new CR Set, the written data stored
in the memory cell array may be lost. Therefore CR Set sequence should be performed prior to regular read/
write operation if necessary to change from the default configuration.
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MB82DBS08164D-70L
• CR Key Table
CR Key 0
CR Key 0 should be set at 4th cycle of the CR Set or Verify sequence.
Register
Pin Name
Function
Key
Name
Description
Note
0
CR Verify
1
CR Set
⎯
1
Reserved for future use
*1
⎯
1
Unused bits must be 1
*2
DQ0
CRSV
CR Set/Verify
DQ7 to DQ1
⎯
DQ15 to DQ8
⎯
CR Key 1
CR Key 1 should be set or read at 5th cycle of the CR Set or Verify sequence.
Register
Pin Name
Function
Key
Description
Name
DQ1, DQ0
PS
Partial Size
00
32M-bit Partial
*3
01
16M-bit Partial
*3
10
64M-bit Partial
*3
11
Sleep [Default]
*3
Reserved for future use
*1
000, 001
DQ4 to DQ2
DQ5
DQ7, DQ6
DQ15 to DQ8
8
BL
M
DS
⎯
Burst Length
010
8 words
011
16 words
100
32 words
101
64 words
110
128 words
111
Reserved for future use
*1
0
Synchronous Mode
(Burst Read/Write)
*4
1
Asynchronous Mode [Default]
(Random Read/Write)
*5
00
+
01
Reserved for future use
10
−
11
Center [Default]
1
Unused bits must be 1
Mode
Driver Size
⎯
Note
*1
*2
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MB82DBS08164D-70L
CR Key 2
CR Key 2 should be set or read at 6th cycle of the CR Set or Verify sequence.
Register
Pin Name
Function
Key
Description
Name
000, 001
DQ2 to DQ0
RL
Read Latency
Reserved for future use
010
4 clocks
011
5 clocks
100
6 clocks
101 to 111 Reserved for future use
Note
*1
*1
DQ3
⎯
⎯
1
Reserved for future use
*2
DQ4
⎯
⎯
0
Reserved for future use
*6
DQ5
⎯
⎯
1
Reserved for future use
*2
DQ6
RA
Reset to Asynchronous
0
Reset to Asynchronous mode
*7
1
Remain the previous mode
*3
0
WE Single Clock Pulse Control
without Write Suspend Function
1
WE Level Control
with Write Suspend Function
1
Unused bits must be 1
DQ7
DQ15 to DQ8
WC
Write Control
⎯
⎯
*2
*1 : It is prohibited to apply this key.
*2 : Must be set to “1”.
*3 : Sleep and Partial power down mode are effective only when RA = 1.
*4 : If M = 0, all the registers must be set with appropriate Key input at the same time.
*5 : If M = 1, PS and DS must be set with appropriate Key input at the same time. Except for PS and DS, all the
other key inputs must be “1”.
*6 : Must be set to "0".
*7 : In case of RA = 0, CE2 brought to Low reset the device to asynchronous standby state regardless PS set
value therefore Sleep and Partial power down mode are not available.
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MB82DBS08164D-70L
• Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode
and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down
mode.
This device has four power down modes, Sleep, 16 M-bit Partial, 32 M-bit Partial, and 64 M-bit Partial. Those
power down modes are effective when RA = 1. The selection of power down mode is set through CR Set
sequence. Each mode has following data retention features.
Mode
Data Retention Size
Retention Address
Sleep [default]
No
N/A
16 M-bit Partial
16 M bits
000000h to 0FFFFFh
32 M-bit Partial
32 M bits
000000h to 1FFFFFh
64 M-bit Partial
64 M bits
000000h to 3FFFFFh
The default state is Sleep and it is the lowest power consumption. However all data will be lost once CE2 is
brought to Low for Power Down. It is not required to perform CR Set sequence to set to Sleep mode after powerup in case of asynchronous operation.
When RA = 0, CE2 brought to Low reset the device to asynchronous standby state regardless PS set value.
• Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that synchronized to the microcontroller
or system bus frequency. Configuration Register(CR) Set is required to perform a burst read & write operation
after power-up. Once CR Set sequence is performed to select the synchronous burst mode, the device is
configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through
CR Set sequence together with the operation mode.
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MB82DBS08164D-70L
• Burst Read Operation
CLK
Address
Valid address
ADV
CE1
OE
WE
High
RL
DQ
High-Z
WAIT
High-Z
Q1
Q2
QBL
BL
• Burst Write Operation
CLK
Address
Valid address
ADV
CE1
OE
High
WE
RL-1
DQ
High-Z
D1
D2
DBL
BL
WAIT
High-Z
• CLK Input Function
The CLK is input signal to synchronize the memory to the microcontroller or system bus frequency during
synchronous burst read & write operation. The CLK input increments the device internal address counter and
the valid edge of CLK is referred for latency counts from address latch, burst write data latch, and the burst read
data output. During synchronous operation mode, CLK input must be supplied except for standby state and
power down state. CLK is a “don't care” during asynchronous operation.
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MB82DBS08164D-70L
• ADV Input Function
The ADV is input signal to latch the valid address. It is applicable to the synchronous operation as well as
asynchronous operation. ADV input is active during CE1 = L and CE1 = H disables ADV input.
During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to
High after the valid address latch, it is inhibited to bring ADV Low until the end of burst or until the burst operation
is terminated. ADV Low pulse is mandatory for the synchronous burst read/write operation mode to latch the
valid address input.
During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during
asynchronous operations and it is not necessary to control ADV to High.
• WAIT Output Function
The WAIT is output signal to indicate the data bus status when the device is operating in the synchronous burst
mode.
During burst read operation, WAIT output is enabled after specified time duration from CE1 = L. WAIT output
Low indicates data output at next clock cycle is invalid, and WAIT output becomes High one clock cycle prior to
valid data output. During OE read suspend, WAIT output doesn’t indicate the data bus status but carries the
same level from previous clock cycle (kept High).
During burst write operation, WAIT output is enabled after specified time duration from CE1 = L. WAIT output to
High level after specified time duration from WE = L or CE1 = L whichever occurs last and kept High for entire
write cycles including WE write suspend. The actual write data latching starts on the appropriate clock edge
with respect to Read Latency, and Burst Length. During WE write suspend, WAIT output doesn’t indicate the
data bus status but carries the same level from previous clock cycle (kept High).
This device doesn’t incur additional output delay against internal refresh operation. Therefore, the burst operation
is always started after the fixed latency with respect to Read Latency. And there is no waiting cycle asserted in
the middle of burst operation except for the burst read or write suspend by OE brought to High or WE brought
to High. Thus, once WAIT output is enabled and brought to High, WAIT output keeps High level until the end of
burst or until the burst operation is terminated.
When the device is operating in the asynchronous mode, WAIT output is always in High Impedance.
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MB82DBS08164D-70L
• Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through CR Set sequence after power-up. Once
specific RL is set through CR Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1.
The burst operation is always started after the fixed latency with respect to Read Latency set in CR.
CLK
0
Address
1
2
3
4
5
6
7
Valid address
ADV
CE1
OE or WE
RL = 4
DQ [Output]
WAIT
Q2
Q3
Q4
D2
D3
D4
D5
Q1
Q2
Q3
D2
D3
D4
Q1
Q2
D2
D3
High-Z
DQ [Input]
WAIT
Q1
D1
High-Z
RL = 5
DQ [Output]
WAIT
High-Z
DQ [Input]
WAIT
D1
High-Z
RL = 6
DQ [Output]
WAIT
High-Z
DQ [Input]
WAIT
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High-Z
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MB82DBS08164D-70L
• Address Latch by ADV
The ADV latches the valid address presence on address inputs. During synchronous burst read/write operation
mode, all the addresses are determined on first rising edge when ADV = CE1 = L. The specified minimum value
of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied for
appropriate RL counts. Valid address must be determined with specified setup time against valid clock edge.
And the determined valid address must not be changed during ADV = L period.
• Burst Length
Burst Length is the number of word to be read or written during synchronous burst read/write operation as the
result of a single address latch cycle. It can be set on 8, 16, 32, 64, 128 words boundary for entire address
through CR Set sequence. The burst type is sequential that is incremental decoding scheme within a boundary
address. Starting from an initial address being latched, the device internal address counter assigns +1 to the
previous address until reaching the end of boundary address and then wrap round to least significant address
(= 0). After completing read data output or write data latch for the set burst length, operation automatically ended.
• Write Control
The device has two types of WE signal control method, "WE Level Control" and "WE Single Clock Pulse Control",
for synchronous burst write operation. It is configured through CR Set sequence. When device is operating in
"WE Single Clock Pulse Control" mode, burst write operation is determined by WE = L at the rising edge of CLK.
In case of "WE Level Control", WE can be High at address latching and WE = L enables burst write operation.
CLK
0
Address
1
2
3
4
5
D1
D2
D3
D4
D1
D2
D3
D4
6
7
Valid address
ADV
RL = 5
CE1
WE Level WAIT
Control
tWLD
WE
DQ [Input]
tWLTH
WAIT
High-Z
WE Single Clock Pulse Control
tWSCK
WE
tCKWH
DQ [Input]
WAIT
14
High-Z
tCLTH
tWLTH
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MB82DBS08164D-70L
• Burst Read Suspend
Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High
suspends the burst read operation. Once OE is brought to High with the specified setup time against clock where
the data being suspended, the device internal counter is suspended, and the data output becomes high impedance after specified time duration. It is inhibited to suspend the first data output at the beginning of burst read.
OE brought to Low resumes the burst read operation. Once OE is brought to Low, data output becomes valid
after specified time duration, and the internal address counter is reactivated. The last data output being suspended as the result of OE = H and first data output as the result of OE = L are from the same address.
In order to guarantee to output last data before suspension and first data after resumption, the specified minimum
value of OE = L hold time and setup time against clock edge must be satisfied respectively.
CLK
tCKOH tOSCK
tCKOH tOSCK
OE
tOHZ
tAC
Q1
DQ
tAC
Q2
tCKQX
tCKTV
tAC
tAC
Q2
Q4
Q3
tCKQX
tCKQX
WAIT
• Burst Write Suspend
Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High
suspends the burst write operation. Once WE is brought to High with the specified setup time against clock
where the data being suspended, the device internal counter is suspended, data input is ignored. It is inhibited
to suspend the first data input at the beginning of burst write.
WE brought to Low resumes the burst write operations. Once WE is brought to Low, data input becomes valid
after specified time duration, and the internal address counter is reactivated. The write address of the cycle
where data being suspended and the first write address as the result of WE = L are the same address.
In order to guarantee to latch the last data input before suspension and first data input after resumption, the
specified minimum value of WE = L hold time and setup time against clock edge must be satisfied respectively.
Burst write suspend function is available only when the device is operating in WE level controlled burst write.
CLK
tCKWH tWSCK
tCKWH tWSCK
WE
tDSCK
tDSCK
D1
DQ
tDHCK
WAIT
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D2
tDSCK
D2
tDHCK
tDSCK
D3
D4
tDHCK
High
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MB82DBS08164D-70L
• Burst Read Termination
Burst read operation can be terminated by CE1 brought to High. It is inhibited to terminate the burst read before
first data output is completed. In order to guarantee last data output, the specified minimum value of CE1 = L
hold time from the clock edge must be satisfied. After termination, the specified minimum recovery time is required
to start a new access.
CLK
Vaild
Address
ADV
tCP
tCKCLH
tCHZ
tCKOH
tOHZ
CE1
OE
WAIT
DQ
High-Z
tCHTZ
Q2
Q1
Q1
tCKQX
tAC
tCKQX
tAC
• Burst Write Termination
Burst write operation can be terminated by CE1 brought to High. It is inhibited to terminate the burst write before
first data input is completed. In order to guarantee last write data being latched, the specified minimum values
of CE1 = L hold time from the clock edge must be satisfied. After termination, the specified minimum recovery
time is required to start a new access.
CLK
Vaild
Address
ADV
tCP
tCHCK
tCKCLH
CE1
tCKWH
WE
WAIT
tDSCK
tCHTZ
tDSCK
High-Z
tDSCK
DQ
D1
tDHCK
16
D2
tDHCK
D1
tDHCK
DS05-11454-1E
MB82DBS08164D-70L
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min
Max
VDD
− 0.5
+ 2.3
V
VIN, VOUT
− 0.5
+ 2.3
V
Short Circuit Output Current
IOUT
− 50
+ 50
mA
Storage Temperature
TSTG
− 55
+ 125
°C
Voltage of VDD Supply Relative to VSS *
Voltage at Any Pin Relative to VSS *
* : All voltages are referenced to VSS = 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Max
VDD
1.7
1.95
V
VSS
0
0
V
High Level Input Voltage* *
VIH
VDD × 0.8
VDD + 0.2
V
Low Level Input Voltage*1, *3
VIL
− 0.3
VDD × 0.2
V
Ambient Temperature
TA
0
+ 70
°C
Power Supply Voltage*1
Ground
1, 2
*1 : All voltages are referenced to VSS = 0 V.
*2 : Maximum DC voltage on input and I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to
VDD + 1.0 V for the periods of up to 5 ns.
*3 : Minimum DC voltage on input and I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to
-1.0 V for the periods of up to 5 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
■ PIN CAPACITANCE
(f = 1 MHz, TA = +25 °C)
Value
Symbol
Test
conditions
Min
Typ
Max
Address Input Capacitance
CIN1
VIN = 0 V
⎯
⎯
5
pF
Control Input Capacitance
CIN2
VIN = 0 V
⎯
⎯
5
pF
Data Input/Output Capacitance
CIO
VIO = 0 V
⎯
⎯
8
pF
Parameter
DS05-11454-1E
Unit
17
MB82DBS08164D-70L
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
(At recommended operating conditions unless otherwise noted)
Value
Test Conditions
Unit
Min
Max
Input Leakage Current
ILI
VSS ≤ VIN ≤ VDD
− 1.0
+ 1.0
μA
Output Leakage Current
ILO
0 V ≤ VOUT ≤ VDD,
Output Disable
− 1.0
+ 1.0
μA
Output High Voltage Level
VOH
VDD = VDD (Min), IOH = − 0.5 mA
1.4
⎯
V
Output Low Voltage Level
VOL
IOL = 1 mA
⎯
0.4
V
Sleep
⎯
10
μA
16 M-bit Partial
⎯
230
μA
32 M-bit Partial
⎯
260
μA
64 M-bit Partial
⎯
310
μA
⎯
1.5
mA
⎯
400
μA
⎯
200
μA
⎯
500
μA
tRC/tWC = Min
⎯
35
mA
tRC/tWC = 1 μs
⎯
5
mA
⎯
24
mA
IDDPS
VDD Power Down Current
IDDP16
IDDP32
VDD = VDD (Max),
VIN = VDD or VSS,
CE2 = VSS
IDDP64
VDD Standby Current
IDDS
VDD = VDD (Max),
VIN (including CLK) = VIH or VIL,
CE1 = CE2 = VIH
IDDS1
VDD = VDD (Max),
TA ≤ + 70 °C
VIN (including CLK) = VDD or VSS,
TA ≤ + 40 °C
CE1 = CE2 = VDD
IDDS2
IDDA1
VDD Active Current
IDDA2
VDD Burst Access Current
IDDA4
VDD = VDD (Max), tCK = tCK (Min) ,
VIN = VDD or VSS, CE1 = CE2 = VDD
VDD = VDD (Max),
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
IOUT = 0 mA
VDD = VDD (Max), VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH, tCK = tCK (Min), BL = 128,
IOUT = 0 mA
Notes : • All voltages are referenced to VSS = 0 V.
• IDD depends on the output termination, load conditions, and AC characteristics.
• After power on, initialization following power-up timing is required. DC characteristics are guaranteed
after the initialization.
• IDDP16, IDDP32, IDDP64, IDDS and IDDS1 might be higher for up to 400 ms after power-up or power down/standby
mode entry.
18
DS05-11454-1E
MB82DBS08164D-70L
2. AC Characteristics
(1) Asynchronous Read Operation
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
Read Cycle Time
tRC
70
1000
ns
*1, *2
CE1 Access Time
tCE
⎯
70
ns
*3
OE Access Time
tOE
⎯
40
ns
*3
Address Access Time
tAA
⎯
70
ns
*3, *4
ADV Access Time
tAV
⎯
70
ns
*3
LB, UB Access Time
tBA
⎯
30
ns
*3
Output Data Hold Time
tOH
3
⎯
ns
*3
CE1 Low to Output Low-Z
tCLZ
10
⎯
ns
*5
OE Low to Output Low-Z
tOLZ
10
⎯
ns
*5
LB, UB Low to Output Low-Z
tBLZ
10
⎯
ns
*5
CE1 High to Output High-Z
tCHZ
⎯
9.5
ns
*3
OE High to Output High-Z
tOHZ
⎯
9.5
ns
*3
LB, UB High to Output High-Z
tBHZ
⎯
9.5
ns
*3
Address Setup Time to ADV Low
tASVL
−5
⎯
ns
*6
Address Setup Time to CE1 Low
tASC
−5
⎯
ns
*6
Address Setup Time to OE Low
tASO
0
⎯
ns
ADV Low Pulse Width
tVPL
7
⎯
ns
ADV High Pulse Width
tVPH
10
⎯
ns
Address Hold Time from ADV High
tAHV
5
⎯
ns
Address Invalid Time
tAX
⎯
10
ns
*4, *7
Address Hold Time from CE1 High
tCHAH
−5
⎯
ns
*8
Address Hold Time from OE High
tOHAH
−5
⎯
ns
WE High to OE Low Time for Read
tWHOL
10
1000
ns
tCP
10
⎯
ns
CE1 High Pulse Width
*6
*9
*1 : Maximum value is applicable if CE1 is kept at Low without change of address input.
*2 : Address should not be changed within a minimum tRC.
*3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*4 : Applicable when CE1 is kept at Low.
*5 : The output load 5 pF without any other load.
*6 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and
tASVL (or tASC) must be equal or greater than the specified minimum value of tVPL.
*7 : Applicable to address access when at least two of address inputs are switched from the previous state.
*8 : tRC (Min) must be satisfied.
*9 : If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become
longer by the amount of subtracting actual value from specified minimum value.
DS05-11454-1E
19
MB82DBS08164D-70L
(2) Asynchronous Write Operation
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
Write Cycle Time
tWC
70
1000
ns
*1, *2
Address Setup Time to ADV Low
tASVL
−5
⎯
ns
*3
Address Setup Time
tAS
0
⎯
ns
ADV Low Pulse Width
tVPL
7
⎯
ns
ADV High Pulse Width
tVPH
10
⎯
ns
Address Hold Time from ADV High
tAHV
5
⎯
ns
CE1 Write Pulse Width
tCW
45
⎯
ns
*2, *4
WE Write Pulse Width
tWP
45
⎯
ns
*2, *4
LB, UB Write Pulse Width
tBW
45
⎯
ns
*2, *4
LB, UB Byte Mask Setup Time
tBS
−5
⎯
ns
*5
LB, UB Byte Mask Hold Time
tBH
−5
⎯
ns
*6
Write Recovery Time
tWR
0
⎯
ns
*2, *7
CE1 High Pulse Width
tCP
10
⎯
ns
WE High Pulse Width
tWHP
10
1000
ns
*8
LB, UB High Pulse Width
tBHP
10
1000
ns
*8
Data Setup Time
tDS
15
⎯
ns
Data Hold Time
tDH
0
⎯
ns
OE High to CE1 Low Setup Time for Write
tOHCL
−5
⎯
ns
*9
OE High to Address Setup Time for Write
tOES
0
⎯
ns
*10
*3
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : The sum of write pulse width (tCW, tWP or tBW) and actual write recovery time (tWR) must be equal or greater than
specified minimum tWC.
*3 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and
tASVL must be equal or greater than the specified minimum value of tVPL.
*4 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last.
*5 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE
whichever occurs last.
*6 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
whichever occurs first.
*7 : Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first.
*8 : Maximum specification of tWHP and tBHP are applicable to Output Disable mode when CE = L, WE = OE = H
after write operation. Refer to “(7) Asynchronous Write Timing 2 (WE Control)” in “ ■ TIMING DIAGRAMS”.
*9 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns
after CE1 is brought to Low.
*10 : If OE is Low after a new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before a new address becomes valid.
20
DS05-11454-1E
MB82DBS08164D-70L
(3) Synchronous Operation - Clock Input (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
RL = 6
Clock Period
tCK
RL = 5
RL = 4
13
⎯
ns
*1
15
⎯
ns
*1
18
⎯
ns
*1
Clock High Time
tCKH
3
⎯
ns
Clock Low Time
tCKL
3
⎯
ns
Clock Transition Time
tCKT
⎯
1.5
ns
*2
*1 : Clock period is defined between valid clock edges.
*2 : Clock transition time is defined between VIH (Min) and VIL (Max)
(4) Synchronous Operation - Address Latch (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Address Setup Time to CLK
tASCK
3
⎯
ns
*1
Address Hold Time from CLK
tCKAH
1
⎯
ns
*1
ADV Low Pulse Width
tVPL
7
⎯
ns
*2
3
⎯
5
⎯
ns
*1
3
⎯
5
⎯
ns
*1
ADV Low Setup Time to CLK
CE1 Low Setup Time to CLK
RL = 6
RL = 4, 5
RL = 6
RL = 4, 5
tVSCK
tCLCK
ADV Low Hold Time from CLK
tCKVH
1
⎯
ns
*1
CE1 High Hold Time from CLK
tCKCH
1
⎯
ns
*3
*1 : Applicable to the 1st rising clock edge.
*2 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
*3 : Applicable to the positive clock edge before address latching.
DS05-11454-1E
21
MB82DBS08164D-70L
(5) Synchronous Read Operation (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Burst Read Cycle Time
CLK Access Time
tRCB
RL = 6
RL = 4, 5
tAC
⎯
8000
ns
⎯
6
ns
*1
⎯
9
ns
*1
Output Hold Time from CLK
tCKQX
2
⎯
ns
*1
CE1 Low to WAIT Low
tCLTL
5
15
ns
*1
CLK to WAIT Valid Time
tCKTV
⎯
6
ns
*1
WAIT Valid Hold Time from CLK
tCKTX
2
⎯
ns
*1
CE1 Low to Output Low-Z
tCLZ
10
⎯
ns
*2
OE Low to Output Low-Z
tOLZ
10
⎯
ns
*2, *3
LB, UB Low to Output Low-Z
tBLZ
10
⎯
ns
*2
CE1 High to Output High-Z
tCHZ
⎯
9.5
ns
*1
OE High to Output High-Z
tOHZ
⎯
9.5
ns
*1
LB, UB High to Output High-Z
tBHZ
⎯
9.5
ns
*1
CE1 High to WAIT High-Z
tCHTZ
⎯
9.5
ns
*1
OE Low Setup Time to 1st Data-output
tOLQ
34
⎯
ns
LB, UB Setup Time to 1st Data-output
tBLQ
26
⎯
ns
OE Setup Time to CLK
tOSCK
3
⎯
ns
OE Hold Time from CLK
tCKOH
1
⎯
ns
Burst End CE1 Low Hold Time from CLK
tCKCLH
1
⎯
ns
LB, UB Hold Time from CLK
tCKBH
1
⎯
ns
tCP
9.5
⎯
ns
CE1 High Pulse Width
*4
*1 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*2 : The output load 5 pF without any other load.
*3 : tOLZ must not be applied after burst read suspend.
*4 : Once LB, UB are determined, LB, UB must not be changed until the end of burst read.
22
DS05-11454-1E
MB82DBS08164D-70L
(6) Synchronous Write Operation (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Burst Write Cycle Time
tWCB
⎯
8000
ns
Data Setup Time to CLK
tDSCK
3
⎯
ns
Data Hold Time from CLK
tDHCK
1
⎯
ns
WE Low Setup Time to 1st Data Input
tWLD
45
⎯
ns
WE Setup Time to CLK
tWSCK
3
⎯
ns
WE Hold Time from CLK
tCKWH
1
⎯
ns
LB, UB Setup Time to CLK
tBSCK
3
⎯
ns
*1
LB, UB Hold Time from CLK
tCKBH
1
⎯
ns
*1
CE1 Low to WAIT High
tCLTH
5
15
ns
*2, *3
WE Low to WAIT High
tWLTH
⎯
15
ns
*2, *3
CE1 High to WAIT High-Z
tCHTZ
⎯
9.5
ns
*2
Burst End CE1 Low Hold Time from CLK
tCKCLH
1
⎯
ns
Burst End CE1 High Setup Time to next CLK
tCHCK
3
⎯
ns
tCP
9.5
⎯
ns
CE1 High Pulse Width
*1 : tBSCK and tCKBH should be satisfied for byte mask control.
*2 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*3 : WAIT outputs Low-Z after tCLTH (Min) from CE1 = L. WAIT outputs to High level after tWLTH or tCLTH from WE = L
or CE1 = L whichever occurs last.
DS05-11454-1E
23
MB82DBS08164D-70L
(7) Power Down Parameters
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
CE2 Low Setup Time for Power Down Entry
tCSP
10
⎯
ns
CE2 Low Hold Time after Power Down Entry
tC2LP
70
⎯
ns
CE2 Low Hold Time for Reset to Asynchronous Mode
tC2LPR
70
⎯
ns
*1
CE1 High Hold Time following CE2 High
after Power Down Exit [Sleep mode only]
tCHH
300
⎯
μs
*2
CE1 High Hold Time following CE2 High
after Power Down Exit [not in Sleep mode]
tCHHP
70
⎯
ns
*3
CE1 High Setup Time following CE2 High
after Power Down Exit
tCHS
0
⎯
ns
*2
*1 : Applicable when RA = 0 (Reset to Asynchronous mode) .
*2 : Applicable also to power-up.
*3 : Applicable when Partial Power Down mode and Reset to Asynchronous mode are set.
(8) Other Timing Parameters
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
CE1 High to OE Invalid Time for Standby Entry
tCHOX
0
⎯
ns
CE1 High to WE Invalid Time for Standby Entry
tCHWX
0
⎯
ns
CE2 Low Hold Time after Power-up
tC2LH
50
⎯
μs
CE1 High Hold Time following CE2 High after Power-up
tCHH
300
⎯
μs
tT
1
25
ns
Input Transition Time (except for CLK)
*1
*2, *3
*1 : Some data might be written into any address location if tCHWX (Min) is not satisfied.
*2 : Except for the CLK input transition time.
*3 : The Input Transition Time (tT) at AC testing is 3 ns for Asynchronous operation and 1.5 ns for Synchronous
operation respectively. If actual tT is longer than 3 ns or 1.5 ns specified as AC test condition, it may violate AC
specification of some timing parameters. Refer to " (9) AC Test Conditions".
24
DS05-11454-1E
MB82DBS08164D-70L
(9) AC Test Conditions
Description
Symbol
Test Setup
Value
Unit
Input High Level
VIH
⎯
VDD × 0.8
V
Input Low Level
VIL
⎯
VDD × 0.2
V
VREF
⎯
VDD × 0.5
V
tT
Between VIL and VIH
3
ns
1.5
ns
Input Timing Measurement Level
Async.
Input Transition Time
Sync.
Notes
• AC MEASUREMENT OUTPUT LOAD CIRCUIT
VDD
50
VDD
0.1 μF
VSS
DS05-11454-1E
0.5 V
Device under
Test
Output
50 pF
25
MB82DBS08164D-70L
■ TIMING DIAGRAMS
(1) Asynchronous Read Timing 1-1 (Basic Timing)
tRC
Address
ADV
Address Valid
Low
tASC
tCHAH
tCE
CE1
tASC
tCP
tCHZ
tOE
OE
tOHZ
tBA
LB, UB
tBHZ
tBLZ
tOLZ
tOH
DQ
(Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
26
DS05-11454-1E
MB82DBS08164D-70L
(2) Asynchronous Read Timing 1-2 (Basic Timing)
tRC
Address
Address Valid
tAHV
tASVL
tAV
ADV
tASVL
tVPH
tVPL
tASC
tCE
CE1
tCP
tCHZ
tASC
tOE
OE
tOHZ
tBA
LB, UB
tBHZ
tBLZ
tOLZ
DQ
tCLZ
(Output)
tOH
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
DS05-11454-1E
27
MB82DBS08164D-70L
(3) Asynchronous Read Timing 2 (OE Control & Address Access)
tRC
Address
tAX
tRC
Address Valid
Address Valid
tAA
tOHAH
tAA
CE1
Low
tASO
tOE
OE
LB, UB
tOHZ
tOLZ
DQ
(Output)
tOH
Valid Data
Output
tOH
Valid Data
Output
Note : This timing diagram assumes CE2 = H, ADV = L and WE = H.
28
DS05-11454-1E
MB82DBS08164D-70L
(4) Asynchronous Read Timing 3 (LB, UB Byte Control Access)
tAX
tRC
Address
tAX
Address Valid
tAA
CE1, OE
Low
tBA
tBA
LB
tBA
UB
tBHZ
tBLZ
tBHZ
tOH
tBLZ
tOH
DQ7 to DQ0
(Output)
Valid Data Output
Valid Data Output
tBLZ
tBHZ
tOH
DQ15 to DQ8
(Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H, ADV = L and WE = H.
DS05-11454-1E
29
MB82DBS08164D-70L
(5) Asynchronous Write Timing 1-1 (Basic Timing)
tWC
Address
ADV
Address Valid
Low
tWR
tCW
tAS
CE1
tAS
tCP
tAS
tWR
tWP
WE
tAS
tWHP
tAS
tWR
tBW
LB, UB
tAS
tBHP
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H.
30
DS05-11454-1E
MB82DBS08164D-70L
(6) Asynchronous Write Timing 1-2 (Basic Timing)
tWC
Address
Address Valid
tASVL
tAHV
tVPL
ADV
tVPH
tASVL
tAS
tAS
tCW
CE1
tCP
tWP
WE
tWHP
tBW
LB, UB
tBHP
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H.
DS05-11454-1E
31
MB82DBS08164D-70L
(7) Asynchronous Write Timing 2 (WE Control)
tWC
Address
tWC
Address Valid
Address Valid
tOHAH
CE1
Low
tAS
tWR
tWP
WE
tAS
tWR
tWP
tWHP
LB, UB
tOES
OE
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H and ADV = L.
32
DS05-11454-1E
MB82DBS08164D-70L
(8) Asynchronous Write Timing 3-1 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tAS
tAS
tWP
tWP
tWHP
WE
tWR
tBH
tBS
LB
tBH
tBS
tWR
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
DS05-11454-1E
33
MB82DBS08164D-70L
(9) Asynchronous Write Timing 3-2 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tWR
WE
tWR
tWHP
tAS
tBW
tBS
tBH
LB
tBH
tBS
tAS
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
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MB82DBS08164D-70L
(10) Asynchronous Write Timing 3-3 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tWHP
WE
tAS
tBW
tWR
tBH
tBS
LB
tBS
tBH
tAS
tWR
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
DS05-11454-1E
35
MB82DBS08164D-70L
(11) Asynchronous Write Timing 3-4 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
WE
tAS
tBW
tWR
LB
tWR
tBW
tBHP
tDH
tDS
DQ7 to DQ0
(Input)
tDS
Valid Data Input
tAS
tBW
tDH
Valid Data Input
tWR
UB
tAS
tWR
tBW
tBHP
tDS
DQ15 to DQ8
(Input)
tAS
tDH
Valid Data Input
tDS
tDH
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
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MB82DBS08164D-70L
(12) Asynchronous Read/Write Timing 1-1 (CE1 Control)
tWC
Address
tRC
Write Address
tCHAH
tAS
Read Address
tWR
tCHAH
tASC
tCW
tCE
CE1
tCP
tCP
WE
LB, UB
tOHCL
OE
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• Write address is valid from either CE1 or WE of last falling edge.
DS05-11454-1E
37
MB82DBS08164D-70L
(13) Asynchronous Read/Write Timing 1-2 (CE1, WE, OE Control)
tWC
Address
tRC
Write Address
tCHAH
tAS
Read Address
tWR
tASC
tCHAH
tCE
CE1
tCP
tCP
tWP
WE
LB, UB
tOHCL
tOE
OE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read
sequence.
38
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MB82DBS08164D-70L
(14) Asynchronous Read/Write Timing 2 (OE, WE Control)
tWC
Address
tRC
Write Address
Read Address
tAA
tOHAH
tOHAH
CE1
Low
tAS
tWR
tWP
WE
tOES
LB, UB
tASO
tOE
OE
tWHOL
tOHZ
tOH
tDS
tDH
tOHZ
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• CE1 can be tied to Low for WE and OE controlled operation.
• Read data will be available after tAA from WE = H if read addresses are not changed from write
address.
DS05-11454-1E
39
MB82DBS08164D-70L
(15) Asynchronous Read/Write Timing 3 (OE, WE, LB, UB Control)
tWC
Address
tRC
Write Address
Read Address
tAA
tOHAH
tOHAH
CE1
Low
WE
tOES
tAS
tBW
tWR
tBA
LB, UB
tASO
tBHZ
OE
tWHOL
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• CE1 can be tied to Low for WE and OE controlled operation.
• Read data will be available after tAA from WE = H if read addresses are not changed from write
address.
40
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MB82DBS08164D-70L
(16) Clock Input Timing
tCK
CLK
tCKH
tCK
tCKT
tCKL
tCKT
Notes : • Stable clock input must be required during CE1 = L.
• tCK is defined between rising clock edges.
• tCKT is defined between VIH (Min) and VIL (Max).
(17) Address Latch Timing (Synchronous Mode)
CLK
tASCK
tCKAH
Address Valid
Address
tVSCK
tCKVH
ADV
tVPL
tCKCH
tCLCK
CE1
Notes : • tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
At least one rising clock edge must be input during ADV = L.
• tASCK, tVSCK and tCLCK are applied to the 1st valid clock edge during ADV = L.
• tCKCH is applied to the rising clock edge before address latching.
DS05-11454-1E
41
MB82DBS08164D-70L
(18) Synchronous Read Timing 1 (OE Control)
RL=5
CLK
tRCB
Address
Address
Valid
Address
Valid
tASCK tCKAH
tVPL
tASCK tCKAH
tVPL
ADV
tVSCK
tCKVH
tVSCK
tCLCK
tCKCH
tCKCH
tCKVH
tCLCK
CE1
tCP
tCLTL
tOLQ
tCLTL
tCKOH
OE
tOHZ
tOLZ
WE
High
tBLQ
tCKBH
LB, UB
tBLZ
WAIT
High-Z
tCKTX
DQ
High-Z
Note : This timing diagram assumes CE2 = H.
42
tBHZ
tCHTZ
tCKTV
tAC
tAC
Q1
tCKQX
tAC
QBL
tCKQX
DS05-11454-1E
MB82DBS08164D-70L
(19) Synchronous Read Timing 2 (CE1 Control)
RL=5
CLK
tRCB
Address
Address
Valid
Address
Valid
tASCK tCKAH
tVPL
tASCK tCKAH
tVPL
ADV
tVSCK
tCKCH
tCKVH
tVSCK
tCLCK
tCKCH
tCKVH
tCLCK
CE1
tCP
tCKCLH
tCLTL
tCLTL
tCLZ
tCLZ
OE
WE
High
LB, UB
tCKTV
tCHTZ
WAIT
tCKTX
DQ
tAC
tAC
Q1
tCKQX
tCHZ
tAC
QBL
tCKQX
Note : This timing diagram assumes CE2 = H.
DS05-11454-1E
43
MB82DBS08164D-70L
(20) Synchronous Write Timing 1 (WE Level Control)
RL=5
CLK
tWCB
Address
Valid
Address
Valid
tASCK tCKAH
tVPL
tASCK tCKAH
tVPL
Address
ADV
tCHCK
tVSCK
tCKCH
tCKVH
tVSCK
tCKCLH
tCLCK
tCKCH
tCKVH
tCLCK
CE1
tCLTH
OE
tCP
High
tWLTH
tCKWH
tWLD
WE
tCKBH
tBSCK
LB, UB
tCHTZ
WAIT
High-Z
tDSCK
DQ
tDSCK
D1
tDHCK
tDSCK
D2
DBL
tDHCK
Note : This timing diagram assumes CE2 = H.
44
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MB82DBS08164D-70L
(21) Synchronous Write Timing 2 (WE Single Clock Pulse Control)
RL=5
CLK
tWCB
Address
Valid
Address
Valid
tASCK tCKAH
tVPL
tASCK tCKAH
tVPL
Address
ADV
tCHCK
tVSCK
tCKCH
tCKVH
tVSCK
tCLCK
tCKCH
tCKCLH
tCKVH
tCLCK
CE1
tCP
tCLTH
tCLTH
High
OE
tWSCK
tCKWH
tWSCK
tCKWH
WE
tWLTH
tCKBH
tBSCK
tWLTH
LB, UB
tCHTZ
WAIT
High-Z
tDSCK
DQ
tDSCK
D1
tDHCK
tDSCK
D2
DBL
tDHCK
Note : This timing diagram assumes CE2 = H.
DS05-11454-1E
45
MB82DBS08164D-70L
(22) Synchronous Write Timing 3 (LB, UB Byte Mask Control)
RL=5
CLK
tWCB
Address
Address
Valid
Address
Valid
tASCK tCKAH
tVPL
tASCK tCKAH
tVPL
ADV
tCHCK
tVSCK
tCKCH
tCKVH
tVSCK
tCLCK
tCKCLH
tCKCH
tCKVH
tCLCK
CE1
tCLTH
OE
tCP
High
tWLTH
tCKWH
tWLD
WE
tCKBH
tCKBH
LB
UB
tBSCK
tBSCK
tBSCK
tCHTZ
WAIT
High-Z
tDSCK
tDSCK
DQ7 to DQ0
D1
DBL
tDHCK
tDSCK
DQ15 to DQ8
D1
D2
tDHCK
Note : This timing diagram assumes CE2 = H and WE Level Control.
46
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MB82DBS08164D-70L
(23) Synchronous Read to Write Timing 1 (CE1 Control)
RL = 5
CLK
tWCB
Address
Valid
Address
tASCK tCKAH
tVPL
ADV
tCKCH
tVSCK tCKVH
tCLCK
tCKCLH
CE1
tCKCLH
tCP
tCLTH
OE
WE
tBSCK
tCKBH
LB,UB
tCHTZ
WAIT
tCHZ
tAC
DQ
QBL-1
tCKQX
QBL
tCKQX
tDSCK
tDSCK
tDSCK
D1
D2
D3
tDHCK
tDHCK
tDHCK
tDSCK
DBL
tDHCK
Note : This timing diagram assumes CE2 = H.
DS05-11454-1E
47
MB82DBS08164D-70L
(24) Synchronous Write to Read Timing 1 (CE1 Control)
RL=5
CLK
tRCB
Address
Address
Valid
tASCK tCKAH
tVPL
ADV
tCHCK
tVSCK
tCKCH
tCKVH
tCLCK
CE1
tCP
tCKCLH
tCKCLH
tCLTL
tCLZ
OE
WE
LB, UB
Low
tCKTV
tCHTZ
WAIT
tDSCK
DQ
tDSCK
DBL-1
tDHCK
tCKTX
DBL
tDHCK
tAC
tAC
Q1
tCKQX
tAC
Q2
tCKQX
QBL
tCKQX
Note : This timing diagram assumes CE2 = H.
48
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MB82DBS08164D-70L
(25) Power-up Timing 1
CE1
tCHS
tCHH
tC2LH
CE2
VDD (Min)
VDD
0V
Note : The tC2LH specifies after VDD reaches specified minimum level.
(26) Power-up Timing 2
CE1
tCHH
CE2
VDD (Min)
VDD
0V
Note : The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1 and CE2.
If transition time of VDD (from 0 V to VDD (Min)) is longer than 50 ms, (25) Power-up Timing 1 must
be applied.
DS05-11454-1E
49
MB82DBS08164D-70L
(27) Power Down Entry and Exit Timing
CE1
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Notes : • Power Down mode can be also used as a reset timing if “Power-up Timing” above could not
be satisfied and Power Down program was not performed prior to this reset.
• CE2 can be brought to Low after the completion of previous Read/Write operation.
• CE2 must be kept at High during the specified minimum time of tCP.
(28) Standby Entry Timing after Read or Write
CE1
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode.
50
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MB82DBS08164D-70L
(29) Configuration Register Set Timing 1 (Asynchronous Operation)
tRC
Address
tWC
MSB*1
MSB*1
tCP
tWC
tWC
tWC
MSB*1
MSB*1
MSB*1
tCP
tCP
tCP
tWC
MSB*1
tWC*6
tCP
CE1
OE
WE
LB, UB
DQ
*2
*2
RDa
Cycle #1
*2
*3
RDa
RDa
Cycle #2
Cycle #3
CR
Key 0*4
Cycle #4
*3
*3
CR
Key 1*5
Cycle #5
CR
Key 2*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “1” for the CR Set as specified in “■FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any
operations and data are not guaranteed.
*6 : After tWC following Cycle #6, the Configuration Register Set is completed and returned to the normal
operation.
DS05-11454-1E
51
MB82DBS08164D-70L
(30) Configuration Register Verify Timing 1 (Asynchronous Operation)
tRC
Address
tWC
MSB*1
MSB*1
tCP
tWC
tWC
tRC
tRC
MSB*1
MSB*1
MSB*1
MSB*1
tCP
tCP
tCP
tRC*6
tCP
CE1
OE
WE
LB, UB
DQ*3
*2
*2
RDa
Cycle #1
*2
*3
RDa
RDa
Cycle #2
Cycle #3
CR
Key 0*4
Cycle #4
*3
CR
Key 1*5
Cycle #5
*3
CR
Key 2*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input or output the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “0” for the CR Verify as specified in “■FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any
operations and data are not guaranteed.
*6 : After tRC following Cycle #6, the Configuration Register Verify is completed and returned to the normal
operation.
52
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MB82DBS08164D-70L
(31) Configuration Register Set Timing 2 (Synchronous Operation)
CLK
Address
MSB
MSB
1
*
*
tRCB
MSB
1
*
MSB
1
*
*
tWCB
tWCB
tWCB
MSB
1
MSB
1
*1
tWCB
tWCB
ADV
tCP
tCP
tCP
tCP
6
tWC*
tCP
CE1
OE
WE
*2
*2
*2
*3
*3
*3
LB,UB
RL
DQ
RL-1
RDa
Cycle #1
RDa
Cycle #2
RL-1
RL-1
RL-1
RDa
Cycle #3
CR
Key 0
*4
Cycle #4
RL-1
CR
Key 1
*5
Cycle #5
CR
Key 2
*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “1” for the CR Set as specified in “■ FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■ FUNCTIONAL DESCRIPTION”. If not,
any operations and data are not guaranteed.
*6 : After tWC following Cycle #6, the Configuration Register Set is completed and returned to the normal
operation.
DS05-11454-1E
53
MB82DBS08164D-70L
(32) Configuration Register Verify Timing 2 (Synchronous Operation)
CLK
Address
MSB
MSB
1
1
*
MSB
*
tRCB
*
tRCB
MSB
MSB
1
1
*
tRCB
*
tRCB
MSB
1
*1
tRCB
tRCB
ADV
tCP
tCP
tCP
tCP
6
tRC*
tCP
CE1
OE
WE
*2
*2
*3
*2
*3
*3
LB,UB
RL
DQ
RL-1
RDa
Cycle #1
RDa
Cycle #2
RL-1
RL-1
CR
Key 0
RDa
Cycle #3
RL
*4
Cycle #4
RL
CR
Key 1
*5
Cycle #5
CR
Key 2
*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input or output the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “0” for the CR Verify as specified in “■FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any
operations and data are not guaranteed.
*6 : After tRC following Cycle #6, the Configuration Register Verify is completed and returned to the normal
operation.
54
DS05-11454-1E
MB82DBS08164D-70L
■ ORDERING INFORMATION
Part Number
MB82DBS08164D-70LTBG
DS05-11454-1E
Package
71-ball plastic FBGA
(BGA-71P-M03)
55
MB82DBS08164D-70L
■ PACKAGE DIMENSIONS
71-ball plastic FBGA
Ball pitch
0.80 mm
Package width ×
package length
7.00 × 11.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
∅0.45 mm
Mounting height
1.20 mm Max.
Weight
0.14 g
(BGA-71P-M03)
71-ball plastic FBGA
(BGA-71P-M03)
11.00±0.10(.433±.004)
B
0.20(.008) S B
1.09
.043
+0.11
–0.10
+.004
–.004
0.80(.031)
REF
0.40(.016)
REF
(Seated height)
0.80(.031)
REF
8
7
6
5
4
3
2
1
A
7.00±0.10
(.276±.004)
0.40(.016)
REF
0.10(.004) S
0.39±0.10
(Stand off)
(.015±.004)
INDEX-MARK AREA
S
0.20(.008) S A
M L K J H G F E D C B A
71-ø0.45 +0.10
–0.05
71-ø.018 +.004
–.002
ø0.08(.003)
M
S AB
0.10(.004) S
©2003-2008 FUJITSU MICROELECTRONICS LIMITED B71003S-c-1-2
C
2003 FUJITSU LIMITED B71003S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest Package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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MEMO
DS05-11454-1E
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MB82DBS08164D-70L
MEMO
58
DS05-11454-1E
MB82DBS08164D-70L
MEMO
DS05-11454-1E
59
MB82DBS08164D-70L
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
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Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
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#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
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Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
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Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department