FUJITSU SEMICONDUCTOR DATA SHEET DS07-12528-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89143A/144A Series MB89143A/144A ■ DESCRIPTION The MB89143A/144A has been developed as a general-purpose version of the F2MC-8L* family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain peripheral functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, an A/D converter, buzzer output, high voltage driver, watch prescaler, and an external interrupt. The MB89143A/144A is applicable to a wide range of applications from welfare products to industrial equipment. * F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • Minimum execution time: 0.50 µs/8.0-MHz oscillation • Interrupt servicing time: 4.50 µs/8.0-MHz oscillation • F2MC-8L family CPU core Multiplication and division instructions Instruction set optimized for controllers 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • Dual-clock control system • High-voltage ports: 24 channel (Continued) ■ PACKAGE 64-pin Plastic SH-DIP (DIP-64P-M01) MB89143A/144A (Continued) • Two types of timers 8/16-bit timer/counter (also usable as two 8-bit timers) 21-bit time-base timer • One 8-bit serial interface Switchable transfer direction allows comunication with various equipment. • 8-bit A/D converter: 8 channels Successive approximation type • External interrupt: 2 channels Two channels are independent and capable of wake-up from low-power consumption modes. (Rising edge/ falling edge/both edges selectability) –0.3 V to +7.0 V can be applied to INT1 (N-ch open-drain) • Low-power consumption modes Subclock mode (The main clock stops, and the device operates at the subclock.) Watch mode (Only the watch prescaler is operating.) Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) • Watch prescaler • Buzzer output • Watchdog reset, reset output, and power-on reset functions 2 MB89143A/144A ■ PRODUCT LINEUP Part number Parameter MB89143A Classification ROM size RAM size 8 K × 8 bits MB89144A MB89P147 Mass production products (mask ROM products) One-time PROM product 12 K × 12 bits 32 K × 8 bits Internal PROM 256 × 8 bits CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Note: Ports High-voltage output ports (P-ch open-drain): Buzzer output (P-ch open-drain, high-voltage): Output ports (CMOS): Input ports (CMOS): I/O ports (CMOS): I/O port (N-channel open-drain): Total: Time-base timer MB89144/5/6 12/16/24 K × 8 bits 256/512/768 × 8 bits MB89PV140 Piggyback/evaluation product (for evaluation and development) 32 K × 8 bits External ROM (Piggyback) 1 K × 8 bits Internal 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.5 µs/8 MHz to 8.0 µs/8 MHz, 61 µs/32.768 kHz 4.5 µs/8 MHz to 72.0 µs/8 MHz, 562.5 µs/32.768 kHz The above times change according to the gear function. 24 (P40 to P47, P50 to P57, and P60 to P67) 1 4 (P20 to P23) 2 (P70 and P71, function as X0A and X1A pins when dual-clock system is used.) 23 (P00 to P07, P10 to P17, P30, and P32 to P37) 1 (P31) 55 Capable of generating four different intervals (at 8.0-MHz oscillation): 0.26 ms, 0.51 ms, 1.02 ms, and 0.524 s 8/16-bit timer counter 8/16-bit timer operation (Operating clock, internal clock, external trigger) 8/16-bit event counter operation (Rising edge/falling edge/both edges selectability) 8-bit Serial I/O 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles) A/D converter External interrupt 8-bit resolution × 8 channels A/D conversion mode (with conversion time of 22 µs/8 MHz, and highest gear speed) Continuous activation by external activation cabable 10-bit resolution × 12 channels A/D conversion mode (with conversion time of 16.5 ms/ 8 MHz, and highest gear speed) Sense mode (with conversion time of 9.0 µs/8 MHz, and highest gear speed) Continuous activation enabled by external activation capable 2 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge/both edges selectability Built-in analog noise canceller Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Buzzer output 1.95 or 3.91 kHz selectable (at 8-MHz oscillation) Output to a high-voltage pin (Continued) 3 MB89143A/144A (Continued) Part number Parameter Watchdog reset MB89143A MB89144A MB89144/5/6 MB89P147 MB89PV140 Internal reset in 524 to 1049 ms (at 8 MHz oscillation) when the program runway occurs 8-bit PWM timer None 8-bit timer operation/8-bit resolution PWM operation 12-bit MPG timer 12-bit resolution PWM operation/reload timer operation/ PPG operation None Standby mode Sleep mode, stop mode, and watch mode Process CMOS Package DIP-64P-M01 FPT-64P-M06 DIP-64P-M01 EPROM for use MDP-64C-P02 MQP-64C-P01 MBM27C256A-20 Operating voltage* 4.0 V to 6.0 V 2.7 V to 6.0 V * : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”) ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89143A MB89144A MB89P147 × DIP-64P-M01 FPT-64P-M06 × MDP-64C-P02 × × MQP-64C-P01 × × : Available MB89PV140 × × : Not available * : Under examination for development Note: For more information about each package, see section “■ Package Dimensions.” 4 MB89143A/144A ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89143A/144A, the upper half of the register bank cannot be used. • The stack area, etc., is set at the upper limit of the RAM. 2. Functions Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following point: • The A/D converter in the MB89143A/144A is an 8-bit resolution type. The MB89143A/144A contains neither the 8-bit PWM timer nor the 12-bit MPG timer. 3. Current Consumption • In the case of the MB89PV140, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section “■ Electrical Characteristics”.) 4. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ Mask Options.” Take particular care on the following point: • A pull-up resistor option is not provided for the MB89PV140. 5 MB89143A/144A ■ PIN ASSIGNMENT (Top view) BZ P67 P66 P65 P64 P63 P62 P61 P60 N.C. P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P23 RST MODA X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC AVR AVSS P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10 P11 P12 P13 P14 P15 P16 P17/ADST P30/INT0 P31/INT1 P32/SCK P33/SO P34/SI P35/EC P36 P37 P20 P21 P22 P70/X0A P71/X1A • When used as general-purpose ports, the P70/X0A and P71/X1A functions as input-only ports. (DIP-64P-M01) 6 MB89143A/144A ■ PIN DESCRIPTION Pin no. Pin name SDIP* 30 X0 31 X1 29 28 Circuit type Function A Main clock oscillator pins Use a crystal oscillator. MODA B Operating mode selection pin Connect directly to VSS in normal operation. RST C Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. This pin is with a noise canceller. 54 to 61 P07/AN7 to P00/AN0 F General-purpose I/O ports These ports are a hysteresis input type. Also serve as an analog input. 46 P17/ADST H General-purpose I/O port This port is a hysteresis input type. Also serves as an A/D converter external activation. 47 to 53 P16 to P10 H General-purpose I/O ports These ports are a hysteresis input type. P70/X0A, P71/X1A J Selectable either general-purpose input ports or the subclock oscillator pins by the mask option. These ports are a hysteresis input type when used as general-purpose input ports. P23 to P20 D General-purpose output ports 38, 39 P37, P36 H General-purpose I/O ports These ports are a hysteresis input type. 40 P35/EC General-purpose I/O port This port is a hysteresis input type. Also serves as the external clock input for the 8/16-bit timer/counter. 41 P34/SI General-purpose I/O port This port is a hysteresis input type. Also serves as the serial data input for the 8-bit serial interface. 42 P33/SO General-purpose I/O port This port is a hysteresis input type. Also serves as the serial data output for the 8-bit serial interface. 43 P32/SCK General-purpose I/O port This port is a hysteresis input type. Also serves as the serial transfer clock for the 8-bit serial interface. 34, 33 27, 35 to 37 * : DIP-64P-M01 (Continued) 7 MB89143A/144A (Continued) Pin no. SDIP* Circuit type Function 44 P31/INT1 E General-purpose I/O port This port is an N-ch open-drain outupt and hysteresis input type. Also serves as an external interrupt. The interrupt input is a hysteresis input type and with a built-in noise canceller. 45 P30/INT0 I General-purpose I/O port This port is a hysteresis input type. Also serves as an external interrupt. The interrupt input is a hysteresis input type and with a built-in noise canceller. 1 BZ G Buzzer output-only pin P-ch high-voltage open-drain output port P47 to P40, P57 to P50, P67 to P60 G P-ch high-voltage open-drain output port 10 N.C. — Be sure to leave them open. 64 VCC — Power supply pin Also serves as an A/D converter power supply. 32 VSS — Power supply (GND) pin 63 AVR — A/D converter reference voltage input pin 62 AVSS — A/D converter power supply pin Use this pin at the same voltage as VSS. 19 to 26, 11 to 18, 2 to 9 * : DIP-64P-M01 8 Pin name MB89143A/144A ■ I/O CIRCUIT TYPE Type Circuit Remarks A • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X1 X0 Standby control signal B C • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • CMOS hysteresis input R P-ch N-ch Hysteresis input D • CMOS output P-ch N-ch E • N-ch open-drain output • CMOS hysteresis input • The interrupt input is with a noise canceller. N-ch Port Hysteresis input Interrupt input With noise canceller F • CMOS output • CMOS hysteresis input P-ch N-ch Port Hysteresis input Analog input (Continued) 9 MB89143A/144A (Continued) Type Circuit Remarks G • P-ch high-voltage open-drain output P-ch H • CMOS output • CMOS hysteresis input • Pull-up resistor optional (Only for P14 to P17 and P32 to P37) P-ch P-ch N-ch Port Hysteresis input I • CMOS output • CMOS hysteresis input • The interrupt input is with a noise canceller. P-ch N-ch Port Interrupt input Hysteresis input with noise canceller J X1A Port Hysteresis input X0A Standby control signal Port Hysteresis input 10 • The oscillation feedback resistor is not provided. • CMOS hysteresis input when subclock is not used MB89143A/144A ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS. (However, up to 7.0 V can be applied to P31/INT1 pin, regardless of VCC.) When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency(50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 11 MB89143A/144A ■ BLOCK DIAGRAM Main clock oscillator (max. 8 MHz) X0 X1 BZ Buzzer output Clock controller High-voltage port 6 P60 to P67 Subclock oscillator (32.768 kHz) Port 7 P70/X0A P71/X1A 8 High-voltage port 5 8 P50 to P57 P20 to P23 4 Port 2 CMOS output port Internal bus CMOS input port High-voltage port 4 8 P40 to P47 Time-base timer CMOS I/O port 8 8-bit serial interface AVR 7 CMOS I/O port 1 RAM (256 × 8 bits) F2MC-8L CPU ROM Note: The A/D converter is an 8-bit, 8-channel type. 8/16-bit timer/ counter P35/EC P30/INT0 External interrupt Port 3 P17/ADST 12 P32/SCK P33/SO P34/SI 8-bit A/D converter AVSS P10 to P16 Port 3 CMOS I/O port 0 P07/AN7 to P00/AN0 N-ch open-drain port Other pins V CC , V SS , M O D A , R S T P31/INT1 MB89143A/144A ■ CPU CORE 1. Memory Space The microcontrollers of the MB89143A/144A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89143A/144A series is structured as illustrated below. MB89143A 0000 H MB89144A 0000 H I/O 0080 H I/O 0080 H RAM 256 0100 H RAM 256 0100 H Register 0180H Register 0180H Not available Not available D000 H E000 H ROM 12 KB ROM 8 KB FFFF H FFFF H 13 MB89143A/144A 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): A 16-bit register for indicating instruction storage positions Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits FFFDH : Program counter PC A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 12 10 9 8 Vacancy Vacancy Vacancy RP RP 14 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89143A/144A The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 15 MB89143A/144A The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89143A/144A. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuraiton This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 16 MB89143A/144A ■ I/O MAP Address Read/write Register name Register description 00H (R/W) PDR0 Port 0 data register 01H (W) DDR0 Port 0 data direction register 02H (R/W) PDR1 Port 1 data register 03H (W) DDR1 Port 1 data direction register 04H (R/W) PDR2 Port 2 data register 05H Vacancy 06H Vacancy 07H (R/W) SYCC System clock control register 08H (R/W) STBC Standby control register 09H (R/W) WDTE Watchdog timer control register 0AH (R/W) TBCR Time-base timer control register 0BH (R/W) WPCR Watch prescaler control register 0CH (R/W) PDR3 Port 3 data register 0DH (W) DDR3 Port 3 data direction register 0EH (R/W) BUZR Buzzer register 0FH (R/W) EIC 10H (R/W) PDR4 Port 4 data register 11H (R/W) PDR5 Port 5 data register 12H (R/W) PDR6 Port 6 data register 13H (R) PDR7 Port 7 data register External interrupt control register 14H Vacancy 15H Vacancy 16H Vacancy 17H Vacancy 18H (R/W) T3CR Timer 3 control register 19H (R/W) T2CR Timer 2 control register 1AH (R/W) T3DR Timer 3 data register 1BH (R/W) T2DR Timer 2 data register 1CH (R/W) SMR Serial mode register 1DH (R/W) SDR Serial data register 1EH (R/W) ADC1 A/D converter control register 1 1FH (R/W) ADC2 A/D converter control register 2 (Continued) 17 MB89143A/144A (Continued) Address Read/write Register name 20H (R/W) ADDH A/D data register (H) 21H (R/W) ADDL A/D data register (L) 22H (W) PCR0 Port input control register 0 23H (W) PCR1 Port input control register 1 24H to 7BH Vacancy 7CH (W) ILR1 Interrupt level setting register 1 7DH (W) ILR2 Interrupt level setting register 2 7EH (W) ILR3 Interrupt level setting register 3 7FH Note: Do not use vacancies. 18 Register description Vacancy MB89143A/144A ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC AVR VSS – 0.3 VSS + 7.0 V AVR ≤ VCC +0.3*1 VI1 VSS – 0.3 VCC + 0.3 V P00 to P07, P10 to P17, P30, P32 to P37, P70, P71 VI2 VSS – 0.3 7 V P31 VI3 VCC – 40 VCC + 0.3 V P40 to P47, P50 to P57, P60 to P67, BZ*2 VO1 VSS – 0.3 VCC + 0.3 V P00 to P07, P10 to P17, P20 to P23, P30 to P37 VO2 — VCC + 0.3 V P40 to P47, P50 to P57, P60 to P67, BZ*2 “H” level total maximum output current ΣIOH — –100 mA “H” level total average output current ΣIOHAV — –75 mA “H” level maximum output current IOH — –12 “H” level average output current IOHAV — –6 “H” level maximum output current IOH — –20 “H” level average output current IOHAV — –10 “L” level total maximum output current ΣIOL — 50 mA “L” level total average output current ΣIOLAV — 30 mA Average value (operating current × operation rate) “L” level maximum output current IOL — 12 “L” level average output current mA IOLAV — 6 P00 to P07, P10 to P17, P20 to P23, P30 to P37 Power consumption PD — 470 mW SDIP64 : DIP-64P-M01 Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage Input voltage Output voltage mA mA Averge value (operating current × operation rate) P00 to P07, P30, P32 to P37, P10 to P17, P20 to P23 Average value (operating current × operation rate) P40 to P47, P50 to P57, P60 to P67, BZ Average value (operating current × operation rate) *1: Take care so that AVR does not exceed VCC + 0.3 V and VCC, such as when power is turned on. *2: VI and VO must not exceed VCC + 0.3 V. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 19 MB89143A/144A 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Value Symbol Power supply voltage VCC Unit Remarks 6.0* V Normal operation assurance range* at highest gear speed 3.5* 6.0* V Normal operation assurance range* at highest gear speed 2.5 6.0 V When in watch mode or subclock operation mode 1.5 6.0 V Retains the RAM state in stop mode Min. Max. 4.0* A/D converter reference input voltage AVR 0.0 VCC V Operating temperature TA –40 +85 °C * : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.” 6 Operating voltage (V) 5 Operation assurance range 4 3 2 1 2 3 4 5 6 7 9 8 10 Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz) 2.0 1.3 1.0 0.8 0.66 0.57 Minimum execution time (instruction cycle) Figure 1 0.5 0.44 0.4 (µs) Operating Voltage vs. Main Clock Operating Frequency Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 20 MB89143A/144A 3. DC Characteristics Parameter Symbol Pin (AVR = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. “H” level input VIHS voltage P00 to P07, P10 to P17, P30 to P37, P70, P71, X0, RST, X1, MODA — 0.8 VCC — VCC + 0.3 V “L” level input voltage VILS P00 to P07, P10 to P17, P30 to P37, P70, P71, X0, RST, X1, MODA — VSS – 0.3 — 0.2 VCC V Open-drain output pin application voltage VD1 P31 — VSS – 0.3 — 7.0 V VOH1 P00 to P07, P10 to P17, P20 to P23, P30 to P37 IOH = –2.0 mA 2.4 — — V VOH2 P40 to P47, P50 to P57, P60 to P67 IOH = –10 mA 3.0 — — V P00 to P07, P10 to P17, P20 to P23, P30 to P37 IOL = 1.8 mA — — 0.4 V VOL2 RST IOL = 4.0 mA — — 0.6 V ILI1 P00 to P07, P10 to P17, P30 to P37, P70, P71 0 V < V1 < VCC — — ±5 µA Except pins with pull-up resistor ILI2 P14 to P17, P32 to P37 VI = 0.0 V –200 –100 –50 µA Only for pins with pull-up resistor Output leakage current ILO1 P40 to P47, P50 to P57, P60 to P67 VI = VCC – 35 V — — –10 µA Pull-up resistance RPULL RST, P14 to P17, P32 to P37 VI = 0.0 V 25 50 100 kΩ VCC FCH = 8 MHz, VCC = 5.0 V, tinst = 0.5 µs, when A/D conversion is stopped — 9 15 mA “H” level output voltage VOL1 “L” level output voltage Input leakage current Power supply current ICC1 Except P31 (Continued) 21 MB89143A/144A (Continued) Parameter Symbol Pin FCH = 8 MHz, VCC = 3.5 V, tinst = 8.0 µs, when A/D conversion is stopped — 1.5 2 mA FCH = 8 MHz VCC = 5.0 V tinst = 0.5 µs — 3 7 mA FCH = 8 MHz VCC = 3.5 V tinst = 8.0 µs — 1 1.5 mA ICCL FCL = 32.768 kHz VCC = 3.0 V Subclock mode — 50 150 µA ICCLS FCL = 32.768 kHz VCC = 3.0 V Subclock mode — 25 50 µA ICCT FCL = 32.768 kHz VCC = 3.0 V • Watch mode • Main clock stop mode at dual-clock system — 3 15 µA ICCH FCL = 32.768 kHz TA = +25°C • Subclock stop mode • Main clock stop mode at single-clock system — — 10 µA ICCA FCH = 8 MHz, VCC = 5.0 V, TA = +25°C, tinst = 0.5 µs, when A/D conversion is activated — 11.5 19.5 mA IR FCH = 8 MHz, TA = +25°C, when A/D conversion is activated — 200 — µA FCH = 8 MHz, TA = +25°C, when A/D conversion is stopped — — 10 µA f = 1 MHz — 10 — pF Sleep mode ICC2 ICCS1 ICCS2 VCC Power supply current AVR IRH Input capacitance (AVR = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. CIN Other than AVSS, AVR, VCC, and VSS Note: The power supply current is measured at the external clock. 22 When the gear function is used, the power supply current varies with the measurement point. MB89143A/144A 4. AC Characteristics (1) Reset Timing Parameter Symbol (AVR = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. RST “L” pulse width tZLZH — 16 tXCYL — — ns RST noise limit width tZLNC — 20 40 60 ns Note: tXCYL is the oscillation cycle (1/FCH) to input to the X0 pin. tZLZH tZLNC RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Condition Value Min. Max. Unit Remarks Power supply rising time tR — — 50 ms Power-on reset function only Power supply cut-off time tOFF — 1 — ms Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 2.0 V 0.2 V VCC 0.2 V 0.2 V 23 MB89143A/144A (3) Clock Timing Parameter Symbol Clock frequency Clock cycle time Input clock pulse width Input clock rising/ falling time Pin (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Typ. Max. Condition Min. FCH X0, X1 — 2 — 8 MHz FCL X0A, X1A — — 32.768 — kHz tXCYL X0, X1 — 125 — 500 ns tLXCYL X0A, X1A — — 30.5 — µs PWH PWL X0 — 30 — — ns PWHL PWLL X0A — — 15.2 — ns tCR tCF X0, X0A — — — 10 ns External clock X0 and X1 Timings and Conditions tXCYL PWH PWL tCR tCF 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic resonator is used X0 X1 When an external clock is used X0 X1 Open C0 24 C1 External clock MB89143A/144A X0A and X1A Timings and Conditions tLXCYL PWHL PWLL tCF tCR 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC Subclock Conditions When a crystal or ceramic resonator is used X0A When an external clock is used X0A X1A X1A Open RF C0 RD C1 Note: The subclock oscillator feedback resistor is connected externally in dual-clock products. (4) Instruction Cycle Parameter Symbol Value (typical) Unit Remarks 4/FCH, 8/FCH, 16/FCH, 32/FCH µs (4/FCH) tinst = 0.5 µs when operating at FCH = 8 MHz 2/FCL µs tinst = 61.036 µs when operating at FCL = 32.768 kHz Instruction cycle time tinst Note: When operating at 8 MHz, the cycle varies with the set execution time. 25 MB89143A/144A (5) Serial I/O timing Parameter Symbol Pin (AVR = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Max. 2 tinst* — µs –200 200 ns 1/2 tinst* — µs 1/2 tinst* — µs 1 tinst* — µs 1 tinst* — µs 0 200 ns SI, SCK 1/2 tinst* — µs SCK, SI 1/2 tinst* — µs Serial clock cycle time tSCYC SCK SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SI, SCK SCK ↑ → valid SI hold time tSHIX SCK, SI Serial clock “H” pulse width tSHSL SCK Serial clock “L” pulse width tSLSH SCK SCK ↓ → SO time tSLOV SCK, SO Valid SI → SCK ↑ tIVSH SCK ↑ → valid SI hold time tSHIX Internal shift clock mode External shift clock mode * : For information on tinst, see “(4) Instruction Cycle.” Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SO 0.8 V tIVSH SI tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH SCK SO tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.8 V tIVSH SI 26 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC MB89143A/144A (6) Peripheral Input Timing (AVR = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Condition Min. Max. Unit Peripheral input “H” pulse width 1 tILIH1 EC, ADST, INT0 to INT1 — 2 tinst — µs Peripheral input “L” pulse width 1 tIHIL1 EC, ADST, INT0 to INT1 — 2 tinst — µs tIHIL1 INT0 to INT1, EC, ADST Remarks tILIH1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC (7) Peripheral Input Noise Limit Width (AVR = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Value Pin Min. Typ. Max. Unit Peripheral input “H” level noise limit width 1 tIHNC1 INT1, INT0 50 100 250 ns Peripheral input “L” level noise limit width 1 tILNC1 INT1, INT0 50 100 250 ns Remarks Note: The minimum values is always canceled, while values over the maximum value are not canceled. tILNC1 tIHNC1 INT0, INT1 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 27 MB89143A/144A 5. A/D Converter Electrical Characteristics Parameter Symbol (VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, FCH = 8 MHz, TA = –40°C to +85°C) Value Condition Unit Remarks Pin Min. Typ. Max. Resolution — — — — — 8 bit Total error — — — — — ±3.0 LSB Linearity error — — — — — ±1.0 LSB Differential linearity error — — — — — ±0.9 LSB Zero transition voltage VOT AN0 to AN7 — AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV Full-scale transition voltage VFST AN0 to AN7 — AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB mV Interchannel disparity — — — — — 1.0 LSB A/D conversion time — — — — 44 tinst — µs Sense mode conversion time — — — — 12 tinst — µs — — 10 µA Analog port input current IAIN = AN0 to AN7 AVR VCC = 5.0 V Analog input voltage — AN0 to AN7 — 0 — AVR V Reference voltage — AVR — 4.5 — VCC V AVR AVR = 5.0 V — 200 — µA Reference-voltage supply current IR Notes: • The smaller the | AVR – AVSS |, the greater the error would become relatively. • The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 kΩ If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 22 µs at 8 MHz oscillation). Analog Input Equivalent Circuit Sample hold circuit . C =. 33 pF Analog input pin Comparator If the analog input impedance is 10 kΩ or more, it is recommended to connect an external capacitor of approx. 0.1 µF. 28 . R =. 6 kΩ Close for 8 instruction cycles after activating A/D conversion. Analog channel selector MB89143A/144A 6. A/D Glossary • Resolution Analog changes that are identifiable with the A/D converter • Linearity error The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error The difference between actual and theoretical value This error is caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise. Theoretical I/O characteristics 1111 1111 1111 1110 Theoretical conversion value 1 LSB = Digital output Actual conversion value AVR 256 Linearity error = (1 LSB × N + VOT) Differential linearity error = Linearity error 0000 0010 Total error = VNT − (1 LSB × N + VOT) 1 LSB V(N+1)T − VNT 1 LSB −1 VNT − (1 LSB × N + 0.5 LSB) 1 LSB 0000 0001 0000 0000 VOT VNT V(N+1)T VFST Analog input 29 MB89143A/144A ■ INSTRUCTIONS Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 30 MB89143A/144A (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: •“–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH immediately before the instruction is executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 31 MB89143A/144A Table 2 Mnemonic ~ # MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) TL TH AH NZVC OP code – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 32 MB89143A/144A Table 3 Arithmetic Operation Instructions (62 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) →C →A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 toDF D3 D2 D0 01 11 63 73 53 12 13 03 ROLC A 2 1 C←A← – – – ++–+ 02 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 33 MB89143A/144A (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) +off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Table 4 Branch Instructions (17 instructions) Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # Operation TL TH AH NZVC OP code 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 Other Instructions (9 instructions) Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI 34 ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 L B C D E F MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP 5 ADDC A SUBC A XCH XOR AND OR A, T A A A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel C D E F rel rel rel rel B MOVW XCHW IX,#d16 A,IX MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 MOVW MOVW A,@IX +d @IX +d,A A CLRB BBC dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 CMP @IX +d,#d8 @IX +d,#d8 9 MOV MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel OR A,@IX +d 8 XOR AND A,@IX +d A,@IX +d MOV CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 MOV @IX +d,A 7 SUBC A,@IX +d CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MOV A,@IX +d ADDC A,@IX +d DAS 6 CMP A,@IX +d XOR AND OR DAA A,#d8 A,#d8 A,#d8 MOVW MOVW CLRB BBC INCW DECW MOVW MOVW CMPW ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP A A SETC 4 A CMP PUSHW POPW MOV MOVW CLRC JMP CALL IX IX ext,A PS,A addr16 addr16 RORC A DIVU 3 CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A ROLC A SETI 7 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 6 9 5 8 4 2 A RETI 3 MULU RET 2 1 SWAP 1 NOP 0 0 H MB89143A/144A ■ INSTRUCTION MAP 35 MB89143A/144A ■ MASK OPTIONS No. Part number Parameter MB89143A/144A Specification method Specify when ordering masking MB89PV140 101 102 MB89P147V1 Set in EPROM 1 Clock mode selection Single-clock mode Dual-clock mode Can be set Single clock Dual clock 2 Pull-up resistors P14 to P17, P32 to P37 Specify by pin Without pull- Without pullCan be set per pin up resistor up resistor 3 Power-on reset With Without With power-on rest With power- With powerCan be set on reset on reset 4 Reset output With Without Can be set With reset output 5 Pull-down resistors P40 to P47 P50 to P57 P60 to P67 Without pull-down resistor Without pull- Without pullWithout pull-down down down resistor resistor resistor With reset output Can be set Can be set ■ ORDERING INFORMATION Part number MB89143AP MB89144AP 36 Package 64-pin Plastic SH-DIP (DIP-64P-M01) Remarks MB89143A/144A ■ PACKAGE DIMENSIONS 64-pin Plastic SH-DIP (DIP-64P-M01) +0.22 58.00 –0.55 +.008 2.283 –.022 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 5.65(.222)MAX 0.25±0.05 (.010±.002) 3.00(.118)MIN +0.50 1.00 –0 +.020 .039 –0 0.45±0.10 (.018±.004) 0.51(.020)MIN 15°MAX 19.05(.750) TYP 1.778±0.18 (.070±.007) 1.778(.070) MAX C 1994 FUJITSU LIMITED D64001S-3C-4 55.118(2.170)REF Dimensions in mm (inches) 37 MB89143A/144A FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. F9606 FUJITSU LIMITED Printed in Japan 38