FUJITSU MB89P867

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12504-5E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89860/850 Series
MB89865/867/P867/W867
MB89855/857/P857/W857/T855
■ DESCRIPTION
The MB89860/850 series has been developed as a general-purpose version of the F2MC*-8L family consisting
of proprietary 8-bit, single-chip, microcontrollers.
In addition to the F2MC-8L CPU core which can operate at low voltage but at high speed, the microcontrollers
contain a variety of peripheral functions such as a timer unit, PWM timers, a UART, a serial interface, a 10-bit
A/D converter, and an external interrupt.
The MB89860/850 series is applicable to a wide range of applications from welfare products to industrial
equipment, including portable devices.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Various package options
QFP package (80 pins): MB89860
SDIP package (64 pins): MB89850
• High-speed processing at low voltage
Minimum execution time: 0.4 µs/3.5 V, 0.8 µs/2.7 V
(Continued)
■ PACKAGE
80-pin Plastic QFP
64-pin Plastic SH-DIP
80-pin Ceramic QFP
64-pin Plastic SH-DIP
(FPT-80P-M06)
(DIP-64P-M01)
(FPT-80C-A02)
(DIP-64C-A06)
MB89860/850 Series
(Continued)
• F2MC-8L family CPU core
Instruction set optimized for controllers
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Bit manipulation instructions, etc.
• 8-bit PWM timers: 2 channels
Also usable as a reload timer
• UART
Full-duplex double buffer
Synchronous and asynchronous data transfer
• 8-bit serial I/O
Switchable transfer direction allows communication with various equipment.
• 10-bit A/D converter
Conversion time: 13.2 µs
Activation by an external input or a timer unit capable
• External interrupt: 4 channels
Four channels are independent and capable of wake-up from low-power consumption modes (with an edge
detection function).
• Low-power consumption modes
Stop mode (Oscillation stops to minimize the current consumption.)
Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)
• Bus interface functions
Including hold and ready functions
• Timer unit
Outputs non-overlap three-phase waveforms to control an AC inverter motor.
Also usable as a PWM timer (4 channels)
2
MB89860/850 Series
■ PRODUCT LINEUP
Part number
Parameter
MB89855
MB89T855
MB89865
MB89857
MB89867
Classification
Mass production products (mask ROM products)
ROM size
32 K × 8 bits
(internal mask ROM)
16 K × 8 bits
(internal mask ROM)
Note: In MB89T855, no
internal ROM can be used but
external ROM is used.
RAM size
512 × 8 bits
MB89P857
MB89W857
MB89P867
MB89W867
One-time PROM pruducts/
EPROM products, also
used for evaluation
32 K × 8 bits
(internal PROM,
programming with generalpurpose EPROM
programmer)
1 K × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 µs/10 MHz
3.6 µs/10 MHz
Ports
Input ports:
Output ports (N-ch open drain):
I/O ports (N-ch open drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
5 (All also serve as peripherals)
8 (All also serve as peripherals)
15 (MB89860 series only)
8 (All also serve as bus control pins)
32 (All also serve as bus pins or peripherals)
68 (53 pins for MB89850 series)
Timer unit
8-bit PWM timer 1,
8-bit PWM timer 2
UART
8-bit serial I/O
10-bit A/D converter
10-bit up/down count timer × 1
Compare registers with buffer × 4
Compare timer unit clear register with buffer × 1
Zero detection pin control
4 output channels
Non-overlap three-phase waveform output
Independent three-phase dead-time timer
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to
25.6 µs)
8-bit resolution PWM operation (conversion cycle: 102 µs to 6.528 ms)
8 bits
Clock synchronous/asynchronous data transfer capable
8 bits
LSB first/MSB first selectability
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
10-bit resolution × 8 channels
A/D conversion time: 13.2 µs
Continous activation by a compare channel 0 in timer unit or an external activation capable
External interrupt
4 independent channels (edge selection, interrupt vector, source flag)
Rising edge/falling edge selectability.
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
Standby modes
Sleep mode, stop mode
Process
Operating voltage*
CMOS
2.7 V to 6.0 V
2.7 V to 5.5 V
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
3
MB89860/850 Series
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89855
MB89T855
MB89857
MB89P857
Package
DIP-64P-M01
MB89W857
MB89865
MB89867
MB89P867
MB89W867
×
×
×
×
×
DIP-64C-A06
×
FPT-80P-M06
×
×
FPT-80C-A02
×
×
: Available
×
×
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the OTPROM (one-time PROM) products (also used for evaluation), verify its differences
from the product that will actually be used.
Take particular care on the following point:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the
product with a mask ROM.
However, the current consumption in sleep/stop modes is the same.
3. Mask Options
In the MB89P857/W857/P867/W867/T855, no option can be set.
Before using options check section “■ Mask Options.”
Take particular care on the following point:
• A pull-up resistor can be set for P00 to P07, P10 to P17 and P20 to P27 only at single-chip mode.
4
MB89860/850 Series
■ PIN ASSIGNMENT
(Top view)
P31/SO1
P30/SCK1
P47/TRGI
P46/Z
P45/Y
P44/X
P43/RTO3/W
P42/RTO2/V
P41/RTO1/U
P40/RTO0
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P64/DTTI
P63/INT3/ADST
P62/INT2
P61/INT1
P60/INT0
RST
MOD0
MOD1
X0
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P32/SI1
P33/SCK2
P34/SO2
P35/SI2
P36/PTO1
P37/PTO2
VSS
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
P07/AD7
P10/A08
P11/A09
P12/A10
P13/A11
P14/A12
P15/A13
P16/A14
P17/A15
P20/BUFC
P21/HAK
P22/HRQ
P23/RDY
P24/CLK
P25/WR
P26/RD
P27/ALE
(DIP-64P-M01)
(DIP-64C-A06)
5
MB89860/850 Series
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P83
AVSS
AVR
AVCC
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
P84
P85
P86
P87
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P17/A15
P16/A14
P15/A13
P14/A12
P13/A11
P12/A10
P11/A09
P10/A08
P07/AD7
P06/AD6
P05/AD5
P04/AD4
P03/AD3
P02/AD2
P01/AD1
P00/AD0
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P82
P81
P80
P76
P75
P74
P73
P72
P71
P70
MOD0
MOD1
X0
X1
VSS
RST
P27/A L E
P26/RD
P25/WR
P24/C L K
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
(FPT-80P-M06)
(FPT-80C-A02)
6
N.C.
P40/RTO0
P41/RTO1/U
P42/RTO2/V
P43/RTO3/W
P44/X
VSS
P45/Y
P46/Z
VCC
P47/TRGI
P60/INT0
P61/INT1
P62/INT2
P63/INT3/ADST
P64/DTTI
P30/SCK1
P31/SO1
P32/SI1
P33/SCK2
P34/SO2
P35/SI2
P36/PTO1
P37/PTO2
MB89860/850 Series
■ PIN DESCRIPTION
Pin no.
SH-DIP
*1
*2
QFP
Pin name
30
13
X0
31
14
X1
28
11
MOD0
29
12
MOD1
27
16
56 to 49
Circuit
type
Function
A
Crystal oscillator pins (10 MHz)
B
Operating mode selection pins
Connect directly to VCC or VSS.
RST
C
Reset I/O pin
This pin is an N-ch open-drain output type with a pull-up
resistor, and a hysteresis input type. “L” is output from this
pin by an internal reset source. The internal circuit is
initialized by the input of “L”.
40 to 33
P00 /AD0 to
P07/AD7
D
General-purpose I/O ports
When an external bus is used, these ports function as
multiplex pins of lower address output and data I/O.
48 to 41
32 to 25
P10 /A08 to
P17/A15
D
General-purpose I/O ports
When an external bus is used, these ports function as
upper address output.
40
24
P20/BUFC
F
General-purpose output port
When an external bus is used, this port can also be used
as a buffer control output.
39
23
P21/HAK
F
General-purpose output port
When an external bus is used, this port can also be used
as a hold acknowledge output.
38
22
P22/HRQ
D
General-purpose output port
When an external bus is used, this port can also be used
as a hold request input.
37
21
P23/RDY
D
General-purpose output port
When an external bus is used, this port functions as a
ready input.
36
20
P24/CLK
F
General-purpose output port
When an external bus is used, this port functions as a
clock output.
35
19
P25/WR
F
General-purpose output port
When an external bus is used, this port functions as a
write signal output.
34
18
P26/RD
F
General-purpose output port
When an external bus is used, this port functions as a
read signal output.
33
17
P27/ALE
F
General-purpose output port
When an external bus is used, this port functions as an
address latch signal output.
2
48
P30/SCK1
E
General-purpose I/O port
Also serves as the clock I/O for the UART.
This port is a hysteresis input type.
*1: DIP-64P-M01, DIP-64C-A06
(Continued)
*2: FPT-80P-M06, FPT-80C-A02
7
MB89860/850 Series
(Continued)
Pin no.
Pin name
Function
QFP*2
1
47
P31/SO1
E
General-purpose I/O port
Also serves as the data output for the UART.
This port is a hysteresis input type.
63
46
P32/SI1
E
General-purpose I/O port
Also serves as the data input for the UART.
This port is a hysteresis input type.
62
45
P33/SCK2
E
General-purpose I/O port
Also serves as the clock I/O for the 8-bit serial I/O.
This port is a hysteresis input type.
61
44
P34/SO2
E
General-purpose I/O port
Also serves as the data output for the 8-bit serial I/O.
This port is a hysteresis input type.
60
43
P35/SI2
E
General-purpose I/O port
Also serves as the data input for the 8-bit serial I/O.
This port is a hysteresis input type.
59
42
P36/PTO1
E
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 1.
This port is a hysteresis input type.
58
41
P37/PTO2
E
General-purpose I/O port
Also serves as the pulse output for the 8-bit PWM timer 2.
This port is a hysteresis input type.
10
63
P40/RTO0
E
General-purpose I/O port
Also serves as the pulse output for the timer unit.
This port is a hystereisis input type.
9,
8,
7
62,
61,
60
P41/RTO1/U,
P42/RTO2/V,
P43/RTO3/W
E
General-purpose I/O ports
Also serve as the pulse output for the timer unit or a nonoverlap three-phase waveform output.
These ports are a hysteresis input type.
6,
5,
4
59,
57,
56
P44/X,
P45/Y,
P46/Z
E
General-purpose I/O ports
Also serve as a non-overlap three-phase output.
These ports are a hysteresis input type.
3
54
P47/TRGI
E
General-purpose I/O port
Also serves as the trigger input for the timer unit.
This port is a hysteresis input type.
11 to 18
69 to 76
P50/AN0 to
P57/AN7
H
N-ch open-drain output ports
Also serve as the analog input for the A/D converter.
26 to 24
53 to 51
P60/INT0 to
P62/INT2
I
General-purpose input ports
Also serve as an external interrupt input.
These ports are a hysteresis input type.
23
50
P63/INT3/
ADST
I
General-purpose input port
Also serves as an external interrupt input and as the
activation trigger input for the A/D converter.
This port is a hysteresis input type.
*1: DIP-64P-M01, DIP-64C-A06
*2: FPT-80P-M06, FPT-80C-A02
8
Circuit
type
SH-DIP*1
(Continued)
MB89860/850 Series
(Continued)
Pin no.
SH-DIP*1
QFP*2
22
49
—
Pin name
Circuit
type
Function
P64/DTTI
I
General-purpose input port
Also serves as a dead-time timer disable input.
This port is a hysteresis input type.
DTTI input is with a noise canceller.
10 to 4
P70 to P76
G
N-ch open-drain I/O ports
These ports are a hysteresis input type.
—
3 to 1, 80,
68 to 65
P80 to P87
G
N-ch open-drain I/O ports
These ports are a hysteresis input type.
64
55
VCC
—
Power supply pin
32, 57
15, 58
VSS
—
Power supply (GND) pins
19
77
AVCC
—
A/D converter power supply pin
20
78
AVR
—
A/D converter reference voltage input pin
21
79
AVSS
—
A/D converter power supply (GND) pin
Use this pin at the same voltage as VSS.
—
64
N.C.
—
Internally connected pin
Be sure to leave it open.
*1: DIP-64P-M01, DIP-64C-A06
*2: FPT-80P-M06, FPT-80C-A02
9
MB89860/850 Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
• At an oscillation feedback resitor of approximately
1 MΩ/5.0 V
X1
X0
Standby control signal
B
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
• Hysteresis input
R
P-ch
N-ch
D
• CMOS output
• CMOS input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
E
• CMOS output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
(Continued)
10
MB89860/850 Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
R
P-ch
P-ch
N-ch
G
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
• N-ch open-drain output
• Hysteresis input
R
P-ch
P-ch
N-ch
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
H
• N-ch open-drain output
• Analog input
P-ch
N-ch
Analog input
I
R
• Hysteresis input
• Pull-up resistor optional (Mask ROM products)
• At a pull-up resistor of approximately 50 kΩ/5.0 V
11
MB89860/850 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pin open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
12
MB89860/850 Series
■ PROGRAMMING TO THE EPROM ON THE MB89P867/W867/P857/W857
The MB89P867/W867/P857/W857 are an OTPROM version of the MB89860/850 series.
1. Features
• 32-Kbyte PROM on chip
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in EPROM mode is diagrammed below.
Address
Single chip
0000H
EPROM mode
( Corresponding addresses on the EPROM programmer)
I/O
0080H
RAM
0480H
Not available
8000H
0000H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P867/W867/P857/W857 functions equivalent to the MBM27C256A. This allows the
PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot
be used) by using the dedicated socket adapter.
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH (note that addresses 8000H to FFFFH
while operating as a single chip assign to addresses 0000H to 7FFFH in EPROM mode.)
(3) Program to 0000H to 7FFFH with the EPROM programmer.
13
MB89860/850 Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This
dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity
of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all
filters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having
wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,
nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and
exposure to them should be prevented to realize maximum system reliability. If used in such an environment,
the package windows should be covered by an opaque label or substance.
7. EPROM Programmer Socket Adapter
Package
Compatible socket adapter
DIP-64P-M01
ROM-64SD-28DP-8L*
FPT-80P-M01
ROM-80QF-28DP-8L2
* : Connect the adapter jumper pin to VSS when using.
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
14
MB89860/850 Series
■ BLOCK DIAGRAM
Time-base timer
Oscillator
Clock controller
Reset circuit
(WDT)
RST
MOD0
MOD1
P36/PTO1
8-bit serial I/O
P35/SI2
P34/SO2
P33/SCK2
External bus
interface
P32/SI1
P31/SO1
P30/SCK1
UART
CMOS I/O port
CMOS I/O port
Port 2
P27/ALE
P26/RD
P25/WR
P24/CLK
P23/RDY
P22/HRQ
P21/HAK
P20/BUFC
8-bit PWM timer 1
6
P47/TRGI
P46/Z
P45/Y
P44/X
P43/RTO3/W
P42/RTO2/V
P41/RTO1/U
P40/RTO0
Port 4
8
Internal bus
P10/A08
to P17/A15
8
P37/PTO2
CMOS I/O port
Port 0 and port 1
P00/AD0
to P07/AD7
8-bit PWM timer 2
Port 3
X0
X1
Timer unit
CMOS output port
(Dead-time timer)
4
RAM
External interrupt
Port 6
P64/DTTI
3
P60/INT0
to P62/INT2
P63/INT3/ADST
F2MC-8L
Input port
CPU
AVR
AVCC
AVSS
8
Other pins
VCC , VSS × 2
10-bit A/D converter
Part number
RAM size
ROM size
MB89865/855/T855*1
512 bytes
16 Kbytes
1 Kbyte
32 Kbytes
MB89857/867
1 Kbyte
8
P50/AN0
to P57/AN7
N-ch open-drain output port
*2
7
P70 to P76
N-ch open-drain I/O port
Port 7 and port 8
MB89W857/P867
Port 5
ROM
8
32 Kbytes
P80 to P87
(EPROM)
*1: In the MB89T855, an external ROM can be used.
*2: Not included in the MB89850 series.
15
MB89860/850 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89860/850 series offer a memory space of 64 Kbytes for storing all of I/O, data,
and program areas. The I/O area is located at the lowest address. The data area is provided immediately above
the I/O area. The data area can be divided into register, stack, and direct areas according to the application.
The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables
of interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89860/850 series is structured as illustrated below.
Memory Space
MB89867/857
MB89W867/P867
MB89W857/P857
MB89865
MB89855/T855*2
0000H
0000H
I/O
I/O
0080H
0080H
RAM
512 B
RAM
1 KB
0100H
0100H
Register
Register
0200H
0200H
0280H
0480H
External area
External area
8000H
C000H
1
ROM *
32 KB
1
ROM *
16 KB
FFFFH
FFFF H
*1: The ROM area is an external area depending on the mode.
*2: In the MB89T855, an external ROM can be used.
16
MB89860/850 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T):
A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 8-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
RP
11
10
9
8
Vacancy Vacancy Vacancy
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
17
MB89860/850 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
18
MB89860/850 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89860/850 series. The bank currently in use
is indicated by the register bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuration
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
32 banks
Memory area
19
MB89860/850 Series
■ I/O MAP
Address
Read/write
Register name
Register description
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
(W)
BCTR
External bus pin control register
06H
Vacancy
07H
Vacancy
08H
(R/W)
STBC
Standby control register
09H
(W)
WDTC
Watchdog timer control register
0AH
(R/W)
TBTC
Time-base timer control register
Vacancy
0BH
0CH
(R/W)
PDR3
Port 3 data register
0DH
(W)
DDR3
Port 3 data direction register
0EH
(R/W)
PDR4
Port 4 data register
0FH
(W)
DDR4
Port 4 data direction register
10H
(R/W)
PDR5
Port 5 data register
11H
12H
Vacancy
(R)
PDR6
13H
14H
Vacancy
(R/W)
PDR7
Port 7 data register
Vacancy
15H
16H
Port 6 data register
(R/W)
PDR8
17H to 1BH
Port 8 data register
Vacancy
1CH
(R/W)
CTR1
PWM control register 1
1DH
(W)
CMR1
PWM compare register 1
1EH
(R/W)
CTR2
PWM control register 2
1FH
(W)
CMR2
PWM compare register 2
20H
(R/W)
SMC
UART serial mode control register
21H
(R/W)
SRC
UART serial rate control register
22H
(R/W)
SSD
UART serial status/data register
23H
(R/W)
SIDR/SODR
24H
(R/W)
SMR
Serial mode register
25H
(R/W)
SDR
Serial data register
UART serial data register
(Continued)
20
MB89860/850 Series
(Continued)
Address
Read/write
Register name
Register description
26H
(R/W)
EIC1
External interrupt control register 1
27H
(R/W)
EIC2
External interrupt control register 2
28H
(R/W)
ADC1
A/D converter control register 1
29H
(R/W)
ADC2
A/D converter control register 2
2AH
(R)
ADDH
A/D converter data register (H)
2BH
(R)
ADDL
A/D converter data register (L)
Vacancy
2CH
2DH
(W)
ZOCTR
2EH
(W)
CLRBRH
Compare clear buffer register (H)
2FH
(W)
CLRBRL
Compare clear buffer register (L)
30H
(R/W)
TCSR
Timer control status register
31H
(R/W)
CICR
Compare interrupt control register
32H
(R/W)
TMCR
Timer mode control register
33H
(R/W)
COER
Compare/port selection register
34H
(R/W)
CMCR
Compare buffer mode control register
35H
(R/W)
DTCR
Dead-time timer control register
36H
(W)
DTSR
Dead-time setting register
37H
(R/W)
OCTBR
38H
(W)
OCPBR0H
Output compare buffer register 0 (H)
39H
(W)
OCPBR0L
Output compare buffer register 0 (L)
3AH
(W)
OCPBR1H
Output compare buffer register 1 (H)
3BH
(W)
OCPBR1L
Output compare buffer register 1 (L)
3CH
(W)
OCPBR2H
Output compare buffer register 2 (H)
3DH
(W)
OCPBR2L
Output compare buffer register 2 (L)
3EH
(W)
OCPBR3H
Output compare buffer register 3 (H)
3FH
(W)
OCPBR3L
Output compare buffer register 3 (L)
40H to 7BH
Zero detection output control register
Output control buffer register
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Vacancy
Notes: • Do not use vacancies.
• When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register
containing a write-only bit, a bit designated by the instruction will have a predetermined value. However,
a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access
to the register should be tried with any read-modefy-write instruction.
21
MB89860/850 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value
Min.
Max.
Unit
Remarks
Power supply voltage
VCC
AVCC
VSS – 0.3
VSS + 7.0
V
*
A/D converter reference input
voltage
AVR
VSS – 0.3
VSS + 7.0
V
AVR must not exceed AVCC +
0.3 V.
Program voltage
VPP
VSS – 0.3
13.0
V
MOD1 pins of MB89P867/
W867 and MB89P857/W857
Input voltage
VI
VSS – 0.3
VCC + 0.3
V
Output voltage
VO
VSS – 0.3
VSS + 0.3
V
“L” level maximum output current
IOL
—
20
mA
“L” level average output current
IOLAV1
—
4
mA
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P76,
P80 to P87
IOLAV2
—
15
mA
P40 to P47
ΣIOLAV1
—
30
mA
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P76,
P80 to P87
ΣIOLAV2
—
50
mA
P40 to P47
“H” level maximum output current IOH
—
–20
mA
“H” level average output current
IOHAV
—
–4
mA
“H” level total maximum output
current
ΣIOH
—
–20
mA
Power consumption
PD
—
300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
“L” level total average output
current
*: Use AVCC and VCC set at the same voltage.
Take care so that AVCC does not exceed VCC, such as when power is turned on.
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
22
MB89860/850 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Value
Symbol
VCC
AVCC
Power supply voltage
Min.
Max.
2.7*
6.0*
Unit
Remarks
V
Normal operation assurance
range*
MB89867/865, MB89857/855
2.7*
5.5*
V
Normal operation assurance
range*
MB89P867/W867,
MB89P857/W855/T855
1.5
6.0
V
Retains the RAM state in stop
mode
A/D converter reference input
voltage
AVR
0.0
AVCC
V
Operating temperature
TA
–40
+85
°C
*: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics.”
Note: Connect the MOD0 and MOD1 pins to VCC or VSS.
6
5.5
Analog accuracy assured in the
VCC = AVCC = 3.5 V to 6.0 V range
5
Operating voltage (V)
Operation assurance range
4
3
2
1
1
2
3
4
5
6
7
8
9
10
Clock operating frequency (MHz)
(µs)
4.0
2.0
0.8
0.4
Minimum execution time (instruction cycle)
Note: The shaded area is assured only for the MB89865/867/855/857.
Figure 1
Operating Voltage vs. Clock Operating Frequency
23
MB89860/850 Series
3. DC Characteristics
(AVCC = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
VIH
P00 to P07, P10 to P17,
P22, P23
VIHS
Unit
Min.
Typ.
Max.
—
0.7 VCC
—
VCC +
0.3
V
RST, P30 to P37,
P40 to P47, P60 to P64,
P70 to P76, P80 to P87
—
0.8 VCC
—
VCC +
0.3
V
VIL
P00 to P07, P10 to P17,
P22, P23
—
VSS –
0.3
—
0.3 VCC
V
VILS
RST, P30 to P37,
P40 to P47, P60 to P64,
P70 to P76, P80 to P87
—
VSS –
0.3
—
0.2 VCC
V
VOH
P00 to P07, P10 to P17, IOH = –2.0
P20 to P27, P30 to P37,
mA
P40 to P47
2.4
—
—
V
VOL1
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P50 to P57, P70 to P76, IOL = 1.8 mA
P80 to P87
—
—
0.4
V
VOL2
P40 to P47
IOL = 15 mA
—
—
1.5
V
Input leackage
current
ILI1
P00 to P07, P10 to P17,
P20 to P27, P30 to P37, 0.0 V < VI <
P40 to P47, P60 to P64,
P70 to P76, P80 to P87, VCC
MOD0, MOD1
—
—
±5
µA
Pull-up resistance
RPULL
RST
VI = 0.0 V
25
50
100
kΩ
FC = 10 MHz
Normal
operation
mode
(External
clock)
—
15
18
mA
ICCS
FC = 10 MHz
Sleep mode
(External
clock)
—
6
8
mA
ICCH
Stop mode
TA = +25°C
—
—
10
µA
IA
AVCC
FC = 10 MHz,
when A/D
conversion is
activated
—
6
—
mA
CIN
Other than AVCC,
AVSS, VCC, and VSS
f = 1 MHz
—
10
—
pF
“H” level input
voltage
“L” level input
voltage
“H” level output
voltage
“L” level output
voltage
ICC
VCC
Power supply
current
Input capacitance
24
Value
Remarks
With pullup resistor
MB89860/850 Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
RST “L” pulse width
Condition
tZLZH
Unit
—
Min.
Max.
16 tXCYL*
—
Remarks
ns
* : tXCYL is the oscillation cycle (1/FC) to input to the X0 pin.
t ZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Power supply rising time
Symbol
Condition
tR
Unit
Remarks
50
ms
Power-on reset function only
—
ms
Due to repeated operations
Min.
Max.
—
1
—
Power supply cut-off time
tOFF
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tOFF
tR
2.0 V
VCC
0.2 V
0.2 V
0.2 V
25
MB89860/850 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Clock frequency
FC
Clock cycle time
tXCYL
Input clock pulse width
PWH
PWL
Input clock rising/falling time
tCR
tCF
Pin
Condition
X0, X1
Value
Unit
Remarks
Min.
Max.
1
10
MHz
100
1000
ns
20
—
ns
External clock
—
10
ns
External clock
—
X0
X0 and X1 Timing Conditions
tXCYL
PWH
PWL
tCR
0.8 VCC
tCF
0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
Clock Conditions
When a crystal
or
ceramic resonator is used
X0
When an external clock is used
X1
X0
X1
Open
(4) Instruction Cycle
Parameter
Instruction cycle
(minimum execution time)
26
Symbol
tinst
Value (typical)
Unit
Remarks
4/FC
µs
tinst = 0.4 µs when operating at
FC = 10 MHz
MB89860/850 Series
(5) Recommended Resonator Manufacturers
Sample Application of Piezoelectric Resonator (FAR Series)
X0
X1
FAR*
C1
C2
*: Fujitsu Acoustic Resonator
C1 = C2 = 20 pF±8 pF (built-in FAR)
FAR part number
(built-in capacitor type)
deviation of
Frequency FAR Initial
frequency (TA = +25°C)
Temperature characteristics
of FAR frequency
(TA = –25°C to +60°C)
FAR-C4CB-08000-M02
8.00 MHz
±0.5%
±0.5%
FAR-C4CB-10000-M02
10.00 MHz
±0.5%
±0.5%
Inquiry: FUJITSU LIMITED
27
MB89860/850 Series
Sample Application of Ceramic Resonator
X0
X1
*
C1
Resonator manufacturer*
Kyocera Corporation
Murata Mfg. Co., Ltd.
Resonator
C2
Frequency
C1 (pF)
C2 (pF)
R (kΩ)
KBR-7.68MWS
7.68 MHz
33
33
—
KBR-8.0MWS
8.0 MHz
33
33
—
CSA8.00MTZ
8.0 MHz
30
30
—
Inquiry: Kyocera Corporation
• AVX Corporation
North American Sales Headquarters: TEL 1-803-448-9411
• AVX Limited
European Sales Headquarters: TEL 44-1252-770000
• AVX/Kyocera H.K. Ltd.
Asian Sales Headquarters: TEL 852-363-3303
Murata Mfg. Co., Ltd.
• Murata Electronics North America, Inc.: TEL 1-404-436-1300
• Murata Europe Management GmbH: TEL 49-911-66870
• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
28
MB89860/850 Series
(6) Clock Output Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Cycle time
Symbol
Pin
tCYC
CLK
CLK ↑ → CLK ↓
tCHCL
Value
Condition
Load
condition:
50 pF
Unit
Remarks
—
ns
tXCYL × 2 at 10 MHz
oscillation
100
ns
Approx. tCYC/2 at
10 MHz oscillation
Min.
Max.
200
30
t CYC
t CHCL
2.4 V
2.4 V
CLK
0.8 V
29
MB89860/850 Series
(7) Bus Read Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Value (10 MHz)
Min.
Max.
Unit
Valid address → RD ↓
time
tAVRL
RD, A15 to A08,
AD7 to AD0
1/4 tinst* – 64 ns
—
ns
RD pulse width
tRLRH
RD
1/2 tinst* – 20 ns
—
ns
Valid address → data
read time
tAVDV
AD7 to AD0,
A15 to A08
—
1/2 tinst*
ns
No wait
RD ↓ → data read time
tRLDV
RD, AD7 to AD0
—
1/2 tinst* – 80 ns
ns
No wait
RD ↑ → data hold time
tRHDX
AD7 to AD0, RD Load
0
—
ns
1/4 tinst* – 40 ns
—
ns
1/4 tinst* – 40 ns
—
ns
1/4 tinst* – 60 ns
—
ns
0
—
ns
RD ↑ → ALE ↑ time
tRHLH
RD ↑ → address invalid time tRHAX
condition:
50 pF
RD, ALE
RD, A15 to A08
RD ↓ → CLK ↑ time
tRLCH
CLK ↓ → RD ↑ time
tCLRH
RD ↓ → BUFC ↓ time
tRLBL
RD, BUFC
–5
—
ns
BUFC ↑ → valid
address time
tBHAV
A15 to A08,
AD7 to AD0,
BUFC
5
—
ns
RD, CLK
* : For information on tinst, see “(4) Instruction Cycle.”
2.4 V
CLK
0.8 V
tRHLH
ALE
0.8 V
AD
2.4 V
0.7 VCC
0.7 VCC
2.4 V
0.8 V
0.3 VCC
0.3 VCC
0.8 V
tRHDX
tAVDV
A
2.4 V
2.4 V
tCLRH
0.8 V
tRLCH
0.8 V
tAVRL
tRLDV
2.4 V
0.8 V
tRHAX
tRLRH
RD
2.4 V
0.8 V
tRLBL
tBHAV
2.4 V
BUFC
0.8 V
30
Remarks
MB89860/850 Series
(8) Bus Write Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Valid address → ALE ↓ time tAVLL
Pin
Value (10 MHz)
Condition
Unit
Min.
Max.
1/4 tinst*1 – 64 ns
—
ns
5
—
ns
1/4 tinst*1 – 60 ns
—
ns
ALE ↓ time → address
invalid time
tLLAX
AD7 to AD0,
ALE, A15 to
A08
Valid address → WR ↓ time
tAVWL
WR, ALE
WR pulse width
tWLWH
WR
1/2 t
– 20 ns
—
ns
AD7 to AD0, WR
1/2 tinst*1 – 60 ns
—
ns
1/4 tinst*1 – 40 ns
—
ns
Write data → WR ↑ time tDVWH
WR ↑ → data hold time tWHDX
Load
WR, A15 to A08
condition:
AD7 to AD0, WR 50 pF
WR ↑ → ALE ↑ time
tWHLH
WR, ALE
WR ↓ → CLK ↑ time
tWLCH
CLK ↓ → WR ↑ time
tCLWH
ALE pulse width
tLHLL
ALE ↓ → CLK ↑ time
tLLCH
WR ↑ → address invalid time
tWHAX
WR, CLK
inst*1
1/4 t
inst*1
– 40 ns
—
ns
1/4 t
inst*1
– 40 ns
—
ns
1/4 tinst*1 – 60 ns
—
ns
0
—
ns
ALE
tXCYL – 35 ns
*2
—
ns
ALE, CLK
tXCYL – 35 ns*2
—
ns
Remarks
*1: For information on tinst, see “(4) Instruction Cycle.”
*2: These characteristics are also applicable to the bus read timing.
2.4 V
CLK
0.8 V
tLHLL
ALE
tLLCH
t WHLH
2.4 V
0.8 V
tAVLL
AD
0.8 V
tLLAX
2.4 V 2.4 V
2.4 V
2.4 V
0.8 V 0.8 V
0.8 V
0.8 V
tDVWH
A
2.4 V
0.8 V
tWHDX
2.4 V
tCLWH
0.8 V
tWLCH
tAVWL
tWHAX
tWLWH
WR
2.4 V
0.8 V
31
MB89860/850 Series
(9) Ready Input Timing
(VCC = +5.0 V±10%, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
RDY valid → CLK ↑ time
tYVCH
CLK ↑ → RDY invalid time
tCHYX
Pin
Condition
RDY,
CLK
Load condition:
50 pF
Unit
Remarks
—
ns
*
—
ns
*
Min.
Max.
60
0
* : These characteristics are also applicable to the read cycle.
2.4 V
CLK
2.4 V
ALE
AD
Address
Data
A
WR
t YVCH t CHYX
0.7 VCC
0.7 VCC
RDY
0.3 VCC
0.3 VCC
t YVCH t CHYX
Note: The bus cycle is also extended in the read cycle in the same manner.
32
MB89860/850 Series
(10) UART and Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK1,SCK2
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
SCK1, SO1
SCK2, SO2
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
SI1, SCK1
SI2, SCK2
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time tSHIX
SCK1, SI1
SCK2, SI2
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
Condition
Internal shift
clock mode
Load
condition:
50 pF
SCK1, SCK2
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
SCK1, SO1
SCK2, SO2
Valid SI1 → SCK1 ↑
Valid SI2 → SCK2 ↑
tIVSH
SI1, SCK1
SI2, SCK2
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time tSHIX
SCK1, SI1
SCK2, SI2
External shift
clock mode
Load
condition:
50 pF
Value
Unit
Min.
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
33
MB89860/850 Series
Internal Shift Clock Mode
tSCYC
SCK1
SCK2
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SO1
SO2
0.8 V
tIVSH
SI1
SI2
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Shift Clock Mode
t SLSH
t SHSL
SCK1
SCK2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
t SLOV
SO1
SO2
2.4 V
0.8 V
tIVSH
SI1
SI2
34
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB89860/850 Series
(11) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Parameter
Symbol
Peripheral input “H”
pulse width 1
tILIH1
Peripheral input “L”
pulse width 1
tIHIL1
Pin
Condition
TRGI, DTTI,
ADST,
INT0 to INT3
Unit
Load
condition:
50 pF
Min.
Max.
2 tinst*
—
µs
2 tinst*
—
µs
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
TRGI
DTTI
ADST
INT0 to INT3
tIHIL1
tILIH1
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Condition
Typ.
Max.
—
—
10
bit
—
—
±2.0
LSB
—
—
±1.5
LSB
—
—
±3.0
LSB
AVSS –
1.5
AVSS +
0.5
AVSS +
2.5
LSB
AVR –
3.5
AVR –
1.5
AVR +
0.5
LSB
—
—
4
LSB
—
—
33 tinst*
—
µs
—
—
—
10
µA
—
0
—
AVR
V
—
0
—
AVCC
V
AVR = 5.0
V
—
200
—
µA
—
Differential linearity error
Total error
AVCC = VCC
Zero transition voltage
VOT
AN0 to
AN7
Full-scale transition voltage VFST
Interchannel disparity
—
A/D mode conversion time
Analog port input current
IAIN
Analog input voltage
AN0 to
AN7
—
Reference voltage
Reference voltage supply
current
—
IR
AVR
Unit Remarks
Min.
Resolution
Linearity error
Value
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
35
MB89860/850 Series
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
• Linearity error
The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with
the full-scale transition point (“11 1111 1111” ↔´“11 1111 1110”) from actual conversion characteristics
• Differential linearity error
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error
The total error indicates the difference between the actual value and theoretical value. This error is caused by
the zero transition error, full-scale transition error, linearity error, quantization, and noise.
Theoretical I/O value
Total error
VFST
3FF
3FF
3FE
3FE
1.5 LSB
3FD
Digital output
Digital output
3FD
004
003
Actual conversion
value
(1 LSB × N + 0.5 LSB)
004
VNT
003
VOT
002
Actual conversion
value
002
1 LSB
Theoretical value
001
001
0.5 LSB
AVSS
AVR
Analog input
1 LSB =
VFST – VOT
1022
AVSS
AVR
Analog input
(V)
Total error of digital output “N” =
VNT – (1 LSB × N + 0.5 LSB)
1 LSB
(Continued)
36
MB89860/850 Series
(Continued)
Zero transition error
Full-scale transition error
004
Theoretical value
Actual conversion
value
3FF
Actual conversion
value
Digital output
Digital output
003
002
3FE
VFST
(Measured value)
3FD
Actual conversion
value
Actual conversion
value
001
3FC
VOT (Measured value)
AVSS
AVR
Analog input
Analog input
Linearity error
Differential linearity error
3FF
Theoretical value
Actual conversion
value
3FE
N+1
(1 LSB × N + VOT)
Actual conversion
value
VNT
VFST
(Measured
value)
Digital output
Digital output
3FD
004
003
V(N + 1)T
N
N–1
Actual conversion
value
VNT
Actual conversion
value
002
Theoretical value
N–2
001
VOT (Measured value)
AVSS
AVR
Analog input
Linearity error of digital output “N” =
Analog input
VNT – (1 LSB × N + VOT)
1 LSB
Differential linearity error of digital output “N” =
V(N + 1)T – VNT
1 LSB
–1
37
MB89860/850 Series
(2) Precautions
• Input impedance of the analog input pins
The A/D converter used for the MB89860/850 series contains a sample hold circuit as illustrated below to
fetch analog input voltage into the sample hold capacitor for fifteen instruction cycles after activation A/D
conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance connot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Analog Input Equivalent Circuit
Sample hold circuit
.
C =. 64 pF
Anlog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R =. 3 kΩ
Close for 15 instruction cycles
after activating A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
38
MB89860/850 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, P50 to P57, P70 to
P76, and P80 to P87)
(2) “L” Level Output Voltage (P40 to P47)
VOL vs. IOL
VOL vs. IOL
VOL (V)
VOL (mV)
600
TA = +25˚C
TA = +25˚C
0.5
500
VCC = 3.0 V
VCC = 3.0 V
0.4
400
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.3
VCC = 4.0 V
300
VCC = 5.0 V
VCC = 6.0 V
200
0.2
100
0.1
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Output Voltage (P00 to P07, P10 to
P17, P20 to P27, P30 to P37, and P40 to P47)
0
0 1 2 3 4 5 6 7 8 9 1011121314151617181920
IOL (mA)
(4) Pull-up Resistance
RPULL vs. VCC
VCC − VOH vs. IOH
RPULL (kΩ)
1000
VCC − VOH (V)
1.0
TA = +25˚C
TA = +25˚C
0.9
0.8
0.7
VCC = 3.0 V
0.6
0.5
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
100
0.3
0.2
0.1
0.0
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
IOH (mA)
10 to 1
1
2
3
4
5
6
VCC (V)
39
MB89860/850 Series
(5) “H” Level Input Voltage/“L” Level Input
Voltage (CMOS Input)
(6) “H” Level Input Voltage/“L” level Input
Voltage (Hysteresis Input)
VIN vs. VCC
VIN vs. VCC
VIN (V)
5.0
VIN (V)
5.0
TA = +25˚C
4.5
TA = +25˚C
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
VIHS
VILS
0
1
2
3
4
5
6
7
1
2
3
4
5
6
VCC (V)
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(7) Operating Supply Current vs. Frequency
(8) Operating Supply Current vs. VCC
ICC vs. FC
ICC vs. VCC
ICC (mA)
25
ICC (mA)
25
TA = +25˚C
TA = +25˚C
20
VCC = 5.0 V
15
10
VCC = 3.5 V
5
VCC = 3.0 V
0
FC = 8 MHz
15
FC = 6 MHz
FC = 4 MHz
10
5
0
2
40
FC = 10 MHz
20
4
6
8
10
FC (MHz)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
MB89860/850 Series
(9) Sleep Power Supply Current vs. Frequency
(10) Sleep Power Supply Current vs. VCC
ICCS vs. VCC
ICCS vs. FC
ICCS (mA)
10
ICCS (mA)
10
TA = +25˚C
TA = +25˚C
8
8
FC = 10 MHz
6
VCC = 5.0 V
4
FC = 8 MHz
6
FC = 6 MHz
4
FC = 4 MHz
VCC = 3.5 V
2
VCC = 3.0 V
0
2
0
2
4
6
8
10
FC (MHz)
3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
41
MB89860/850 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
42
MB89860/850 Series
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
Number of instructions
#:
Number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
43
MB89860/850 Series
Table 2
Mnemonic
Transfer Instructions (48 instructions)
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
44
MB89860/850 Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 toDF
D3
D2
D0
01
11
63
73
53
12
13
03
C←A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
45
MB89860/850 Series
(Continued)
Mnemonic
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
~
#
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) +off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
Table 5 Other Instructions (9 instructions)
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
46
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Operation
L
D
E
F
A
XCH
XOR
AND
OR
A, T
A
A
A
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir dir,#d8 dir,#d8
dir: 5 dir: 5,rel
A,dir
dir,A SP,#d16
A,SP
SUBC
5
A
MOV
CMP
ADDC SUBC
A,#d8
A,#d8
A,#d8
A,#d8
ADDC
MOV
MOV
CLRB
BBC
INCW
DECW MOVW MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNZ
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4 R4,#d8 R4,#d8
dir: 4 dir: 4,rel
R4
R4
#4
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BZ
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5 R5,#d8 R5,#d8
dir: 5 dir: 5,rel
R5
R5
#5
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BGE
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6 R6,#d8 R6,#d8
dir: 6 dir: 6,rel
R6
R6
#6
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BLT
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7 R7,#d8 R7,#d8
dir: 7 dir: 7,rel
R7
R7
#7
rel
D
E
F
rel
rel
rel
rel
CLRB
BBC
MOVW MOVW MOVW XCHW
dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16
A,EP
C
MOVW XCHW
IX,#d16
A,IX
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BN
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3 R3,#d8 R3,#d8
dir: 3 dir: 3,rel
R3
R3
#3
MOVW
MOVW
A,@IX +d @IX +d,A
B
CLRB
BBC
dir: 6 dir: 6,rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BP
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2 R2,#d8 R2,#d8
dir: 2 dir: 2,rel
R2
R2
#2
CMP
@EP,#d8
@IX +d,#d8
A
CMP
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1 R1,#d8 R1,#d8
dir: 1 dir: 1,rel
R1
R1
#1
MOV
@EP,#d8
@IX +d,#d8
9
MOV
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0 R0,#d8 R0,#d8
dir: 0 dir: 0,rel
R0
R0
#0
rel
OR
A,@IX +d
8
XOR
AND
A,@IX +d A,@IX +d
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP
MOV @IX
+d,A
7
SUBC
A,@IX +d
CLRB
BBC
MOVW MOVW MOVW XCHW
dir: 4 dir: 4,rel
A,ext
ext,A A,#d16
A,PC
MOV
A,@IX +d
ADDC
A,@IX +d
DAS
6
CMP
A,@IX +d
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
MOVW MOVW CLRB
BBC
INCW
DECW MOVW MOVW
CMPW ADDCW SUBCW XCHW XORW ANDW ORW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
A
CMP
A
4
A
A
CLRB
BBC
INCW
DECW MOVW MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
RORC
CLRB
BBC
INCW
DECW JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
C
3
SETC
PUSHW POPW MOV
MOVW CLRC
JMP
CALL
IX
IX
ext,A
PS,A
addr16 addr16
RETI
B
ROLC
DIVU
RET
A
2
A
7
MULU
A
6
SETI
5
PUSHW POPW MOV
MOVW CLRI
A
A
A,ext
A,PS
4
9
3
8
2
1
SWAP
1
NOP
0
0
H
MB89860/850 Series
■ INSTRUCTION MAP
47
MB89860/850 Series
■ MASK OPTIONS (MB89855/857/865/867)
Option type
Option selection
Power-on reset
0: Without power-on reset
1: With power-on reset
Initial value of oscillation
stabilization delay time
0: 218/FC (s) (Crystal oscillator)
1: 214/FC (s) (Ceramic oscillator)
Reset pin output
0: Without reset output
1: With reset output
Pull-up resistor at port pin
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
P70 to P76, P80 to P87
1: Without pull-up resistor
0: With pull-up resistor
Remarks
—
Selects the initial value of the OSCS bit
in the STBC register during power-on
reset.
—
• Can be set per pin.
• P70 to P76, and P80 to P87 are used
in the MB89860 series only.
• P00 to P07, P10 to P17, and P20 to
P27 with a pull-up resistor can be set
only for single-chip mode.
■ STANDARD OPTION LIST
Part number
Parameter
MB89P857/W857/
P867/W867/T855
Power-on reset
Available
Initial value of oscillation
stabilization delay time
218/FC (s)
Output at reset pin
Available
Pull-up resistor at port pin
Not available
■ ORDERING INFORMATION
Part number
MB89865PF
MB89867PF
MB89P867PF
Remarks
80-pin Plastic QFP
(FPT-80P-M06)
MB89855P-SH
MB89T855P-SH
MB89857P-SH
MB89P857P-SH
64-pin Plastic SH-DIP
(DIP-64P-M01)
MB89W867CF
80-pin Ceramic QFP
(FPT-80C-A02)
ES level only
64-pin Ceramic SH-DIP
(DIP-64C-A06)
ES level only
MB89W857C-SH
48
Package
MB89860/850 Series
■ PACKAGE DIMENSIONS
80-pin Plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
64
20.00±0.20(.787±.008)
3.35(.132)MAX
0.05(.002)MIN
(STAND OFF)
41
65
40
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
80
25
"A"
LEAD No.
1
24
0.35±0.10
(.014±.004)
0.80(.0315)TYP
0.16(.006)
0.15±0.05(.006±.002)
M
Details of "A" part
Details of "B" part
0.25(.010)
"B"
0.10(.004)
0.30(.012)
0.18(.007)MAX
18.40(.724)REF
0 10°
0.80±0.20
(.031±.008)
0.58(.023)MAX
22.30±0.40(.878±.016)
1994 FUJITSU LIMITED F80010S-3C-2
Dimensions in mm (inches)
64-pin Plastic SH-DIP
(DIP-64P-M01)
+0.22
58.00 –0.55
+.008
2.283 –.022
INDEX-1
17.00±0.25
(.669±.010)
INDEX-2
5.65(.222)MAX
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.50
1.00 –0
+.020
.039 –0
0.45±0.10
(.018±.004)
0.51(.020)MIN
15°MAX
19.05(.750)
TYP
1.778±0.18
(.070±.007)
1.778(.070)
MAX
C
1994 FUJITSU LIMITED D64001S-3C-4
55.118(2.170)REF
Dimensions in mm (inches)
49
MB89860/850 Series
80-pin Ceramic QFP
(FPT-80P-A02)
0.51(.020) TYP
17.91(.705)
TYP
16.00(.630)
14.00±0.25
TYP
(.551±.010)
12.00(.472)
REF
8.50(.335)TYP
16.31(.642)
TYP
INDEX AREA
+0.08
0.80±0.10
0.35 –0.07
(.0315±.0040)
(.014±.003)
18.40(.725) REF
0.80±0.10
(.0315±.0040)
20.00±0.25
(.787±.010)
23.90(.941) TYP
0.15±0.05
(.006±.002)
1.60(.063) TYP
4.45(.175)MAX
22.00(.866) TYP
22.30(.878) TYP
C
0.80(.0315) TYP
1994 FUJITSU LIMITED F80014SC-1-2
Dimensions in mm (inches)
64-pin Ceramic SH-DIP
(DIP-64C-A06)
56.90±0.56
(2.240±.022)
8.89(.350) DIA
TYP
R1.27(.050)
REF
18.75±0.25
(.738±.010)
INDEX AREA
1.27±0.25
(.050±.010)
5.84(.230)MAX
0.25±0.05
(.010±.004)
3.40±0.36
(.134±.014)
1.45(.057)
MAX
C
50
1994 FUJITSU LIMITED D64006SC-1-2
1.778±0.180
(.070±.007)
0.90±0.10
(.0355±.0040)
+0.13
0.46 –0.08
+.005
.018 –.003
19.05±0.25
(.750±.010)
0°~9°
55.118(2.170)REF
Dimensions in mm (inches)
MB89860/850 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 1015, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06-04 to #06-07
Singapore 189554
Tel: 336-1600
Fax: 336-1609
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully
checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey
any license under the copyrights, patent rights or trademarks
claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications
without notice.
No part of this publication may be copied or reproduced in any
form or by any means, or transferred to any third party without
prior written consent of Fujitsu.
The information contained in this document are not intended for
use with equipments which require extremely high reliability
such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9606
 FUJITSU LIMITED Printed in Japan
51