FUJITSU MB89165A-PF

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12405-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89160/160A Series
MB89161/163/165/P165/PV160/W165
MB89161A/163A/165A
■ DESCRIPTION
The MB89160 series is a line of the general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers contain a variety of peripheral functions such as an LCD controller/driver,
an A/D converter, timers, a serial interface, PWM timers, and external interrupts.
■ FEATURES
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F2MC-8L family CPU core
Dual-clock control system
Maximum memory size: 16-Kbyte ROM, 512-byte RAM (max.)
Minimum execution time: 0.95 µs/4.2 MHz
I/O ports: max. 54 channels
21-bit time-base counter
8/16-bit timer/counter: 2 or 1 channels
8-bit serial I/O: 1 channel
External interrupts (wake-up function): Four channels with edge selection plus eight level-interrupt channels
8-bit A/D converter: 8 channels
8-bit PWM timers: 2 channels
Watch prescaler (15 bits)
LCD controller/driver: 24 segments × 4 commons (max. 96 pixels)
LCD driving reference voltage generator and booster (option)
Remote control transmission output
Buzzer output
Power-on reset function (option)
Low-power consumption modes (stop, sleep, and watch mode)
CMOS technology
MB89160/160A Series
■ PACKAGE
80-pin Plastic QFP
80-pin Plastic SQFP
(FTP-80P-M06)
(FTP-80P-M05)
2
80-pin Plastic QFP
(FTP-80P-M11)
80-pin Ceramic QFP
80-pin Ceramic MQFP
(FPT-80C-A02)
(MQP-80C-P01)
MB89160/160A Series
■ PRODUCT LINEUP
Part number
Parameter
Classification
ROM size
RAM size
CPU functions
Ports
MB89161/
MB89161A*1
MB89163/
MB89163A*1
MB89165/
MB89165A*1
Mass production products
(mask ROM products)
4 K × 8 bits
(internal
mask ROM)
128 × 8 bits
LCD controller/
driver
A/D converter
EPROM
product
programmer)
256 × 8 bits
I/O port (N-ch open-drain):
MB89PV160
Piggyback/
evaluation
product (for
development)
32 K × 8 bits
(external
ROM)
512 × 8 bits
Number of instructions:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
I/O ports (CMOS):
Output ports (CMOS):
Total:
Serial I/O
One-time
PROM
product
MB89W165
8 K × 8 bits
16 K × 8 bits
16 K × 8 bits
(internal PROM, programming
(internal mask (internal
with general-purpose EPROM
ROM)
mask ROM)
Output ports (N-ch open-drain):
Timer/counter
MB89P165
136
8 bits
1 to 3 bytes
1, 8,16 bits
0.95 µs/4.2 MHz
9 µs/4.2 MHz
8 (6 ports also serve as peripherals, 3 ports
are a heavy-current drive type.)
28 (16 ports also serve as segment pins, 2 ports
serve as booster capacitor connection pins,
2 ports serve as common pins.)*3
(8 ports also serve as an A/D input)
16 (12 ports also serve as an external interrupt)
2 (Also serve as peripherals)
54 (max.)
8-bit timer operation (toggled output capable, operating clock cycle 1.9 µs to 486 µs)
16-bit timer operation (toggled output capable, operating clock cycle 1.9 µs to 486 µs)
8 bits
LSB first/MSB first selectability
One clock selectable from four operation clocks
(one external shift clock, three internal shift clocks: 1.9 µs, 7.6 µs, 30.4 µs)
Common output:
Segment output:
Bias power supply pins:
LCD display RAM size:
Booster for LCD driving:
Dividing resistor for LCD driving:
4 (max.)
24 (max.) *3
4
24 × 4 bits
Built-in (product with a booster)*3
Built-in (an external resistor
selectability)
Without a
booster for
LCD driving
8-bit resolution × 8 channels
A/D conversion mode (conversion time 43 µs/4.2 MHz (44 instruction cycles))
Sense mode (conversion time 11.9 µs/4.2 MHz)
Continuous activation by an internal timer capable
Reference voltage input
(Continued)
3
MB89160/160A Series
(Continued)
Part number
Parameter
MB89163/
MB89163A*1
MB89161/
MB89161A*1
MB89165/
MB89165A*1
MB89P165
MB89W165
MB89PV160
8 bits × 2 channels
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.95 µs to
124 ms)
8-bit resolution PWM operation (conversion cycle: 243 µs to 32 s)
PWM timer 1,
PWM timer 2
External interrupt 1
(wake-up function)
4 independent channels (edge selectability)
Rising edge/falling edge selectability
Used also for wake-up from stop/sleep mode.
(Edge detection is also permitted in stop mode.)
External interrupt 2
“L” level interrupts × 8 channels
Buzzer output
1 (7 frequencies are selectable by the software.)
Remote control
transmission
output
1 (Pulse width and cycle are software selectable.)
Standby modes
Subclock mode, sleep mode, stop mode, and watch mode
Process
CMOS
2.2 V to 6.0 V (single clock)/
2.2 V to 4.0 V (dual clock)
Operating voltage*2
EPROM for use
2.7 V to 6.0 V
MBM27C256A20TV
—
*1: Products with an internal booster.
*2: Varies with conditions such as the operating frequency. (The operating voltage of the A/D converter is assured
separately. See section “■ Electrical Characteristics.”)
*3: See section “■ Mask Options.”
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB89161
MB89161A
MB89163
MB89163A
MB89165
MB89165A
MB89PW165
MB89W165
MB89PV160
FPT-80P-M05
×
×
FPT-80P-M06
×
×
FPT-80P-M11
×
×
MQP-80C-P01
×
×
×
×
FPT-80C-A02
×
×
×
×
: Available
× : Not available
Note: For more information about each package, see section “■ Package Dimensions.”
4
×
×
MB89160/160A Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• On the MB89161/A and MB89163/A, the upper half of each register bank cannot be used.
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV160, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in the sleep/stop modes is the same. (For more information, see section
“■ Electrical Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-up resistor cannot be set for P20 to P27 on the MB89P165.
• A pull-up resistor is not selectable for P40 to P47 and P60 to P67 if they are used as LCD pins.
• Options are fixed on the MB89PV160.
5
MB89160/160A Series
■ PIN ASSIGNMENT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P45/SEG21*7
P44/SEG20*7
P43/SEG19*6
P42/SEG18*6
P41/SEG17*6
P40/SEG16*6
P67/SEG15*5
P66/SEG14*5
P65/SEG13*5
P64/SEG12*5
P63/SEG11*4
P62/SEG10*4
P61/SEG9*4
P60/SEG8*4
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
COM0
V3
VCC
V2
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
X0A
P27/PWM2*3
P26*3
P25/SCK
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
P12/INT12
P13/INT13
P14
P15
P16
P17
P20/EC
P21*3
P22/TO
P23/SI
P24/SO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P46/SEG22*7
P47/SEG23*7
AVSS
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
VSS
P57/AN7
X1
X0
MOD1
MOD0
RST
P00/INT20
(FPT-80P-M11)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section ■ Mask Options."
6
MB89160/160A Series
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P43/SEG19*6
P42/SEG18*6
P41/SEG17*6
P40/SEG16*6
P67/SEG15*5
P66/SEG14*5
P65/SEG13*5
P64/SEG12*5
P63/SEG11*4
P62/SEG10*4
P61/SEG9*4
P60/SEG8*4
SEG7
SEG6
SEG5
SEG4
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG3
SEG2
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
COM0
V3
VCC
V2
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
X0A
P27/PWM2*3
P26*3
P25/SCK
P24/SO
P23/SI
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
P12/INT12
P13/INT13
P14
P15
P16
P17
P20/EC
P21*3
P22/TO
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/SEG20*7
P45/SEG21*7
P46/SEG22*7
P47/SEG23*7
AVSS
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
VSS
P57/AN7
X1
X0
MOD1
MOD0
RST
P00/INT20
P01/INT21
P02/INT22
(FPT-80P-M06)
(FPT-80C-A02)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section “■ Mask Options.”
7
MB89160/160A Series
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P45/SEG21*7
P44/SEG20*7
P43/SEG19*6
P42/SEG18*6
P41/SEG17*6
P40/SEG16*6
P67/SEG15*5
P66/SEG14*5
P65/SEG13*5
P64/SEG12*5
P63/SEG11*4
P62/SEG10*4
P61/SEG9*4
P60/SEG8*4
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
COM0
V3
VCC
V2
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
X0A
P27/PWM2*3
P26*3
P25/SCK
P01/INT21
P02/INT22
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
P12/INT12
P13/INT13
P14
P15
P16
P17
P20/EC
P21*3
P22/TO
P23/SI
P24/SO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P46/SEG22*7
P47/SEG23*7
AVSS
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
VSS
P57/AN7
X1
X0
MOD1
MOD0
RST
P00/INT20
(FPT-80P-M05)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section “■ Mask Options.”
8
MB89160/160A Series
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P43/SEG19*6
P42/SEG18*6
P41/SEG17*6
P40/SEG16*6
P67/SEG15*5
P66/SEG14*5
P65/SEG13*5
P64/SEG12*5
P63/SEG11*4
P62/SEG10*4
P61/SEG9*4
P60/SEG8*4
SEG7
SEG6
SEG5
SEG4
(Top view)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
100
99
98
97
96
95
94
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
93
92
91
90
89
88
87
86
85
110
111
112
81
82
83
84
101
102
103
104
105
106
107
108
109
SEG3
SEG2
SEG1
SEG0
P71/COM3*8
P70/COM2*8
COM1
COM0
V3
VCC
V2
V1
V0
P33*2/C0*1
P32*2/C1*1
P31/PWM1
P30/RCO/BUZ
X1A
X0A
P27/PWM2*3
P26*3
P25/SCK
P24/SO
P23/SI
P03/INT23
P04/INT24
P05/INT25
P06/INT26
P07/INT27
P10/INT10
P11/INT11
P12/INT12
P13/INT13
P14
P15
P16
P17
P20/EC
P21*3
P22/TO
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/SEG20*7
P45/SEG21*7
P46/SEG22*7
P47/SEG23*7
AVSS
AVR
AVCC
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
VSS
P57/AN7
X1
X0
MOD1
MOD0
RST
P00/INT20
P01/INT21
P02/INT22
(MQP-80C-P01)
*1: For products with a booster circuit
*2: For products without a booster circuit
*3: N-ch open-drain heavy-current drive type
*4 to *7: Selected using the mask option (in units of 4 pins)
*8: Selected using the mask option (in units of 2 pins)
Note: For more information on mask option combinations of *4 to *8, see section “■ Mask Options.”
• Pin assignment on package top (MB89PV160 only)
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
Pin no.
Pin name
81
N.C.
89
A2
97
N.C.
105
OE
82
VPP
90
A1
98
O4
106
N.C.
83
A12
91
A0
99
O5
107
A11
84
A7
92
N.C.
100
O6
108
A9
85
A6
93
O1
101
O7
109
A8
86
A5
94
O2
102
O8
110
A13
87
A4
95
O3
103
CE
111
A14
88
A3
96
VSS
104
A10
112
VCC
N.C.: Internally connected. Do not use.
9
MB89160/160A Series
■ PIN DESCRIPTION
Pin no.
*1
MQFP*3
QFP*4
16
18
X0
15
17
X1
Circuit
type
Function
A
Main clock crystal oscillator pins
CR oscillation selectability (mask products only)
C
Operating mode selection pins
Connect directly to VSS.
18
20
MOD0
17
19
MOD1
19
21
RST
D
Reset I/O pin
This pin is an N-ch open-drain output type with a
pull-up resistor, and a hysteresis input type. “L” is
output from this pin by an internal reset source. The
internal circuit is initialized by the input of “L”.
20 to 27
22 to 29
P00/INT20 to
P07/INT27
E
General-purpose I/O ports
Also serve as an external interrupt 2 input (wake-up
function).
External interrupt 2 input is hysteresis input.
28 to 31
30 to 33
P10/INT10 to
P13/INT13
E
General-purpose I/O ports
Also serve as an external interrupt 1 input. External
interrupt 1 input is hysteresis input.
32 to 35
34 to 37
P14 to P17
F
General-purpose I/O ports
36
38
P20/EC
H
N-ch open-drain general-purpose I/O port
Also serves as the external clock input for the timer.
The peripheral is a hysteresis input type.
37
39
P21
I
N-ch open-drain general-purpose I/O port
38
40
P22/TO
I
N-ch open-drain general-purpose I/O port
Also serves as a timer output.
39
41
P23/SI
H
N-ch open-drain general-purpose I/O port
Also serves as the data input for the serial I/O. The
peripheral is a hysteresis input type.
40
42
P24/SO
I
N-ch open-drain general-purpose I/O port
Also serves as the data output for the serial I/O.
41
43
P25/SCK
H
N-ch open-drain general-purpose I/O port
Also serves as the clock I/O for the serial I/O. The
peripheral is a hysteresis input type.
42
44
P26
I
N-ch open-drain general-purpose I/O port
43
45
P27/PWM2
I
N-ch open-drain general-purpose I/O port
Also serves as the square wave or PWM wave
output for the 8-bit PWM timer 2.
49
51
P33
J
Functions as an N-ch open-drain general-purpose
output port only in the products without a booster.
C0
—
Functions as a capacitor connection pin in the
products with a booster.
*1:
*2:
*3:
*4:
10
Pin name
SQFP
QFP*2
FPT-80P-M05
FPT-80P-M11
MQP-80C-P01
FPT-80P-M06
(Continued)
MB89160/160A Series
(Continued)
Pin no.
*1
SQFP
QFP*2
MQFP*3
QFP*4
48
50
Circuit
type
Function
P32
J
Functions as an N-ch open-drain general-purpose
output port only in the products without a booster.
C1
—
Functions as a capacitor connection pin in the
products with a booster.
Pin name
47
49
P31/PWM1
G
General-purpose output-only port
Also serves as the square wave or PWM wave
output for the 8-bit PWM timer 1.
46
48
P30/RCO/BUZ
G
General-purpose output-only port
Also serves as a buzzer output and a remote
control transmission frequency output.
14,
12 to 6
16,
14 to 8
P57/AN7 to
P50/AN0
L
N-ch open-drain general-purpose output ports
Also serve as an analog input.
2, 1,
80 to 75
4 to 1
80 to 77
P47/SEG23 to
P40/SEG16
J/K
74 to 67
76 to 69
P67/SEG15 to
P60/SEG8
J/K
66 to 59
68 to 61
SEG7 to SEG0
K
58,
57
60,
59
P71/COM3,
P70/COM2
56,
55
58,
57
COM1,
COM0
K
LCD controller/driver common output-only pins
54,
52 to 50
56,
54 to 52
V3,
V2 to V0
—
LCD driving power supply pins
44
46
X0A
B
Subclock crystal oscillator pins (32.768 KHz)
45
47
X1A
53
55
VCC
—
Power supply pin
13
15
VSS
—
Power supply (GND) pin
5
7
AVSS
—
A/D converter power supply pin
Use this pin at the same voltage as VCC.
4
6
AVR
—
A/D converter reference voltage input pin
3
5
AVSS
—
A/D converter power supply pin
Use this pin at the same voltage as VSS.
*1:
*2:
*3:
*4:
J/K
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver segment
output. Switching between port and segment output
is done by the mask option.
LCD controller/driver segment output pins
N-ch open-drain general-purpose output ports
Also serve as an LCD controller/driver common
output. Switching between port and common output
is done by the mask option.
FPT-80P-M05
FPT-80P-M11
MQP-80C-P01
FPT-80P-M06
11
MB89160/160A Series
• External EPROM pins (MB89PV160 only)
Pin no.
12
Pin name
I/O
Function
82
VPP
O
“H” level output pin
83
84
85
86
87
88
89
90
91
A12
A7
A6
A5
A4
A3
A2
A1
A0
O
Address output pins
93
94
95
O1
O2
O3
I
Data input pins
96
VSS
O
Power supply (GND) pin
98
99
100
101
102
O4
O5
O6
O7
O8
I
Data input pins
103
CE
O
ROM chip enable pin
Outputs “H” during standby.
104
A10
O
Address output pin
105
OE
O
ROM output enable pin
Outputs “L” at all times.
107
108
109
A11
A9
A8
O
Address output pins
110
A13
O
111
A14
O
112
VCC
O
EPROM power supply pin
81
92
97
106
N.C.
—
Internally connected pins
Be sure to leave them open.
MB89160/160A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
Main clock
• At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
• CR oscillation is selectable (MB8916X/A only).
X1
X0
Standby control signal
B
Subclock
• At an oscillation feedback resistor of approximately
4.5 MΩ/5.0 V
X1A
X0A
Standby control signal
C
D
• At an output pull-up resistor of approximately
50 kΩ/5.0 V
• Hysteresis input
R
P-ch
N-ch
E
• CMOS I/O
• The peripheral is a hysteresis input type.
R
P-ch
P-ch
N-ch
Port
Peripheral
• Pull-up resistor optional
(Not available on the MB89PV160.)
(Continued)
13
MB89160/160A Series
(Continued)
Type
Circuit
Remarks
F
• CMOS I/O
R
P-ch
P-ch
N-ch
• Pull-up resistor optional
(Not available on the MB89PV160)
G
• CMOS output
• P-ch output is a heavy-current drive type.
P-ch
N-ch
Port
H
•
•
•
•
•
R
P-ch
N-ch
N-ch open-drain I/O
CMOS input
The peripheral is a hysteresis input type.
P21, P26, and P27 are a heavy-current drive type.
Pull-up resistor optional
(Not available on the MB89P165/A, MB89W165/A
and MB89PV160)
Port
Peripheral
I
• N-ch open-drain output
• CMOS input
R
P-ch
N-ch
Port
J
• Pull-up resistor optional
(Not available on the MB89P165/A, MB89W165/A
and MB89PV160)
• N-ch open-drain output
• Pull-up resistor optional
(Not available on the MB89P165/A, MB89W165/A
and MB89PV160)
• P32 and P33 are not provided with a pull-up resistor.
R
P-ch
N-ch
(Continued)
14
MB89160/160A Series
(Continued)
Type
Circuit
Remarks
K
• LCD controller/driver segment output
P-ch
N-ch
P-ch
N-ch
L
• N-ch open-drain output
• Analog input
R
P-ch
P-ch
N-ch
Analog input
• Pull-up resistor optional
(Not available on the MB89PV160)
15
MB89160/160A Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- to high-voltage pins or if higher than the voltage which shows on “ 1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC to VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pin
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is
therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations
(P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the
transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power
is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and
wake-up from stop mode.
16
MB89160/160A Series
■ PROGRAMMING TO THE EPROM ON THE MB89P165
The MB89P165 is an OTPROM version of the MB89160 series.
1. Features
• 32-Kbyte PROM on chip
• Options can be set using the EPROM programmer.
• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below.
Address
Single-chip
0000H
EPROM mode
(Corresponding addresses on the EPROM programmer)
I/O
0080H
RAM
0280H
Not available
8000H
0000H
Not available
Not available
3FF0H
Not available
Option area
3FF6H
Not available
C000H
Not available
4000H
EPROM
16 KB
PROM
16 KB
FFFFH
7FFFH
3. Programming to the EPROM
In EPROM mode, the MB89P165 functions equivalent to the MBM27C256A. This allows the PROM to be
programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by
using the dedicated socket adapter.
When the operating area for a single chip is 16 Kbyte (C000H to FFFFH) the PROM can be programmed as follows:
• Programming procedure
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program into the EPROM programmer at 4000H to 7FFFH.
(Note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM
mode.)
Load option data into address 3FF0H to 3FF5H of the EPROM programmer.
(For information about each corresponding option, see “8. Setting OTPROM Options.”)
(3) Program with the EPROM programmer.
17
MB89160/160A Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Adapter Socket
Package
Compatible adapter socket
FPT-80P-M05
ROM-80SQF-28DP-8L
FPT-80P-M06
ROM-80QF-28DP-8L3
FPT-80P-M11
ROM-80QF2-28DP-8L2
7. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an
ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This
dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms (Å)) with intensity
of 12000 µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all
filters should be removed from the UV light source prior to erasure.
It is important to note that the internal EPROM and similar devices, will erase with light sources having
wavelengths shorter than 4000Å. Although erasure time will be much longer than with UV source at 2537Å,
nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and
exposure to them should be prevented to realize maximum system reliability. If used in such an environment,
the package windows should be covered by an opaque label or substance.
18
MB89160/160A Series
8. Setting OTPROM Options
The programming procedure is the same as that for the PROM. Options can be set by programming value at
the addresses shown on the memory map. The relationship between bits and options is shown on the following
bit map:
• OTPROM option bit map
Bit 7
Bit 6
Vacancy
Vacancy
Readable
Readable
3FF0H
Bit 5
Bit 4
Oscillation stabilization time
WTM1
WTM0
Bit 3
Vacancy
Bit 2
Bit 1
Bit 0
Readable
Reset pin
output
1: Yes
0: No
Clock mode
selection
1: Dual clock
0: Single
clock
Power-on
reset
1: Yes
0: No
See section “■ Mask Option.”
3FF1H
P07
Pull-up
1: No
0: Yes
P06
Pull-up
1: No
0: Yes
P05
Pull-up
1: No
0: Yes
P04
Pull-up
1: No
0: Yes
P03
Pull-up
1: No
0: Yes
P02
Pull-up
1: No
0: Yes
P01
Pull-up
1: No
0: Yes
P00
Pull-up
1: No
0: Yes
3FF2H
P17
Pull-up
1: No
0: Yes
P16
Pull-up
1: No
0: Yes
P15
Pull-up
1: No
0: Yes
P14
Pull-up
1: No
0: Yes
P13
Pull-up
1: No
0: Yes
P12
Pull-up
1: No
0: Yes
P11
Pull-up
1: No
0: Yes
P10
Pull-up
1: No
0: Yes
3FF3H
P57
Pull-up
1: No
0: Yes
P56
Pull-up
1: No
0: Yes
P55
Pull-up
1: No
0: Yes
P54
Pull-up
1: No
0: Yes
P53
Pull-up
1: No
0: Yes
P52
Pull-up
1: No
0: Yes
P51
Pull-up
1: No
0: Yes
P50
Pull-up
1: No
0: Yes
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
Readable
Readable
Readable
Readable
Readable
Readable
Readable
Readable
3FF4H
3FF5H
Notes: • Set each bit to 1 to erase.
• Do not write 0 to the vacant bit.
The read value of the vacant bit is 1, unless 0 is written to it.
19
MB89160/160A Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato
Co., Ltd.) listed below.
Package
LCC-32 (Rectangle)
Adapter socket part number
ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address
Single chip
Corresponding addresses on the EPROM programmer
0000H
I/O
0080H
RAM
0280H
Not available
8000H
0000H
PROM
32 KB
FFFFH
EPROM
32 KB
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH.
(3) Program to 0000H to 7FFFH with the EPROM programmer.
20
MB89160/160A Series
■ BLOCK DIAGRAM
Main clock
oscillator
X0
X1
Time-base timer
Clock controller
Watch prescaler timer
Reset circuit
( W DT)
RST
8
8-bit timer/counter
P20/EC
P27/PWM2*4
8-bit PWM timer 2
8
External interrupt 2
(Wake-up)
Port 0
P00/INT20
to P07/INT27
P22/TO
Port 2
Subclock oscillator
(32.768 KHz)
X0A
X1A
Internal bus
8-bit timer/counter
P25/SCK
P24/SO
P23/SI
8-bit serial
CMOS I/O port
P21*4, P26*4
N-ch open-drain I/O port
4
4
External interrupt 1
(Wake-up)
4
N-ch open-drain output port
8
P14 to P17
CMOS I/O port
8
RAM
LCD
F 2 M C- 8L
CPU
2
controller/driver
P40/SEG16*3
to P43/SEG19
Port 6 and port 7 Port 4
P10/INT10
to P13/INT13
Port 1
4
4
P44/SEG20*3
to P47/SEG23
4
4
P60/SEG8*3
to P63/SEG11
P64/SEG12*3
to P67/SEG15
2
P70/COM2*3,
P71/COM3
8
SEG0 to SEG7
2
RO M
24 × 4 bits
VRAM
8
P50/AN0
to P57/AN7
Port 5
N-ch open-drain output port
8
Reference voltage
8-bit A/D converter
AVCC
AVR
AVSS
Other pins
MOD0, MOD1, VCC, VSS
generator and booster*1
COM0, COM1
4
V0 to V3
P33/C0*2
P32/C1*2
8-bit PWM timer 1
P31/PWM1
Remote control output
P30/RCO/BUZ
Buzzer output
N-ch open-drain I/O port
(P30 and P31 are a CMOS
output type.)
*1: Selected by mask option
*2: Used as ports without a reference voltage generator and booster
*3: Functions selected by mask option. (For information on selecting procedure, see section “■ Mask Options.”)
*4: Heavy-current drive type
21
MB89160/160A Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89160 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located at the lowest address. The data area is provided immediately above the
I/O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area. The
memory space of the MB89160 series is structured as illustrated below.
Memory Space
0000H
MB89PV160
0000H
I/O
0080H
MB89161/A
0000H
I/O
0080H
MB89163/A
0000H
I/O
0080H
MB89165/A
MB89P165
I/O
0080H
Not available
00C0H
RAM
256 B
0100H
0100H
0140H
RAM
128 B
RAM
256 B
0100H
RAM
512 B
0100H
Register
Register
Register
Register
0180H
0200H
0200H
0280H
0280H
Not available
Not available
Not available
8000H
Not available
C000H
E000H
External ROM
32 KB
FFFFH
22
ROM
16 KB
F000H
FFFFH
ROM
4 KB
ROM
8 KB
FFFFH
FFFFH
MB89160/160A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following dedicated registers are provided:
Program counter (PC):
A 16-bit register for indicating instruction storage positions
Accumulator (A):
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
When the instruction is an 18-bit data processing instruction, the lower byte is used.
Index register (IX):
A 16-bit register for index modification
Extra pointer (EP):
A 16-bit pointer for indicating a memory address
Stack pointer (SP):
A 16-bit register for indicating a stack area
Program status (PS):
A 16-bit register for storing a register pointer, a condition code
Initial value
16 bits
FFFDH
: Program counter
PC
A
: Accumulator
Undefined
T
: Temporary accumulator
Undefined
IX
: Index register
Undefined
EP
: Extra pointer
Undefined
SP
: Stack pointer
Undefined
PS
: Program status
I-flag = 0, IL1, 0 = 11
Other bits are undefined.
The PS can further be divide into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15
PS
14
13
12
11
10
9
8
Vacancy Vacancy Vacancy
RP
RP
7
6
H
I
5
4
IL1, 0
3
2
1
0
N
Z
V
C
CCR
23
MB89160/160A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP
Lower OP codes
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
b1
b0
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
0
0
0
1
1
0
2
1
1
3
1
High-low
High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set the shift-out value in the case of a shift instruction.
24
MB89160/160A Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit register for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers. Up to a total of 16 banks can be used on the MB89163 (RAM 256 × 8 bits), and a total of 32
banks can be used on the MB89165 (RAM 256 × 8 bits). The bank currently in use is indicated by the register
bank pointer (RP).
Note: The number of register banks that can be used varies with the RAM size.
Register Bank Configuraiton
This address = 0100H + 8 × (RP)
R0
R1
R2
R3
R4
R5
R6
R7
16 banks (MB89163)
32 banks (MB89165)
Memory area
25
MB89160/160A Series
■ I/O MAP
Address
Read/write
Register name
00H
(R/W)
PDR0
Port 0 data register
01H
(W)
DDR0
Port 0 data direction register
02H
(R/W)
PDR1
Port 1 data register
03H
(W)
DDR1
Port 1 data direction register
04H
(R/W)
PDR2
Port 2 data register
05H
(W)
DDR2
Port 2 data direction register
06H
Register description
Vacancy
07H
(R/W)
SYCC
System clock control register
08H
(R/W)
STBC
Standby control register
09H
(R/W)
WDTE
Watchdog timer control register
0AH
(R/W)
TBTC
Time-base timer control register
0BH
(R/W)
WPCR
Watch prescaler control register
0CH
(R/W)
PDR3
Port 3 data register
0DH
Vacancy
0EH
(R/W)
PDR4
Port 4 data register
0FH
(R/W)
PDR5
Port 5 data register
10H
(R/W)
BUZR
Buzzer register
11H
Vacancy
12H
(R/W)
PDR6
Port 6 data register
13H
(R/W)
PDR7
Port 7 data register
14H
(R/W)
RCR1
Remote control transmission register 1
15H
(R/W)
RCR2
Remote control transmission register 2
16H
Vacancy
17H
Vacancy
18H
(R/W)
T2CR
Timer 2 control register
19H
(R/W)
T1CR
Timer 1 control register
1AH
(R/W)
T2DR
Timer 2 data register
1BH
(R/W)
T1DR
Timer 1 data register
1CH
(R/W)
SMR
Serial mode register
1DH
(R/W)
SDR
Serial data register
1EH
(R/W)
CNTR1
PWM 1 control register
1FH
(W)
COMP1
PWM 1 compare register
(Continued)
26
MB89160/160A Series
(Continued)
Address
Read/write
Register name
20H
(R/W)
CNTR2
PWM 2 control register
21H
(W)
COMP2
PWM 2 compare register
22H to 2CH
Register description
Vacancy
2DH
(R/W)
ADC1
A/D converter control register 1
2EH
(R/W)
ADC2
A/D converter control register 2
2FH
(R/W)
ADCD
A/D converter data register
30H
(R/W)
EIE1
External interrupt 1 enable register 1
31H
(R/W)
EIF1
External interrupt 1 flag register 1
32H
(R/W)
EIE2
External interrupt 2 enable register 2
33H
(R/W)
EIF2
External interrupt 2 flag register 2
34H to 5FH
60H to 6BH
Vacancy
(R/W)
VRAM
6CH to 71H
72H
Display data RAM
Vacancy
(R/W)
LCDR
73H to 7BH
LCD controller/driver control register 1
Vacancy
7CH
(W)
ILR1
Interrupt level setting register 1
7DH
(W)
ILR2
Interrupt level setting register 2
7EH
(W)
ILR3
Interrupt level setting register 3
7FH
Access prohibited
ITR
Interrupt test register
Note: Do not use vacancies.
27
MB89160/160A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
LCD power supply voltage
Symbol
Value
Unit
Max.
VCC
VSS – 0.3
VSS + 7.0
V
AVCC
VSS – 0.3
VSS + 7.0
V
AVCC must not exceed VCC + 0.3 V.
AVR
VSS – 0.3
VSS + 7.0
V
AVR must not exceed AVCC + 0.3 V.
V0 to V3
VSS – 0.3
VSS + 7.0
V
V0 to V3 on the product without
booster must not exceed VCC.
VI1
VSS – 0.3
VCC + 0.3
V
VI1 must not exceed VSS + 7.0 V.
All pins except P20 to P27 without
a pull-up resistor
VI2
VSS – 0.3
VSS + 7.0
V
P20 to P27 without a pull-up
resistor
Input voltage
VO1
VSS – 0.3
VCC + 0.3
V
VO1 must not exceed VSS + 7.0 V.
All pins except P20 to P27, P32,
P33, P40 to P47, and P60 to P67
without a pull-up resistor
VO2
VSS – 0.3
VSS + 7.0
V
P20 to P27, P32, P33, P40 to P47,
and P60 to P67 without a pull-up
resistor
IOL1

10
mA
All pins except P21, P26, and P27
IOL2

20
mA
P21, P26, and P27
Output voltage
“L” level maximum output current
Remarks
Min.
IOLAV1

4
mA
All pins except P21, P26, P27, and
power supply pins
Average value (operating current ×
operating rate)
IOLAV2

8
mA
P21, P26, and P27
Average value (operating current ×
operating rate)
“L” level total maximum output current
ΣIOL

100
mA
Peak value
“L” level total average output current
ΣIOLAV

40
mA
Average value (operating current ×
operating rate)
IOH1

–5
mA
All pins except P30, P31, and
power supply pins
IOH2

–10
mA
P30 and P31
“L” level average output current
“H” level maximum output current
(Continued)
28
MB89160/160A Series
(Continued)
(AVSS = VSS = 0.0 V)
Value
Symbol
Parameter
Min.
Max.
Unit
Remarks
IOHAV1
—
–2
mA
All pins except P30, P31, and
power supply pins
Average value (operating current ×
operating rate)
IOHAV2
—
–4
mA
P30 and P31
Average value (operating current ×
operating rate)
ΣIOH
—
–50
mA
Peak value
“H” level total average output current ΣIOHAV
—
–10
mA
Average value (operating current ×
operating rate)
Power consumption
PD
—
300
mW
Operating temperature
TA
–40
+85
°C
Storage temperature
Tstg
–55
+150
°C
“H” level average output current
“H” level total maximum output current
Precautions: Parmanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this
data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Power supply voltage
Symbol
VCC
AVCC
AVR
Value
Unit
Remarks
Min.
Max.
2.2*1
6.0*1
V
Normal operation assurance range*1
2.2*1
4.0
V
Dual-clock mask ROM products
2.7
6.0
V
Normal operation assurance range for
MB89P165/A and MB89W165/A
1.5
6.0
V
Retains the RAM state in stop mode
2.0
AVCC
V
Normal operation assurance range
LCD power supply voltage
V0 to V3
VSS
VCC
V
V0 to V3 pins on the products without a
booster
LCD power supply range
(The optimum value dependent on the
LCD element in use.)
EPROM program power
supply voltage
VPP
—
VSS + 13.0
V
MOD1 pin of the MB89P165
Operating temperature
TA
–40
+85
°C
*1: The minimum operating power supply voltage varies with the execution time (instruction cycle time) setting for
the operating frequency.
A/D converter assurance accuracy varies with the operating power supply voltage.
*2: P32 and P33 are applicable only for procucts of the MB89160 series (without “A” suffix).
P40 to P47 and P60 to P67 are applicable when selected as ports.
29
MB89160/160A Series
6
Analog accurancy
assured in the AVCC
= VCC = 3.5 V to 6.0 V
range
Operating voltage (V)
5
Operation assurance range
4
3
2
1
1
2
3
4
(MHz)
1.0
(µs)
Main clock operating frequency
4.0
2.0
Minimum execution time (instruction cycle)
Note: The shaded area is assured only for the MB8916X/A.
Figure 1
30
Operating Voltage vs. Main Clock Operating Frequency
(Single-clock MB8916X/A and MB89P165/PV160)
MB89160/160A Series
Operating voltage (V)
6
5
4
Analog accurancy
assured in the
AVCC = VCC = 3.5 V
to 6.0 V range
Operation assurance range
3
2
1
1
2
Main clock operating frequency
4.0
2.0
Minimum execution time (instruction cycle)
Figure 2
3
4 (MHz)
1.0 (µs)
Operating Voltage vs. Main Clock Operating Frequency (Dual-clock MB8916X/A)
Figures 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
31
MB89160/160A Series
3. DC Characteristics
(1) Pin DC characteristics (VCC = +5.0 V)
Parameter
Min.
P00 to P07,
P10 to P17,
P20 to P27
0.7 VCC

VCC + 0.3
V
VIHS
RST,
MOD0, MOD1,
EC, SI, SCK,
INT10 to INT13,
INT20 to INT27
0.8 VCC

VCC + 0.3
V
VIL
P00 to P07,
P10 to P17,
P20 to P27
VSS − 0.3

0.3 VCC
V
VILS
RST,
MOD0, MOD1,
EC, SI, SCK,
INT10 to INT13,
INT20 to INT27
VSS − 0.3

0.2 VCC
V
VD1
P20 to P27,
P33, P32,
P40 to P47,
P60 to P67
VSS − 0.3

VSS + 6.0*2
V
VD2
P50 to P57
VSS − 0.3

VCC + 0.3
V
VOH1
P00 to P07,
P10 to P17
IOH = –2.0 mA
2.4


V
VOH2
P30, P31
IOH = –6.0 mA
4.0


V
VOL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P33,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P71
IOL = 1.8 mA


0.4
V
VOL2
P21, P26, P27
IOL = 8.0 mA


0.4
V
VOL3
RST
IOL = 4.0 mA


0.6
V
P00 to P07,
P10 to P17,
MOD0, MOD1,
P30, P31
0.45 V < VI < VCC


±5
µA
“L” level input
voltage
“H” level output
voltage
Condition
VIH
“H” level input
voltage
Open-drain
output pin
application
voltage
Pin
Symbol
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Typ.
Max.
“L” level output
voltage
Input leakage
current (Hi-z output ILI1
leakage current)

P20 to P27, P40 to
P47, and P60 to
P67 without pullup resistor only
Without pullup resistor
(Continued)
32
MB89160/160A Series
(Continued)
Parameter
Pin
Symbol
Condition
Min.
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Typ.
Max.
ILO1
P20 to P27,
P32, P33,
P40 to P47,
P60 to P67,
P70, P71
0.45 V < VI < 6.0 V
—
—
±1
µA
Without pullup resistor
ILO2
P50 to P57
0.45 V < VI < VCC
—
—
±1
µA
Without pullup resistor
Pull-up
resistance
RPULL
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57,
P60 to P67,
RST
VI = 0.0 V
25
50
100
kΩ
With pull-up
resistor
Common output
impedance
RVCOM COM0 to COM3
—
—
2.5
kΩ
Segment output
impedance
RVSEG
SEG0 to SEG24
—
—
15
kΩ
LCD divided
resistance
RLCD
—
Between VCC and V0
300
500
750
kΩ
—
—
—
±1
µA
4.3
4.5
4.7
V
2.9
3.0
3.1
V
1.27
1.5
1.73
V
600
1000
1400
kΩ
—
10
—
pF
Open-drain
output leakage
current
V1 to V3 = +5.0 V
LCD controller/driver
ILCDL
leakage current
V0 to V3,
COM0 to COM3,
SEG0 to SEG23
VOV3
V3
VOV2
V2
Reference output
voltage for LCD
VOV1
driving
V1
Reference voltage
input impedance
V1
Booster for LCD
driving output voltage
RRIN
Input capacitance CIN
Other than
VCC, VSS
V1 = 1.5 V
IIN = 0 µA
—
f = 1 MHz
Products
without
a booster only
Products with
a booster only
Procucts with
a booster only
Note: For pins which serve as the segment (SEG8 to SEG24) and ports (P40 to P47, P50 to P57, and P60 to P67),
see the port parameter when these pins are used as ports and the segment parameter when they are used
as segments. P32 and P33 are applicable only for products of the MB89160 series (without “A” suffix).
Applicable as external capacitor connection pins for products of the MB89160A series (with “A” suffix).
33
MB89160/160A Series
(2) Pin DC Characteristics (VCC = +3.0 V)
Parameter
“H” level output
voltage
34
Condition
VOH1
P00 to P07,
P10 to P17
IOH = –1.0 mA
2.4
—
—
V
VOH2
P30, P31
IOH = –3.0 mA
2.4
—
—
V
VOL
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P33,
P40 to P47,
P50 to P57,
P60 to P67,
P70 to P71
IOL = 1.8 mA
—
—
0.4
V
VOL2
RST
IOL = 1.8 mA
—
—
0.4
V
VOL3
P21, P26, P27
IOL = 3.6 mA
—
—
0.4
V
RPULL
P00 to P07,
P10 to P17,
P20 to P27,
P40 to P47,
P50 to P57,
P60 to P67,
RST
VI = 0.0 V
50
100
150
kΩ
“L” level output
voltage
Pull-up
resistance
Pin
Symbol
(VCC = 3.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Min.
Typ.
Max.
With pull-up
resistor
MB89160/160A Series
(3)
Power Supply Current Characteristics (MB8916X)
Parameter
Symbol
Pin
Condition
Min.
(VSS = 0.0 V, TA = –40°C to +85°C)
Value
Unit
Remarks
Typ. Max.
MB8916X/A,
MB89PV160
FCH = 4.2 MHz, VCC = 5.0 V
tinst*2 = 4/FCH
Main clock operation mode
—
5.0
10.0
mA
—
8.0
15.0
mA MB89PV165
FCH = 4.2 MHz, VCC = 3.0 V
tinst*2 = 64/FCH
Main clock operation mode
—
1.5
2.0
mA
—
2.4
2.8
mA MB89P165
FCL = 32.768 kHz, VCC = 3.0 V
tinst*2 = 2/FCL
Subclock operation mode
—
0.05
0.1
mA
—
1.0
3.0
mA MB89PV165
FCH = 4.2 MHz, VCC = 5.0 V
tinst*2 = 4/FCH
Main clock sleep mode
—
2.5
5.0
mA
FCH = 4.2 MHz, VCC = 3.0 V
tinst*2 = 64/FCH
Main clock sleep mode
—
1.0
1.5
MB8916X/A,
mA MB89PV160,
MB89PV165
ICCSL
FCL = 32.768 kHz, VCC = 3.0 V
tinst*2 = 2/FCL
Subclock sleep mode
—
25
50
µA
ICCT
FCL = 32.768 kHz, VCC = 3.0 V
Watch mode
—
10
15
µA
ICC1
ICC2
ICCL
ICCS1
ICCS2
VCC
Power supply
current*1
MB8916X/A,
MB89PV160
MB8916X/A,
MB89PV160
MB8916X,
MB89P165-1XX,
MB89PV160
FCL = 32.768 kHz, VCC = 3.0 V
• Watch mode
• During reference voltage
generator and booster operation
ICCT2
ICCH
IA
AVCC
MB8916XA,
—
250
400
µA
MB89P165-2XX
TA = +25°C, VCC = 5.0 V
Stop mode
—
0.1
1.0
µA
MB8916X
—
0.1
10
µA
MB89PV160,
MB89P165-1XX
FCH = 4.2 MHz, VCC = 5.0 V
—
1.0
3.0
When A/D
mA conversion is
activated
*1: The power supply current is measured at the external clock, open output pins, and the external LCD dividing
resistor (or external input for the reference voltage). In the case of the MB89PV160, the current consumed by
the connected EPROM and ICE is not included.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
35
MB89160/160A Series
4. AC Characteristics
(1) Reset Timing
Parameter
(VCC = +5.0 V ±10 %, VSS = 0.0 V, TA = –40°C to +85°C)
Value
Condition
Unit
Remarks
Min.
Max.
Symbol
RST “L” pulse width
tZLZH
RST “H” pulse width
tZHZL
—
48 tXCYL
—
ns
24 tXCYL
—
ns
tZLZH
tZHZL
RST
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
(2) Power-on Reset
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Condition
Value
Min.
Max.
Unit
Remarks
Power supply rising time
tR
—
—
50
ms
Power-on reset
function only
Power supply cut-off time
tOFF
—
1
—
ms
Due to repeated
operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage
needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
2.0 V
VCC
36
0.2 V
0.2 V
0.2 V
MB89160/160A Series
(3) Clock Timing
(VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Value
Min.
Typ.
Max.
Unit
Remarks
FCH
X0, X1
1
—
4.2
MHz
Main clock
FCL
X0A, X1A
—
32.768
—
kHz
Subclock
tHCYL
X0, X1
238
—
1000
ns
Main clock
tLCYL
X0A, X1A
—
30.5
—
µs
Subclock
Input clock pulse width
PWH
PWL
X0
20
—
—
ns
Input clock rising/falling
time
tCR
tCF
X0
—
—
24
ns
Clock frequency
Clock cycle time
External clock
Main Clock Timing and Conditions
tHCYL
0.8 VCC
X0
0.2 VCC
PWH
PWL
tCR
tCF
Main Clock Conditions
When a crystal
or
ceramic resonator is used
X0
X1
When an external clock is used
X0
X1
When the CR
oscillation option is used
X0
X1
Open
FCH
FCH
FCH
C0
C1
R
C
37
MB89160/160A Series
Subclock Timing and Conditions
tLCYL
0.8 VCC
X0A
Subclock Conditions
When a crystal
or
ceramic oscillator is used
X0A
When the single-clock option is used
X0A
X1A
FCL
C0
Rd
X1A
Open
C1
(4) Instruction Cycle
38
Parameter
Symbol
Instruction cycle
(minimum execution time)
tinst
Value (typical)
4/FCH, 8/FCH, 16/FCH,
64/FCH
2/FCL
Unit
Remarks
µs
(4/FCH) tinst = 1.0 µs at FCH = 4 MHz
µs
tinst = 62 µs at FCL = 32.768 kHz
MB89160/160A Series
(5) Serial I/O Timing
(VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SO time
tSLOV
SCK, SO
Valid SI → SCK ↑
tIVSH
SI, SCK
SCK ↑ → valid SI hold time
tSHIX
SCK, SI
Value
Condition
Internal clock
operation
Max.
2 tinst*
—
µs
–200
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
1 tinst*
—
µs
1 tinst*
—
µs
0
200
ns
1/2 tinst*
—
µs
1/2 tinst*
—
µs
SCK
External
clock
operation
Unit
Min.
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
Internal Clock Operation
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
SO
2.4 V
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External Clock Operation
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO
2.4 V
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
39
MB89160/160A Series
(6) Peripheral Input Timing
Parameter
Symbol
Peripheral input “H” pulse width 1
tILIH1
Peripheral input “L” pulse width 1
tIHIL1
Peripheral input “H” pulse width 2
tILIH2
Peripheral input “L” pulse width 2
tIHIL2
(VCC = +5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Pin
Unit
Remarks
Min.
Max.
INT10 to INT13, EC
INT20 to INT27
1 tinst*
—
µs
1 tinst*
—
µs
2 tinst*
—
µs
2 tinst*
—
µs
* : For information on tinst, see “(4) Instruction Cycle.”
t IHIL1
INT10 to 13,
EC
t ILIH1
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
t IHIL2
t ILIH2
INT20 to 27
0.8 VCC
0.2 VCC
40
0.2 VCC
0.8 VCC
MB89160/160A Series
5. A/D Converter Electrical Characteristics
(3 MHz, AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
Resolution
Condition
—
Total error
—
Linearity error
Differential linearity error
Zero transition voltage
Full-scale transition
voltage
Value
Unit Remarks
Min.
Typ.
Max.
—
—
8
bit
—
—
±1.5
LSB
—
—
±1.0
LSB
—
—
±0.9
LSB
AVR = AVCC AVSS – 1.0 LSB AVSS + 0.5 LSB AVSS + 2.0 LSB mV
VOT
—
VFST
AVR – 3.0 LSB AVR – 1.5 LSB
Interchannel disparity
A/D mode conversion time
—
0.5
LSB
—
44 tinst
—
µs
—
12 tinst
—
µs
—
—
10
µA
0.0
—
AVR
V
2.0
—
AVCC
V
AVR = 5.0 V,
when A/D
conversion
is activated
—
100
—
µA
AVR = 5.0 V,
when A/D
conversion
is stopped
—
—
1
µA
Sense mode
conversion time
—
Analog input voltage
—
Reference voltage
—
AN0 to
AN7
IR
AVR
Reference voltage
supply current
IRH
mV
—
—
Analog port input current IAI
AVR
(1) A/D Glossary
• Resolution
Analog changes that are identifiable with the A/D converter.
When the number of bits is 8, analog voltage can be divided into 28=256.
• Linearity error (unit: LSB)
The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the
full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
41
MB89160/160A Series
Digital output
1111 1111
1111 1110
•
•
•
•
•
•
•
•
•
•
•
0000 0010
0000 0001
0000 0000
Actual conversion value
1 LSB =
AVR
256
Theoretical conversion value
VNT − (1 LSB × N + VOT)
Linearity error =
(1 LSB × N + VOT)
1 LSB
V(N+1)T − VNT
Defferential linearity error =
Total error =
1 LSB
−1
VNT − (1 LSB × N + 1 LSB)
1 LSB
Linearity error
VOT
VNT V(N + 1)T
VFST
Analog input
(2) Precautions
• Input impedance of analog input pins
The A/D converter contains a sample hold circuit as illustrated below to fetch analog input voltage into the
sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low (below 10 kΩ).
Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about
0.1 µF for the analog input pin.
Analog Input Equivalent Circuit
Sample hold circuit
.
C =. 33 pF
Analog input pin
Comparator
If the analog input
impedance is higher
than 10 kΩ, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R =. 6 kΩ
Close for 8 instruction cycles after
activating A/D conversion.
Analog channel selector
• Error
The smaller the |AVR – AVSS|, the greater the error would become relatively.
42
MB89160/160A Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
VOL1 vs. IOL
VOL1 (V)
VOL2 vs. IOL
VCC = 2.5 V
VCC = 3.0 V
VCC = 2.0 V
0.6
VCC = 4.0 V
VOL2 (V)
VCC = 2.0 V
1.0
TA = +25°C
0.9
VCC = 5.0 V
0.8
VCC = 6.0 V
0.7
VCC = 4.0 V
0.6
VCC = 5.0 V
TA = +25°C
0.5
0.4
VCC = 2.5 V VCC = 3.0 V
VCC = 6.0 V
0.5
0.3
0.4
0.2
0.3
0.2
0.1
0
0.1
0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
0
2
4
6
8
10
12 14
16 18
20
IOL (mA)
(2) “H” Level Output Voltage
VCC – VOH1 vs. IOH
VCC – VOH1 (V)
VCC = 2.0 V VCC = 2.5 V VCC = 3.0 V
1.0
TA = +25°C
0.9
VCC – VOH2 vs. IOH
VCC – VOH2 (V)
VCC = 2.0 V VCC = 2.5 V
1.0
TA = +25°C
0.9
VCC = 3.0 V
0.8
VCC = 4.0 V
0.8
VCC = 4.0 V
0.7
VCC = 5.0 V
VCC = 6.0 V
0.7
VCC = 5.0 V
VCC = 6.0 V
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–1
–2
–3
–4
–5
IOH (mA)
0
0
–1
–2
–3
–4 –5
–6
–7
–8
–9 –10
IOH (mA)
43
MB89160/160A Series
(3) “H” Level Input Voltage/“L” level Input Voltage
CMOS input
CMOS hysteresis input
VIN (V)
5.0
TA = +25°C
4.5
VIN (V)
5.0
TA = +25°C
4.5
4.0
4.0
3.5
3.5
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
VIHS
VILS
0
1
2
3
4
5
6
7
VCC (V)
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis
characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis
characteristics is set to “L” level
(4) Power Supply Current (External Clock)
ICC1 vs. VCC (Mask ROM products)
ICC2 vs. VCC (Mask ROM products)
ICC1 (mA)
7
ICC2 (mA)
TA = +25°C
TA = +25°C
6
FCH = 4.2 MHz
2.0
5
4
FCH = 4.2 MHz
FCH = 3 MHz
FCH = 3 MHz
3
1.0
2
FCH = 1 MHz
FCH = 1 MHz
1
0
1
2
3
4
5
6
7
VCC (V)
0
1
2
3
4
5
6
7
VCC (V)
(Continued)
44
MB89160/160A Series
ICC2S vs. VCC (Mask ROM products)
ICC1S vs.VCC (Mask ROM products)
ICC2S (mA)
ICC1S (mA)
TA = +25°C
TA = +25°C
3.0
FCH = 4.2 MHz
2.0
FCH = 3 MHz
2.0
FCH = 4.2 MHz
FCH = 3 MHz
1.0
1.0
FCH = 1 MHz
FCH = 1 MHz
0
1
2
3
4
5
6
7
VCC (V)
0
1
2
4
5
6
7
VCC (V)
ICCT vs. VCC
ICCL vs. VCC (Mask ROM products)
ICCL (µA)
200
3
ICCT (µA)
30
TA = +25°C
TA = +25°C
180
25
160
140
FCL = 32.768 kHz
FCL = 32.768 kHz
20
120
100
15
80
10
60
40
5
20
0
1
2
3
4
5
6
7
VCC (V)
0
1
2
3
4
5
6
7
VCC (V)
(Continued)
45
MB89160/160A Series
(Continued)
ICCT2 vs. VCC
ICCSL vs. VCC
ICCSL (µA)
200
ICCT2 (µA)
1,000
TA = +25°C
TA = +25°C
180
900
160
800
140
700
120
600
100
500
FCL = 32.768 kHz
60
300
40
200
20
100
0
IA (mA)
5.0
400
FCL = 32.768 kHz
80
1
2
3
4
5
6
0
7
VCC (V)
IA vs. AVCC
4.5
1
2
3
160
3.5
140
3.0
120
2.5
100
2.0
80
1.5
60
1.0
40
0.5
20
0
1.5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
AVCC (V)
2
2.5
3
3.5
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
TA = +85°C
TA = +25°C
50
TA = –40°C
10
46
3
4
5
7
VCC (V)
TA = +25°C
(5) Pull-up Resistance
2
6
180
4.0
1
5
IR vs. AVR
IR (µA)
200
FCH = 4 MHz
TA = +25°C
4
6
7
VCC (V)
4
4.5
5
5.5
6
6.5
AVR (V)
MB89160/160A Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
•
•
•
•
Transfer
Arithmetic operation
Branch
Others
Table 1 lists symbols used for notation for instructions.
Table 1
Instruction Symbols
Symbol
Meaning
dir
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
#vct
Vector table number (3 bits)
#d8
Immediate data (8 bits)
#d16
Immediate data (16 bits)
dir: b
Bit direct address (8:3 bits)
rel
Branch relative address (8 bits)
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
AH
Upper 8 bits of accumulator A (8 bits)
AL
Lower 8 bits of accumulator A (8 bits)
T
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
TH
Upper 8 bits of temporary accumulator T (8 bits)
TL
Lower 8 bits of temporary accumulator T (8 bits)
IX
Index register IX (16 bits)
(Continued)
47
MB89160/160A Series
(Continued)
Symbol
Meaning
EP
Extra pointer EP (16 bits)
PC
Program counter PC (16 bits)
SP
Stack pointer SP (16 bits)
PS
Program status PS (16 bits)
dr
Accumulator A or index register IX (16 bits)
CCR
Condition code register CCR (8 bits)
RP
Register bank pointer RP (5 bits)
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
×
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(×)
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
Assembler notation of an instruction
~:
Number of instructions
#:
Number of bytes
Operation:
Operation of an instruction
TL, TH, AH:
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
OP code:
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
48
MB89160/160A Series
Table 2
Transfer Instructions (48 instructions)
Mnemonic
~
#
Operation
TL
TH
AH
NZVC
OP code
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
++––
++––
++––
++––
++––
++––
++––
––––
––––
––––
––––
––––
––––
45
46
61
47
48 to 4F
04
05
06
60
92
07
08 to 0F
85
86
87
88 to 8F
D5
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
––––
––––
––––
++––
++––
++––
D4
D7
E3
E4
C5
C6
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
SETB dir: b
CLRB dir: b
XCH A,T
XCHW A,T
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
(dir) ← (A)
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
(A) ← (Ri)
(dir) ← d8
( (IX) +off ) ← d8
( (EP) ) ← d8
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
–
–
–
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AH
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
++––
++––
++––
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
++++
––––
––––
––––
––––
––––
––––
––––
––––
––––
––––
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
A8 to AF
A0 to A7
42
43
F7
F6
F5
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
49
MB89160/160A Series
Table 3
Mnemonic
~
#
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ROLC A
2
1
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
DAS
XOR A
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
AND A,#d8
AND A,dir
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
Arithmetic Operation Instructions (62 instructions)
Operation
TL
TH
AH
NZVC
OP code
(A) ← (A) + (Ri) + C
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) ∧ (T)
(A) ← (A) ∨ (T)
(A) ← (A) ∀ (T)
(TL) − (AL)
(T) − (A)
→ C→A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
–
dH
dH
00
dH
dH
dH
–
–
–
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
++++
+++–
––––
––––
++––
+++–
––––
––––
++––
––––
––––
++R–
++R–
++R–
++++
++++
++–+
28 to 2F
24
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
D2
D0
01
11
63
73
53
12
13
03
C ← A←
–
–
–
++–+
02
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++++
++++
++++
++++
++++
++++
++++
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
14
15
17
16
18 to 1F
84
94
52
54
55
57
56
58 to 5F
62
64
65
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) ∀ (TL)
(A) ← (AL) ∀ d8
(A) ← (AL) ∀ (dir)
(A) ← (AL) ∀ ( (EP) )
(A) ← (AL) ∀ ( (IX) +off)
(A) ← (AL) ∀ (Ri)
(A) ← (AL) ∧ (TL)
(A) ← (AL) ∧ d8
(A) ← (AL) ∧ (dir)
(Continued)
50
MB89160/160A Series
(Continued)
Mnemonic
~
#
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
DECW SP
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
Operation
(A) ← (AL) ∧ ( (EP) )
(A) ← (AL) ∧ ( (IX) +off)
(A) ← (AL) ∧ (Ri)
(A) ← (AL) ∨ (TL)
(A) ← (AL) ∨ d8
(A) ← (AL) ∨ (dir)
(A) ← (AL) ∨ ( (EP) )
(A) ← (AL) ∨ ( (IX) +off)
(A) ← (AL) ∨ (Ri)
(dir) – d8
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
Table 4
Mnemonic
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
RETI
~
#
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
Mnemonic
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
CLRI
SETI
~
#
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++R–
++++
++++
++++
++++
––––
––––
67
66
68 to 6F
72
74
75
77
76
78 to 7F
95
97
96
98 to 9F
C1
D1
Branch Instructions (17 instructions)
Operation
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V ∀ N = 1 then PC ← PC + rel
If V ∀ N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
Table 5
TL
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
––––
––––
––––
––––
––––
––––
––––
––––
–+––
–+––
––––
––––
––––
––––
––––
––––
Restore
FD
FC
F9
F8
FB
FA
FF
FE
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
Other Instructions (9 instructions)
Operation
TL
TH
AH
NZVC
OP code
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
––––
––––
––––
––––
––––
–––R
–––S
––––
––––
40
50
41
51
00
81
91
80
90
51
L
52
D
E
F
MOVW
MOVW
CLRB
BBC
MOVW XCHW
dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16
A,IX
MOV
CMP
CLRB
BBC
MOVW MOVW MOVW XCHW
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
A,EP
dir: 7 dir: 7,rel A,@EP @EP,A EP,#d1
A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8
6
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNC
A,R0
A,R0
A,R0
A,R0
R0,A
A,R0
A,R0
A,R0 R0,#d8 R0,#d8
dir: 0 dir: 0,rel
R0
R0
#0
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BC
A,R1
A,R1
A,R1
A,R1
R1,A
A,R1
A,R1
A,R1 R1,#d8 R1,#d8
dir: 1 dir: 1,rel
R1
R1
#1
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BP
A,R2
A,R2
A,R2
A,R2
R2,A
A,R2
A,R2
A,R2 R2,#d8 R2,#d8
dir: 2 dir: 2,rel
R2
R2
#2
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BN
A,R3
A,R3
A,R3
A,R3
R3,A
A,R3
A,R3
A,R3 R3,#d8 R3,#d8
dir: 3 dir: 3,rel
R3
R3
#3
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BNZ
A,R4
A,R4
A,R4
A,R4
R4,A
A,R4
A,R4
A,R4 R4,#d8 R4,#d8
dir: 4 dir: 4,rel
R4
R4
#4
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BZ
A,R5
A,R5
A,R5
A,R5
R5,A
A,R5
A,R5
A,R5 R5,#d8 R5,#d8
dir: 5 dir: 5,rel
R5
R5
#5
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BGE
A,R6
A,R6
A,R6
A,R6
R6,A
A,R6
A,R6
A,R6 R6,#d8 R6,#d8
dir: 6 dir: 6,rel
R6
R6
#6
rel
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
SETB
BBS
INC
DEC
CALLV BLT
A,R7
A,R7
A,R7
A,R7
R7,A
A,R7
A,R7
A,R7 R7,#d8 R7,#d8
dir: 7 dir: 7,rel
R7
R7
#7
rel
7
8
9
A
B
C
D
E
F
A
MOV
CMP
MOV
CMP
ADDC
SUBC
MOV
XOR
AND
OR
A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
XCH
XOR
AND
OR
A, T
A
A
6
A
MOVW MOVW MOVW XCHW
MOV
CMP
ADDC SUBC
MOV
XOR
AND
OR
MOV
CMP
CLRB
BBC
A,dir
dir,A SP,#d16
A,SP
A,dir
A,dir
A,dir
A,dir
dir,A
A,dir
A,dir
A,dir dir,#d8 dir,#d8
dir: 5 dir: 5,rel
SUBC
5
A
MOV
CMP
ADDC SUBC
A,#d8
A,#d8
A,#d8
A,#d8
ADDC
MOV
MOV
CLRB
BBC
INCW
DECW MOVW MOVW
@A,T
A,@A
dir: 2 dir: 2,rel
IX
IX
IX,A
A,IX
XOR
AND
OR
DAA
A,#d8
A,#d8
A,#d8
DAS
rel
rel
rel
rel
BBC
MOVW MOVW MOVW XCHW
CLRB
A,ext
ext,A A,#d16
A,PC
dir: 4 dir: 4,rel
MOVW MOVW CLRB
BBC
INCW
DECW MOVW MOVW
CMPW ADDCW SUBCW XCHW XORW ANDW ORW
A
A
A, T
A
A
A
@A,T
A,@A
dir: 3 dir: 3,rel
EP
EP
EP,A
A,EP
A
CMP
A
4
A
A
CLRB
BBC
INCW
DECW MOVW MOVW
dir: 1 dir: 1,rel
SP
SP
SP,A
A,SP
RORC
CLRB
BBC
INCW
DECW JMP
MOVW
dir: 0 dir: 0,rel
A
A
@A
A,PC
C
3
SETC
PUSHW POPW
MOV
MOVW CLRC
JMP
CALL
IX
IX
ext,A
PS,A
addr16 addr16
RETI
B
ROLC
DIVU
RET
A
2
A
7
MULU
A
6
SETI
5
PUSHW POPW MOV
MOVW CLRI
A
A
A,ext
A,PS
4
9
3
8
2
1
SWAP
1
NOP
0
0
H
MB89160/160A Series
■ INSTRUCTION MAP
MB89160/160A Series
■ MASK OPTIONS
Part number
MB89161/3/5
MB89P165
MB89PV160
Specifying procedure
Specify when
ordering masking
Set with EPROM
programmer
Setting not possible
Pull-up resistors (SEG)
P00 to P07, P10 to P17,
P20 to P27, P40 to P47,
P50 to P57, P60 to P67
Power-on reset (POR)
With power-on reset
Without power-on reset
Slectable per pin
(The pull-up resistors for
P40 to P47 and P60 to
P67 are only selectable
when these pins are not
set as segment outputs.
When the A/D is used,
P50 to P57 are must not
selected.)
Selectable
Can be set per pin
(P20 to P27, P40 to
P47, and P60 to P67
are available only for
without a pull-up
resistor.)
Selectable
Fixed to without
pull-up resistor
Fixed to with power-on
reset
Selection of oscillation stabilization
Selectable
time (OSC)
OSC
• The initial value of the oscillation
0
: 22/FCH
stabilization time for the main clock
1
: 212/FCH
can be set by selecting the values of
2
: 216/FCH
the WTM1 and WTM0 bits on the
3
: 218/FCH
right.
Selectable
WTM1 WTM0
Fixed to oscillation
0
0
: 22/FCH
stabilization time of
12
0
1
: 2 /FCH 16
2 /FCH
16
1
0
: 2 /FCH
1
1
: 218/FCH
Main clock oscillation type (XSL)
Crystal or ceramic resonator
CR
Selectable
Crystal or ceramic only
Fixed to crystal or
ceramic
Reset pin output (RST)
With reset output
Without reset output
Selectable
Selectable
Fixed to with reset
output
Clock mode selection (CLK)
Dual-clock mode
Single-clock mode
Selectable
Selectable
Fixed to dual-clock
mode
53
MB89160/160A Series
• Segment Options
No.
7
Part number
MB89161/3/5
MB89P165
MB89PV160
Specifying procedure
Specify when
ordering masking
Select by version
number
Select by version
number
LCD output pin configuration
choices
Specify by the option
combinations listed
below
SEG = 4:
P40 to P47 segment output
P60 to P67 segment output
P70, P71 common output
Specify as SEG = 4
–101 : SEG 24 pins
–201 COM 4 pins
–101 : SEG 24 pins
COM 4 pins
SEG = 3:
P40 to P43 segment output
P44 to P47 port output
P60 to P67 segment output
P70, P71 common output
Specify as SEG = 3
–102 : SEG 20 pins
–202 COM 4 pins
–102 : SEG 20 pins
COM 4 pins
SEG = 2:
P40 to P47 port output
P60 to P67 segment output
P70, P71 common output
Specify as SEG = 2
–103 : SEG 16 pins
–203 COM 4 pins
–103 : SEG 16 pins
COM 4 pins
SEG = 1:
P40 to P47 port output
P60 to P63 segment output
P64 to P67 port output
P70, P71 port output
Specify as SEG = 1
–104 : SEG 12 pins
COM 2 pins
–104 : SEG 12 pins
COM 2 pins
SEG = 0:
P40 to P47 port output
P60 to P67 port output
P70, P71 port output
Specify as SEG = 0
–105 : SEG 8 pins
COM 2 pins
–105 : SEG 8 pins
COM 2 pins
■ VERSIONS
Version
Mass production
product
54
Features
One-time PROM
product
Piggyback/evaluation
product
Number of segment
pins
Booster
MB89160A series
MB89P165-201
-202
-203
—
24 (4 commons)
20 (4 commons)
16 (4 commons)
Yes
MB89160 series
MB89P165-101
-102
-103
-104
-105
MB89PV160-101
-102
-103
-104
-105
24 (4 commons)
20 (4 commons)
16 (4 commons)
12 (2 commons)
8 (2 commons)
No
MB89160/160A Series
■ ORDERING INFORMATION
Part number
MB89161-PFV
MB89161A-PFV
MB89163-PFV
MB89163A-PFV
MB89165-PFV
MB89165A-PFV
MB89P165-×××-PFV
Package
Remarks
80-pin Plastic SQFP
(FPT-80P-M05)
MB89161-PF
MB89161A-PF
MB89163-PF
MB89163A-PF
MB89165-PF
MB89165A-PF
MB89P165-×××-PF
80-pin Plastic QFP
(FPT-80P-M06)
MB89161-PFS
MB89161A-PFS
MB89163-PFS
MB89163A-PFS
MB89165-PFS
MB89165A-PFS
MB89P165-×××-PFS
80-pin Plastic QFP
(FPT-80P-M11)
MB89W165-×××-PF
80-pin Ceramic QFP
(FPT-80C-A02)
MB89PV160-×××-PF
80-pin Ceramic MQFP
(MQP-80C-P01)
Note: For information on ×××, see section “■ Versions.”
55
MB89160/160A Series
■ PACKAGE DIMENSIONS
80-pin plastic LQFP
(FPT-80P-M05)
+0.20
14.00±0.20(.551±.008)SQ
1.50 –0.10
+.008
.059 –.004
12.00±0.10(.472±.004)SQ
60
(Mounting height)
41
61
40
9.50
(.374)
REF
13.00
(.512)
NOM
INDEX
80
21
LEAD No.
1
20
0.18
0.50±0.08
(.0197±.0031)
.007
Details of "A" part
"A"
+0.08
–0.03
+.003
–.001
+0.05
–0.02
+.002
–.001
0.127
.005
0.10±0.10
(STAND OFF)
(.004±.004)
0.50±0.20(.020±.008)
0.10(.004)
0
Dimensions in mm (inches).
1995 FUJITSU LIMITED F80008S-2C-5
C
10°
80-pin plastic QFP
(FPT-80P-M06)
23.90±0.40(.941±.016)
3.35(.132)MAX
(Mounting height)
0.05(.002)MIN
(STAND OFF)
20.00±0.20(.787±.008)
64
41
65
40
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
12.00(.472)
REF
16.30±0.40
(.642±.016)
INDEX
80
25
"A"
LEAD No.
1
24
0.80(.0315)TYP
0.35±0.10
(.014±.004)
0.16(.006)
0.15±0.05(.006±.002)
M
Details of "A" part
Details of "B" part
0.25(.010)
"B"
0.10(.004)
18.40(.724)REF
22.30±0.40(.878±.016)
C
1994 FUJITSU LIMITED F80010S-3C-2
0.30(.012)
0.18(.007)MAX
0.58(.023)MAX
0
10°
0.80±0.20
(.031±.008)
Dimensions in mm (inches).
56
MB89160/160A Series
80-pin plastic LQFP
(FPT-80P-M11)
+0.20
16.00±0.20(.630±.008)SQ
1.50 –0.10
+.008
14.00±0.10(.551±.004)SQ
60
.059 –.004
41
61
(Mounting height)
40
12.35
(.486)
REF
15.00
(.591)
NOM
1 PIN INDEX
80
LEAD No.
21
1
Details of "A" part
"A"
0.65(.0256)TYP
0.30±0.10
(.012±.004)
20
0.13(.005)
0.127
M
.005
0.10(.004)
C
0.10±0.10
(STAND OFF)
(.004±.004)
+0.05
–0.02
+.002
–.001
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches).
1995 FUJITSU LIMITED F80016S-1C-3
80-pin ceramic QFP
(FPT-80C-A02)
0.51(.020) TYP
17.91(.705)
TYP
16.00(.630)
14.00±0.25
TYP
(.551±.010)
12.00(.472)
REF
8.50(.335)TYP
16.31(.642)
TYP
INDEX AREA
+0.08
0.35 –0.07
0.80±0.10
(.0315±.0040)
(.014±.003)
18.40(.725) REF
0.15±0.05
(.006±.002)
1.60(.063) TYP
0.80±0.10
(.0315±.0040)
20.00±0.25
(.787±.010)
23.90(.941) TYP
4.45(.175)MAX
22.00(.866) TYP
22.30(.878) TYP
C
1994 FUJITSU LIMITED F80014SC-1-2
0.80(.0315) TYP
Dimensions in mm (inches).
57
MB89160/160A Series
(Continued)
80-pin ceramic MQFP
(MQP-80C-P01)
18.70(.736)TYP
12.00(.472)TYP
INDEX AREA
16.30±0.33
(.642±.013)
15.58±0.20
(.613±.008)
1.50(.059)TYP
1.00(.040)TYP
4.50(.177)
TYP
+.016
.047 –.008
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
0.30(.012)
TYP
0.80±0.25
(.0315±.010)
0.80±0.25
(.0315±.010)
+0.40
1.20 –0.20
INDEX AREA
18.12±0.20
12.02(.473)
(.713±.008)
TYP
10.16(.400)
14.22(.560)
TYP
TYP
18.40(.724)
REF
INDEX
1.27±0.13
(.050±.005)
6.00(.236)
TYP
0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.40±0.10
(.016±.004)
1.50(.059)
TYP
1.00(.040)
TYP
0.40±0.10
(.016±.004)
+0.40
1.20 –0.20
+.016
.047 –.008
0.15±0.05 8.70(.343)
(.006±.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches).
58
MB89160/160A Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
F0004
 FUJITSU LIMITED Printed in Japan
59