FUJITSU MB91460

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16602-1E
32-bit Microcontroller
CMOS
FR60 MB91460 Series
MB91461
■ DESCRIPTION
MB91461 is a line of the general-purpose 32-bit RISC microcontrollers designed for embedded control applications such as consumer devices and vehicle system, which require high-speed real-time processing. MB91461
uses the FR60 CPU compatible with the FR family* CPUs.
MB91461 contains the LIN-UART and CAN controller.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
• FR60 CPU
• 32-bit RISC, load/store architecture, five-stage pipeline
• Maximum operating frequency : 80 MHz (oscillation frequency 20 MHz, oscillation frequency 4 multiplier (PLL
clock multiplication method))
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed : 1 instruction per cycle
• Instructions including memory-to-memory transfer, bit manipulation instructions, and barrel shift instructions:
Instructions suitable for embedded applications
• Function entry/exit instructions and register data multi load store instructions: Instructions supporting C
language
• Register interlock function : Facilitating assembly-language coding
• Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC/PS saving) : 6 cycles (16 priority levels)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved
MB91460 Series
• Harvard architecture enabling simultaneous execution of both program access and data access
• Instructions compatible with the FR family
• Internal peripheral resources
• MB91461 does not contain the ROM and flash memory.
• Internal RAM capacity : Instruction cache 4 Kbytes + 64 Kbytes (Instruction/data common RAM)
• General-purpose port : Maximum 72 ports
• DMAC (DMA Controller)
Maximum of 5 channels for simultaneous operation is possible. (1 channel for external-to-external)
3 transfer sources (external pin/internal peripheral/software)
Activation source can be selected using software.
Addressing mode with 32-bit full address indication (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Fly-by transfer support (between external I/O and memory)
Transfer data size selection 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (sequential comparison)
10-bit resolution: 13 channels
Conversion time: 1 µs (peripheral macro operation clock at 16.67 MHz)
• External interrupt input: 16 channels
Pins shared with RX pins of CAN0 and CAN1
• Bit search module (for REALOS)
Function of searching for the first “0” data/ “1” data/change bit position in 1 word from the MSB (upper bit)
• LIN-UART (full duplex double buffer): 7 channels
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
• I2C* bus interface (400 kbps supported): 3 channels
Master/slave sending and receiving
Arbitration function, clock synchronization function
• CAN controller (C-CAN) : 2 channels
Maximum transfer speed : 1 Mbps
32 sent/received message buffers
• 16-bit PPG timer : 8 channels
• 16-bit reload timer : 5 channels
• 16-bit free-run timer : 4 channels (1 channel each for ICU and OCU)
• Input capture : 4 channels (work with free-run timer)
• Output compare : 4 channels (work with free-run timer)
• Watchdog timer
Watchdog reset output pin available
• Real-time clock
• Low-power consumption mode: Sleep/stop/shutdown mode function
(Continued)
2
MB91460 Series
(Continued)
• Package : LQFP-176 (FPT-176P-M07)
• CMOS 0.18 µm technology
• 3 V/5 V power supplies [Internal logic is kept at 1.8 V by step-down circuit, some I/Os have the withstand voltage
of 5.0 V]
• Operating temperature range : between − 40°C and + 85°C
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
3
MB91460 Series
■ PIN ASSIGNMENT
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VCC5
P17_3/PPG3
P17_2/PPG2
P17_1/PPG1
P17_0/PPG0
P14_3/ICU3/TIN3/TRG3
P14_2/ICU2/TIN2/TRG2
P14_1/ICU1/TIN1/TRG1
P14_0/ICU0/TIN0/TRG0
P22_3
P22_2/INT13
P22_0/INT12
P23_6/INT11
P23_4/INT10
VCC5
VSS
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P18_2/SCK6
P18_1/SOT6
P18_0/SIN6
P19_6/SCK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4
P19_1/SOT4
P19_0/SIN4
VCC5
VSS
P20_6/SCK3/FRCK3
P20_5/SOT3
P20_4/SIN3
P20_2/SCK2/FRCK2
P20_1/SOT2
P20_0/SIN2
P21_6/SCK1/FRCK1
P21_5/SOT1
P21_4/SIN1
P21_2/SCK0/FRCK0
P21_1/SOT0
P21_0/SIN0
VCC5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
(1)
(2)
(3)
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VSS
INIT
TRST
MD0
MD1
MD2
MD3
P23_3/TX1
P23_2/RX1/INT9
P23_1/TX0
P23_0/RX0/INT8
P24_7/INT7
P24_6/INT6
P22_5/SCL0
P22_4/SDA0/INT14
P24_1/INT1
P24_0/INT0
AVRH
AVCC3
AVSS/AVRL
P28_4/AN12
P28_3/AN11
P28_2/AN10
P28_1/AN9
P28_0/AN8
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
WDRESET
BREAK
ICLK
ICS2
ICS1
ICS0
ICD3
ICD2
ICD1
ICD0
VCC3
VSS
D24
D25
D26
D27
D28
D29
D30
D31
A00
A01
A02
VCC3
VSS
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
VCC3
VSS
A17
A18
A19
A20
A21
A22
A23
NMI
P16_7/ATG
P17_4/PPG4
P17_5/PPG5
P17_6/PPG6
P17_7/PPG7
VSS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
P24_2/INT2
P24_3/INT3
P22_6/SDA1/INT15
P22_7/SCL1
P24_4/SDA2/INT4
P24_5/SCL2/INT5
DREQ0
DACK0
DEOP0
VCC3
VCC3
VSS
C_1
CS4
CS3
CS2
CS1
CS0
IORD
IOWR
RDY
BRQ
BGRNT
RD
WR0
WR1
SYSCLK
AS
VCC3
C_2
VSS
X0
X1
VSS
D16
D17
D18
D19
D20
D21
D22
D23
VCC3
(FPT-176P-M07)
Note : (1) to (3) are 3.3 V/5 V pin supported pin, and can set 3.3 V and 5 V to the voltage in each block. I2C pin in
(1) can be inputted at 5 V power supply. However, 3.3 V of the input threshold value is used as the standard
value regardless of the power supply voltage.
If 5 V is set in (1) or (2), also set 5 V to (3).
4
MB91460 Series
■ PIN DESCRIPTION
Pin no.
2
3
Pin name
P24_2
INT2
P24_3
INT3
I/O
I/O circuit
type*
I/O
D
I/O
D
P22_6
4
SDA1
P22_7
SCL1
C
SDA2
I/O
Open Drain
C
C
External interrupt input pin
I2C bus data input/output pin
General-purpose input/output port
I2C bus clock input/output pin
I2C bus data input/output pin
External interrupt input pin
P24_5
SCL2
General-purpose input/output port
General-purpose input/output port
I/O
Open Drain
INT4
7
External interrupt input pin
External interrupt input pin
P24_4
6
General-purpose input/output port
General-purpose input/output port
I/O
Open Drain
INT15
5
Function
General-purpose input/output port
I/O
Open Drain
C
INT5
I2C bus clock input/output pin
External interrupt input pin
8
DREQ0
I
H
DMA external transfer request input
9
DACK0
O
H
DMA external transfer acknowledge output
10
DEOP0
O
H
DMA external transfer EOP (End of Process) output
15
CS4
O
H
Chip select 4 output
16
CS3
O
H
Chip select 3 output
17
CS2
O
H
Chip select 2 output
18
CS1
O
H
Chip select 1 output
19
CS0
O
H
Chip select 0 output
20
IORD
O
H
Read strobe output at DMA fly-by transfer
21
IOWR
O
H
Write strobe output at DMA fly-by transfer
22
RDY
I
H
External ready input
23
BRQ
I
H
External bus open request input
24
BGRNT
O
H
External bus open acknowledge output
25
RD
O
H
External read strobe output
26
WR0
O
H
External write strobe output
27
WR1
O
H
External write strobe output
28
SYSCLK
O
H
System clock output
29
AS
O
H
Address strobe output
33
X0
⎯
G
Clock (oscillation) input
34
X1
⎯
G
Clock (oscillation) output
(Continued)
5
MB91460 Series
Pin no.
Pin name
I/O
I/O circuit
type*
36 to 43
46 to 53
D16 to D31
I/O
H
External data bus signal
54 to 56
59 to 72
75 to 81
A00 to A23
O
H
External address bus signal
82
NMI
I
H
NMI (Non Maskable Interrupt) input
I/O
H
I/O
H
83
84 to 87
P16_7
ATG
P17_4 to P17_7
PPG4 to PPG7
Function
General-purpose input/output port
A/D converter external trigger input
General-purpose input/output ports
PPG timer output pins
90 to 93
ICD0 to ICD3
I/O
H
Data input/output pins for development tool
94 to 96
ICS0 to ICS2
O
H
Status output pins for development tool
97
ICLK
O
I
Clock output pin for development tool
98
BREAK
I
H
Break input pin for development tool
99
WDRESET
O
J
Watchdog reset output pin
I/O
F
I/O
F
100 to 107
108 to 112
P29_0 to P29_7
AN0 to AN7
P28_0 to P28_4
AN8 to AN12
P24_0, P24_1
116, 117
INT0, INT1
SDA0
I/O
D
P22_5
SCL0
C
INT6
I/O
Open Drain
C
I/O
D
INT7
External interrupt input pins.
Can be used as a return source from shutdown.
I2C bus data input/output pin
General-purpose input/output port
I2C bus clock input/output pin
General-purpose input/output port
P24_7
121
Analog input pins for A/D converter
External interrupt input pin
P24_6
120
General-purpose input/output ports
General-purpose input/output port
I/O
Open Drain
INT14
119
Analog input pins for A/D converter
General-purpose input/output ports
P22_4
118
General-purpose input/output ports
External interrupt input pin.
Can be used as a return source from shutdown.
General-purpose input/output port
I/O
D
External interrupt input pin.
Can be used as a return source from shutdown.
(Continued)
6
MB91460 Series
Pin no.
Pin name
I/O
I/O circuit
type*
P23_0
122
RX0
General-purpose input/output port
I/O
D
P23_1
TX0
I/O
D
P23_2
124
RX1
P23_3
TX1
General-purpose input/output port
TX output pin of CAN0
General-purpose input/output port
I/O
D
RX input pin of CAN1
External interrupt input pin.
Can be used as a return source from shutdown.
INT9
125
RX input pin of CAN0
External interrupt input pin.
Can be used as a return source from shutdown.
INT8
123
Function
I/O
D
General-purpose input/output port
TX output pin of CAN1
126
MD3
I
A
127
MD2
I
A
128
MD1
I
A
129
MD0
I
B
130
TRST
I
E
Reset input pin for development tool
131
INIT
I
B
External reset input
I/O
D
I/O
D
134
135
P21_0
SIN0
P21_1
SOT0
P21_2
136
SCK0
138
P21_4
SIN1
P21_5
SOT1
I/O
D
SCK1
I/O
D
I/O
D
P20_0
SIN2
General-purpose input/output port
Data output pin of UART0
Clock input/output pin of UART0
General-purpose input/output port
Data input pin of UART1
General-purpose input/output port
Data output pin of UART1
General-purpose input/output port
I/O
D
FRCK1
140
Data input pin of UART0
External clock input pin of free-run timer0
P21_6
139
General-purpose input/output port
General-purpose input/output port
FRCK0
137
Mode setting pins
Clock input/output pin of UART1
External clock input pin of free-run timer1
I/O
D
General-purpose input/output port
Data input pin of UART2
(Continued)
7
MB91460 Series
Pin no.
141
Pin name
P20_1
SOT2
I/O
I/O circuit
type*
I/O
D
P20_2
142
SCK2
144
P20_4
SIN3
P20_5
SOT3
I/O
D
SCK3
I/O
D
I/O
D
149
150
151
152
153
154
155
156
P19_0
SIN4
P19_1
SOT4
P19_2
SCK4
P19_4
SIN5
P19_5
SOT5
P19_6
SCK5
P18_0
SIN6
P18_1
SOT6
P18_2
SCK6
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
P23_4
INT10
Data input pin of UART3
General-purpose input/output port
Data output pin of UART3
Clock input/output pin of UART3
General-purpose input/output port
Data input pin of UART4
General-purpose input/output port
Data output pin of UART4
General-purpose input/output port
Clock input/output pin of UART4
General-purpose input/output port
Data input pin of UART5
General-purpose input/output port
Data output pin of UART5
General-purpose input/output port
Clock input/output pin of UART5
General-purpose input/output port
Data input pin of UART6
General-purpose input/output port
Data output pin of UART6
General-purpose input/output port
Clock input/output pin of UART6
General-purpose input/output ports
I/O
D
TOT0 to TOT3
163
General-purpose input/output port
External clock input pin of free-run timer3
P15_0 to P15_3
157 to 160 OCU0 to OCU3
Clock input/output pin of UART2
General-purpose input/output port
FRCK3
148
Data output pin of UART2
External clock input pin of free-run timer2
P20_6
145
General-purpose input/output port
General-purpose input/output port
FRCK2
143
Function
Output compare output pins
Reload timer output pins
I/O
D
General-purpose input/output port
External interrupt input pin
(Continued)
8
MB91460 Series
(Continued)
Pin no.
164
165
166
167
Pin name
P23_6
INT11
P22_0
INT12
P22_2
INT13
P22_3
I/O
I/O circuit
type*
I/O
D
I/O
D
I/O
D
I/O
D
P14_0 to P14_3
168 to 171
ICU0 to ICU3
TIN0 to TIN3
P17_0 to P17_3
PPG0 to PPG3
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
General-purpose input/output ports
I/O
D
TRG0 to TRG3
172 to 175
Function
Input capture input pins
External trigger input pins of reload timer
External trigger input pins of PPG
I/O
D
General-purpose input/output ports
PPG timer output pins
*: For details of I/O circuit types, refer to “■ I/O CIRCUIT TYPE”.
9
MB91460 Series
[Power supply/GND pins]
Pin number
Pin name
Function
1, 13, 32, 35, 45,
58, 74, 88, 132,
146, 161
VSS
(VSS)
11, 12, 30, 44,
57,
73, 89
VCC3
(VCC3)
3.3 V power supply pins
(VCC5)
5 V power supply pins. These pins are I/O power supplies
corresponding to 116 to 145 pins. The corresponding I/O pin
operates at 3.3 V when supplying 3.3 V, and at 5 V when
supplying 5V. Be sure to supply 5 V if more than one 5V
operating pin is specified, or 5V is supplied at pin 162 or pin
176.
(VCC5)
5 V power supply pin. This pin is an I/O power supply
corresponding to 148 to 160 pins. The corresponding I/O pin
operates at 3.3 V when supplying 3.3 V, and at 5V when
supplying 5 V. Be sure to supply 5 V if more than one 5 V
operating pin is specified.
133, 147
162
10
I/O
VCC5
VCC5
GND pins
176
VCC5
(VCC5)
5 V power supply pin. This pin is an I/O power supply
corresponding to 2 to 7 pins. The corresponding I/O pin
operates at 3.3 V when supplying 3.3 V, and at 5 V when
supplying 5 V. Be sure to supply 5 V if more than one 5 V
operating pin is specified.
113
AVSS/AVRL
(AVSS)
Analog GND pin for A/D converter
114
AVCC3
(AVCC3)
3.3 V power supply pin for A/D converter
115
AVRH
(AVRH)
Reference power supply pin for A/D converter
14
C_1
⎯
Capacitor connection pin for internal regulator. Connect a
4.8 µF capacitor.
31
C_2
⎯
Capacitor connection pin for internal regulator. Connect a
4.8 µF capacitor.
MB91460 Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
5 V CMOS hysteresis input
5 V level
Input
A
N-ch
5 V CMOS hysteresis input
P-ch
B
Input
5 V level
N-ch
Output drive N-ch
Input/output pin for I2C
IOL = 3 mA
With stand voltage of 5 V
With standby control
C
Input
Standby control
(Continued)
11
MB91460 Series
Type
Circuit type
Remarks
P-ch
Pull-up control
P-ch
5 V level
5 V CMOS output
IOL = 4 mA
5 V CMOS input
5 V CMOS hysteresis input
With 50 kΩ pull-up/pull-down
control
With standby control
Output drive P-ch
N-ch
Output drive N-ch
D
N-ch
Pull-down control
Input
Standby control
Input
Standby control
3.3 V level
E
Input
P-ch
3.3 V level
Output drive P-ch
N-ch
Output drive N-ch
F
3.3 V CMOS hysteresis input
With stand voltage of 5 V
With standby control
3.3 V CMOS output
IOL = 4 mA
3.3 V CMOS input
3.3 V CMOS hysteresis input
Analog input
With standby control
Input
Standby control
Input
Standby control
Analog input
(Continued)
12
MB91460 Series
(Continued)
Type
Circuit type
Remarks
3.3 V oscillation cell
3.3 V level
Input
G
Standby control
P-ch
Pull-up control
P-ch
3.3 V level
Output drive P-ch
3.3 V CMOS output
IOL = 4 mA
3.3 V CMOS input
3.3 V CMOS hysteresis input
With 33 kΩ pull-up/pull-down control
With standby control
N-ch
Output drive N-ch
H
N-ch
Pull-down control
Input
Standby control
Input
Standby control
P-ch
Output drive P-ch
3.3 V level
3.3 V CMOS output
I : IOL = 8 mA
J : IOL = 4 mA
I, J
N-ch
Output drive N-ch
13
MB91460 Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than VCC or less than VSS is applied to an input or output
pin or if a voltage exceeding the rating is applied between VCC pin and VSS pin. If latch-up occurs, the power
supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, when using
a CMOS IC, do not exceed the maximum rating.
• Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor.
• Power supply pins
When provided with multiple VCC pins or VSS pins, the device is designed such that the pins having equal
potential are interconnected internally to prevent malfunctions such as latch-up. All of these pins must however
be connected to the power supply and ground externally to reduce unwanted radiation, to prevent the strobe
signal from malfunctioning due to a rise of ground level, and to follow the total output current standards. In
addition, VCC pin and VSS pin of this device should be connected from the power supply source with the lowest
possible impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
VCC pin and VSS pin near this device.
This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 µF to C_1 and C_2 pins for
the regulator.
• Crystal oscillator circuit
Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards
should be designed so that the X0 and X1 pins, and crystal oscillator, as well as bypass capacitors connected
to ground, are placed as close together as possible.
The use of printed circuit board architecture in which the X0 and X1 pins are surrounded by ground contributes
to stable operation and is strongly recommended.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Notes on using external clock
In principle, when using external clock, supply a clock to the X0 pin and X1 pin simultaneously. Also, an opposite
phase clock to the X0 pin must be supplied to the X1 pin. However, in this case the stop mode (oscillation stop
mode) must not be used (This is because the X1 pin stops at ”H” output in STOP mode).
X0
X1
(Note) Stop mode (oscillation stop mode) cannot be used.
Example of using external clock (normal)
14
MB91460 Series
• Mode pins (MD0 to MD3)
When using mode pins, connect them directly to VCC pin or VSS pin. To prevent the device from entering test
mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and VCC pin or
VSS pin on the printed circuit board as possible and connect them with low impedance.
• Power-on sequences for 3.3 V and 5 V
• Immediately after power-on, keep “L” level input to the INIT pin for the oscillation stabilization wait time (8 ms)
to ensure the oscillation stabilization wait time for the oscillator circuit.
• There is no power-on sequences.
• When executing a reset cancellation (changing INIT pin from “L” level to “H” level), be sure to execute it while
3 V and 5 V power supplies are stable.
• Caution on operations during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
• External bus setting
This model guarantees the maximum frequency of 40 MHz for the external bus clock SYSCLK.
Setting the base clock frequency to 80 MHz without changing the initial value of DIVR1 (external bus base clock
division setting register) sets the external bus frequency also to 80 MHz. Before changing the base clock
frequency, set SYSCLK not exceeding 40 MHz.
• Pull-up control
Connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the AC standard.
• Notes on PS register
Since some instructions process the PS register in advance, the following exceptional operations may cause a
break in the interrupt process routine or an update of display contents of the flag in the PS register when the
debugger is being used. In either case, as the device is designed to carry out reprocessing correctly upon
returning from such an EIT event, it performs operations before and after the EIT as specified.
1) The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S
instruction accepts a user interrupt/NMI, executes a step, or breaks in response to a data event or emulator
menu.
-D0 and D1 flags are updated in advance.
-An EIT process routine (user interrupt/NMI or emulator) is executed.
-Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated
to the same values as those in 1).
2) The following operations are performed when each instruction of OR CCR, ST ILM, MOV Ri and PS is
executed to enable interrupts while a user interrupt/NMI source has been occurring.
-The PS register is updated in advance.
-An EIT process routine (user interrupt/NMI or emulator) is executed.
-Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same
value as that in 1).
15
MB91460 Series
■ NOTES ON DEBUGGER
• Step execution of RETI instruction
In the environment where interrupts occur frequently when stepping, only the corresponding interrupt process
routines are executed repeatedly. As the result of that, the main routine and low-interrupt-level programs are not
executed (For example, if an interrupt to the time base timer is enabled, a break always occurs at the beginning
of the time base routine when stepping RETI) .
Disable the corresponding interrupts when the debug on the corresponding interrupt process routines becomes
unnecessary.
• Break function
If the target address of a hardware break (including an event break) is set to the address currently contained in
the system stack pointer or in the area containing the stack pointer, the user program causes a break after
execution of one instruction even though there is no actual data access instruction in the user program.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the
target of a hardware break (including an event break).
• Operand break
If a stack pointer exists in the area which is set as the DSU operand break, malfunctions may occur. Do not set
the access to the areas containing the address of system stack pointer as a target of data event break.
16
MB91460 Series
■ DSU4 (ICE) DEDICATED CONNECTION PINS
MB91461 DSU4 (ICE) dedicated connection pins
Pin no.
Pin name
Function
93 to 90
ICD3 to ICD0
Data input/output pins for development tool
96 to 94
ICS2 to ICS0
Status output pins for development tool
97
ICLK
Clock pin for development tool
98
BREAK
Break pin for development tool
130
TRST
Reset pin for development tool
(3 V/5 V supported input pin)
• User target side connector and the MB91461 connection
The recommended connector for the user target side is shown below.
Manufacturer : YAMAICHI ELECTRONICS CO., LTD.
Model number : FAP-20-08#*
Note : The asterisk (*) in the model number represents each of the following pin shapes:
• 1 : Right angle/wrapping
• 2 : Right angle/solder dip
• 4 : Straight/solder dip
Pin 19
Pin 1
Pin 20
Pin 2
17
MB91460 Series
18
Connector
pin no.
Signal line
name
I/O
1
EVCC2
I
Open
2
EVCC3
I
Open
3
DSUIO
I/O
Open
4
UVCC
O
User VCC output
6
XRSTIN
O
Connected to user circuit INIT signal
8
PLVL
I
Open
5
XTRST
I
Connected to TRST (130 pin)
7
XINIT
I
Connected to INIT (131 pin)
9
GND
⎯
10
BREAK
I
11
ICD3
12
ICD2
13
ICD1
14
ICD0
15
GND
16
ICS2
17
ICS1
18
ICS0
19
GND
⎯
Connected to VSS
20
ICLK
O
Connected to ICLK (97 pin)
Pin handling
Connected to VSS
Connected to BREAK (98 pin)
Connected to ICD3 (93 pin)
Connected to ICD2 (92 pin)
I/O
MB91461
⎯
Connected to ICD1 (91 pin)
Connected to ICD0 (90 pin)
Connected to VSS
Connected to ICS2 (96 pin)
O
Connected to ICS1 (95 pin)
Connected to ICS0 (94 pin)
MB91460 Series
Handling of dedicated pin for DSU4 (ICE) in mass production
Handling of dedicated pin for DSU4 (ICE) in mass production
MB91461 pin no.
Pin name
93 to 90
ICD3 to ICD0
Open
96 to 94
ICS2 to ICS0
Open
97
ICLK
Open
98
BREAK
Open
130
TRST
Pin handling
Connected to INIT (131 pin: external reset input pin)
Connection handling of the reset pin (TRST) for development tool (DSU) in mass production
INIT
Reset input
MB91461
TRST
Since the reset pin (TRST) for development tool is the input pin supporting 3V/5V, it can be connected to INIT
pin directly.
19
MB91460 Series
■ BLOCK DIAGRAM
TRST
BREAK
ICS0 to ICS2
ICD0 to ICD3
ICLK
DSU
(debug
support)
FR60 CPU
core
Bit search
Instruction
cache 4 Kbytes
I-bus
32
RAM
64 Kbytes
D-bus
32
CAN
2 channels
RX0,RX1
TX0,TX1
32↔ 16
bus adapter
External
bus
interface
Bus converter
SYSCLK
AS
RD
WR0
WR1
BRQ
BGRNT
CS0 to CS4
A23 to A00
D31 to D16
DREQ0
DACK0
DEOP0
IOWR
IORD
DMAC
5 channels
R-bus
16
Interrupt controller
Clock control
TRG0 to TRG3
PPG0 to PPG7
PPG
8 channels
TIN0 to TIN3
TOT0 to TOT3
Reload timer
5 channels
FRCK0 to FRCK3
ICU0 to ICU3
Free-run timer
4 channels
Input capture
4 channels
External interrupt
16 channels
PORT interface
NMI
INT0 to INT15
PORT
LIN-UART 7 channels
(including BGR)
SIN0 to SIN6
SOT0 to SOT6
SCK0 to SCK6
I2C
3 channels
SDA0 to SDA2
SCL0 to SCL2
RTC
OCU0 to OCU3
: Pin for development tool
20
Output compare
4 channels
A/D converter
13 channels
AN0 to AN12
ATG
MB91460 Series
■ CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced
instructions for embedded applications.
1. Features
• Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
• General-purpose registers: 32-bit × 16 registers
• 4 Gbytes linear memory space
• Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
• Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode/stop mode/shutdown mode
21
MB91460 Series
2. Internal architecture
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of
each other.
A 32-bit ↔ 16-bit bus adapter is connected to the 32-bit bus (D-bus) to provide an interface between the CPU
and peripheral resources.
A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
The following figure shows the internal architecture structure.
DSU
(debug support)
FR60 CPU
core
Bit search
Instruction
cache RAM
D-bus
32
I-bus
32
RAM
64 Kbytes
Bus converter
CAN
2 channels
32 ↔ 16
bus adapter
R-bus
16
External
bus
interface
DMAC
5 channels
Peripheral
resource
22
MB91460 Series
3. Programming model
• Basic programming model
32 bits
Initial value
R0
XXXX XXXXH
R1
...
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply and divide result
registers
MDH
ILM
SCR
CCR
MDL
23
MB91460 Series
4. Registers
• General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
R1
...
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation
operations and as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
• PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits
is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
24
bit 10 bit 8 bit 7
SCR
bit 0
CCR
MB91460 Series
• CCR (Condition Code Register)
bit 7
S
: Stack flag
I
: Interrupt enable flag
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
S
I
N
Z
V
C
Initial value
- - 00XXXXB
N : Negative enable flag
Z
: Zero flag
V
: Overflow flag
C : Carry flag
• SCR (System Condition Register)
bit 10 bit 9
D1
bit 8
D0
Initial value
T
XX0B
Flag for step multiplication (D1, D0)
This flag stores interim data during execution of step multiplication.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
• ILM
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
• PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
25
MB91460 Series
• TBR (Table Base Register)
bit 31
bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
• RP (Return Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
• USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
• Multiply & divide registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
26
MB91460 Series
■ MODE SETTING
In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating
mode.
1. Mode pins
The three pins MD2, MD1, MD0 are used to specify the mode vector fetch related settings.
Settings other than shown in the table are not allowed.
Mode pins*
Reset vector
Mode name
access area
MD2 MD1 MD0
Remarks
0
0
0
Internal ROM mode vector
Internal
Not allowed
0
0
1
External ROM mode vector
External
Bus width is set by mode register.
* : Always use MD3 with “0”.
Note : The FR family does not support the external mode vector fetch using multiplex bus.
2. Mode register (MODR)
The data written to the mode register using mode vector fetch is called mode data.
After the mode register (MODR) is set, the device operates according to the operation mode set in this register.
The mode register is set by all reset sources. User programs cannot write data to the mode register.
Rewriting is allowed in the emulator mode. In this case, use an 8-bit length data transfer instruction.
A 16/32-bit length transfer instruction cannot be used for writing.
Description of the mode register is given below.
[Mode register description]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
0
0
ROMA
WTH1
WTH0
Initial value
XXXXXXXXB
Operation mode setting bits
[bit7 to bit3] Reserved bits
Be sure to set these bits to “00000B”.
Operation is not guaranteed when any value other than “00000B” is set.
[bit2] ROMA (Internal enable bit)
The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.
ROMA
Function
Remarks
0
External ROM mode
Internal F-bus RAM becomes valid. The internal ROM area
(40000H to FFFFFH) is used as an external area.
1
Internal ROM mode
Internal F-bus RAM and F-bus ROM become valid.
Note : Use ”0” in MB91461.
27
MB91460 Series
[bit1, bit0] WTH1, WTH0 (Bus width setting bits)
These bits are used to set the bus width to be used in the external bus mode.
When the operation mode is the external bus mode, these values are set in bits BW1 and BW0 in AMD0 (CS0
area).
WTH1
WTH0
Function
Remarks
28
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
⎯
Setting disabled
1
1
Single chip mode
Setting disabled
MB91460 Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access : 000H to 0FFH
Half word access : 000H to 1FFH
Word data access : 000H to 3FFH
2. Memory map
MB91461
External ROM
External bus mode
0000 0000H
I/O
Direct addressing area
Refer to “■ I/O MAP”.
0000 0400H
I/O
0000 8000H
0000 BFFFH
BI-ROM
I/O
0001 0000H
0002 0000H
Instruction cache
0003 0000H
0004 0000H
F-bus RAM
External area
0010 0000H
Reset/vector mode
External area
FFFF FFFFH
: Access prohibited
Each mode is set depending on the mode vector fetch after INIT is negated. (For details on
mode settings, refer to “■ MODE SETTING”.)
29
MB91460 Series
■ I/O MAP
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]B
XXXXXXXX
PDR1 [R/W]B
XXXXXXXX
PDR2 [R/W]B
XXXXXXXX
PDR3 [R/W]B
XXXXXXXX
Block
T-unit
port data register
Read/write attribute, Access unit
(B: Byte, H: Half word, W: Word)
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1
becomes the MSB side of the data.)
Note : Initial values of register bits are represented as follows:
“ 1 ” : Initial value “ 1 ”
“ 0 ” : Initial value “ 0 ”
“ X ” : Initial value “ undefined ”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
30
MB91460 Series
Address
Register
0
1
2
000000H
Reserved
000004H
Reserved
000008H
Reserved
00000CH
3
Block
PDR14 [R/W] B,H PDR15 [R/W] B,H
----XXXX
----XXXX
Reserved
000010H
PDR16 [R/W] B,H PDR17 [R/W] B,H PDR18 [R/W] B,H PDR19 [R/W] B,H
X------XXXXXXXX
-----XXX
-XXX-XXX
000014H
PDR20 [R/W] B,H PDR21 [R/W] B,H PDR22 [R/W] B,H PDR23 [R/W] B,H
-XXX-XXX
-XXX-XXX
XXXXXX-X
-X-XXXXX
000018H
PDR24 [R/W] B,H
XXXXXXXX
00001CH
PDR28 [R/W] B,H PDR29 [R/W] B,H
---XXXXX
XXXXXXXX
R-bus port data
register
Reserved
Reserved
000020H
Reserved
000024H
to
00002CH
Reserved
Reserved
000030H
EIRR0 [R/W] B
00000000
ENIR0 [R/W] B
00000000
ELVR0 [R/W] B,H
00000000 00000000
External interrupt
(INT0 to INT7)
NMI
000034H
EIRR1 [R/W] B
00000000
ENIR1 [R/W] B
00000000
ELVR1 [R/W] B,H
00000000 00000000
External interrupt
(INT 8 to INT15 )
000038H
DICR [R/W] B
-------0
HRCL [R/W] B
0--11111
Reserved
Delay interrupt
00003CH
Reserved
000040H
SCR00 [R/W,W]
B,H,W
00000000
SMR00 [R/W,W]
B,H,W
00000000
000044H
ESCR00 [R/W]
B,H
00000X00
ECCR00
[R/W,R,W] B,H
-00000XX
000048H
SCR01 [R/W,W]
B,H,W
00000000
SMR01 [R/W,W]
B,H,W
00000000
00004CH
ESCR01 [R/W]
B,H
00000X00
ECCR01
[R/W,R,W] B,H
-00000XX
Reserved
SSR00 [R/W,R]
B,H,W
00001000
RDR00/TDR00
[R/W] B,H,W
00000000
UART (LIN) 0
Reserved
SSR01 [R/W,R]
B,H,W
00001000
RDR01/TDR01
[R/W] B,H,W
00000000
LIN-UART 1
Reserved
(Continued)
31
MB91460 Series
Address
Register
0
1
2
3
000050H
SCR02 [R/W,W]
B,H,W
00000000
SMR02 [R/W,W]
B,H,W
00000000
SSR02 [R/W,R]
B,H,W
00001000
RDR02/TDR02
[R/W] B,H,W
00000000
000054H
ESCR02
[R/W]B,H
00000X00
ECCR02
[R/W,R,W] B,H
-00000XX
000058H
SCR03 [R/W,W]
B,H,W
00000000
SMR03 [R/W,W]
B,H,W
00000000
00005CH
ESCR03
[R/W] B,H
00000X00
ECCR03
[R/W,R,W] B,H
-00000XX
000060H
SCR04 [R/W,W]
B,H,W
00000000
SMR04 [R/W,W]
B,H,W
00000000
SSR04 [R/W,R]
B,H,W
00001000
RDR04/TDR04
[R/W] B,H,W
00000000
000064H
ESCR04 [R/W]
B,H,W
00000X00
ECCR04
[R/W,R,W] B,H,W
-00000XX
FSR04 [R]
B,H,W
---00000
FCR04 [R/W]
B,H,W
0001-000
000068H
SCR05 [R/W,W]
B,H,W
00000000
SMR05 [R/W,W]
B,H,W
00000000
SSR05 [R/W,R]
B,H,W
00001000
RDR05/TDR05
[R/W] B,H,W
00000000
00006CH
ESCR05 [R/W]
B,H,W
00000X00
ECCR05
[R/W,R,W] B,H,W
-00000XX
FSR05 [R]
B,H,W
---00000
FCR05 [R/W]
B,H,W
0001-000
000070H
SCR06 [R/W,W]
B,H,W
00000000
SMR06 [R/W,W]
B,H,W
00000000
SSR06 [R/W,R]
B,H,W
00001000
RDR06/TDR06
[R/W] B,H,W
00000000
000074H
ESCR06 [R/W]
B,H,W
00000X00
ECCR06
[R/W,R,W] B,H,W
-00000XX
FSR06 [R]
B,H,W
---00000
FCR06 [R/W]
B,H,W
0001-000
000078H
to
00007CH
Block
LIN-UART 2
Reserved
SSR03 [R/W,R]
B,H,W
00001000
RDR03/TDR03
[R/W] B,H,W
00000000
LIN-UART 3
Reserved
Reserved
LIN-UART 4
LIN-UART 5
LIN-UART 6
Reserved
000080H
BGR100 [R/W]
B,H,W
00000000
BGR000 [R/W]
B,H,W
00000000
BGR101 [R/W]
B,H,W
00000000
BGR001 [R/W]
B,H,W
00000000
000084H
BGR102 [R/W]
B,H,W
00000000
BGR002 [R/W]
B,H,W
00000000
BGR103 [R/W]
B,H,W
00000000
BGR003 [R/W]
B,H,W
00000000
000088H
BGR104 [R/W]
B,H,W
00000000
BGR004 [R/W]
B,H,W
00000000
BGR105 [R/W]
B,H,W
00000000
BGR005 [R/W]
B,H,W
00000000
Baud rate
generator UART
(LIN)
0 to 6
(Continued)
32
MB91460 Series
Address
00008CH
Register
0
1
BGR106 [R/W]
B,H,W
00000000
BGR006 [R/W]
B,H,W
00000000
000090H
to
0000CCH
0000D0H
0000D4H
2
IBCR0 [R/W] B,H
00000000
IBSR0 [R] B,H
00000000
ITMKH0 [R/W] B,H ITMKL0 [R/W] B,H
00----11
11111111
Reserved
IDAR0 [R/W] B,H
00000000
0000DCH
IBCR1 [R/W] B,H
00000000
IBSR1 [R] B,H
00000000
0000E4H
ITMKH1 [R/W] B,H ITMKL1 [R/W] B,H
00----11
11111111
Reserved
IDAR1 [R/W] B,H
00000000
0000E8H
to
0000FCH
Block
Baud rate
generator UART
(LIN)
0 to 6
Reserved
Reserved
0000D8H
0000E0H
3
Reserved
ITBAH0 [R/W] B,H ITBAL0 [R/W] B,H
------00
00000000
ISMK0 [R/W] B,H
01111111
ISBA0 [R/W] B,H
-0000000
ICCR0 [R/W] B
-0011111
Reserved
I2C 0
ITBAH1 [R/W] B,H ITBAL1 [R/W] B,H
------00
00000000
ISMK1 [R/W] B,H
01111111
ISBA1 [R/W] B,H
-0000000
ICCR1 [R/W] B
-0011111
Reserved
Reserved
I2C 1
Reserved
000100H
GCN10 [R/W] B,H
00110010 00010000
Reserved
GCN20 [R/W] B
----0000
PPG control
0 to 3
000104H
GCN11 [R/W] B,H
00110010 00010000
Reserved
GCN21 [R/W] B
----0000
PPG control
4 to 7
000108H
Reserved
000110H
PTMR00 [R] H
11111111 11111111
000114H
PDUT00 [W] H
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R] H
11111111 11111111
00011CH
PDUT01 [W] H
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R] H
11111111 11111111
000124H
PDUT02 [W] H
XXXXXXXX XXXXXXXX
Reserved
PCSR00 [W] H
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
B,H
00000000
PCNL00 [R/W]
B,H
000000-0
PPG 0
PCSR01 [W] H
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
B,H
00000000
PCNL01 [R/W]
B,H
000000-0
PPG 1
PCSR02 [W] H
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
B,H
00000000
PCNL02 [R/W]
B,H
000000-0
PPG 2
(Continued)
33
MB91460 Series
Address
Register
0
1
000128H
PTMR03 [R] H
11111111 11111111
00012CH
PDUT03 [W] H
XXXXXXXX XXXXXXXX
000130H
PTMR04 [R] H
11111111 11111111
000134H
PDUT04 [W] H
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R] H
11111111 11111111
00013CH
PDUT05 [W] H
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R] H
11111111 11111111
000144H
PDUT06 [W] H
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R] H
11111111 11111111
00014CH
PDUT07 [W] H
XXXXXXXX XXXXXXXX
000170H
to
00017CH
000180H
2
3
PCSR03 [W] H
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
B,H
00000000
PCNL03 [R/W]
B,H
000000-0
PPG 3
PCSR04 [W] H
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
B,H
00000000
PCNL04 [R/W]
B,H
000000-0
PPG 4
PCSR05 [W] H
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
B,H
00000000
PCNL05 [R/W]
B,H
000000-0
PPG 5
PCSR06 [W] H
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
B,H
00000000
PCNL06 [R/W]
B,H
000000-0
PGG 6
PCSR07 [W] H
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
B,H
00000000
PCNL07 [R/W]
B,H
000000-0
Reserved
Reserved
Block
ICS01 [R/W] B
00000000
PPG 7
Reserved
Reserved
ICS23 [R/W] B
00000000
000184H
IPCP0 [R] H
XXXXXXXX XXXXXXXX
IPCP1 [R] H
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R] H
XXXXXXXX XXXXXXXX
IPCP3 [R] H
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
11101100 00001100
OCS23 [R/W]
11101100 00001100
000190H
OCCP0 [R/W] H
XXXXXXXX XXXXXXXX
OCCP1 [R/W] H
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W] H
XXXXXXXX XXXXXXXX
OCCP3 [R/W] H
XXXXXXXX XXXXXXXX
Input capture
0 to 3
Output compare
0 to 3
(Continued)
34
MB91460 Series
Address
Register
0
1
000198H
to
00019CH
2
3
Reserved
Reserved
0001A0H
ADERH [R/W] B,H,W
00000000 00000000
0001A4H
ADCS1 [R/W] B,H ADCS0 [R/W] B,H
00000000
00000000
0001A8H
ADCT1 [R/W] B,H ADCT0 [R/W] B,H ADSCH [R/W] B,H ADECH [R/W] B,H
00010000
00101100
---00000
---00000
0001ACH
Reserved
0001B0H
Reserved
0001B8H
TMRLR1 [W] H
XXXXXXXX XXXXXXXX
0001BCH
Reserved
0001C0H
TMRLR2 [W] H
XXXXXXXX XXXXXXXX
0001C4H
Reserved
0001C8H
TMRLR3 [W] H
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
to
0001E4H
0001E8H
ADERL [R/W] B,H,W
00000000 00000000
ADCR1 [R] B,H
000000XX
TMRLR0 [W] H
XXXXXXXX XXXXXXXX
0001B4H
ADCR0 [R] B,H
XXXXXXXX
A/D converter
Reserved
TMR0 [R] H
XXXXXXXX XXXXXXXX
TMCSRC0 [R/W]
B,H
---00000
TMCSRC0 [R/W]
B,H
0-000000
TMR1 [R] H
XXXXXXXX XXXXXXXX
TMCSRC1 [R/W]
B,H
---00000
TMCSRC1 [R/W]
B,H
0-000000
TMR2 [R] H
XXXXXXXX XXXXXXXX
TMCSRC2 [R/W]
B,H
---00000
TMCSRC2 [R/W]
B,H
0-000000
TMR3 [R] H
XXXXXXXX XXXXXXXX
TMCSRC3 [R/W]
B,H
---00000
TMCSRC3 [R/W]
B,H
0-000000
Reserved
TMRLR7 [W] H
XXXXXXXX XXXXXXXX
Block
Reload timer 0
(PPG 0, 1)
Reload timer 1
(PPG 2, 3)
Reload timer 2
(PPG 4, 5)
Reload timer 3
(PPG 6, 7)
Reserved
TMR7 [R] H
XXXXXXXX XXXXXXXX
0001ECH
Reserved
TMCSRC7 [R/W]
B,H
---00000
0001F0H
TCDT0 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TMCSRC7 [R/W]
B,H
0-000000
TCCS0 [R/W]
-0000000
Reload timer 7
(A/D converter)
Free-run timer 0
(ICU 0, 1)
(Continued)
35
MB91460 Series
Address
Register
0
1
2
3
Block
0001F4H
TCDT1 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
-0000000
Free-run timer 1
(ICU 2, 3)
0001F8H
TCDT2 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
-0000000
Free-run timer 2
(OCU 0, 1)
0001FCH
TCDT3 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
-0000000
Free-run timer 3
(OCU 2, 3)
000200H
DMACA0 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B,H,W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B,H,W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
B,H,W
00--0000
DMAC
Reserved
000244H
to
000254H
Reserved
000258H
to
000364H
Reserved
Reserved
(Continued)
36
MB91460 Series
Address
000368H
00036CH
000370H
Register
0
1
2
IBCR2 [R/W] B,H
00000000
IBSR2 [R] B,H
00000000
3
ITBAH2 [R/W] B,H ITBAL2 [R/W] B,H
------00
00000000
ITMKH2 [R/W] B,H ITMKL2 [R/W] B,H ISMK2 [R/W] B,H
00----11
11111111
01111111
ISBA2 [R/W] B,H
-0000000
IDAR2 [R/W] B,H
00000000
Reserved
Reserved
Block
ICCR2 [R/W] B
-0011111
000374H
to
0003BCH
Reserved
0003C0H
Reserved
I2C 2
Reserved
0003C4H
ISIZE [R/W] B
------11
Reserved
Reserved
0003D0H
0003E4H
Instruction cache
Reserved
ICHRC [R/W] B
0-000000
Reserved
0003E8H
to
0003ECH
Reserved
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
Instruction cache
Reserved
Bit search module
Reserved
000440H
ICR00 [R/W]
B,H,W
---11111
ICR01 [R/W]
B,H,W
---11111
ICR02 [R/W]
B,H,W
---11111
ICR03 [R/W]
B,H,W
---11111
000444H
ICR04 [R/W]
B,H,W
---11111
ICR05 [R/W]
B,H,W
---11111
ICR06 [R/W]
B,H,W
---11111
ICR07 [R/W]
B,H,W
---11111
000448H
ICR08 [R/W]
B,H,W
---11111
ICR09 [R/W]
B,H,W
---11111
Reserved
ICR11 [R/W]
B,H,W
---11111
00044CH
ICR12 [R/W]
B,H,W
---11111
ICR13 [R/W]
B,H,W
---11111
Interrupt
controller
Reserved
(Continued)
37
MB91460 Series
Address
Register
0
1
2
3
000450H
ICR16 [R/W]
B,H,W
---11111
000454H
ICR20 [R/W]
B,H,W
---11111
ICR21 [R/W]
B,H,W
---11111
ICR22 [R/W]
B,H,W
---11111
ICR23 [R/W]
B,H,W
---11111
000458H
Reserved
ICR25 [R/W]
B,H,W
---11111
ICR26 [R/W]
B,H,W
---11111
ICR27 [R/W]
B,H,W
---11111
00045CH
Reserved
ICR29 [R/W]
B,H,W
---11111
000468H
Reserved
Reserved
Reserved
Reserved
00046CH
000470H
ICR19 [R/W]
B,H,W
---11111
Reserved
000460H
000464H
ICR38 [R/W]
B,H,W
---11111
ICR39 [R/W]
B,H,W
---11111
ICR42 [R/W]
B,H,W
---11111
ICR43 [R/W]
B,H,W
---11111
Interrupt
controller
Reserved
ICR48 [R/W]
B,H,W
---11111
ICR49 [R/W]
B,H,W
---11111
000474H
ICR50 [R/W]
B,H,W
---11111
ICR51 [R/W]
B,H,W
---11111
Reserved
000478H
Reserved
ICR58 [R/W]
B,H,W
---11111
ICR59 [R/W]
B,H,W
---11111
00047CH
Reserved
ICR62 [R/W]
B,H,W
---11111
ICR63 [R/W]
B,H,W
---11111
STCR [R/W]
B,H,W
00110011
TBCR [R/W]
B,H,W
X0000X00
CTBR [W] B,H,W
XXXXXXXX
WPR [W] B,H,W
XXXXXXXX
DIVR0 [R/W]
B,H,W
00000011
DIVR1 [R/W]
B,H,W
00000000
000480H
RSRR [R/W]
B,H,W
10000000
000484H
CLKR [R/W]
B,H,W
00000000
000488H
Block
Reserved
Clock control
Reserved
(Continued)
38
MB91460 Series
Address
00048CH
Register
0
1
2
PLLDIVM [R/W]
B,H
---00000
PLLDIVN [R/W]
B,H
---00000
Reserved
000490H
Reserved
000494H
to
00049CH
Reserved
Reserved
0004A4H
Reserved
0004A8H
WTHR [R/W] B,H
---XXXXX
WTCER [R/W] B,H
------00
PLL interface
WTCR [R/W] B,H
00000000 000-00-0
WTBR [R/W] B, B,H
---XXXXX XXXXXXXX XXXXXXXX
WTMR [R/W] B,H
--XXXXXX
0004ACH
to
0004BCH
WTSR [R/W] B
--XXXXXX
CANPRE [R/W]
B,H
00000000
Reserved
CAN
(clock control)
Reserved
HWDCS [R/W,W]
B
00011000
Reserved
OSCR [R/W] B,H
00---000
Reserved
0004CCH
Reserved
0004D0H
Reserved
Real-time clock
Reserved
Reserved
0004C4H
0004C8H
Block
Reserved
0004A0H
0004C0H
3
Hardware
watchdog
Interval timer
Reserved
0004D4H
0004D8H
SHDE [R/W] B
0-------
Reserved
EXTE [R/W] B,H
00000000
EXTLV [R/W] B,H
00000000 00000000
0004DCH
to
00063CH
EXTF [R/W] B,H
00000000
Reserved
Reserved
Shutdown
controller
Reserved
000640H
ASR0 [R/W] B,H,W
00000000 00000000
ACR0*2 [R/W] B,H,W
1111XX00 00000000
000644H
ASR1 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR1 [R/W] B,H,W
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR2 [R/W] B,H,W
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W] B,H,W
XXXXXXXX XXXXXXXX
ACR3 [R/W] B,H,W
XXXXXXXX XXXXXXXX
External bus
(Continued)
39
MB91460 Series
Address
000650H
Register
0
1
2
ASR4 [R/W] B,H,W
XXXXXXXX XXXXXXXX
3
ACR4 [R/W] B,H,W
XXXXXXXX XXXXXXXX
000654H
Reserved
000658H
Reserved
00065CH
Reserved
000660H
AWR0 [R/W] B,H,W
01111111 11111011
AWR1 [R/W] B,H,W
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W] B,H,W
XXXXXXXX XXXXXXXX
AWR3 [R/W] B,H,W
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W] B,H,W
XXXXXXXX XXXXXXXX
Reserved
00066CH
Reserved
000670H
Reserved
000674H
Reserved
000678H
IOWR0 [R/W]
B,H,W
XXXXXXXX
IOWR1 [R/W]
B,H,W
XXXXXXXX
00067CH
000680H
CSER [R/W]
B,H,W
00000001
CHER [R/W]
B,H,W
11111111
Reserved
MODR [W] B
XXXXXXXX
Reserved
Reserved
000800H
to
000CFCH
Reserved
000D00H
Reserved
000D04H
Reserved
000D08H
Reserved
Reserved
PDRD16 [R] B,H
X-------
PDRD17 [R] B,H
XXXXXXXX
TCR [R/W]*3
B,H,W
0000XXXX
Reserved
000688H
to
0007F8H
000D10H
Reserved
Reserved
Reserved
000D0CH
External bus
IOWR2 [R/W]
B,H,W
XXXXXXXX
000684H
0007FCH
Block
Mode register
Reserved
PDRD14 [R] B,H
----XXXX
PDRD15 [R] B,H
----XXXX
PDRD18 [R] B,H
-----XXX
PDRD19 [R] B,H
-XXX-XXX
R-bus port data
direct read register
(Continued)
40
MB91460 Series
Address
Register
0
1
2
3
000D14H
PDRD20 [R] B,H
-XXX-XXX
PDRD21 [R] B,H
-XXX-XXX
PDRD22 [R] B,H
XXXXXX-X
PDRD23 [R] B,H
-X-XXXXX
000D18H
PDRD24 [R] B,H
XXXXXXXX
000D1CH
PDRD28 [R] B,H
---XXXXX
Reserved
PDRD29 [R] B,H
XXXXXXXX
Reserved
000D20H
Reserved
000D24H
to
000D3CH
Reserved
000D40H
Reserved
000D44H
Reserved
000D48H
Reserved
000D4CH
DDR14 [R/W] B,H DDR15 [R/W] B,H
----0000
----0000
Reserved
DDR16 [R/W] B,H DDR17 [R/W] B,H DDR18 [R/W] B,H DDR19 [R/W] B,H
0------00000000
-----000
-000-000
000D54H
DDR20 [R/W] B,H DDR21 [R/W] B,H DDR22 [R/W] B,H DDR23 [R/W] B,H
-000-000
-000-000
000000-0
-0-00000
000D58H
DDR24 [R/W] B,H
---00000
000D5CH
DDR28 [R/W] B,H DDR29 [R/W] B,H
---00000
00000000
Reserved
Reserved
000D64H
to
000D7CH
Reserved
000D80H
Reserved
000D84H
Reserved
000D88H
Reserved
Reserved
PFR16 [R/W] B,H
0-------
R-bus port
direction register
Reserved
000D60H
000D90H
R-bus port data
direct read register
Reserved
000D50H
000D8CH
Block
PFR17 [R/W] B,H
00000000
Reserved
R-bus port function
register
PFR14 [R/W] B,H
----0000
PFR15 [R/W] B,H
----0000
PFR18 [R/W] B,H
-----000
PFR19 [R/W] B,H
-000-000
(Continued)
41
MB91460 Series
Address
Register
0
1
2
3
000D94H
PFR20 [R/W] B,H
-000-000
PFR21 [R/W] B,H
-000-000
PFR22 [R/W] B,H
000000-0
PFR23 [R/W] B,H
-0-00000
000D98H
PFR24 [R/W] B,H
00000000
Reserved
Reserved
Reserved
000D9CH
PFR28 [R/W] B,H
---00000
PFR29 [R/W] B,H
00000000
Reserved
Reserved
000DA0H
Reserved
000DA4H
to
000DBCH
Reserved
000DC0H
Reserved
000DC4H
Reserved
000DC8H
Reserved
000DCCH
Reserved
Block
R-bus port function
register
Reserved
EPFR14 [R/W]
B,H
----0000
EPFR15 [R/W]
B,H
----0000
000DD0H
EPFR16 [R/W]
B,H
0-------
EPFR17 [R/W]
B,H
00000000
EPFR18 [R/W]
B,H
-----000
EPFR19 [R/W]
B,H
-000-000
000DD4H
EPFR20 [R/W]
B,H
-000-000
EPFR21 [R/W]
B,H
-000-000
EPFR22 [R/W]
B,H
000000-0
EPFR23 [R/W]
B,H
-0-00000
000DD8H
EPFR24 [R/W]
B,H
00000000
000DDCH
EPFR28 [R/W]
B,H
---00000
R-bus expansion
port function
register
Reserved
EPFR29 [R/W]
B,H
00000000
000DE0H
Reserved
000DE4H
to
000DFCH
Reserved
000E00H
to
000E3CH
Reserved
Reserved
Reserved
(Continued)
42
MB91460 Series
Address
Register
0
1
2
000E40H
Reserved
000E44H
Reserved
000E48H
Reserved
000E4CH
3
PILR14 [R/W] B,H PILR15 [R/W] B,H
----0000
----0000
Reserved
000E50H
PILR16 [R/W] B,H PILR17 [R/W] B,H PILR18 [R/W] B,H PILR19 [R/W] B,H
0------00000000
-----000
-000-000
000E54H
PILR20 [R/W] B,H PILR21 [R/W] B,H PILR22 [R/W] B,H PILR23 [R/W] B,H
-000-000
-000-000
000000-0
-0-00000
000E58H
PILR24 [R/W] B,H
00000000
000E5CH
PILR28 [R/W] B,H PILR29 [R/W] B,H
---00000
00000000
Reserved
Reserved
000EC0H
Reserved
000EC4H
Reserved
000EC8H
Reserved
Reserved
PPER14 [R/W]
B,H
----0000
PPER15 [R/W]
B,H
----0000
000ED0H
PPER16 [R/W]
B,H
0-------
PPER17 [R/W]
B,H
00000000
PPER18 [R/W]
B,H
-----000
PPER19 [R/W]
B,H
-000-000
000ED4H
PPER20 [R/W]
B,H
-000-000
PPER21 [R/W]
B,H
-000-000
PPER22 [R/W]
B,H
000000-0
PPER23 [R/W]
B,H
-0-00000
000ED8H
PPER24 [R/W]
B,H
00000000
000EDCH
PPER28 [R/W]
B,H
---00000
000EE0H
R-bus pin input
level selection
register
Reserved
000E60H
to
000EBCH
000ECCH
Block
R-bus port
pull-up/pull-down
enable register
Reserved
PPER29 [R/W]
B,H
00000000
Reserved
Reserved
(Continued)
43
MB91460 Series
Address
Register
0
1
2
000EE4H
to
000EFCH
Reserved
000F00H
Reserved
000F04H
Reserved
000F08H
Reserved
000F0CH
Reserved
3
Block
Reserved
PPCR14 [R/W]
B,H
----1111
PPCR15 [R/W]
B,H
----1111
000F10H
PPCR16 [R/W]
B,H
1-------
PPCR17 [R/W]
B,H
-111-111
PPCR18 [R/W]
B,H
111111-1
PPCR19 [R/W]
B,H
-1-11111
000F14H
PPCR20 [R/W]
B,H
-111-111
PPCR21 [R/W]
B,H
-111-111
PPCR22 [R/W]
B,H
111111-1
PPCR23 [R/W]
B,H
-1-11111
000F18H
PPCR24 [R/W]
B,H
---11111
000F1CH
PPCR28 [R/W]
B,H
---11111
R-bus port
pull-up/pull-down
control register
Reserved
PPCR29 [R/W]
B,H
11111111
Reserved
000F20H
Reserved
000F24H
to
000F3CH
Reserved
001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
DMAC
(Continued)
44
MB91460 Series
Address
Register
0
1
2
3
001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
007FFCH
Reserved
008000H
to
00BFFCH
Reserved
Block
DMAC
Reserved
00C000H
CTRLR0 [R/W] B,H
00000000 00000001
STATR0 [R/W] B,H
00000000 00000000
00C004H
ERRCNT0 [R] B,H,W
00000000 00000000
BTR0 [R/W] B,H,W
00100011 00000001
00C008H
INTR0 [R]B,H,W
00000000 00000000
TESTR0 [R/W]B,H,W
00000000 X0000000
00C00CH
BRPE0 [R/W]B,H,W
00000000 00000000
Reserved
00C010H
IF1CREQ0 [R/W] B,H
00000000 00000001
IF1CMSK0 [R/W] B,H
00000000 00000000
00C014H
IF1MSK20 [R/W] B,H,W
11111111 11111111
IF1MSK10 [R/W] B,H,W
11111111 11111111
00C018H
IF1ARB20 [R/W] B,H,W
00000000 00000000
IF1ARB10 [R/W] B,H,W
00000000 00000000
00C01CH
IF1MCTR0 [R/W] B,H,W
00000000 00000000
Reserved
00C020H
IF1DTA10 [R/W] B,H,W
00000000 00000000
IF1DTA20 [R/W] B,H,W
00000000 00000000
00C024H
IF1DTB10 [R/W] B,H,W
00000000 00000000
IF1DTB20 [R/W]B,H,W
00000000 00000000
00C028H
to
00C02CH
CAN 0 control
register
CAN 0 IF 1
register
Reserved
00C030H
IF1DTA20 [R/W] B,H,W
00000000 00000000
IF1DTA10 [R/W] B,H,W
00000000 00000000
00C034H
IF1DTB20 [R/W] B,H,W
00000000 00000000
IF1DTB10 [R/W] B,H,W
00000000 00000000
(Continued)
45
MB91460 Series
Address
Register
0
1
00C038H
to
00C03CH
2
3
CAN 0 IF 1
register
Reserved
00C040H
IF2CREQ0 [R/W] B,H
00000000 00000001
IF2CMSK0 [R/W] B,H
00000000 00000000
00C044H
IF2MSK20 [R/W] B,H,W
11111111 11111111
IF2MSK10 [R/W] B,H,W
11111111 11111111
00C048H
IF2ARB20 [R/W] B,H,W
00000000 00000000
IF2ARB10 [R/W] B,H,W
00000000 00000000
00C04CH
IF2MCTR0 [R/W] B,H,W
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W] B,H,W
00000000 00000000
IF2DTA20 [R/W] B,H,W
00000000 00000000
00C054H
IF2DTB10 [R/W] B,H,W
00000000 00000000
IF2DTB20 [R/W] B,H,W
00000000 00000000
00C058H
to
00C05CH
IF2DTA20 [R/W] B,H,W
00000000 00000000
IF2DTA10 [R/W] B,H,W
00000000 00000000
00C064H
IF2DTB20 [R/W] B,H,W
00000000 00000000
IF2DTB10 [R/W] B,H,W
00000000 00000000
00C068H
to
00C07CH
Reserved
TREQR20 [R] B,H,W
00000000 00000000
TREQR10 [R] B,H,W
00000000 00000000
00C084H
Reserved
00C088H
Reserved
00C08CH
Reserved
00C090H
CAN 0 IF 2
register
Reserved
00C060H
00C080H
Block
NEWDT20 [R] B,H,W
00000000 00000000
NEWDT10 [R] B,H,W
00000000 00000000
00C094H
Reserved
00C098H
Reserved
00C09CH
Reserved
CAN 0
status flag
(Continued)
46
MB91460 Series
Address
00C0A0H
Register
0
1
2
INTPND20 [R] B,H,W
00000000 00000000
Block
INTPND10 [R] B,H,W
00000000 00000000
00C0A4H
Reserved
00C0A8H
Reserved
00C0ACH
Reserved
00C0B0H
3
MSGVAL20 [R] B,H,W
00000000 00000000
MSGVAL10 [R] B,H,W
00000000 00000000
00C0B4H
Reserved
00C0B8H
Reserved
00C0BCH
Reserved
00C0C0H
to
00C0FCH
Reserved
00C100H
CTRLR1 [R/W] B,H
00000000 00000001
STATR1 [R/W] B,H
00000000 00000000
00C104H
ERRCNT1 [R] B,H,W
00000000 00000000
BTR1 [R/W] B,H,W
00100011 00000001
00C108H
INTR1 [R] B,H,W
00000000 00000000
TESTR1 [R/W] B,H,W
00000000 X0000000
00C10CH
BRPE1 [R/W] B,H,W
00000000 00000000
Reserved
00C110H
IF1CREQ1 [R/W] B,H
00000000 00000001
IF1CMSK1 [R/W] B,H
00000000 00000000
00C114H
IF1MSK21 [R/W] B,H,W
11111111 11111111
IF1MSK11 [R/W] B,H,W
11111111 11111111
00C118H
IF1ARB21 [R/W] B,H,W
00000000 00000000
IF1ARB11 [R/W] B,H,W
00000000 00000000
00C11CH
IF1MCTR1 [R/W] B,H,W
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W] B,H,W
00000000 00000000
IF1DTA21 [R/W] B,H,W
00000000 00000000
00C124H
IF1DTB11 [R/W] B,H,W
00000000 00000000
IF1DTB21 [R/W] B,H,W
00000000 00000000
CAN 0
status flag
CAN 1
control register
CAN 1 IF 1
register
(Continued)
47
MB91460 Series
Address
Register
0
1
00C128H
to
00C12CH
2
3
Reserved
00C130H
IF1DTA21 [R/W] B,H,W
00000000 00000000
IF1DTA11 [R/W] B,H,W
00000000 00000000
00C134H
IF1DTB21 [R/W] B,H,W
00000000 00000000
IF1DTB11 [R/W] B,H,W
00000000 00000000
00C138H
to
00C13CH
IF2CREQ1 [R/W]B,H
00000000 00000001
IF2CMSK1 [R/W]B,H
00000000 00000000
00C144H
IF2MSK21 [R/W]B,H,W
11111111 11111111
IF2MSK11 [R/W]B,H,W
11111111 11111111
00C148H
IF2ARB21 [R/W]B,H,W
00000000 00000000
IF2ARB11 [R/W]B,H,W
00000000 00000000
00C14CH
IF2MCTR1 [R/W]B,H,W
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W]B,H,W
00000000 00000000
IF2DTA21 [R/W]B,H,W
00000000 00000000
00C154H
IF2DTB11 [R/W]B,H,W
00000000 00000000
IF2DTB21 [R/W]B,H,W
00000000 00000000
00C158H
to
00C15CH
CAN 1 IF 2
register
Reserved
00C160H
IF2DTA21 [R/W]B,H,W
00000000 00000000
IF2DTA11 [R/W]B,H,W
00000000 00000000
00C164H
IF2DTB21 [R/W]B,H,W
00000000 00000000
IF2DTB11 [R/W]B,H,W
00000000 00000000
00C168H
to
00C17CH
00C184H
CAN 1 IF 1
register
Reserved
00C140H
00C180H
Block
Reserved
TREQR21 [R]B,H,W
00000000 00000000
TREQR11 [R]B,H,W
00000000 00000000
Reserved
00C188H
Reserved
00C18CH
Reserved
CAN 1
status flag
(Continued)
48
MB91460 Series
Address
00C190H
Register
0
1
2
NEWDT21 [R]B,H,W
00000000 00000000
Reserved
00C198H
Reserved
00C19CH
Reserved
INTPND21 [R]B,H,W
00000000 00000000
INTPND11 [R]B,H,W
00000000 00000000
00C1A4H
Reserved
00C1A8H
Reserved
00C1ACH
Reserved
00C1B0H
Block
NEWDT11 [R]B,H,W
00000000 00000000
00C194H
00C1A0H
3
MSGVAL21 [R]B,H,W
00000000 00000000
CAN 1
status flag
MSGVAL11 [R]B,H,W
00000000 00000000
00C1B4H
Reserved
00C1B8H
Reserved
00C1BCH
Reserved
00C1C0H
to
00C1FCH
Reserved
00F000H
to
00FFFCH
Reserved
010000H
to
013FFCH
Cache TAG way 1 (010000H to 0107FCH)
014000H
to
017FFCH
Cache TAG way 2 (014000H to 0147FCH)
018000H
to
01BFFCH
Cache RAM way 1 (018000H to 0187FCH)
01C000H
to
01FFFCH
Cache RAM way 2 (01C000H to 01C7FCH)
Reserved
Instruction cache
(Continued)
49
MB91460 Series
(Continued)
Address
Register
0
1
2
3
020000H
to
02FFFCH
Reserved
Reserved
030000H
to
03FFFCH
I/D-RAM: 64 Kbytes
(instruction access is 0 wait cycle, data access is 1 wait cycle)
I/D-RAM
64 Kbytes
040000H
to
07FFFCH
External memory area (256 Kbytes)
080000H
to
0BFFFCH
External memory area (256 Kbytes)
0C0000H
to
0FFFF4H
External memory area (256 Kbytes)
0FFFF8H
FMV [R]
0FFFFCH
FRV [R]
100000H
to
13FFFCH
External memory area (256 Kbytes)
140000H
to
17FFFCH
External memory area (256 Kbytes)
180000H
to
1BFFFCH
External memory area (256 Kbytes)
1C0000H
to
1FFFFCH
External memory area (256 Kbytes)
200000H
to
2FFFFCH
External memory area (1 Mbyte)
300000H
to
3FFFFCH
External memory area (1 Mbyte)
External bus
Reset vector/
mode vector
External bus
*1 : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes.
*2 : ACR0[11:10] depends on the mode vector fetch information on bus width.
*3 : TCR[3:0] INIT value = 0000, the value is kept after RST.
50
Block
MB91460 Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
number
Decimal
Interrupt level
Setting
Hexadecimal register
Offset
TBR default Resource
address
number*1
Register
address
Reset
0
00
⎯
⎯
3FCH
000FFFFCH
2
Mode vector
1
01
⎯
⎯
3F8H
000FFFF8H
3
System reserved
2
02
⎯
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
⎯
3D8H
000FFFD8H
⎯
Instruction break exception
10
0A
⎯
⎯
3D4H
000FFFD4H
⎯
Operand break trap
11
0B
⎯
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
15 (F)
fixed
15 (F)
fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
000FFFBCH
⎯
17
11
440H
3BCH
External interrupt 1
ICR00
3B8H
000FFFB8H
⎯
External interrupt 2
18
12
000FFFB4H
⎯
19
13
441H
3B4H
External interrupt 3
ICR01
3B0H
000FFFB0H
⎯
External interrupt 4
20
14
000FFFACH
⎯
21
15
442H
3ACH
External interrupt 5
ICR02
3A8H
000FFFA8H
⎯
External interrupt 6
22
16
000FFFA4H
⎯
23
17
443H
3A4H
External interrupt 7
ICR03
3A0H
000FFFA0H
⎯
External interrupt 8
24
18
000FFF9CH
⎯
25
19
444H
39CH
External interrupt 9
ICR04
398H
000FFF98H
⎯
External interrupt 10
26
1A
000FFF94H
⎯
27
1B
445H
394H
External interrupt 11
ICR05
390H
000FFF90H
⎯
External interrupt 12
28
1C
000FFF8CH
⎯
29
1D
446H
38CH
External interrupt 13
ICR06
388H
000FFF88H
⎯
External interrupt 14
30
1E
000FFF84H
⎯
31
1F
447H
384H
External interrupt 15
ICR07
380H
000FFF80H
⎯
(Continued)
51
MB91460 Series
Interrupt source
Interrupt
number
Decimal
Interrupt level
Offset
Setting
Hexadecimal register
Reload timer 0
32
20
Reload timer 1
33
21
Reload timer 2
34
22
Reload timer 3
35
23
System reserved
36
24
System reserved
37
25
System reserved
38
26
Reload timer 7
39
27
Free-run timer 0
40
28
Free-run timer 1
41
29
Free-run timer 2
42
2A
Free-run timer 3
43
2B
System reserved
44
2C
System reserved
45
2D
System reserved
46
2E
System reserved
47
2F
CAN0
48
30
CAN1
49
31
System reserved
50
32
System reserved
51
33
System reserved
52
34
System reserved
53
35
LIN-USART 0 RX
54
36
LIN-USART 0 TX
55
37
LIN-USART 1 RX
56
38
LIN-USART 1 TX
57
39
LIN-USART 2 RX
58
3A
LIN-USART 2 TX
59
3B
LIN-USART 3 RX
60
3C
LIN-USART 3 TX
61
3D
System reserved
62
3E
Delay interrupt
63
3F
Register
address
ICR08
448H
ICR09
449H
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
ICR23*3
457H
TBR default Resource
address
number*1
37CH
000FFF7CH
4
378H
000FFF78H
5
374H
000FFF74H
⎯
370H
000FFF70H
⎯
36CH
000FFF6CH
⎯
368H
000FFF68H
⎯
364H
000FFF64H
⎯
360H
000FFF60H
⎯
35CH
000FFF5CH
⎯
358H
000FFF58H
⎯
354H
000FFF54H
⎯
350H
000FFF50H
⎯
34CH
000FFF4CH
⎯
348H
000FFF48H
⎯
344H
000FFF44H
⎯
340H
000FFF40H
⎯
33CH
000FFF3CH
⎯
338H
000FFF38H
⎯
334H
000FFF34H
⎯
330H
000FFF30H
⎯
32CH
000FFF2CH
⎯
328H
000FFF28H
⎯
324H
000FFF24H
6
320H
000FFF20H
7
31CH
000FFF1CH
8
318H
000FFF18H
9
314H
000FFF14H
⎯
310H
000FFF10H
⎯
30CH
000FFF0CH
⎯
308H
000FFF08H
⎯
304H
000FFF04H
⎯
300H
000FFF00H
⎯
(Continued)
52
MB91460 Series
Interrupt source
Interrupt
number
Decimal
Setting
Hexadecimal register
System reserved*2
64
40
System reserved*2
65
41
LIN-USART 4 RX
66
42
LIN-USART 4 TX
67
43
LIN-USART 5 RX
68
44
LIN-USART 5 TX
69
45
LIN-USART 6 RX
70
46
LIN-USART 6 TX
71
47
System reserved
72
48
System reserved
73
49
I2C_0/I2C_2
74
4A
I C_1/I C_3
75
4B
System reserved
76
4C
System reserved
77
4D
System reserved
78
4E
System reserved
79
4F
System reserved
80
50
System reserved
81
51
System reserved
82
52
System reserved
83
53
System reserved
84
54
System reserved
85
55
System reserved
86
56
System reserved
87
57
System reserved
88
58
System reserved
89
59
System reserved
90
5A
System reserved
91
5B
Input capture 0
92
5C
Input capture 1
93
5D
Input capture 2
94
5E
Input capture 3
95
5F
2
2
Interrupt level
Offset
TBR default Resource
address
number*1
2FCH
000FFEFCH
⎯
2F8H
000FFEF8H
⎯
2F4H
000FFEF4H
10
2F0H
000FFEF0H
11
2ECH
000FFEECH
12
2E8H
000FFEE8H
13
2E4H
000FFEE4H
⎯
2E0H
000FFEE0H
⎯
2DCH
000FFEDCH
⎯
2D8H
000FFED8H
⎯
2D4H
000FFED4H
⎯
2D0H
000FFED0H
⎯
2CCH
000FFECCH
⎯
2C8H
000FFEC8H
⎯
2C4H
000FFEC4H
⎯
2C0H
000FFEC0H
⎯
2BCH
000FFEBCH
⎯
2B8H
000FFEB8H
⎯
2B4H
000FFEB4H
⎯
2B0H
000FFEB0H
⎯
2ACH
000FFEACH
⎯
2A8H
000FFEA8H
⎯
2A4H
000FFEA4H
⎯
2A0H
000FFEA0H
⎯
29CH
000FFE9CH
⎯
298H
000FFE98H
⎯
294H
000FFE94H
⎯
290H
000FFE90H
⎯
28CH
000FFE8CH
⎯
288H
000FFE88H
⎯
284H
000FFE84H
⎯
280H
000FFE80H
⎯
Register
address
(ICR24)
458H
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
(Continued)
53
MB91460 Series
Interrupt source
Interrupt
number
Decimal
Interrupt level
Offset
Setting
Hexadecimal register
System reserved
96
60
System reserved
97
61
System reserved
98
62
System reserved
99
63
Output compare 0
100
64
Output compare 1
101
65
Output compare 2
102
66
Output compare 3
103
67
System reserved
104
68
System reserved
105
69
System reserved
106
6A
System reserved
107
6B
System reserved
108
6C
System reserved
109
6D
System reserved
110
6E
System reserved
111
6F
PPG0
112
70
PPG1
113
71
PPG2
114
72
PPG3
115
73
PPG4
116
74
PPG5
117
75
PPG6
118
76
PPG7
119
77
System reserved
120
78
System reserved
121
79
System reserved
122
7A
System reserved
123
7B
System reserved
124
7C
System reserved
125
7D
System reserved
126
7E
System reserved
127
7F
Register
address
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47*3
46FH
ICR48
470H
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
ICR54
476H
ICR55
477H
TBR default Resource
address
number*1
27CH
000FFE7CH
⎯
278H
000FFE78H
⎯
274H
000FFE74H
⎯
270H
000FFE70H
⎯
26CH
000FFE6CH
⎯
268H
000FFE68H
⎯
264H
000FFE64H
⎯
260H
000FFE60H
⎯
25CH
000FFE5CH
⎯
258H
000FFE58H
⎯
254H
000FFE54H
⎯
250H
000FFE50H
⎯
24CH
000FFE4CH
⎯
248H
000FFE48H
⎯
244H
000FFE44H
⎯
240H
000FFE40H
⎯
23CH
000FFE3CH
15
238H
000FFE38H
⎯
234H
000FFE34H
⎯
230H
000FFE30H
⎯
22CH
000FFE2CH
⎯
228H
000FFE28H
⎯
224H
000FFE24H
⎯
220H
000FFE20H
⎯
21CH
000FFE1CH
⎯
218H
000FFE18H
⎯
214H
000FFE14H
⎯
210H
000FFE10H
⎯
20CH
000FFE0CH
⎯
208H
000FFE08H
⎯
204H
000FFE04H
⎯
200H
000FFE00H
⎯
(Continued)
54
MB91460 Series
(Continued)
Interrupt source
Interrupt
number
Decimal
Interrupt level
Setting
Hexadecimal register
System reserved
128
80
System reserved
129
81
System reserved
130
82
System reserved
131
83
Real-time clock
132
84
System reserved
133
85
A/D converter 0
134
86
System reserved
135
87
System reserved
136
88
System reserved
137
89
System reserved
138
8A
System reserved
139
8B
Time base overflow
140
8C
PLL clock gear
141
8D
DMA controller
142
8E
Main/sub oscillation stabilization wait
143
8F
System reserved
144
Used by INT instruction
145
:
255
Offset
TBR default Resource
address
number*1
1FCH
000FFDFCH
⎯
1F8H
000FFDF8H
⎯
1F4H
000FFDF4H
⎯
1F0H
000FFDF0H
⎯
1ECH
000FFDECH
⎯
1E8H
000FFDE8H
⎯
1E4H
000FFDE4H
14
1E0H
000FFDE0H
⎯
1DCH
000FFDDCH
⎯
1D8H
000FFDD8H
⎯
1D4H
000FFDD4H
⎯
1D0H
000FFDD0H
⎯
1CCH
000FFDCCH
⎯
1C8H
000FFDC8H
⎯
1C4H
000FFDC4H
⎯
1C0H
000FFDC0H
⎯
Register
address
ICR56
478H
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
ICR63
47FH
90
⎯
⎯
1BCH
000FFDBCH
⎯
91
:
FF
⎯
⎯
1B8H
:
000H
000FFDB8H
:
000FFC00H
⎯
*1 : The peripheral resources to which RN (Resource Number) is assigned are capable of being DMA transfer
activation sources. In addition, RN has a one-to-one correspondence with an IS (Input Source) of the DMAC
channel control register A(DMACA0 to DMACA4), and the IS (Input Source) can be obtained by representing
RN in a binary number and adding “1” to the head of it.
*2 : Used by REALOS
*3 : ICR23 and ICR47 are interchangeable by setting REALOS bit (address 0C03H ISO[0]).
55
MB91460 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute maximum rating
Parameter
Symbol
Power supply voltage 1*1
Rating
Unit
Min
Max
VCC3
VSS − 0.5
VSS + 4.0
V
Remarks
VCC5
VSS − 0.5
VSS + 6.0
V
1
AVCC3
VSS − 0.5
VSS + 4.0
V
*2
1
AVRH
VSS − 0.5
VSS + 4.0
V
*2
VI1
VSS − 0.3
VCC3 + 0.3
V
VI2
VSS − 0.3
VCC5 + 0.3
V
Power supply voltage 2*1
Analog power supply voltage*
Analog power supply voltage*
Input voltage 1*1
Input voltage 2*1
VIA
VSS − 0.3
AVCC3 + 0.3
V
1
VO1
VSS − 0.3
VCC3 + 0.3
V
Output voltage 2*1
VO2
VSS − 0.3
VCC3 + 0.3
V
ICLAMP
− 2.0
+ 2.0
mA
*6
Σ⏐ICLAMP⏐
⎯
20
mA
*6
IOL
⎯
10
mA
*3
“L” level average output current
IOLAV
⎯
8
mA
*4
“L” level total maximum output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*5
IOL
⎯
− 10
mA
*3
“H” level average output current
IOHAV
⎯
−4
mA
*4
“H” level total maximum output current
ΣIOH
⎯
− 50
mA
“H” level total average output current
ΣIOHAV
⎯
− 20
mA
Power consumption
PD
⎯
1000
mW
Operation temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 125
°C
Analog pin input voltage*
Output voltage 1*
1
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level total average output current
“H” level maximum output current
Storage temperature
*5
*1 : The parameter is based on VSS = AVSS = 0.0 V.
*2 : Do not let AVCC3 and AVRH exceed VCC+0.3 [V], for example, when the power is turned on.
Also, do not let AVCC3 exceed VCC3.
*3 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding
pins.
*4 : Average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 100 ms period.
*5 : Total average output current is defined as the value of the average current flowing through all of the
corresponding pins for a 100 ms period.
(Continued)
56
MB91460 Series
(Continued)
*6 : •
•
•
•
•
•
•
•
•
•
•
Corresponding pins: Pin number 2, 3, 116, 117, 120 to 125, 134 to 145, 148 to 160, 163 to 175
Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied by connecting
a limiting resistor between the +B signal and the microcontroller.
The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed rated values at any time regardless of instantaneously or constantly when the +B signal is input.
Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+B input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other
devices.
Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied
through the pin, the microcontroller may operate incompletely.
Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power supply
voltage may become the voltage at which a power-on reset does not work.
Do not leave +B input pin open.
Note that analog input/output pins cannot accept +B signal input.
Example of recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
Limiting
resistor
P-ch
+B input (0 V to 16 V)
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
57
MB91460 Series
2. Recommended operating conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
Symbol
Value
Unit
Min
Typ
Max
VCC5
4.5
⎯
5.5
V
VCC3
3.0
⎯
3.6
V
AVCC3
3.0
⎯
3.6
V
Smoothing capacitor
CS
⎯
4.7
(accuracy
within ± 50%)
⎯
µF
Operating temperature
TA
− 40
⎯
+ 85
°C
Remarks
Use a ceramic capacitor or a
capacitor having the similar
frequency characteristic. For a
smoothing capacitor of VCC pin,
use one having a capacitance
value greater than CS.
WARNING: : The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
C_1
VSS
CS
58
C_2
AVSS
CS
MB91460 Series
3. DC characteristics
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
Condition
VIH1
P14_0 to P14_3,
P15_0 to P15_3,
P16_7,
P17_0 to P17_7,
P18_0 to P18_2,
P19_0 to P19_2,
P19_4 to P19_6,
P20_0 to P20_2,
P20_4 to P20_6,
P21_0 to P21_2,
P21_4 to P21_6,
P22_0, P22_2,
P22_3,
P23_0 to P23_4,
P23_6,
P24_0 to P24_3,
P24_6, P24_7,
P28_0 to P28_4,
P29_0 to P29_7,
NMI, BREAK,
MD0 to MD3
Value
Unit
Remarks
Min
Typ
Max
⎯
0.8 × VCC
⎯
VCC + 0.3
V
CMOS
hysteresis
input*1
VIH2
P14_0 to P14_3,
P15_0 to P15_3,
P16_7,
P17_0 to P17_7,
P18_0 to P18_2,
P19_0 to P19_2,
P19_4 to P19_6,
P20_0 to P20_2,
P20_4 to P20_6,
P21_0 to P21_2,
P21_4 to P21_6,
P22_0, P22_2,
P22_3,
P23_0 to P23_4,
P23_6,
P24_0 to P24_3,
P24_6, P24_7,
P28_0 to P28_4,
P29_0 to P29_7,
D16 to D31,
DREQ0, RDY,
BRQ,
ICD0 to ICD3
⎯
0.7 × VCC
⎯
VCC + 0.3
V
CMOS input*1
VIH3
P22_4 to P22_7,
P24_4, P24_5
⎯
0.7 × VCC
⎯
VCC5 + 0.3
V
I2C input*2
“H“ level
input voltage
(Continued)
59
MB91460 Series
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
Condition
VIL1
P14_0 to P14_3,
P15_0 to P15_3,
P16_7,
P17_0 to P17_7,
P18_0 to P18_2,
P19_0 to P19_2,
P19_4 to P19_6,
P20_0 to P20_2,
P20_4 to P20_6,
P21_0 to P21_2,
P21_4 to P21_6,
P22_0, P22_2,
P22_3,
P23_0 to P23_4,
P23_6,
P24_0 to P24_3,
P24_6, P24_7,
P28_0 to P28_4,
P29_0 to P29_7,
NMI, BREAK,
MD0 to MD3
Value
Unit
Remarks
Min
Typ
Max
⎯
VSS−0.3
⎯
0.2 × VCC
V
CMOS
hysteresis
input*1
VIL2
P14_0 to P14_3,
P15_0 to P15_3,
P16_7,
P17_0 to P17_7,
P18_0 to P18_2,
P19_0 to P19_2,
P19_4 to P19_6,
P20_0 to P20_2,
P20_4 to P20_6,
P21_0 to P21_2,
P21_4 to P21_6,
P22_0, P22_2,
P22_3,
P23_0 to P23_4,
P23_6,
P24_0 to P24_3,
P24_6, P24_7,
P28_0 to P28_4,
P29_0 to P29_7,
D16 to D31,
DREQ0, RDY,
BRQ,
ICD0 to ICD3
⎯
VSS−0.3
⎯
0.3 × VCC
V
CMOS input*1
VIL3
P22_4 to P22_7,
P24_4, P24_5
⎯
VSS−0.3
⎯
0.3 × VCC3
V
I2C input*2
“L“ level
input voltage
(Continued)
60
MB91460 Series
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
VOH1
P14_0 to P14_3,
P15_0 to P15_3,
P17_0 to P17_3,
P18_0 to P18_2,
P19_0 to P19_2,
P19_4 to P19_6,
P20_0 to P20_2,
P20_4 to P20_6,
P21_0 to P21_2,
P21_4 to P21_6,
P22_0, P22_2,
P22_3,
P23_0 to P23_4,
P23_6,
P24_0 to P24_3,
P24_6, P24_7
VOH2
P16_7,
P17_4 to P17_7,
P28_0 to P18_4,
P29_0 to P19_7,
D16 to D31,
ICD0 to ICD3,
A00 to A23,
AS, BGRNT,
CS0 to CS4,
DACK0, DEOP0,
ICLK,
ICS0 to ICS2,
IORD,
IOWR, RD,
SYSCLK,
WDRESET,
WR0, WR1
“H“ level
output
voltage
Condition
Value
Unit
Remarks
Min
Typ
Max
VCC = 5.0 V,
IOH = 4.0 mA/
VCC = 3.3 V,
IOH = 2.0 mA
VCC−0.5
⎯
⎯
V
3.3 V, 5 V
switch pin*3
VCC3 = 3.3 V,
IOH = 4.0 mA
VCC3−0.5
⎯
⎯
V
3.3 V
dedicated pin
(Continued)
61
MB91460 Series
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
VOL1
P14_0 to P14_3,
P15_0 to P15_3,
P17_0 to P17_3,
P18_0 to P18_2,
P19_0 to P19_2,
P19_4 to P19_6,
P20_0 to P20_2,
P20_4 to P20_6,
P21_0 to P21_2,
P21_4 to P21_6,
P22_0, P22_2,
P22_3,
P23_0 to P23_4,
P23_6,
P24_0 to P24_3,
P24_6, P24_7
Condition
Value
Unit
Remarks
Min
Typ
Max
VCC = 5.0 V,
IOL = 4.0 mA/
VCC = 3.3 V,
IOL = 2.0 mA
⎯
⎯
0.4
V
3.3 V, 5 V
switch pin*3
VOL2
P16_7,
P17_4 to P17_7,
P28_0 to P28_4,
P29_0 to P29_7,
D16 to D31,
ICD0 to ICD3,
A00 to A23,
AS, BGRNT,
CS0 to CS4,
DACK0, DEOP0,
ICLK,
ICS0 to ICS2,
IORD,
IOWR, RD,
SYSCLK,
WDRESET,
WR0, WR1
VCC3 = 3.3 V,
IOL = 4.0 mA
⎯
⎯
0.4
V
3.3 V
dedicated pin
VOL3
P22_4 to P22_7,
P24_4, P24_5
VCC3 = 3.3 V,
IOL = 3.0 mA
⎯
⎯
0.4
V
I2C output
Input leak
current
IIL
All input pins
VCC = DVCC =
AVCC = 5.0 V,
VSS < VI < VCC
−5
⎯
+5
µA
Pull-up
resistance
value
PUP
INIT, pull-up pin
⎯
25
50
100
kΩ
Pull-down
resistance
value
PDOWN
INIT, pull-up pin
⎯
25
50
100
kΩ
“L“ level
output
voltage
(Continued)
62
MB91460 Series
(Continued)
Parameter
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Symbol
Pin name
Condition
ICC3
VCC3
CPU core :
80 MHz,
External bus :
40 MHz
(no-load)
Peripheral
macro : 10 MHz
CAN : 20 MHz
ICC5
VCC5
⎯
Power supply current
ICCH
Input
capacitance
CIN
Value
Min
⎯
Unit
Typ
Max
120
150
mA
15
20
mA
Remarks
VCC3
TA = + 85 °C
⎯
1
3
mA At stop
VCC3
TA = + 85 °C
⎯
10
50
µA
f = 1 MHz
⎯
5
15
pF
Except
VCC3, VCC5,
VSS, AVCC,
AVSS, AVRH
At shutdown
*1 : For a pin which can select the I/O power supply between 3.3 V and 5 V, the value is based on the power supply
voltage currently used.
Although 5 V input is possible for TRST, the input becomes CMOS hysteresis based on the input threshold
value VCC3.
*2 : Although 5 V input is possible for I2C pin, the input is made based on the input threshold value VCC3.
*3 : For a pin which can select the I/O power supply between 3.3 V and 5 V, the drive capability changes depending
on the power supply voltage.
63
MB91460 Series
4. AC characteristics
(1) Clock timing
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Clock frequency
Clock cycle time
Pin
Conname dition
fC
X0
X1
tC
X0
X1
fCPP
⎯
fCPT
fCAN
⎯
tCP
tCPP
Internal operation clock
cycle time
⎯
tCPT
Unit
Remarks
Min
Typ
Max
10
18.5
20
MHz
50
54
100
ns
4.6
⎯
80
MHz CPU
4.6
⎯
20
MHz Peripheral
4.6
⎯
40
MHz External bus
⎯
⎯
20
MHz
12.5
⎯
217
ns
CPU
50
⎯
217
ns
Peripheral
26.7
⎯
217
ns
External bus
50
⎯
⎯
ns
Clock after divided by
CAN prescaler
⎯
fCP
Internal operation clock
frequency
Value
tCAN
Clock after divided by
CAN prescaler
Note : These values are assumed based on the division setting of each clock set to 16.
• Conditions for measuring the clock timing ratings
tC
Output pin
0.8 VCC
0.2 VCC
PWH
64
PWL
C = 50 pF
MB91460 Series
(2) Clock output timing
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol Pin name
Cycle time
tCYC
SYSCLK
SYSCLK↑→SYSCLK↓
tCHCL
SYSCLK
SYSCLK↓→SYSCLK↑
tCLCH
SYSCLK
Value
Condition
⎯
Unit
Min
Max
tCPT
⎯
ns
12.5
108.5
ns
12.5
108.5
ns
Remarks
*
* : tCYC is the frequency of 1 clock cycle.
tCYC
tCHCL
tCLCH
VOH
VOH
VOL
SYSCLK
(3) Reset input ratings
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
INIT input time
(at power-on, at return from
shutdown mode)
Symbol
tINTL
Pin name
INIT
Condition
Value
Unit
Min
Max
8
⎯
ms
20
⎯
µs
⎯
INIT input time
(other than the above)
tINTL
INIT
0.2 VCC
65
MB91460 Series
(4) Normal bus access read/write operation
(VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
CS0 to CS4 setup
CS0 to CS4 hold
Address setup
Address hold
Valid address/valid data
input time
WR0, WR1 delay time
Symbol
Pin name
Condition
tCSLCH
tCSDLCH
SYSCLK
CS0 to CS4
tCHCSH
Value
Unit Remarks
Min
Max
3
⎯
ns
−3
⎯
ns
3
tCYC/2 + 6
ns
tASCH
SYSCLK
A23 to A00
3
⎯
ns
tASWL
WR0, WR1
A23 to A00
3
⎯
ns
tASRL
RD
A23 to A00
3
⎯
ns
tCHAX
SYSCLK
A23 to A00
3
tCYC/2 + 6
ns
tWHAX
WR0, WR1
A23 to A00
3
⎯
ns
tRHAX
RD
A23 to A00
3
⎯
ns
tAVDV
A23 to A00
D31 to D16
⎯
3/2 × tCYC − 15
ns
⎯
6
ns
⎯
6
ns
tCHWL
tCHWH
SYSCLK
WR0, WR1
⎯
Data setup time
(WRn rising)
tDSWH
D31 to D16
WR0, WR1
tCYC − 3
⎯
ns
Data hold time
(WRn rising)
tWHDX
D31 to D16
WR0, WR1
3
⎯
ns
WR0, WR1 minimum pulse
width
tWLWH
WR0, WR1
tCYC − 3
⎯
ns
tCHRL
SYSCLK
RD
⎯
6
ns
⎯
6
ns
RD delay time
tCHRH
Data setup time (RD rising)
tDSRH
D31 to D16
RD
20
⎯
ns
Data hold time (RD rising)
tRHDX
D31 to D16
RD
0
⎯
ns
RD minimum pulse width
tRLRH
RD
tCYC − 3
⎯
ns
AS setup
tASLCH
3
⎯
ns
AS hold
tCHASH
SYSCLK
AS
3
tCYC/2 + 6
ns
*
* : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
66
MB91460 Series
tCYC
VOH
BA1
VOH
VOH
VOH
SYSCLK
tASLCH
tCHASH
AS
VOH
VOL
tCHCSH
tCSLCH
CS0 to CS4
VOH
VOL
tCHAX
tASCH
A23 to A00
VOH
VOL
VOH
VOL
tCHRH
tCHRL
tRLRH
RD
VOH
VOL
tASRL
tRHAX
tDSRH
tRHDX
tAVDV
VIH
D31 to D16
VIH
Read
VIL
VIL
tCHWH
tCHWL
tWLWH
VOH
VOL
WR0, WR1
tWHAX
tASWL
tWHDX
tDSWH
D31 to D16
VOH
VOL
Write
VOH
VOL
67
MB91460 Series
(5) Ready input timing
(VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
RDY setup time
→ SYSCLK ↓
tRDYS
SYSCLK
RDY
SYSCLK ↑
→ RDY hold time
tRDYH
SYSCLK
RDY
Value
Condition
VOH
VOH
VOL
VOL
tRDYS tRDYH
When RDY
wait is
applied
When RDY
wait is not
applied
68
tRDYS tRDYH
VOH
VOH
VOL
VOL
VOH
VOH
VOL
Max
10
⎯
ns
0
⎯
ns
⎯
tCYC
SYSCLK
Unit
Min
VOL
MB91460 Series
(6) Hold timing
(VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
tCHBGL
tCHBGH
SYSCLK
BGRNT
BGRNT rising from pin floating
tXHAL
⎯
BGRNT rising from pin valid
tHAHV
BGRNT
BGRNT delay time
Value
Condition
⎯
Unit
Min
Max
⎯
10
ns
⎯
10
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Note : After a BRQ is captured, a minimum of 1 cycle is required before BGRNT changes.
tCYC
SYSCLK
VOH
VOH
VOH
VOH
BRQ
tCHBGL
BGRNT
tCHBGH
VOL
tXHAL
VOH
tHAHV
Each pin
High impedance
69
MB91460 Series
(7) LIN-UART timing
(VCC5 = 4.5 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
Condition
Unit
Min
Max
SCK0 to SCK6
5tCYCP
⎯
ns
tSLOV
SCK0 to SCK6,
SOT0 to SOT6
− 50
+ 50
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK6,
SIN0 to SIN6
tCYCP + 80
⎯
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to SCK6,
SIN0 to SIN6
0
⎯
ns
Serial clock ”H” pulse width
tSHSL
SCK0 to SCK6
tCYCP + 10
⎯
ns
Serial clock ”L” pulse width
tSLSH
SCK0 to SCK6
3tCYCP
⎯
ns
SCK ↓ → SOT delay time
tSLOV
SCK0 to SCK6,
SOT0 to SOT6
⎯
150
ns
Valid SIN → SCK ↑
tIVSH
SCK0 to SCK6,
SIN0 to SIN6
30
⎯
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0 to SCK6,
SIN0 to SIN6
tCYCP + 30
⎯
ns
SCK rising time
tF
SCK0 to SCK6
⎯
10
ns
SCK falling time
tR
SCK0 to SCK6
⎯
10
ns
Internal shift
clock mode
External shift
clock mode
Notes : • Above values are AC characteristics for CLK synchronous mode.
• tCYCP is the cycle time of the peripheral clock.
70
Value
MB91460 Series
• Internal shift clock mode
tSCYC
SCK0 to SCK6
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT6
tIVSH
tSHIX
VOH
VOL
SIN0 to SIN6
VOH
VOL
• External shift clock mode
tSLSH
SCK0 to SCK6
tSHSL
VOL
VOL
VOH
VOL
tSLOV
SOT0 to SOT6
VOH
VOL
tIVSH
SIN0 to SIN6
VOH
VOL
tSHIX
VOH
VOL
71
MB91460 Series
(8) DMA controller timing
(VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
DREQ0 input pulse
DACK0 delay time
DEOP0 delay time
IORD delay time
IOWR delay time
Symbol
Pin name
tDRWH
DREQ0
tCLDL
Value
Condition
DACK0
tCLDH
tCLEL
DEOP0
tCLEH
tCHIRL
⎯
IORD
tCHIRH
tCHIWL
IOWR
tCHIWH
Max
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
Note : After a BREQ is captured, a minimum of 1 cycle is required before BGRNT changes.
tCYC
SYSCLK
VOH
VOH
VOH
tCLDL
DACK0
VOH
tCLDH
VOH
VOL
tCLEL
tCLEH
VOH
DEOP0
VOL
tCHIRL
IORD
tCHIRH
VOH
VOL
tCHIWL
IOWR
tCHIWH
VOL
VOH
tDRWH
DREQ0
72
VOL
Unit
Min
VOH
MB91460 Series
(9) Free-run timer clock
(VCC5 = 4.0 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
FRCK0 to FRCK3
⎯
Value
Min
Max
4tCYCP
⎯
Unit
ns
Note : tCYCP is the cycle time of the peripheral clock.
FRCK0 to FRCK3
tTIWH
tTIWL
(10) Trigger input timing
(VCC5 = 4.0 V to 5.5 V, VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Input capture input trigger
A/D converter trigger
Symbol
Pin name
Condition
tINP
ICU0 to ICU3
tATGX
ATG
Value
Unit
Min
Max
⎯
5tCYCP
⎯
ns
⎯
5tCYCP
⎯
ns
Note : tCYCP is the cycle time of the peripheral clock.
tATGX, tINP
ICU0 to ICU3,
ATG
73
MB91460 Series
5. A/D converter
(1) Electrical characteristics
(VCC3 = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
Resolution
⎯
Total error*1
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3
LSB
Linearity error*1
⎯
⎯
⎯
⎯
± 2.5
LSB
Differential linearity
error*1
⎯
⎯
⎯
⎯
± 1.9
LSB
Zero transition voltage*1
VOT
AN0 to AN12 AVRL−1.5 AVRL−0.5 AVRL−2.5
LSB
Full transition voltage*1
VFST
AN0 to AN12 AVRH−3.5 AVRH−1.5 AVRH−0.5
LSB
Conversion time
⎯
⎯
1 *2
⎯
⎯
µs
Analog port input
current
IAIN
AN0 to AN12
⎯
⎯
10
µA
Analog input voltage
VAIN
AN0 to AN12
AVSS
⎯
AVRH
V
Reference voltage
⎯
AVRH
AVSS
⎯
AVCC3
V
Analog power supply
current
(analog + digital)
IA
⎯
1.5
2.5
mA
⎯
⎯
10
µA
AVCC3
IAH*3
Remarks
At AVCC3 = 3.3 V,
AVRH = 3.3 V
Including
reference
supply
Analog input equivalent
capacity
Cin
AN0 to AN12
⎯
⎯
14.7
pF
Analog input equivalent
resistance
Rin
AN0 to AN12
⎯
⎯
1.9
kΩ
AVCC3 ≥ 2.7 V
Output impedance of
analog signal source
Rext
⎯
⎯
⎯
1.9
kΩ
AVCC3 ≥ 2.7 V
*1 : Measured in the CPU sleep state
*2 : Set the peripheral clock and conversion time setting register to set a time equal to or longer than this time.
*3 : The current when A/D converter is not operating, or in the CPU stop mode (at VCC3 = AVCC3 = AVRH = 3.3 V).
74
MB91460 Series
(2) Cautions Relating to the A/D Converter
The diagram below shows the equivalent circuit of the sampling circuit in the A/D converter.
The output impedance of the external circuit connected to the analog input must satisfy the following criteria.
• The recommended output impedance for the external circuit is 1.9 kΩ or less.
• If an external capacitor is used, remember to consider the capacitive voltage divider effect due to the external
capacitor and the internal capacitor in the chip. Accordingly, an external capacitance several thousand times
that of the internal capacitance is recommended.
• The analog voltage sampling period may be too short if the output impedance of the external circuit is high.
In this case, select Rext and Tsamp such that they satisfy the following condition.
Rext = Tsamp/ (7 × Cin) − Rin
Rext
Tsamp
Cin
Rin
: Output impedance of the analog signal source
: Sampling time
: Equivalent capacitance of analog input
: Equivalent resistance of analog input
• Input impedance
Analog
signal source
Rext
Analog
input pin Analog SW
Rin:1.9 kΩ (Max)
Cin:14.7 pF (Max)
A/D converter
Device internal circuit
75
MB91460 Series
(3) Definition of A/D converter terms
• Resolution
Analog variation that is recognizable by an A/D converter.
• Linearity error
Deviation between actual conversion characteristics and a straight line connecting zero transition point
(00 0000 0000 ↔ 00 0000 0001) and full scale transition point (11 1111 1110 ↔ 11 1111 1111).
• Differential linearity error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error
This error indicates the difference between actual and theoretical values, including the zero transition error/
full scale transition error/linearity error.
Total error
3FFH
Digital output
3FEH
3FDH
1.5 LSB
Actual conversion
characteristics
{1 LSB (N − 1) + 0.5 LSB}
004H
VNT
(measurement value)
003H
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS
AVRH
Analog input
1LSB' (ideal value) = AVRH − AVSS
1024
[V]
Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'}
1 LSB'
N : A/D converter digital output value
VOT' (ideal value) = AVSS + 0.5 LSB' [V]
VFST' (ideal value) = AV − 1.5 LSB' [V]
VNT : A voltage at which digital output transits from (N + 1) H to NH
76
MB91460 Series
Linearity error
3FFH
Differential linearity error
Actual conversion characteristics
Actual conversion characteristics
3FEH
(N+1)H
{1 LSB (N − 1) + VOT}
VFST
(measurement value)
004H
VNT
(measurement value)
003H
002H
Digital output
Digital output
3FDH
Ideal
characteristics
NH
(N-1)H
VFST
Actual conversion
characteristics
VNT
(measurement value)
Ideal characteristics
001H
(N-2)H
Actual conversion
characteristics
VTO (measurement value)
AVSS
AVRH
AVSS
Analog input
Linearity error of digital output N =
(measurement value)
AVRH
Analog input
VNT − {1LSB × (N − 1) + VOT} [LSB]
1LSB
Differential linearity error of digital output N = V (N + 1) T − VNT [LSB]
1LSB
1LSB =
VFST − VOT
1022
[V]
N
: A/D converter digital output value
VOT : A voltage at which digital output transits from 000H to 001H.
VFST : A voltage at which digital output transits from 3FEH to 3FFH.
77
MB91460 Series
■ ORDERING INFORMATION
Part number
MB91461PMC-GSE1
78
Package
Remarks
176-pin, plastic LQFP
(FPT-176P-M07)
Lead-free package
MB91460 Series
■ PACKAGE DIMENSION
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0˚~8˚
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2004 FUJITSU LIMITED F176013S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
79
MB91460 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
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operation of the device with respect to use based on such
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device based on such information, you must assume any
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function and schematic diagrams, shall not be construed as license
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Please note that Fujitsu will not be liable against you and/or any
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Edited
Business Promotion Dept.
F0704