SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or 100 counter and a programmable divide–by–N 4–bit binary counter (all positive–edge triggered) constructed with MOS P–channel and N–channel enhancement mode devices (complementary MOS) in a monolithic structure. The MC14568B has been designed for use in conjunction with a programmable divide–by–N counter for frequency synthesizers and phase– locked loop applications requiring low power dissipation and/or high noise immunity. This device can be used with both counters cascaded and the output of the second counter connected to the phase comparator (CTL high), or used independently of the programmable divide–by–N counter, for example cascaded with a MC14569B, MC14522B or MC14526B (CTL low). P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION • Supply Voltage Range = 3.0 to 18 V • Capable of Driving Two Low–Power TTL Loads, One Low–Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range. • Chip Complexity: 549 FETs or 137 Equivalent Gates MC14XXXBCP MC14XXXBCL MC14XXXBD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. MAXIMUM RATINGS* (Voltages referenced to VSS) Rating DC Supply Voltage Input Voltage, All Inputs DC Input Current, per Pin Power Dissipation, per Package† Operating Temperature Range Storage Temperature Range Symbol Value Unit VDD Vin – 0.5 to + 18 Vdc – 0.5 to VDD + 0.5 Vdc Iin PD ± 10 mAdc 500 mW TA Tstg – 55 to + 125 _C – 65 to + 150 _C TRUTH TABLE F Pin 10 G Pin 11 Division Ratio of Counter D1 0 0 1 1 0 1 0 1 4 16 64 100 The divide by zero state on the programmable divide–by–N 4–bit binary counter, D2, is illegal. * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C BLOCK DIAGRAM PCin 14 A 13 PCout PHASE COMPARATOR (REF.) B 12 LD TG CTL HIGH TG CTL LOW 11 G C1 9 10 F P/C CTL 15 TG PE 2 PCout LD D2 DP3 4 5 6 DP2 DP1 7 P/C LD C1 D1 “0” D2 1 Q1/C2 “0” VDD = PIN 16 VSS = PIN 8 PCin C1 D1 4–BIT PROGRAMMABLE COUNTER D2 “0” 3 PCout PCin COUNTER D1 Q1/C2 Q1/C2 DP0 REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14568B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 1.2 – 0.25 – 0.62 – 1.8 — — — — – 1.0 – 0.2 – 0.5 – 1.5 – 1.7 – 0.36 – 0.9 – 3.5 — — — — – 0.7 – 0.14 – 0.35 – 1.1 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 µA IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Three–State Leakage Current Pins 1, 13 ITL 15 Vin = 0 or VDD Input Voltage#‡ “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Vdc Vdc IOH Source (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Sink mAdc IT = (0.2 µA/kHz) f + IDD IT = (0.4 µA/kHz) f + IDD IT = (0.9 µA/kHz) f + IDD — ± 0.1 — ± 0.0001 ± 0.1 µAdc — ± 3.0 µAdc #Noise immunity for worst input combination. Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 1 x 10–3 (CL – 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_C. ‡Pin 15 is connected to VSS or VDD for input voltage test. PIN ASSIGNMENT MC14568B 2 Q1/C2 1 16 VDD PE 2 15 CTL “0” 3 14 PCin DP3 4 13 PCout DP2 5 12 LD DP1 6 11 G DP0 7 10 F VSS 8 9 C1 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD V Min Typ Max Unit Output Rise Time tTLH 5.0 10 15 — — — 180 90 65 360 180 130 ns Output Fall Time tTHL 5.0 10 15 — — — 100 50 40 200 100 80 ns Minimum Pulse Width, C1, Q1/C2, or PCin Input tWH 5.0 10 15 — — — 125 60 45 250 120 90 ns Maximum Clock Rise and Fall Time, C1, Q1/C2, or PCin Input tTLH, tTHL 5.0 10 15 15 15 15 — — — — — — µs Input Resistance Rin 5.0 to 15 — 106 — MΩ Input Sensitivity, dc Coupled — 5.0 to 15 Turn–Off Delay Time, PCout and LD Outputs tPHL 5.0 10 15 — — — 550 195 120 1100 390 240 ns Turn–On Delay Time. PCout and LD Outputs tPLH 5.0 10 15 — — — 675 300 190 1350 600 380 ns 5.0 10 15 3.0 8.0 10 6.0 16 22 — — — 5.0 10 15 1.0 3.0 50 2.5 6.3 9.7 — — — 5.0 10 15 — — — 450 190 130 900 380 260 5.0 10 15 — — — 720 300 200 1440 600 400 fcl 5.0 10 15 1.2 3.0 4.0 1.8 8.5 12 — — — MHz Turn–On Delay Time, “0” Output (Figure 3a) tPLH 5.0 10 15 — — — 450 190 130 900 380 260 ns Turn–Off Delay Time, “0” Output (Figure 3a) tPHL 5.0 10 15 — — — 225 85 60 450 170 150 ns tWH(PE) 5.0 10 15 — — — 75 40 30 250 100 75 ns PHASE COMPARATOR See Input Voltage DIVIDE–BY–4, 16, 64 OR 100 COUNTER (D1) Maximum Clock Pulse Frequency Division Ratio = 4, 64 or 100 fcl Division Ratio = 16 Propagation Delay Time, Q1/C2 Output Division Ratio = 4, 64 or 100 tPLH, tPHL Division Ratio = 16 MHz ns PROGRAMMABLE DIVIDE–BY–N 4–BIT COUNTER (D2) Maximum Clock Pulse Frequency (Figure 3a) Minimum Preset Enable Pulse Width MOTOROLA CMOS LOGIC DATA MC14568B 3 SWITCHING TIME TEST CIRCUITS AND WAVEFORMS VDD A LAGS B, PCout IS LOW. VDD 2 “0”out REF B 10 k CTL DP0 DP1 DP2 DP3 PCin F G C1 PE PULSE GENERATOR 1 PULSE GENERATOR 2 A LEADS B, PCout IS HIGH. 50% 20 ns 20 ns PCout LD CL PCin PG1 CL tW(PCin) 90% 50% 10% A tPLH tPLH tTHL Q1/C2 tPLH 90% LD “0” 10% tPHL THREE–STATE PCout VSS Figure 1. Phase Comparator tTLH tPHL 75% THREE–STATE 25% VOH VOL tPHL tPLH VDD CTL DP0 DP1 DP2 DP3 PCin F G C1 PE PULSE GENERATOR 20 ns C1 10% 90% 50% fin fmax tPHL Q1/C2 CL Q1/C2 10% “0” 90% 50% tTLH VSS tTHL Figure 2. Counter D1 VDD DP0 DP1 PCout DP2 LD DP3 Q1/C2 PCin F G “0” C1 CTL PE VSS PULSE GENERATOR tW(C1) 20 ns PCout LD PULSE GENERATOR 1 PULSE GENERATOR 2 VDD DP0 DP1 PCout DP2 LD DP3 Q1/C2 PCin F G “0” C1 CTL PE CL CL VSS N PULSES* 20 ns Q1/C2 Q1/C2 = PG 1 20 ns tPHL 10% 50% 20 ns 90% 50% 10% tPLH “0” tW(Q1/C2) 20 ns fin fmax PE = PG2 90% 50% 90% 50% 10% tW(PE) tTLH tTHL “0” * N is the value programmed on the DP Inputs. a. MC14568B 4 Figure 3. Counter D2 b. MOTOROLA CMOS LOGIC DATA LOGIC DIAGRAM PCin A 14 13 B (REF.) PCout LD D D Q Q Q C C C COUNTER D1 9 C1 10 F 11 G 1 Q1/C2 15 CTL 3 “0” PE 2 PE COUNTER D2 C Q D VDD = PIN 16 VSS = PIN 8 4 DP3 MOTOROLA CMOS LOGIC DATA 5 DP2 6 DP1 7 DP0 MC14568B 5 Typical Maximum Frequency Divider D1 Division ratios: 4, 64 or 100 (CL = 50 pF) Typical Maximum Frequency Divider D1 Division ratio: 16 (CL = 50 pF) 12 26 10 f, FREQUENCY (MHz) 28 24 22 20 f, FREQUENCY (MHz) VDD = 15 V 8 VDD = 15 V 6 VDD = 10 V 4 18 2 16 0 – 40 VDD = 5 V – 20 0 14 + 20 + 40 + 60 T, TEMPERATURE (°C) + 80 + 100 VDD = 10 V 12 Typical Maximum Frequency Divider D2 Division ratio: 2 (CL = 50 pF) 10 6 8 5 VDD = 5 V 4 2 0 – 40 – 20 0 + 20 + 40 + 60 T, TEMPERATURE (°C) + 80 + 100 f, FREQUENCY (MHz) 6 4 VDD = 15 V 3 VDD = 10 V 2 0 – 40 MC14568B 6 VDD = 5 V 1 – 20 0 + 20 + 40 + 60 T, TEMPERATURE (°C) + 80 + 100 MOTOROLA CMOS LOGIC DATA OPERATING CHARACTERISTICS The MC14568B contains a phase comparator, a fixed divider (÷ 4, ÷ 16, ÷ 64, ÷ 100) and a programmable divide– by–N 4–bit counter. PHASE COMPARATOR The phase comparator is a positive edge controlled logic circuit. It essentially consists of four flip–flops and an output pair of MOS transistors. Only one of its inputs (PCin, pin 14) is accessible externally. The second is connected to the output of one of the two counters D1 or D2 (see block diagram). Duty cycles of both input signals (at A and B) need not be taken into consideration since the comparator responds to leading edges only. If both input signals have identical frequencies but different phases, with signal A (pin 14) leading signal B (Ref.), the comparator output will be high for the time equal to the phased difference. If signal A lags signal B, the output will be low for the same time. In between, the output will be in a three–state condition and the voltage on the capacitor of an RC filter normally connected at this point will have some intermediate value (see Figure 4). When used in a phase locked loop, this value will adjust the Voltage Controlled Oscillator frequency by reducing the phase difference between the reference signal and the divided VCO frequency to zero. VDD VSS A (PCin) 1/f VOH VOL VOH B (REF.) LD VOL VOH PCout VOL Figure 4. Phase Comparator Waveforms If the input signals have different frequencies, the output signal will be high when signal B has a lower frequency than signal A, and low otherwise. Under the same conditions of frequency difference, the output will vary between VOH (or VOL) and some intermediate value until the frequencies of both signals are equal and their phase difference equal to zero, i.e. until locked condition is obtained. Capture and lock range will be determined by the VCO frequency range. The comparator is provided with a lock indicator output, which will stay at logic 1 in locked conditions. The state diagram (Figure 5) depicts the internal state transitions. It assumes that only one transition on either signal occurs at any time. It shows that a change of the output state is always associated with a positive transition of either signal. For a negative transition, the output does not change state. A positive transition may not cause the output to change, this happens when the signals have different frequencies. DIVIDE BY 4, 16, 64 OR 100 COUNTER (D1) This counter is able to work at an input frequency of 5 MHz for a VDD value of 10 volts over the standard temperature range when dividing by 4, 64 and 100. Programming is accomplished by use of inputs F and G (pins 10 and 11) according to the truth table shown. Connecting the Control input (CTL, pin 15), to VDD allows cascading this counter with the programmable divide–by–N counter provided in the same package. Independent operation is obtained when the Control input is connected to VSS. The different division ratios have been chosen to generate the reference frequencies corresponding to the channel spacings normally required in frequency synthesizer applications. For example. with the division ratio 100 and a 5 MHz crystal stabilized source a reference frequency of 50 kHz is supplied to the comparator. The lower division ratios permit operation with low frequency crystals. INPUT STATE 00 01 X X 10 11 A 00 10 00 01 01 11 10 11 B PCout 0 3–STATE OUTPUT DISCONNECTED 1 LD (LOCK DETECT) 0 1 0 Figure 5. Phase Comparator State Diagram MOTOROLA CMOS LOGIC DATA MC14568B 7 If used in cascade with the programmable divide–by–N counter, practically all usual reference frequencies, or channel spacings of 25, 20, 12.5, 10, 6.25 kHz, etc. are easily achievable. (pins 7 ... 4). The Preset Enable input enables the parallel preset inputs DP0... D P3. The “0” output must be externally connected to the PE input for single stage applications. Since there is not a cascade feedback input, this counter, when cascaded, must be used as the most significant digit. Because of this, it can be cascaded with binary counters as well as with BCD counters (MC14569B, MC14522B, MC14526B). PROGRAMMABLE DIVIDE–BY–N 4–BIT COUNTER (D2) This counter is programmable by using inputs DP0 ... DP3 TYPICAL APPLICATIONS fin CF C C MC14569B ZERO DETECT PE CF MC14522B OR MC14526B Q4 C “0” PE DP0 – – – – – – DP3 CF MC14522B OR MC14526B Q4 Q1/C2 “0” PE MC14568B DP0 – – – – – – DP3 “0” DP0 – – – – – – DP3 LSD fout MSD Figure 6. Cascading MC14568B and MC14522B or MC14526B with MC14569B (40 kHz) PCin C1 CTI VSS “0” MC14568B fout VCO PCout G (144 – 146 MHz) VSS VSS F Q1/C2 PE VDD DP0 – – – – DP3 MC14011 Q CF MC14569B ZERO DETECT C MIXER 2k 2M CRYSTAL OSCILLATOR Frequencies shown in parenthesis are given as an example. (143.5 MHz) Figure 7. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer (Channel Spacing 10 kHz) MC14568B 8 MOTOROLA CMOS LOGIC DATA PCin C1 (5 MHz) (VDD) CTL “0” MC14568B PCout G F PE VDD VDD VDD VSS fout VCO C C MC14569B MC14522B DP0 – – – – – DP3 CF Q ZERO DETECT “0” PE (BCD) BINARY DP0 – – – – – DP3 N1 (0 – 5) (625 kHz STEPS) N2 (0 – 9) (62.5 kHz STEPS) N3 (0, 4, 8, 12) (6.25 kHz STEPS) Divide ratio = 160N1 + 16N2 + N3 Figures shown in parenthesis refer to example. Example: Recommended reading: fout = N1 (MHz) + N2 (x 100 kHz) + N3 (x25 kHz) Frequency range = 5 MHz (1) AN535: “Phase–Lock Techniques” (2) AR254: “Phase–Locked Loop Design Articles” Channel spacing = 25 kHz Reference frequency = 6.25 kHz Figure 8. Frequency Synthesizer Using MC14568B, MC14569B and MC14522B (Without Mixer) MOTOROLA CMOS LOGIC DATA MC14568B 9 Figure 9. Typical 23–Channel CB Frequency Synthesizer for Double Conversion Transceivers MC14568B 10 MOTOROLA CMOS LOGIC DATA ÷2 VDD NOTE: 1. 10 kHz Channel Spacing 2. Expandable to 165 Channels (Expanded frequency range shown in parenthesis) 10.24 MHz REFERENCE OSCILLATOR TO 455 kHz IF RECEIVER SECOND MIXER X3 ÷8 RCV TRX 10.695 MHz ÷N φ 10.695 MHz OSCILLATOR (TRASMIT ONLY) ÷N MC14526B 10 kHz LOOP LOW PASS FILTER RF AMP DOWN MIXER .91–1.20 (2.55) MHz D N = 91–120 (255) MHz ÷64 MC14568B LOCK DETECTOR RECEIVER FIRST MIXER MIXER VCO TO TRANSMITTER 26.965–27.255 (28.605) MHz 16.270–16.560 (17.910) MHz 26.965–27.255 (28.605) MHz OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14568B 11 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC14568B 12 ◊ *MC14568B/D* MOTOROLA CMOS LOGIC DATA MC14568B/D